Display device

Abstract

A display device is disclosed, comprising a pixel disposed in a display area. The pixel includes a light-emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light-emitting element, configured to control a drive current flowing in the light-emitting element in response to a voltage at a first node; and at least one switching transistor configured to transmit a data signal or an initialization power supply voltage to the first node. The switching transistor includes a first channel region, a first conductive region and a second conductive region disposed on opposite sides of the first channel region, and a first wide bandgap region disposed between the first channel region and the second conductive region.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0092503, filed on July 30, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] A display device uses pixels arranged in a display area to display an image. The pixels can be connected to scan lines and data lines and can include transistors. For example, a pixel of an active light emitting display device can include a light emitting element, a driving transistor, and at least one switching transistor.

[0004] To achieve the desired brightness in a pixel during the emission period of each frame, the gate voltage of the drive transistor must remain stable. However, due to the characteristics of the transistor, leakage current may occur in the pixel. This leakage current may cause variations in the gate voltage of the drive transistor, in which case the desired brightness may not be fully achieved in each pixel.

[0005] It will be understood that this background technology section is intended, in part, to provide a useful context for understanding the technology. However, this background technology section may also include ideas, concepts, or realizations that were not part of what was known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0006] The disclosed embodiments provide a display device capable of effectively reducing or preventing leakage current of a pixel and a method of manufacturing the display device.

[0007] A display device includes a pixel disposed in a display area. The pixel includes a light-emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light-emitting element and configured to control a drive current flowing in the light-emitting element in response to a voltage at a first node; and at least one switching transistor configured to transmit a data signal or an initialization power supply voltage to the first node. The at least one switching transistor includes a first channel region, a first conductive region and a second conductive region disposed on opposite sides of the first channel region, and a first wide bandgap region disposed between the first channel region and the second conductive region.

[0008] In an embodiment, the first channel region, the first conductive region, and the second conductive region may include polysilicon, and the first wide bandgap region may include amorphous silicon.

[0009] In an embodiment, the first wide bandgap region may have an energy bandgap of approximately 1.7 eV, and the first channel region and the first and second conductive regions may have energy bandgaps of approximately 1.12 eV.

[0010] In an embodiment, the at least one switching transistor may include a plurality of transistors connected in series to each other.

[0011] In an embodiment, the at least one switching transistor may further include: a second channel region disposed between the first channel region and the second conductive region; a third conductive region disposed between the first channel region and the second channel region; and a second wide bandgap region disposed between the second channel region and the third conductive region. The first wide bandgap region may be disposed between the first channel region and the third conductive region.

[0012] In an embodiment, the first wide bandgap region may be in direct contact with the first channel region and the third conductive region, and the second wide bandgap region may be in direct contact with the second channel region and the third conductive region.

[0013] In an embodiment, the at least one switching transistor may include a first gate electrode overlapping the first channel region and a second gate electrode overlapping the second channel region. The first gate electrode and the second gate electrode may be electrically connected to each other.

[0014] In an embodiment, the at least one switching transistor may further include a second wide bandgap region disposed between the first channel region and the first conductive region.

[0015] In an embodiment, each of the first wide band gap region and the second wide band gap region may include amorphous silicon.

[0016] In an embodiment, at least one switching transistor may include at least one of: a second transistor connected between the first electrode of the first transistor and the data line, the second transistor including a gate electrode connected to the scan line; a third transistor connected between the second electrode of the first transistor and the first node, the third transistor including a gate electrode connected to the scan line; and a fourth transistor connected between the first node and the initialization power supply, the fourth transistor including a gate electrode connected to the first control line.

[0017] In an embodiment, the third transistor may include a first channel region, a first conductive region, a second conductive region, and a first wide bandgap region.

[0018] In an embodiment, the third transistor may include a plurality of transistors connected to each other in series.

[0019] In an embodiment, the third transistor may further include: a second channel region disposed between the first channel region and the second conductive region; a third conductive region disposed between the first channel region and the second channel region; and a second wide bandgap region disposed between the second channel region and the third conductive region. The first wide bandgap region may be disposed between the first channel region and the third conductive region.

[0020] In an embodiment, the third transistor may include a first gate electrode overlapping the first channel region and a second gate electrode overlapping the second channel region.The first gate electrode and the second gate electrode may be commonly connected to the scan line.

[0021] In an embodiment, the fourth transistor may include a first channel region, a first conductive region, a second conductive region, and a first wide bandgap region.

[0022] In an embodiment, the fourth transistor may include a plurality of transistors connected to each other in series.

[0023] In an embodiment, the second transistor may include a first channel region, a first conductive region, a second conductive region, a first wide bandgap region, and a second wide bandgap region disposed between the first channel region and the first conductive region.

[0024] In an embodiment, the pixel may include a plurality of switching transistors, and a predetermined number of the switching transistors may include a first wide bandgap region.

[0025] A method for manufacturing a display device including a switching transistor includes: forming a semiconductor pattern in a switching transistor region; setting a first mask and a second mask on a first region and a second region of the semiconductor pattern, respectively, and exposing a remaining region of the semiconductor pattern; crystallizing the remaining region of the semiconductor pattern to include separated amorphous regions corresponding to the first region and the second region and a crystalline region corresponding to the remaining region; forming a first insulating film on the semiconductor pattern; forming a gate electrode on a region of the crystallized region; and doping another region of the crystallized region with impurities using the gate electrode as a mask.

[0026] In an embodiment, the switching transistor may include a plurality of transistors connected in series. In this case, the region between the channel regions of the transistors may be doped with impurities to form a conductive region, and the amorphous region may be formed between the conductive region and the channel region.

[0027] In an embodiment, the switch transistor may be formed as a single transistor. In this case, the amorphous region may be formed at an opposite side of the crystallized region overlapping the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A display device according to an embodiment is shown.

[0029] Figure 2 and Figure 3 A pixel according to an embodiment is shown.

[0030] Figure 4 and Figure 5 A switching transistor according to an embodiment is shown.

[0031] Figure 6 and Figure 7 A switching transistor according to an embodiment is shown.

[0032] Figures 8A to 8I A method of manufacturing a display device according to an embodiment is shown, and a method of manufacturing a switching transistor for a display device is shown.

[0033] Figure 9 A pixel including a switching transistor according to an embodiment is shown.

[0034] Figure 10 is a graph showing leakage current characteristics of a switching transistor according to an embodiment. DETAILED DESCRIPTION

[0035] Although the disclosure can be modified in various ways and have additional embodiments, the embodiments are shown in the drawings and will be mainly described in the specification. However, the scope of the disclosure is not limited to the embodiments in the drawings and the specification, and should be interpreted as including all changes, equivalents and substitutes included in the spirit and scope of the disclosure.

[0036] For the purpose of describing the disclosed embodiments, some parts that are not related to the description may not be provided, and like reference numerals refer to like elements throughout the specification.

[0037] In the accompanying drawings, the sizes and thicknesses of elements may be exaggerated for better understanding and ease of description. However, the disclosure is not limited to the sizes and thicknesses shown. In the accompanying drawings, the thicknesses of layers, films, panels, regions, and other elements may be exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0038] Furthermore, in the specification, the phrase “in a plan view” refers to a case where an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” refers to a case where a schematic cross-section taken by vertically cutting the object portion is viewed from the side.

[0039] In addition, the term "overlying" or variations thereof means that a first object can be above or below or to the side of a second object, and vice versa. In addition, the term "overlying" can include layers, stacks, facing or variations thereof, extending above, covering or partially covering or any other suitable terms that will be appreciated and understood by those of ordinary skill in the art. The term "facing" and variations thereof mean that a first element can be directly or indirectly opposite to a second element. In the case where a third element is inserted between the first and second elements, the first and second elements can be understood to be indirectly opposite to each other, although still facing each other. When an element is described as "not overlapping" with another element or using similar expressions, this can include elements being spaced apart from each other, offset from each other or separated from each other or any other suitable terms that will be appreciated and understood by those of ordinary skill in the art.

[0040] When a layer, film, zone, substrate or region is referred to as being "on" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region can be directly on the other layer, film, zone, substrate or region, or an intermediate layer, film, zone, substrate or region can be present therebetween. On the contrary, when a layer, film, zone, substrate or region is referred to as being "directly on" another layer, film, zone, substrate or region, there will be no intermediate layer, film, zone, substrate or region therebetween. In addition, when a layer, film, zone, substrate or region is referred to as being "below" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region can be directly below the other layer, film, zone, substrate or region, or an intermediate layer, film, zone, substrate or region can be present therebetween. On the contrary, when a layer, film, zone, substrate or region is referred to as being "directly on" another layer, film, zone, substrate or region, there will be no intermediate layer, film, zone, substrate or region therebetween. Furthermore, "above" or "over" may include positioning above or below an object and does not necessarily imply a direction based on gravity.

[0041] For ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” “on,” etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, in a case where the device shown in the accompanying drawings is flipped, an element positioned “below” or “beneath” another device may be positioned “above” another device. Thus, the exemplary term “below” may include both a position below and a position above. Devices may also be positioned in other orientations, so the spatially relative terms may be interpreted differently depending on the positioning.

[0042] Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element, or “electrically connected” to the other element with one or more intervening elements interposed therebetween. It will also be understood that when the terms “comprises,” “includes,” and / or their variations are used in this specification, they or it may specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0043] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the stated value.

[0044] Although terms such as first and second are used to describe various elements, elements are not limited by such terms. Such terms are only used to distinguish one element from another element. Therefore, the first element mentioned below can also be the second element within the spirit and scope of the disclosure.

[0045] In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined otherwise in the specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0047] Figure 1 The display device 1 according to the embodiment is shown. Figure 1 A light-emitting display device including a light-emitting element is illustrated as an example of the display device 1 , but the display device 1 according to the disclosure is not limited thereto.

[0048] Reference Figure 1 The display device 1 according to the embodiment may include a display area 10 in which pixels PXL are provided, a scan driver 20 driving the pixels PXL, an emission control driver 30 , a data driver 40 , and a timing controller 50 .

[0049] The display area 10 may include pixels PXL connected to scan lines S1 to Sn, emission control lines E1 to En, and data lines D1 to Dm. In the description of the embodiments, "connection" may refer to electrical connection and / or physical connection. For example, the pixels PXL may be electrically connected to the scan lines S1 to Sn, the emission control lines E1 to En, and the data lines D1 to Dm.

[0050] In other embodiments, the emission control lines E1 to En may be omitted. For example, the structure and / or driving method of the pixel PXL may determine whether the emission control lines E1 to En are provided. As an example, according to an embodiment, the pixel PXL may be connected to at least one control line (not shown). In this case, the operation of the pixel PXL may be controlled by a control signal supplied from the control line.

[0051] The pixel PXL may receive scan signals, emission control signals (if applicable), and data signals from scan lines S1 to Sn, emission control lines E1 to En (if applicable), and data lines D1 to Dm. The pixel PXL may receive driving power from a first power source ELVDD and a second power source ELVSS. The pixel PXL may be connected to other power sources (e.g., an initialization power source) depending on the structure of the pixel PXL and / or its driving method.

[0052] When a scan signal is supplied from each of the scan lines S1 to Sn, the pixel PXL described above can receive a data signal from each of the data lines D1 to Dm and emit light having a brightness corresponding to the data signal. Thus, an image corresponding to the data signal of each frame can be displayed in the display area 10.

[0053] Each pixel PXL may include a light-emitting element and a pixel circuit for driving the light-emitting element. The pixel circuit may control the driving current flowing from the first power source ELVDD to the second power source ELVSS in response to a data signal. Therefore, the pixel circuit may include a driving transistor and at least one switching transistor.

[0054] The scan driver 20 may receive a scan drive control signal SCS from the timing controller 50 and supply a scan signal to the scan lines S1 to Sn in response to the scan drive control signal SCS. For example, the scan driver 20 may sequentially supply the scan signal to the scan lines S1 to Sn in response to the scan drive control signal SCS. When the scan signal is supplied to the scan lines S1 to Sn, the pixels PXL connected to the scan lines may be selected by the scan signal.

[0055] According to an embodiment, a scan signal may be used to select pixels PXL in units of horizontal lines. For example, the scan signal may have a gate-on voltage (e.g., a low voltage), and the transistors of each of the pixels PXL connected to the data lines D1 to Dm may be turned on by the gate-on voltage. The scan signal may be supplied to the pixels PXL of the horizontal line corresponding to each horizontal period. During the period in which the scan signal is supplied, the pixels PXL receiving the scan signal may be connected to the data lines D1 to Dm to receive the data signal.

[0056] The emission control driver 30 may receive an emission drive control signal ECS from the timing controller 50 and supply the emission control signal to the emission control lines E1 to En in response to the emission drive control signal ECS. In an example, the emission control driver 30 may sequentially supply the emission control signal to the emission control lines E1 to En in response to the emission drive control signal ECS. The structure and / or driving method of the pixel PXL may determine whether the emission control driver 30 is provided. Therefore, the emission control driver 30 may be omitted.

[0057] The emission control signal can be used to control the emission period (e.g., emission time point and / or emission duration) of the pixel PXL. For example, the emission control signal can have a gate-off voltage (e.g., a high voltage), and at least one switching transistor positioned on the current path of each of the pixels PXL can be turned off by the gate-off voltage. In this case, the pixel PXL receiving the emission control signal can be set to a non-emitting state during the period in which the emission control signal is supplied and can be set to an emitting state during other periods. When a data signal corresponding to a black grayscale is supplied to a certain pixel PXL, the pixel PXL can maintain a non-emitting state in response to the data signal even when an emission control signal having a gate-off voltage is not supplied.

[0058] The data driver 40 may receive a data driving control signal DCS and image data RGB from the timing controller 50 and supply data signals to the data lines D1 to Dm in response to the data driving control signal DCS and the image data RGB. The data signals supplied to the data lines D1 to Dm may be supplied to the pixels PXL selected by the scan signal.

[0059] The timing controller 50 may receive various timing control signals (e.g., vertical / horizontal synchronization signals and a main clock signal) from an external device (e.g., a host processor), and may generate a scan drive control signal SCS, an emission drive control signal ECS, and a data drive control signal DCS in response to the timing control signals. The scan drive control signal SCS, the emission drive control signal ECS, and the data drive control signal DCS may be supplied to the scan driver 20, the emission control driver 30, and the data driver 40, respectively.

[0060] The scan drive control signal SCS may include a first start pulse (e.g., a scan start pulse) and a first clock signal (e.g., at least one scan clock signal). The first start pulse may be used to control the output timing of the first scan signal (e.g., the scan signal supplied to the first scan line S1). The first clock signal may be used to sequentially shift the first start pulse.

[0061] The emission drive control signal ECS may include a second start pulse (e.g., an emission start pulse) and a second clock signal (e.g., at least one emission clock signal). The second start pulse may be used to control the output timing of the first emission control signal (e.g., the emission control signal supplied to the first emission control line E1). The second clock signal may be used to sequentially shift the second start pulse.

[0062] The data driving control signal DCS may include a source sampling pulse, a source sampling clock, and a source output enable signal. The data sampling operation may be controlled by the data driving control signal DCS.

[0063] For example, the timing controller 50 may receive input image data from the outside and may rearrange the input image data to generate image data RGB. The timing controller 50 described above may supply the image data RGB to the data driver 40. The image data RGB supplied to the data driver 40 may be used to generate data signals to be supplied to the pixels PXL.

[0064] Figure 2 and Figure 3 Pixel PXL according to an embodiment is shown. For example, Figure 2 and Figure 3 Shows that can be set in Figure 1Different embodiments of pixels PXL in the display area 10 of the present invention are provided. The pixel PXL can be arranged in the i-th pixel row (e.g., the i-th horizontal line) and the j-th pixel column (e.g., the j-th vertical line) of the display area 10, and can be connected to the i-th scan line Si, the i-th emission control line Ei, and the j-th data line Dj (where i and j are natural numbers). For example, the pixel PXL can be connected to at least one control line. In this example, the pixel PXL can be connected to the i-th first control line CL1i and the i-th second control line CL2i.

[0065] According to an embodiment, the Figure 1 The pixels PXL in the display area 10 may have substantially the same or similar structures. Hereinafter, the "i-th scan line Si," the "i-th emission control line Ei," and the "j-th data line Dj" will be referred to as the "scan line Si," the "emission control line Ei," and the "data line Dj," respectively. The "i-th first control line CL1i" and the "i-th second control line CL2i" will be referred to as the "first control line CL1i" and the "second control line CL2i," respectively.

[0066] Reference Figure 2 According to an embodiment, a pixel PXL may include a light-emitting element EL and a pixel circuit PXC for driving the light-emitting element EL. According to an embodiment, the light-emitting element EL may be connected between the pixel circuit PXC and the second power supply ELVSS, but the position of the light-emitting element EL is not limited thereto. For example, in an embodiment, the light-emitting element EL may be connected between the first power supply ELVDD and the pixel circuit PXC.

[0067] According to an embodiment, the light emitting element EL may be an organic light emitting diode (OLED) including an organic light emitting layer, but is not limited thereto. For example, in an embodiment, the pixel PXL may include a micro light emitting element having a small size ranging from about nanometer level to about micrometer level.

[0068] The light-emitting element EL may be connected between a first power source ELVDD and a second power source ELVSS. For example, the anode electrode of the light-emitting element EL may be connected to the first power source ELVDD through the pixel circuit PXC, and the cathode electrode of the light-emitting element EL may be connected to the second power source ELVSS. When a driving current is supplied from the first transistor T1, the light-emitting element EL generates light having a brightness corresponding to the driving current.

[0069] The first power source ELVDD and the second power source ELVSS may have a potential difference that allows the light-emitting element EL to emit light. For example, the first power source ELVDD may be a high-potential pixel power source, and the second power source ELVSS may be a low-potential pixel power source having a potential lower than the potential of the first power source ELVDD by at least a threshold voltage of the light-emitting element EL.

[0070] The pixel circuit PXC may include a driving transistor, at least one switching transistor, and a storage capacitor Cst. For example, the pixel circuit PXC may include a first transistor T1 as a driving transistor, second to seventh transistors T2 to T7 as switching transistors, and a storage capacitor Cst. At least one of the switching transistors may be configured to transmit a data signal or a voltage of an initialization power supply to a first node N1 to which the gate electrode of the driving transistor is connected.

[0071] It will be understood that the structure of the pixel circuit PXC may be variously changed according to embodiments. For example, the pixel PXL may include a pixel circuit PXC having various structures and / or driving methods.

[0072] It will be understood that the assignment of transistors T1 to T7 as drive transistors or switch transistors is arbitrary. For example, the drive transistor can be any of the second transistor T2 to the seventh transistor T7 and is therefore not limited to the first transistor T1. Furthermore, the number of transistors is not limited to the number shown and can include any number of transistors within the spirit and scope of the disclosure.

[0073] In an embodiment, each of the first to seventh transistors T1 to T7 may be a p-type transistor. However, the disclosure is not limited thereto. For example, in an embodiment, each of the first to seventh transistors T1 to T7 may be an n-type transistor. Alternatively, some of the first to seventh transistors T1 to T7 may be p-type transistors, and the other transistors of the first to seventh transistors T1 to T7 may be n-type transistors.

[0074] The first transistor T1 may be connected or disposed between the first power supply ELVDD and the second power supply ELVSS on a current path of the driving current. In an example, the first transistor T1 may be connected or disposed between the first power supply ELVDD and the light-emitting element EL. For example, a first electrode (e.g., a source electrode) of the first transistor T1 may be connected to the first power supply ELVDD via a fifth transistor T5, and a second electrode (e.g., a drain electrode) of the first transistor T1 may be connected to the anode electrode of the light-emitting element EL via a sixth transistor T6. The gate electrode of the first transistor T1 may be connected to a first node N1.

[0075] The first transistor T1 described above controls the driving current flowing in the light emitting element EL in response to the gate voltage (e.g., the voltage of the first node N1). For example, during the emission period of each frame, the first transistor T1 can control the driving current flowing from the first power source ELVDD through the light emitting element EL to the second power source ELVSS in response to the voltage of the first node N1.

[0076] The second transistor T2 may be connected or disposed between the data line Dj and the first electrode of the first transistor T1. A gate electrode of the second transistor T2 may be connected to the scan line Si.

[0077] When a scan signal having a gate-on voltage is supplied to the scan line Si, the second transistor T2 can be turned on to connect the data line Dj and the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal from the data line Dj can be transmitted to the first electrode of the first transistor T1. During the period in which the second transistor T2 is turned on by the scan signal, the third transistor T3 can also be turned on by the scan signal, and the first transistor T1 can be turned on in the form of a diode connection through the third transistor T3. Therefore, the data signal from the data line Dj can be transmitted to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3. The storage capacitor Cst can be charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0078] The third transistor T3 may be connected or disposed between the first node N1 and the second electrode of the first transistor T1. The gate electrode of the third transistor T3 may be connected or disposed to the scan line Si. When a scan signal having a gate-on voltage is supplied to the scan line Si, the third transistor T3 may be turned on to connect the first node N1 and the second electrode of the first transistor T1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0079] The fourth transistor T4 may be connected or provided between the first node N1 and the initialization power supply Vint. A gate electrode of the fourth transistor T4 may be connected to the first control line CL1i. According to an embodiment, the first control line CL1i may be an initialization control line for initializing the pixels PXL of the i-th horizontal line, and may receive an initialization control signal having a gate-on voltage during an initialization period before a scan signal having a gate-on voltage is supplied to each scan line Si.

[0080] In an embodiment, the first control line CL1i may be any of the previous scan lines for selecting the pixels PXL of the previous horizontal line, for example, the i-1th scan line Si-1 for selecting the pixels PXL of the immediately previous horizontal line. In this case, the initialization control signal supplied to the first control line CL1i may be the i-1th scan signal supplied to the i-1th scan line Si-1. In an embodiment, the first control line CL1i may be a control line formed separately from the scan lines S1 to Sn of the pixels PXL.

[0081] When a first control signal having a gate-on voltage is supplied to the first control line CL1i, the fourth transistor T4 may be turned on. When the fourth transistor T4 is turned on, the voltage of the initialization power supply Vint may be transmitted to the first node N1, and thus the voltage of the first node N1 may be initialized based on the voltage of the initialization power supply Vint.

[0082] The voltage of the initialization power supply Vint can be set to a voltage that is less than or equal to the voltage of the data signal. For example, the voltage of the initialization power supply Vint can be set to be less than or equal to the lowest voltage of the data signal. When the voltage of the first node N1 is initialized based on the voltage of the initialization power supply Vint before the data signal of the current frame is supplied to each pixel PXL, the first transistor T1 can be connected as a forward diode during the scan period of each horizontal line (for example, the period in which the scan signal is supplied to each scan line Si), regardless of the data signal of the previous frame. Therefore, regardless of the data signal of the previous frame, the data signal of the current frame can be stably transmitted to the first node N1.

[0083] The fifth transistor T5 may be connected or provided between the first power source ELVDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the emission control line Ei, and turned on otherwise.

[0084] The sixth transistor T6 may be connected or provided between the first transistor T1 and the light emitting element EL. The gate electrode of the sixth transistor T6 may be connected to the emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the emission control line Ei, and may be turned on otherwise.

[0085] For example, the fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on or off in response to the emission control signal to control the emission period of the pixel PXL. When the fifth transistor T5 and the sixth transistor T6 are turned on, a current path through which the drive current flows can be formed in the pixel PXL. Therefore, the pixel PXL can emit light with a brightness corresponding to the voltage of the first node N1. Conversely, when the fifth transistor T5 and the sixth transistor T6 are turned off, the current path is blocked, and therefore, the pixel PXL does not emit light.

[0086] According to an embodiment, the emission control signal may be supplied as a signal having a gate-off voltage to turn off the fifth transistor T5 and the sixth transistor T6 during the initialization period and the data programming period (e.g., the scan period) of the pixel PXL. In an example, during a period in which each of the scan signal, the first control signal, and the second control signal has a gate-on voltage, an emission control signal having a gate-off voltage may be supplied to overlap with the scan signal, the first control signal, and the second control signal. After the voltage of each of the scan signal, the first control signal, and the second control signal changes to the gate-off voltage, the voltage of the emission control signal may change to the gate-on voltage, and thus, the emission period of each frame may begin. Therefore, the data signal may be stably stored in the pixel PXL prior to the emission period of each frame.

[0087] The seventh transistor T7 may be connected or provided between an initialization power supply Vint and the anode electrode of the light-emitting element EL. The gate electrode of the seventh transistor T7 may be connected to a second control line CL2i. According to an embodiment, the second control line CL2i may be a bypass control line for initializing a voltage charged in an organic capacitor (e.g., a parasitic capacitor formed due to the structure of the light-emitting element EL) formed in each of the light-emitting elements EL in the pixels PXL located in the i-th horizontal line. The second control line CL2i may receive a bypass control signal having a gate-on voltage before each emission period.

[0088] In an embodiment, the second control line CL2i may be any one of the subsequent scan lines for selecting the pixels PXL of the subsequent horizontal line. For example, the second control line CL2i may be the i+1th scan line Si+1 for selecting the pixels PXL of the i+1th horizontal line, but is not limited thereto. For example, in an embodiment, the second control line CL2i may be the current scan line (e.g., scan line Si) of each pixel PXL or may be a control line formed separately from the scan lines S1 to Sn of the pixels PXL.

[0089] Before the emission period of each frame, when the second control signal having a gate-on voltage is supplied to the second control line CL2i, the seventh transistor T7 can be turned on to supply the voltage of the initialization power supply Vint to the anode electrode of the light emitting element EL. Therefore, the pixel PXL can exhibit more uniform brightness characteristics in response to each data signal.

[0090] The storage capacitor Cst may be connected to the first power source ELVDD and the first node N1. The storage capacitor Cst described above may be charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0091] As in the embodiments described above, each pixel PXL may include transistors including a driving transistor (e.g., a first transistor T1) and at least one switching transistor (e.g., at least one of the second to seventh transistors T2 to T7). In an embodiment, the transistors may be formed as transistors having similar structures, sizes, and / or types. In an embodiment, at least one of the transistors may be formed as a transistor having a structure, size, and / or type that may be different from the structure, size, and / or type of the remaining transistors.

[0092] For example, to ensure an operating range within a wider voltage range, the driving transistor may have a relatively long channel region. In an example, the driving transistor may be formed as a long-channel transistor. In order to effectively utilize the limited pixel area while ensuring faster operating characteristics, each switching transistor may have a channel region that is relatively shorter than the channel region of the driving transistor. Each switching transistor may be formed as a short-channel transistor. However, according to embodiments, when the channel region of the switching transistor is shortened, the leakage current occurring in the switching transistor increases, thereby causing the brightness of the pixel PXL to vary.

[0093] Reference Figure 3 In order to reduce leakage current, at least one switching transistor may include transistors connected in series. For example, each of the third transistor T3 and the fourth transistor T4, which are capable of changing the voltage of the first node N1 when leakage current occurs in the off state, may be formed as a transistor connected in series. For example, each of the third transistor T3 and the fourth transistor T4 may be formed as a transistor having a dual structure including two transistors connected in series.

[0094] As an example, the third transistor T3 may include two transistors, such as a 3_1 transistor T3_1 and a 3_2 transistor T3_2 connected in series between the first node N1 and the second electrode of the first transistor T1. The gate electrodes of the 3_1 transistor T3_1 and the 3_2 transistor T3_2 may be commonly connected to the scan line Si. Therefore, the 3_1 transistor T3_1 and the 3_2 transistor T3_2 may be simultaneously turned on or off in response to a scan signal.

[0095] Similarly, the fourth transistor T4 may include two transistors, such as a 4_1th transistor T4_1 and a 4_2th transistor T4_2, connected in series between the first node N1 and the initialization power supply Vint. Gate electrodes of the 4_1th transistor T4_1 and the 4_2nd transistor T4_2 may be commonly connected to the first control line CL1i. Therefore, the 4_1th transistor T4_1 and the 4_2nd transistor T4_2 may be simultaneously turned on or off in response to a first control signal (e.g., a previous scan signal).

[0096] When the third transistor T3 and the fourth transistor T4 are configured as a multi-transistor having at least a dual structure, leakage current in each of the third transistor T3 and the fourth transistor T4 can be reduced or prevented. Therefore, leakage current through the third transistor T3 and the fourth transistor T4, which are in an off state, during the emission period of each frame can be reduced or prevented, thereby stably maintaining the voltage of the first node N1. Therefore, the grayscale representation of the pixel PXL can be improved, and the image quality of the display device 1 can be improved.

[0097] Figure 3 An embodiment in which each of the third transistor T3 and the fourth transistor T4 is configured as a transistor having a dual structure is shown, but the disclosure is not limited thereto. For example, in an embodiment, among the third transistor T3 and the fourth transistor T4, only one transistor (e.g., the third transistor T3) can be formed as a transistor having a multiple structure, and the other transistor (e.g., the fourth transistor T4) can be formed as a transistor having a single structure. In an embodiment, switching transistors other than the third transistor T3 and the fourth transistor T4, for example, at least one transistor (e.g., the second transistor T2 and at least one of the fifth transistor T5 to the seventh transistor T7) can also be formed as a transistor having a multiple structure including transistors connected in series.

[0098] In the pixel PXL and the display device 1 including the pixel PXL according to the embodiment described above, the change in the gate voltage of the first transistor T1 (e.g., the voltage of the first node N1) caused by the leakage current can be reduced or lowered. Therefore, the pixel PXL can more accurately represent the grayscale corresponding to each data signal during each emission period.

[0099] It will be understood that in the disclosure, the structure of the pixel PXL is not limited to Figure 2 and Figure 3 For example, the pixel PXL may include a pixel circuit PXC having various structures and / or driving methods within the spirit and scope of the disclosure.

[0100] exist Figure 2 and Figure 3 In the embodiment of the present invention, each transistor may be shown as a p-type transistor, but the disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be an n-type transistor. In this case, the gate turn-on voltage for turning on the n-type transistor may be a high voltage.

[0101] The voltage of the data signal may be determined according to the type of the first transistor T1. For example, when the first transistor T1 is a p-type transistor, as the grayscale to be represented becomes higher, a data signal with a lower voltage may be supplied to each pixel PXL. When the first transistor T1 is an n-type transistor, as the grayscale to be represented becomes higher, a data signal with a higher voltage may be supplied to each pixel PXL.

[0102] For example, in the disclosure, the types of transistors constituting the pixel PXL and the voltage levels of various control signals (e.g., scan signals, data signals, first control signals, second control signals and / or emission control signals) used to control the transistors can be variously changed according to embodiments.

[0103] Figure 4 and Figure 5 1 shows a switching transistor Ts according to an embodiment. For example, Figure 4 shows a schematic cross-sectional structure of a switching transistor Ts, Figure 5 An equivalent circuit diagram of the switching transistor Ts is shown.

[0104] according to Figure 4 and Figure 5 The switching transistor Ts of the embodiment may be arranged according to Figures 1 to 3 For example, the switching transistor Ts may be any switching transistor in the pixel PXL according to the embodiment of the present invention. Figure 3 The third transistor T3 of the embodiment has a dual structure.

[0105] Reference Figures 3 to 5 According to an embodiment, the switching transistor Ts may include: an active layer pattern 120, which may be provided on one surface of the base layer 100 on which the buffer layer 110 may be formed; a gate electrode 140, which overlaps a region of the active layer pattern 120, with a first insulating film 130 interposed between the active layer pattern 120 and the gate electrode 140; a first electrode 160 and a second electrode 170, which are spaced apart from the active layer pattern 120 and with the first insulating film 130 and the second insulating film 150 interposed between the first electrode 160 and the second electrode 170 and the active layer pattern 120, the first electrode 160 and the second electrode 170 being connected to different regions of the active layer pattern 120.

[0106] According to an embodiment, the switch transistor Ts may include a first switch transistor Ts_1 and a second switch transistor Ts_2 connected in series with each other. In an example, the first switch transistor Ts_1 and the second switch transistor Ts_2 may be Figure 3 The 3_1st transistor T3_1 and the 3_2nd transistor T3_2 are shown in FIG.

[0107] For example, the switch transistor Ts may include a channel region. In an example, the switch transistor Ts may include a first channel region 120a1 forming a channel of the first switch transistor Ts_1 and a second channel region 120a2 forming a channel of the second switch transistor Ts_2. A conductive region may be provided on each of opposite sides of each of the first channel region 120a1 and the second channel region 120a2.

[0108] For example, the first conductive region 120b1 and the third conductive region 120b3 can be disposed on opposite sides of the first channel region 120a1. One of the first conductive region 120b1 and the third conductive region 120b3 can be the source region of the first switching transistor Ts_1, and the other of the first conductive region 120b1 and the third conductive region 120b3 can be the drain region of the first switching transistor Ts_1. In this example, when the first conductive region 120b1 is the source region of the first switching transistor Ts_1, the third conductive region 120b3 can be the drain region of the first switching transistor Ts_1. Conversely, when the first conductive region 120b1 is the drain region of the first switching transistor Ts_1, the third conductive region 120b3 can be the source region of the first switching transistor Ts_1. This can vary depending on the carrier type (e.g., n-type or p-type) and current direction of the first switching transistor Ts_1.

[0109] Similarly, the second conductive region 120b2 and the third conductive region 120b3 can be disposed on opposite sides of the second channel region 120a2. One of the second conductive region 120b2 and the third conductive region 120b3 can be the source region of the second switching transistor Ts_2, and the other of the second conductive region 120b2 and the third conductive region 120b3 can be the drain region of the second switching transistor Ts_2. In an example, when the second conductive region 120b2 is the drain region of the second switching transistor Ts_2, the third conductive region 120b3 can be the source region of the second switching transistor Ts_2. Conversely, when the second conductive region 120b2 is the source region of the second switching transistor Ts_2, the third conductive region 120b3 can be the drain region of the second switching transistor Ts_2. This can vary depending on the carrier type (e.g., n-type or p-type) and current direction of the second switching transistor Ts_2.

[0110] In an embodiment, the first switch transistor Ts_1 and the second switch transistor Ts_2 may share any conductive region. For example, the first switch transistor Ts_1 and the second switch transistor Ts_2 may share the third conductive region 120b3. However, the disclosure is not limited thereto. For example, in an embodiment, the conductive regions of the first switch transistor Ts_1 and the second switch transistor Ts_2 may be formed in patterns separated from each other, and any conductive regions of the first switch transistor Ts_1 and the second switch transistor Ts_2 (for example, the source region of the first switch transistor Ts_1 and the drain region of the second switch transistor Ts_2) may be electrically connected to each other.

[0111] According to an exemplary embodiment, the switching transistor Ts may include at least one wide bandgap region. In an example, the switching transistor Ts may include a first wide bandgap region 120c1 disposed on one side of the first channel region 120a1 and a second wide bandgap region 120c2 disposed on one side of the second channel region 120a2.

[0112] According to an embodiment, the first wide bandgap region 120c1 and the second wide bandgap region 120c2 may be positioned between the first channel region 120a1 and the second channel region 120a2. For example, the first wide bandgap region 120c1 may be disposed between the first channel region 120a1 and the third conductive region 120b3, and the second wide bandgap region 120c2 may be disposed between the second channel region 120a2 and the third conductive region 120b3.

[0113] The switching transistor Ts according to the embodiments described above may include at least one channel region, at least two conductive regions respectively disposed at opposite sides of the channel region, and at least one wide bandgap region disposed between the channel region and any one of the conductive regions. For example, when the switching transistor Ts has one or more dual structures or multiple structures, the switching transistor Ts may include at least one additional channel region, at least one conductive region, and at least one wide bandgap region.

[0114] For example, the switching transistor Ts may include a first channel region 120a1, a first conductive region 120b1 and a third conductive region 120b3 disposed on opposite sides of the first channel region 120a1, and a first wide bandgap region 120c1 disposed between the first channel region 120a1 and the third conductive region 120b3. For example, the switching transistor Ts may include a second channel region 120a2 disposed between the first channel region 120a1 and the second conductive region 120b2, a third conductive region 120b3 disposed between the first channel region 120a1 and the second channel region 120a2, and a second wide bandgap region 120c2 disposed between the second channel region 120a2 and the third conductive region 120b3. In this case, the first wide bandgap region 120c1 may be disposed between the first channel region 120a1 and the third conductive region 120b3.

[0115] For example, the first wide band gap region 120c1 and the second wide band gap region 120c2 may be respectively disposed at opposite sides of the third conductive region 120b3. For example, the first wide band gap region 120c1 may be disposed between the first channel region 120a1 and the third conductive region 120b3 to directly contact the first channel region 120a1 and the third conductive region 120b3. The second wide band gap region 120c2 may be disposed between the second channel region 120a2 and the third conductive region 120b3 to directly contact the second channel region 120a2 and the third conductive region 120b3. In other words, the active layer pattern 120 may be disposed in a manner such as, for example, Figure 4 The schematic cross-sectional view shown in FIG includes a conductive region, a channel region, a wide bandgap region, a conductive region, a wide bandgap region, a channel region, and a conductive region in a symmetrical order.

[0116] In this example, as described above, the active layer pattern 120 of the switching transistor Ts may include a first conductive region 120b1, a first channel region 120a1, a first wide bandgap region 120c1, a third conductive region 120b3, a second wide bandgap region 120c2, a second channel region 120a2, and a second conductive region 120b2, sequentially disposed along one direction on the buffer layer 110. Here, the first conductive region 120b1, the first channel region 120a1, the first wide bandgap region 120c1, and the third conductive region 120b3 may constitute the active layer pattern of the first switching transistor Ts_1. The second conductive region 120b2, the second channel region 120a2, the second wide bandgap region 120c2, and the third conductive region 120b3 may constitute the active layer pattern of the second switching transistor Ts_2. The active layer patterns of the first and second switching transistors Ts_1 and Ts_2 may share the third conductive region 120b3 and may be integrally formed with each other.

[0117] The active layer pattern 120 may have a relatively wide bandgap in the first wide bandgap region 120c1 and the second wide bandgap region 120c2, and may have a relatively narrow bandgap in the remaining region. For example, each of the first wide bandgap region 120c1 and the second wide bandgap region 120c2 may be an amorphous silicon region including amorphous silicon (a-Si). Each of the first and second channel regions 120a1 and 120a2 and the first to third conductive regions 120b1 to 120b3 may be a polycrystalline silicon region including polycrystalline silicon (Poly-Si).

[0118] When the switching transistor Ts is a transistor having a dual structure, the switching transistor Ts may include a gate electrode 140 having a dual structure. For example, the gate electrode 140 may include a first gate electrode 140a1 overlapping the first channel region 120a1 and a second gate electrode 140a2 overlapping the second channel region 120a2. Similarly, when the switching transistor Ts is a transistor having a multi-structure including three or more transistors, the switching transistor Ts may include three or more channel regions and three or more gate electrodes overlapping the channel regions.

[0119] In an embodiment, the gate electrode 140 may include multiple layers. For example, the first gate electrode 140a1 may include multiple layers including a lower electrode 140a1_1 disposed between the first insulating film 130 and the second insulating film 150, and an upper electrode 140a1_2 connected to the lower electrode 140a1_1 and disposed on the second insulating film 150. Similarly, the second gate electrode 140a2 may include multiple layers including a lower electrode 140a2_1 disposed between the first insulating film 130 and the second insulating film 150, and an upper electrode 140a2_2 connected to the lower electrode 140a2_1 and disposed on the second insulating film 150. When the gate electrode 140 includes multiple layers, the resistance of the gate electrode 140 and the gate control line GC (e.g., the scan line Si) connected to the gate electrode 140 can be reduced, thereby reducing or preventing signal delay.

[0120] However, the disclosure is not limited thereto. For example, in an embodiment, one of the first gate electrode 140a1 and the second gate electrode 140a2 may include multiple layers, and the other of the first gate electrode 140a1 and the second gate electrode 140a2 may include a single layer. In an embodiment, each of the first gate electrode 140a1 and the second gate electrode 140a2 may include a single layer, and the first gate electrode 140a1 and the second gate electrode 140a2 may be provided in the same layer or in different layers. In an example, each of the first gate electrode 140a1 and the second gate electrode 140a2 may also include lower electrodes 140a1_1 and 140a2_1 located between the first insulating film 130 and the second insulating film 150, or may only include the lower electrodes 140a1_1 and 140a2_1 located between the first insulating film 130 and the second insulating film 150.

[0121] The first gate electrode 140a1 and the second gate electrode 140a2 are electrically connected to each other. For example, the first gate electrode 140a1 and the second gate electrode 140a2 can be connected to the same gate control line GC. In the example, when the switching transistor Ts is Figure 3 When the third transistor T3 is configured, the first gate electrode 140a1 and the second gate electrode 140a2 may be commonly connected to the scan line Si.

[0122] The first electrode 160 and the second electrode 170 may be disposed on the second insulating film 150 to be connected to different regions of the active layer pattern 120. For example, the first electrode 160 may be connected to the first conductive region 120b1 via a first contact hole passing through the first insulating film 130 and the second insulating film 150, and the second electrode 170 may be connected to the second conductive region 120b2 via a second contact hole passing through the first insulating film 130 and the second insulating film 150.

[0123] According to an embodiment, the first electrode 160 may be one of the source electrode and the drain electrode of the switching transistor Ts, and the second electrode 170 may be the other of the source electrode and the drain electrode of the switching transistor Ts. For example, when the first electrode 160 is a source electrode, the second electrode 170 may be a drain electrode. Conversely, when the first electrode 160 is a drain electrode, the second electrode 170 may be a source electrode.

[0124] On the other hand, the positions of the first electrode 160 and the second electrode 170 in the disclosure are not particularly limited and may be variously changed according to the embodiment. As an example, according to the embodiment, at least one of the first electrode 160 and the second electrode 170 may be omitted.

[0125] For example, when the switching transistor Ts is directly connected to another circuit element (e.g., at least one other transistor and / or capacitor) through the first conductive region 120b1, the first electrode 160 can be omitted. The first conductive region 120b1 can be the source electrode or the drain electrode of the switching transistor Ts. Similarly, when the switching transistor Ts is directly connected to another circuit element through the second conductive region 120b2, the second electrode 170 can be omitted. The second conductive region 120b2 can be the source electrode or the drain electrode of the switching transistor Ts. Alternatively, as another example, the first conductive region 120b1 and / or the second conductive region 120b2 can be considered as the source electrode and / or the drain electrode of the switching transistor Ts, and the first electrode 160 and / or the second electrode 170 can be considered as wiring connected to one electrode of the switching transistor Ts or an electrode of another circuit element.

[0126] The switching transistor Ts according to the embodiment described above can exhibit improved leakage current characteristics in both directions. For example, in both the first direction DR1 and the second direction DR2, the first wide bandgap region 120c1 or the second wide bandgap region 120c2 can be positioned between the channel region and the drain region of either the first switching transistor Ts_1 or the second switching transistor Ts_2. Therefore, leakage current can be low in both directions of the switching transistor Ts.

[0127] Due to the characteristics of transistors, leakage current may occur between the channel region and the drain region. Therefore, when a region with a wide bandgap (e.g., the first wide bandgap region 120c1 and / or the second wide bandgap region 120c2) is provided between the channel region and the drain region of the first switching transistor Ts_1 and / or the second switching transistor Ts_2, leakage current that may occur in the switching transistor Ts can be effectively reduced or prevented.

[0128] For example, when each of the first switching transistor Ts_1 and the second switching transistor Ts_2 is a p-type transistor, given that Figure 5 Regarding the first leakage current Ioff_1 in the first direction DR1, the first conductive region 120b1 and the third conductive region 120b3 may be the source region and the drain region of the first switching transistor Ts_1, respectively. Therefore, the first wide bandgap region 120c1 may be positioned at the drain-active junction between the first channel region 120a1, which serves as the channel region of the first switching transistor Ts_1, and the third conductive region 120b3, which serves as the drain region of the first switching transistor Ts_1. When the first wide bandgap region 120c1 widens the bandgap between the channel region and the drain region of the first switching transistor Ts_1, leakage current of the first switching transistor Ts_1 may be effectively reduced or prevented.

[0129] The leakage current of the transistor can be mainly manifested as two types of leakage current (for example, thermal current I G and gate-induced drain leakage current I GIDL ). Figure 10 The thermal current I shown in G and gate-induced drain leakage current I GIDL Each of the band gap functions can be a band gap function with the band gap as a variable. As the band gap increases, the thermal current I G and gate-induced drain leakage current I GIDL Therefore, the first leakage current Ioff_1 in the first direction DR1 can be suppressed by the first wide bandgap region 120c1 in the first switching transistor Ts_1.

[0130] On the other hand, given that Figure 5 The second conductive region 120b2 and the third conductive region 120b3 may be the source region and the drain region of the second switch transistor Ts_2, respectively. Therefore, the second wide bandgap region 120c2 may be located at the junction between the second channel region 120a2, which may serve as the channel region of the second switch transistor Ts_2, and the third conductive region 120b3, which may serve as the drain region of the second switch transistor Ts_2.

[0131] Therefore, when the bandgap is widened between the channel region and the drain region of the second switch transistor Ts_2 by the second wide bandgap region 120c2, leakage current of the second switch transistor Ts_2 can be effectively reduced or prevented. For example, the second leakage current Ioff_2 in the second direction DR2 can be suppressed by the second wide bandgap region 120c2 in the second switch transistor Ts_2.

[0132] As described above, in the disclosed embodiments, at least one switching transistor Ts may include at least one dual structure including transistors (e.g., a first switching transistor Ts_1 and a second switching transistor Ts_2). A junction bandgap widening (JBW) structure may be formed by providing a wide bandgap region (e.g., a first wide bandgap region 120c1 and a second wide bandgap region 120c2) between the conductive region (e.g., the third conductive region 120b3) and the channel region (e.g., the first channel region 120a1 and the second channel region 120a2) between the transistors. Therefore, even if the wide bandgap region is formed on only one side of each of the channel regions, two bidirectional leakage currents can be effectively reduced or prevented. Even when the active layer pattern 120 is formed to be relatively short, the effect of reducing the leakage current caused by each wide bandgap region can be achieved.

[0133] Therefore, the limited pixel area can be effectively utilized, and the leakage current characteristics of the pixel PXL can be improved. Therefore, even in a high-resolution display device 1 with a relatively narrow pixel area, the switching transistor Ts according to the disclosed embodiment can be easily formed, thereby achieving the effect of reducing the leakage current of the pixel PXL.

[0134] According to the embodiment described above, at least one switching transistor Ts constituting the pixel PXL can be formed to have at least a dual structure, thereby fundamentally reducing leakage current. A wide bandgap region can be formed between the channel region and the drain region of at least one switching transistor Ts (e.g., the first switching transistor Ts_1 or the second switching transistor Ts_2) constituting the switching structure having the multi-structure in each of the first direction DR1 and the second direction DR2, thereby more effectively reducing or preventing leakage current.

[0135] For example, when Figure 3 The third transistor T3 is Figure 4 and Figure 5 When the switching transistor Ts of the embodiment is implemented, the leakage current of the third transistor T3 in the off state can be significantly reduced. In the embodiment, the third transistor T3 may not be directly connected to the power supply, etc., and may be arranged closer to the center area of ​​the pixel area than the other switching transistors of the pixel PXL. Therefore, there is a smaller possibility of performing aging on the third transistor T3 than other switching transistors. In this case, there is also a possibility that the leakage current characteristics of the third transistor T3 will deteriorate. However, when the third transistor T3 is formed to include Figure 4 and Figure 5 When the wide bandgap region shown in FIG. 3 is selected, the leakage current characteristic of the third transistor T3 can be improved. Therefore, the grayscale representation of the pixel PXL can be improved by stabilizing the voltage of the first node N1.

[0136] according to Figure 4 and Figure 5 The structure of the switching transistor Ts of the embodiment can be applied not only to the third transistor T3. For example, Figure 3 The fourth transistor T4 can be connected with Figure 4 and Figure 5 In the example, the fourth transistor T4 may include a transistor T5 according to Figure 4 and Figure 5The first channel region 120a1, the first conductive region 120b1, the second conductive region 120b2 and the first wide bandgap region 120c1 of the embodiment. For example, when the fourth transistor T4 is a transistor having one or more dual structures or multiple structures, the fourth transistor T4 may include the second channel region 120a2, the third conductive region 120b3 and the second wide bandgap region 120c2. In the example, Figure 4 and Figure 5 The first switching transistor Ts_1 and the second switching transistor Ts_2 may be Figure 3 Therefore, the leakage current of the fourth transistor T4 can be significantly reduced, thereby stabilizing the voltage of the first node N1 and improving the grayscale representation of the pixel PXL.

[0137] For example, in the disclosed embodiment, according to Figure 4 and Figure 5 The structure of the switching transistor Ts of the embodiment can be applied to at least one switching transistor constituting the pixel PXL within the spirit and scope of the invention. Figure 2 and Figure 3 In an embodiment, when each pixel PXL includes switching transistors (such as the second to seventh transistors T2 to T7), the wide bandgap region may be formed in only some or a predetermined number of the switching transistors that may be susceptible to leakage current or in which reduction of leakage current is more important or prominent among any given transistors. In an example, Figure 3 The third transistor T3 and / or the fourth transistor T4 may be implemented as Figure 4 and Figure 5 Optionally, according to an embodiment, the second transistor T2 may be formed to have a dual structure and Figure 4 and Figure 5 The structure of the switching transistor Ts of the embodiment is the same as the structure.

[0138] According to the above-described embodiment, the leakage current of the pixel PXL can be effectively reduced, thereby improving the grayscale expression of the pixel PXL and the image quality of the display device 1 including the pixel PXL.

[0139] Figure 6 and Figure 7 1 shows a switching transistor Ts' according to an embodiment. For example, Figure 6 shows a schematic cross-sectional structure of a switching transistor Ts', Figure 7 An equivalent circuit diagram of the switching transistor Ts' is shown.

[0140] According to the embodiment, according to Figure 6 and Figure 7 The switching transistor Ts' of the embodiment may be arranged according to Figures 1 to 3 Any switching transistor in the pixel PXL of the embodiment, for example, according to Figure 2 The second transistor T2 to the fourth transistor T4 of the embodiment have a single structure and according to Figure 3 In the embodiment of the present invention, at least one switching transistor is included in the second transistor T2 having a single structure. For ease of explanation, when Figure 2 When the third transistor T3 has the structure of the switching transistor Ts' according to the embodiment, the structure of the switching transistor Ts' is Figure 6 and Figure 7 As shown in Figure 6 and Figure 7 In the embodiment, Figure 4 and Figure 5 The same or similar components as those of the embodiments are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted because they have been previously described.

[0141] Reference Figure 6 and Figure 7 According to an embodiment, the switching transistor Ts' may include an active layer pattern 120' including a single channel region, for example, a first channel region 120a1. The active layer pattern 120' may include: a first channel region 120a1; a first conductive region 120b1 and a second conductive region 120b2, which may be disposed on opposite sides of the first channel region 120a1; a first wide bandgap region 120c1, which may be disposed between the first channel region 120a1 and the second conductive region 120b2; and a second wide bandgap region 120c2', which may be disposed between the first channel region 120a1 and the first conductive region 120b1. According to an embodiment, the first wide bandgap region 120c1 and the second wide bandgap region 120c2' may be disposed on opposite sides of the first channel region 120a1 to contact different regions of the first channel region 120a1.

[0142] The first wide bandgap region 120c1 and the second wide bandgap region 120c2' may be made of a material having a wider bandgap than the remaining region of the active layer pattern 120'. For example, each of the first wide bandgap region 120c1 and the second wide bandgap region 120c2' may be an amorphous silicon region including amorphous silicon. The first channel region 120a1 and the first conductive region 120b1 and the second conductive region 120b2 may each be a polycrystalline silicon region including polycrystalline silicon. Therefore, the bandgap of the first wide bandgap region 120c1 and the second wide bandgap region 120c2' may be larger than the bandgap of the first channel region 120a1 and the first conductive region 120b1 and the second conductive region 120b2. In an example, the first wide bandgap region 120c1 and the second wide bandgap region 120c2′ may have an energy bandgap of approximately 1.7 eV, and the first channel region 120a1 and the first and second conductive regions 120b1 and 120b2 may have an energy bandgap of approximately 1.12 eV. The first wide bandgap region 120c1 and the second wide bandgap region 120c2′ may reduce or prevent leakage current of the switching transistor Ts′.

[0143] As an example, the switching transistor Ts' may include a single gate electrode 140' overlapping the first channel region 120a1. The gate electrode 140' may include a single layer or multiple layers. In an example, the gate electrode 140' may have a multilayer structure including a lower electrode 140_1 located between the first insulating film 130 and the second insulating film 150 and an upper electrode 140_2 disposed on the second insulating film 150 and connected to the lower electrode 140_1.

[0144] As described above, the switching transistor Ts′ according to the embodiment may include the first wide bandgap region 120c1 and the second wide bandgap region 120c2′ between the first conductive region 120b1 and the second conductive region 120b2 and the first channel region 120a1. Therefore, the switching transistor Ts′ may exhibit improved leakage current characteristics (e.g., low leakage current characteristics) in both directions.

[0145] Given that Figure 7 The first conductive region 120b1 and the second conductive region 120b2 may be the source region and the drain region of the switch transistor Ts', respectively.

[0146] On the other hand, considering the second leakage current Ioff_2 in the second direction DR2, the second conductive region 120b2 and the first conductive region 120b1 may be the source region and the drain region of the switching transistor Ts', respectively. Therefore, the second wide bandgap region 120c2' may reduce or prevent the second leakage current Ioff_2 in the second direction DR2.

[0147] According to an embodiment, the switching transistor Ts' according to an embodiment is Figure 6 and Figure 7 Shown in the following Figure 2 However, the structure of the switch transistor Ts' according to the embodiment described above may not only be applicable to the third transistor T3. Figure 2 The fourth transistor T4 can be connected with Figure 6 and Figure 7 The switching transistor Ts' of the embodiment is similar.

[0148] Optionally, according to Figure 2 and Figure 3 The second transistor T2 of the embodiment can be connected with Figure 6 and Figure 7 For example, the second transistor T2 may include a transistor Ts′ according to Figure 6 and Figure 7 The first channel region 120a1, the first conductive region 120b1, the second conductive region 120b2, the first wide bandgap region 120c1, and the second wide bandgap region 120c2' of the embodiment can thus stabilize the operation of the pixel PXL and improve the grayscale representation of the pixel PXL.

[0149] Figures 8A to 8I A method for manufacturing a display device according to an embodiment is shown. In this example, Figures 8A to 8I A method for manufacturing a switching transistor for a display device is shown. As an example, Figures 8A to 8I Shows the manufacturing method Figure 4 and Figure 5 However, the method of manufacturing a switching transistor is not limited thereto and may be applied to, for example, Figure 6 and Figure 7 For example, in terms of the size and / or structure of the active layer pattern 120', according to Figure 6 and Figure 7 The switching transistor Ts' of the embodiment may have Figure 4 and Figure 5 The structure of the switching transistor Ts of the embodiment is partially different or slightly different. The process of manufacturing the switching transistor Ts' can be the same as that of manufacturing the switching transistor Ts' according to Figure 4and Figure 5 The process of the switching transistor Ts in the embodiment is basically the same or similar.

[0150] Reference Figures 4 to 8A After forming the buffer layer 110 on the base layer 100, a semiconductor pattern SCP may be formed in each transistor region (e.g., a switching transistor region where the switching transistor Ts is to be disposed) on the buffer layer 110. In other embodiments, the buffer layer 110 may be omitted, in which case the semiconductor pattern SCP may be directly formed on one surface of the base layer 100.

[0151] The base layer 100 may be a base member for forming a panel of the display device 1. According to an embodiment, the base layer 100 may be a rigid substrate or a flexible substrate or film, and the material and physical properties of the base layer 100 are not specifically limited. In an example, the base layer 100 may be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one insulating film, and the material and / or physical properties of the base layer 100 are not specifically limited. As an example, the base layer 100 may be transparent, but is not limited thereto. In an example, the base layer 100 may be made of a transparent, translucent, opaque, or reflective base member or material.

[0152] A buffer layer 110 may be formed on one surface of the base layer 100. Since the buffer layer 110 is formed, impurities may be prevented from diffusing into circuit elements to be formed on the buffer layer 110. The buffer layer 110 may include a single layer and may include at least two layers. When the buffer layer 110 is provided as a multilayer, the layers may be made of the same material or different materials. In an example, the buffer layer 110 may be formed to include a multilayer including a silicon nitride layer (SiN x ) and silicon oxide layer (SiO x ).

[0153] The semiconductor pattern SCP can be used to form an active layer pattern of each transistor (e.g., the active layer pattern 120 of the first transistor T1). The semiconductor pattern SCP can be formed on one surface of the base layer 100 on which the buffer layer 110 can be formed. For example, a semiconductor material can be deposited on the buffer layer 110 to form a semiconductor material film, and then the semiconductor material layer can be patterned to form each semiconductor pattern SCP.

[0154] According to an embodiment, the semiconductor patterns SCP may be made of amorphous silicon (a-Si). For example, an amorphous silicon film may be formed on the buffer layer 110 and then patterned to form each semiconductor pattern SCP.

[0155] Reference Figures 4 to 8B, a mask 200 may be provided on an area of ​​the semiconductor pattern SCP. The mask 200 may be made of a material for forming the first insulating film 130 to be formed in a subsequent process (e.g., a gate insulating film material), a photoresist, or various hard mask materials, and the material and / or physical properties of the mask 200 are not particularly limited.

[0156] According to embodiments, mask 200 may include a mask pattern for covering at least two regions of semiconductor pattern SCP. For example, mask 200 may include first mask 200_1 and second mask 200_2, which may be spaced apart from each other on semiconductor pattern SCP to cover different regions of semiconductor pattern SCP.

[0157] According to an embodiment, the first mask 200_1 and the second mask 200_2 can partially crystallize the semiconductor pattern SCP so that a region of the semiconductor pattern SCP remains in an amorphous state. The first mask 200_1 and the second mask 200_2 can be placed on a region where a wide bandgap region is to be formed. For example, the first mask 200_1 can be placed on a region (hereinafter referred to as the "first region") where the first wide bandgap region 120c1 is to be formed. The second mask 200_2 can be placed on a region (hereinafter referred to as the "second region") where the second wide bandgap region 120c2 is to be formed. For example, the first mask 200_1 and the second mask 200_2 can be placed on the first and second regions of the semiconductor pattern SCP, respectively, and the remaining region of the semiconductor pattern SCP can be exposed.

[0158] Reference Figures 4 to 8C and Figure 8D , a crystallization process can be performed to crystallize the remaining areas of the semiconductor pattern SCP except for the first and second areas. For example, a laser irradiation device 300 (e.g., a laser bar) can be provided on the base layer 100 on which each semiconductor pattern SCP and the mask 200 are formed. The laser irradiation device 300 can move in one direction (e.g., the first direction DR1) to irradiate the laser 310 and crystallize an area of ​​the semiconductor pattern SCP not covered by the mask 200. Therefore, the semiconductor pattern SCP can be divided into an amorphous region (e.g., an a-Si region) corresponding to the first and second areas under the first and second masks 200_1 and 200_2, and a crystallized region (e.g., a poly-Si region) corresponding to the remaining areas except for the first and second areas.

[0159] In an embodiment, when the switching transistor Ts comprises Figure 4 and Figure 5In the embodiment of the present invention, when transistors are connected in series, the amorphous regions corresponding to the first and second regions may constitute the first wide bandgap region 120c1 and the second wide bandgap region 120c2 of the switching transistor Ts. The crystallized region between the first wide bandgap region 120c1 and the second wide bandgap region 120c2 may undergo a subsequent doping process and then constitute the third conductive region 120b3 of the switching transistor Ts. After the doping process, the crystallized region located on one side of the first wide bandgap region 120c1 may be divided into a first channel region 120a1 and a first conductive region 120b1. The crystallized region located on one side of the second wide bandgap region 120c2 may be divided into a second channel region 120a2 and a second conductive region 120b2.

[0160] In an embodiment, when the switching transistor Ts' comprises Figure 6 and Figure 7 When a single transistor is formed in an embodiment of the present invention, the amorphous regions corresponding to the first and second regions may constitute the second wide bandgap region 120c2' and the first wide bandgap region 120c1 of the switching transistor Ts'. The crystalline region between the first wide bandgap region 120c1 and the second wide bandgap region 120c2' may constitute the first channel region 120a1 of the switching transistor Ts'. The remaining crystalline region located on one side of the first wide bandgap region 120c1 and the second wide bandgap region 120c2' may undergo a subsequent doping process and then constitute the second conductive region 120b2 and the first conductive region 120b1 of the switching transistor Ts'.

[0161] According to an embodiment, the mask 200 may be removed after the crystallization process of the semiconductor pattern SCP is completed. In an example, the mask 200 may be removed before or after the next process of forming the first insulating film 130. According to an exemplary embodiment, when the mask 200 is removed after the first insulating film 130 is formed, the first insulating film 130 may protrude upward from the first and second regions of the semiconductor pattern SCP during some processes of manufacturing the switching transistor Ts (e.g., a film formation process of the first insulating film 130 and / or a doping process of forming each conductive region).

[0162] Reference Figures 4 to 8E , a first insulating film 130 may be formed on the semiconductor pattern SCP on which a crystallization process may be performed. According to an embodiment, the first insulating film 130 may be a gate insulating film and may include at least one layer of an organic insulating film such as silicon nitride (SiN x ) film or silicon oxide (SiO x However, the material and / or physical properties of the first insulating film 130 are not limited thereto and may be variously changed or modified according to embodiments.

[0163] Reference Figures 4 to 8FThe gate electrode 140 may be formed on the semiconductor pattern SCP so as to be positioned on one region of the crystallization region corresponding to each channel region. In an example, lower electrodes 140a1_1 and 140a2_1 of the first and second gate electrodes 140a1 and 140a2 may be formed on the semiconductor pattern SCP so as to be positioned on the first and second channel regions 120a1 and 120a2, respectively.

[0164] Reference Figures 4 to 8G , the gate electrode 140 (e.g., the lower electrodes 140a1_1 and 140a2_1 of the first and second gate electrodes 140a1 and 140a2) formed on the first insulating film 130 can be used as a mask to highly dope other regions of the crystallized region not covered by the gate electrode 140 with impurities. Thus, the active layer pattern 120 can be formed by forming each conductive region.

[0165] In an embodiment, when the switching transistor Ts comprises Figure 4 and Figure 5 When transistors are connected in series in the embodiment of the present invention, a region between the channel regions of the transistors (e.g., the first channel region 120a1 and the second channel region 120a2) can be doped with impurities to form a third conductive region 120b3. The third conductive region 120b3 can be formed between the first wide bandgap region 120c1 and the second wide bandgap region 120c2. Because the first wide bandgap region 120c1 and the second wide bandgap region 120c2 are amorphous regions that have not been crystallized, even when impurities are implanted, the first wide bandgap region 120c1 and the second wide bandgap region 120c2 have a bandgap wider than the bandgap of the remaining crystalline region. Therefore, the wide bandgap regions (e.g., the first wide bandgap region 120c1 and the second wide bandgap region 120c2) can be located between the third conductive region 120b3 and the channel regions (e.g., between the first channel region 120a1 and the third conductive region 120b3, and between the third conductive region 120b3 and the second channel region 120a2).

[0166] In an embodiment, when the switching transistor Ts' comprises Figure 6 and Figure 7 When forming a single transistor in an embodiment of the present invention, the gate electrode 140' (e.g., the lower electrode 140_1 of the gate electrode 140') can be provided on the region between the first wide bandgap region 120c1 and the second wide bandgap region 120c2' to block the implantation of impurities, thereby forming the first channel region 120a1. For example, according to an embodiment, wide bandgap regions (e.g., the first wide bandgap region 120c1 and the second wide bandgap region 120c2') can be formed on opposite sides of the first channel region 120a1.

[0167] During the doping process, impurities may also be doped into both ends of the semiconductor pattern SCP. Therefore, a first conductive region 120b1 and a second conductive region 120b2 may be formed at both ends of the semiconductor pattern SCP.

[0168] According to an embodiment, the impurity may be a p-type impurity including boron (B), etc. For example, boron (B) ions may be injected at a rate of about 0.1E12 / cm 2 to about 7E12 / cm 2 The semiconductor pattern SCP is ion-implanted with a dose within a range of 100 Å to 100 Å. However, the type and doping concentration of the impurities are not particularly limited in the disclosure and may be variously modified according to the type or characteristics of the switching transistors Ts and Ts' to be formed. In an example, when the switching transistors Ts and Ts' are formed as n-type, n-type impurities may be doped into the first conductive region 120b1, the second conductive region 120b2, and the third conductive region 120b3.

[0169] Reference Figures 4 to 8H , a second insulating film 150 may be formed on the lower electrodes 140a1_1 and 140a2_1 of the gate electrodes (i.e., the first gate electrode 140a1 and the second gate electrode 140a2). According to an embodiment, the second insulating film 150 may be an interlayer insulating film and may be formed to include a single layer or multiple layers through a film formation process of at least one layer of an organic insulating film and / or an inorganic insulating film. The material and / or physical properties of the second insulating film 150 are not particularly limited and may be variously modified according to the embodiment. According to an embodiment, the second insulating film 150 may be formed to have a flat surface through a chemical mechanical polishing process.

[0170] Reference Figures 4 to 8I , a first electrode 160 and a second electrode 170 connected to the first conductive region 120b1 and the second conductive region 120b2, respectively, may be formed on the second insulating film 150. When the gate electrodes (e.g., the first gate electrode 140a1 and the second gate electrode 140a2) each have a multi-layer structure, the upper electrodes 140a1_2 and 140a2_2 of the first gate electrode 140a1 and the second gate electrode 140a2 may be formed simultaneously in the process of forming the first electrode 160 and the second electrode 170.

[0171] Figure 9 FIG. 4 shows a pixel PXL including a switching transistor Ts according to an embodiment. Figure 9 Shown including according to Figure 4 and Figure 5 When the pixel PXL includes a switching transistor Ts according to the embodiment of the present invention, Figure 6 and Figure 7When the switching transistor Ts' of the embodiment is used, only the structure of the switching transistor Ts' can be partially changed, and the remaining components can be the same as Figure 9 The components of the pixel PXL disclosed in are substantially the same or similar. Figure 9 In the embodiment of FIG. 1 , components that are the same as or similar to those of the above-described embodiment are denoted by the same reference numerals and symbols, and redundant descriptions thereof will be omitted because they have been previously described.

[0172] Reference Figures 1 to 9 , the pixel PXL may include various circuit elements and a light-emitting element EL, wherein the circuit elements include a switching transistor Ts and a storage capacitor Cst. For example, the pixel PXL and the display panel including the pixel PXL may include a backplane layer BPL (also referred to as a "circuit element layer" or "circuit layer") and a display element layer DPL. The circuit elements of each pixel PXL and wiring connected to the circuit elements may be provided in the backplane layer BPL, the display element layer DPL may be provided on the backplane layer BPL, and the light-emitting element EL of each pixel PXL may be provided in the display element layer DPL.

[0173] According to an embodiment, the storage capacitor Cst may include a lower electrode 142 and an upper electrode 144, and the lower electrode 142 and the upper electrode 144 may be provided on the same layer as one electrode of the switching transistor Ts or on a different layer. In an example, the lower electrode 142 of the storage capacitor Cst may be provided on the first insulating film 130 together with the lower electrodes 140a1_1 and 140a2_1 of the first gate electrode 140a1 and the second gate electrode 140a2. The upper electrode 144 of the storage capacitor Cst may be provided on a different layer from the electrode of the switching transistor Ts.

[0174] For example, the second insulating film 150 may have a multi-layer structure including a lower insulating film 150_1 and an upper insulating film 150_2 . The upper electrode 144 of the storage capacitor Cst may be disposed between the lower insulating film 150_1 and the upper insulating film 150_2 of the second insulating film 150 .

[0175] In the embodiment, the upper electrodes 140a1_2 and 140a2_2 of the first gate electrode 140a1 and the second gate electrode 140a2 may be disposed on the second insulating film 150 together with the first electrode 160 and the second electrode 170, however, the disclosure is not limited thereto. For example, in the embodiment, the upper electrodes 140a1_2 and 140a2_2 of the first gate electrode 140a1 and the second gate electrode 140a2 may also be disposed on the lower insulating film 150_1 of the second insulating film 150 together with the upper electrode 144 of the storage capacitor Cst.

[0176] For example, the structures and positions of various circuit elements, wirings, and insulating films formed in the backplane layer BPL may be variously changed or modified according to embodiments. A third insulating film 180 may be provided on the circuit elements and wirings.

[0177] The third insulating film 180 may include a single layer or multiple layers. When the third insulating film 180 is configured to include multiple layers, the layers may be made of the same or similar materials or different materials. In an example, the third insulating film 180 may include multiple layers, the multiple layers including a first passivation layer composed of at least one inorganic insulating film and a second passivation layer composed of at least one organic insulating film. When the third insulating film 180 includes at least one organic insulating film, the surface of the backplane layer (BPL) may be substantially flattened.

[0178] The display element layer DPL may include the light-emitting element EL and may further include a bank structure for defining an emission region in which each light-emitting element EL may be provided (e.g., an emission region of each pixel PXL), for example, a pixel-defining film 240. A protective layer 250 may be provided on the light-emitting element EL and the pixel-defining film 240.

[0179] The light emitting element EL may include a first electrode 210, a light emitting layer 220, and a second electrode 230, which may be sequentially stacked on the third insulating film 180. According to an embodiment, one of the first electrode 210 and the second electrode 230 of the light emitting element EL may be an anode electrode, and the other of the first electrode 210 and the second electrode 230 may be a cathode electrode. For example, when the first electrode 210 is an anode electrode, the second electrode 230 may be a cathode electrode.

[0180] The first electrode 210 of the light emitting element EL may be provided on the third insulating film 180 and may be connected to at least one circuit element constituting each pixel circuit PXC through a contact hole, not shown, etc. In an example, the first electrode 210 may be connected to one electrode of the sixth transistor T6 and one electrode of the seventh transistor T7 through a contact hole or a through-hole passing through the third insulating film 180.

[0181] A pixel-defining film 240, which can separate the emission regions of corresponding pixels PXL, can be formed in each pixel region in which the first electrode 210 can be formed. The pixel-defining film 240 can be disposed between the emission regions of the pixels PXL and can have an opening in the emission region of each pixel PXL to expose the first electrode 210. For example, the pixel-defining film 240 can extend upward from one surface of the base layer 100, on which the first electrode 210 and the like are formed, along the periphery of the emission region of each pixel PXL.

[0182] The light-emitting layer 220 may be formed in each emission area surrounded by the pixel defining film 240. In an example, the light-emitting layer 220 may be provided on the exposed surface of the first electrode 210. According to an embodiment, the light-emitting layer 220 may have a multilayer thin film structure including a light-generating layer. For example, the light-emitting layer 220 may include a light-generating layer that emits light having a certain color, a first common layer provided between the light-generating layer and the first electrode 210, and a second common layer provided between the light-generating layer and the second electrode 230. According to an embodiment, the first common layer may include at least one of a hole injection layer and a hole transport layer. According to an embodiment, the second common layer may include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer. According to an embodiment, the light-generating layer may be patterned separately to correspond to each emission area. The first common layer and the second common layer may be formed entirely in the display area 10 in which the pixel PXL may be provided.

[0183] The second electrode 230 of the light emitting element EL may be formed on the light emitting layer 220. According to an embodiment, the second electrode 230 may be entirely formed in the display region 10, but the disclosure is not limited thereto.

[0184] A protective layer 250 may be formed on the light-emitting element EL to cover the second electrode 230 of the light-emitting element EL. In some embodiments, the protective layer 250 may include an encapsulation layer or an encapsulation substrate for sealing the pixels. The encapsulation layer or encapsulation substrate may be provided in a region of the display panel (at least the display region 10) where the pixels PXL may be provided. For example, the protective layer 250 may include a thin film encapsulation layer (TFE). When the TFE is formed to seal the display region 10, the thickness of the display panel may be reduced, and flexibility may be ensured while protecting the pixels PXL.

[0185] In an embodiment, the protective layer 250 may have a single-layer or multi-layer structure. In an example, the protective layer 250 may include a plurality of films including at least two inorganic films stacked on each other and at least one organic film disposed between the inorganic films. However, the structure and material of the protective layer 250 may be variously changed or modified according to the embodiment.

[0186] In the disclosure, the structure of the pixel PXL and the display panel including the pixel PXL is not limited to Figure 9 The embodiments shown in FIG. 1 and various changes or modifications may be made according to the embodiments. For example, the pixel PXL and the display panel including the pixel PXL may be formed in various structures within the spirit and scope of the disclosure.

[0187] Figure 10 is a graph showing leakage current characteristics of the switching transistors Ts and Ts' according to an embodiment. For example, Figure 10Shown are drain-source currents Ids according to gate-source voltages Vgs of switching transistors Ts and Ts′, which include a wide bandgap region between each channel region and a drain region.

[0188] Reference Figures 1 to 10 , the switching transistors Ts and Ts' according to the embodiment may include a wide bandgap region on at least one side of each channel region. Therefore, compared with the transistor of the comparative example that does not include the wide bandgap region, the leakage current can be lower in the off period (for example, the period in which the gate-source voltage Vgs is a high positive voltage). For example, with respect to the switching transistors Ts and Ts' according to the embodiment, compared with the transistor of the comparative example that does not include the wide bandgap region between each channel region and the drain region, the leakage current I G and gate-induced drain leakage current I GIDL The leakage current can be significantly reduced by reducing the

[0189] In an embodiment, instead of forming a wide bandgap region between each channel region and the drain region, a low concentration doping region (hereinafter referred to as an "LDD region") may be formed. However, in this case, the magnitude of the electric field may be changed by the LDD region, and thus the gate induced drain leakage current I GIDL Can be reduced, but the thermal current I G This is because the gate-induced drain leakage current I GIDL It is a current that takes the magnitude of the electric field and the band gap as variables, but the thermal current I G It is the current with the band gap as a variable and is independent of the magnitude of the electric field.

[0190] When LDD regions are formed instead of wide bandgap regions and the length of active layer patterns 120 and 120' is reduced, it may be difficult to achieve the effect of reducing leakage current through the LDD regions. For example, when the length of active layer patterns 120 and 120' is reduced, the length of the LDD regions formed may be reduced. Therefore, due to the dispersion of the length of the LDD regions and / or the dispersion of the dose, it may be difficult to achieve the desired effect of reducing leakage current.

[0191] On the other hand, as in the embodiments described above, in the switching transistors Ts and Ts' having the wide bandgap region formed between each channel region and the drain region, compared to the transistor using the LDD region, even when the length of the active layer patterns 120 and 120' is reduced, excellent leakage current characteristics can be exhibited. For example, according to various embodiments, the wide bandgap region can be formed between each channel region and the drain region, thereby more effectively preventing or reducing leakage current.

[0192] According to the display device and the method for manufacturing the display device according to the embodiment, leakage current of the pixel can be effectively reduced or prevented, thereby improving the grayscale expression of the pixel and improving the image quality of the display device.

[0193] The disclosed spirit and scope have been described according to the embodiments, but it will be noted that the embodiments are provided for description rather than limitation. In addition, it will be appreciated by those skilled in the art that various modifications may be made without departing from the disclosed spirit and scope.

[0194] The scope of the disclosure is not limited to the details described in the detailed description of the specification, but should be defined by the claims. In addition, it should be understood that all modifications and embodiments that come within the meaning and scope of the claims and their equivalents are included in the scope of the disclosure.

Claims

1. A display device comprising pixels arranged in a display area, wherein: The pixels include: a light emitting element connected between the first power source and the second power source; a first transistor connected between the first power source and the light emitting element, for controlling a driving current flowing in the light emitting element in response to a voltage of a first node; and at least one switching transistor, configured to transmit a data signal or an initialization power supply voltage to the first node, Wherein, the at least one switching transistor comprises: a first channel region; A first conductive region and a second conductive region are respectively disposed at opposite sides of the first channel region; a first wide bandgap region; a second channel region, disposed between the first channel region and the second conductive region; a third conductive region disposed between the first channel region and the second channel region; and a second wide bandgap region disposed between the second channel region and the third conductive region, and The first wide bandgap region is disposed between the first channel region and the third conductive region.

2. The display device according to claim 1, wherein The first channel region, the first conductive region, and the second conductive region include polysilicon, and The first wide bandgap region includes amorphous silicon.

3. The display device according to claim 1, wherein The at least one switching transistor includes a plurality of transistors connected to each other in series.

4. The display device according to claim 1, wherein The first wide bandgap region is in direct contact with the first channel region and the third conductive region, and The second wide bandgap region is in direct contact with the second channel region and the third conductive region.

5. The display device according to claim 1, wherein The at least one switching transistor comprises: a first gate electrode overlapping the first channel region; and a second gate electrode overlapping the second channel region, and The first gate electrode and the second gate electrode are electrically connected to each other. The display device according to claim 1 , wherein: The at least one switching transistor further includes a second wide bandgap region disposed between the first channel region and the first conductive region.

7. The display device according to claim 6, wherein: Each of the first wide bandgap region and the second wide bandgap region includes amorphous silicon.

8. The display device according to claim 1, wherein The at least one switching transistor includes at least one of the following: a second transistor connected between the first electrode of the first transistor and the data line, the second transistor including a gate electrode connected to the scan line; a third transistor connected between the second electrode of the first transistor and the first node, the third transistor including a gate electrode connected to the scan line; as well as A fourth transistor is connected between the first node and the initialization power source, and includes a gate electrode connected to a first control line.

9. The display device according to claim 1, wherein The pixel includes a plurality of switching transistors, and A predetermined number of switching transistors include the first wide bandgap region.

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