Light emitting diode display device

Abstract

A light-emitting diode display device includes: an organic light-emitting diode, the organic light-emitting diode including an anode electrode; a first transistor, the first transistor is used to provide current to the anode electrode of the organic light-emitting diode; a second transistor, the second transistor is used to transmit voltage to the gate electrode of the first transistor; a first capacitor, the first capacitor is used to store the voltage transmitted to the gate electrode of the first transistor; and a second capacitor is arranged between the first electrode of the second transistor and a data line, wherein the first electrode of the second transistor is directly connected to the anode electrode of the organic light-emitting diode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0096736 filed on August 8, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present invention relates to a light emitting diode display device, and more particularly, to a light emitting diode display device including transistors using different semiconductors. Background Art

[0004] Recently, an organic light emitting diode display device has been used as a device for displaying images.

[0005] Since the organic light emitting diode display device does not require an additional light source due to its self-emission characteristics, its thickness and weight can be reduced. In addition, the organic light emitting diode display device has high quality characteristics such as low power consumption, high brightness and high response speed.

[0006] Generally speaking, an organic light emitting diode display device includes: a substrate; a plurality of thin film transistors disposed on the substrate; a plurality of insulating films disposed between wirings for configuring the thin film transistors; and an organic light emitting diode (OLED) connected to the thin film transistors. The OLED may include an emitting electroluminescent layer that emits light in response to current supplied from the plurality of thin film transistors. However, since a plurality of thin film transistors are used to operate one OLED to emit light, there is a limitation in reducing the area occupied by a pixel. Summary of the invention

[0007] An exemplary embodiment of the present invention provides a light-emitting diode display device, which includes: an organic light-emitting diode, which includes an anode electrode; a first transistor, which is used to provide current to the anode electrode of the organic light-emitting diode; a second transistor, which is used to transmit a voltage to the gate electrode of the first transistor; a first capacitor, which is used to store the voltage transmitted to the gate electrode of the first transistor; and a second capacitor, which is arranged between a first electrode of the second transistor and a data line, wherein the first electrode of the second transistor is directly connected to the anode electrode of the organic light-emitting diode.

[0008] The second capacitor may include a first electrode connected to the first electrode of the second transistor and a second electrode connected to the data line, and the first electrode of the second capacitor may be connected to an anode electrode of the organic light emitting diode.

[0009] The first capacitor may include a first electrode connected to a gate electrode of the first transistor and a second electrode for receiving a predetermined voltage.

[0010] The predetermined voltage received at the second electrode of the first capacitor may be an initialization voltage.

[0011] The first transistor may further include a first electrode for receiving a driving voltage and a second electrode connected to an anode electrode of the organic light emitting diode.

[0012] The second electrode of the first transistor may be connected to the anode electrode, the first electrode of the second capacitor, and the first electrode of the second transistor.

[0013] The organic light emitting diode may further include a cathode electrode for receiving a driving low voltage, and the driving voltage and the driving low voltage may have a high voltage and a low voltage, respectively, in the emission period.

[0014] An exemplary embodiment of the present invention provides a light-emitting diode display device, the light-emitting diode display device comprising: a substrate; a polycrystalline semiconductor layer, the polycrystalline semiconductor layer being disposed on the substrate; a first gate insulating film, the first gate insulating film covering the polycrystalline semiconductor layer; a first gate electrode, the first gate electrode being disposed on the first gate insulating film and overlapping a portion of the polycrystalline semiconductor layer; a first interlayer insulating film, the first interlayer insulating film covering the first gate electrode; an oxide semiconductor layer, the oxide semiconductor layer being disposed on the first interlayer insulating film; a second gate insulating film, the second gate insulating film covering at least a portion of the oxide semiconductor layer; a second gate electrode, the second gate electrode being disposed on the second gate insulating film; a third interlayer insulating film, the third interlayer insulating film covering the second gate electrode; an electrode of a first capacitor, the electrode of the first capacitor being disposed on the third interlayer insulating film; and a fourth interlayer insulating film, the fourth interlayer insulating film covering the first gate electrode. An insulating film covers the electrode of the first capacitor; a first electrode and a second electrode of the first transistor, which are arranged on a fourth interlayer insulating film and are electrically connected to a first region and a second region of the polycrystalline semiconductor layer, respectively; a first electrode and a second electrode of the second transistor, which are arranged on the fourth interlayer insulating film and are electrically connected to the first region and the second region of the oxide semiconductor layer, respectively; a passivation film, which covers the first electrode and the second electrode of the first transistor and the first electrode and the second electrode of the second transistor, and includes a first opening exposing the second electrode of the first transistor; an anode electrode, which is connected to the second electrode of the first transistor through the first opening; and a partition wall, which includes a second opening, which exposes a portion of the anode electrode, wherein the first opening and the second opening overlap each other in a vertical direction.

[0015] The first opening may be disposed within the second opening.

[0016] An electrode of the first capacitor and the second electrode of the first transistor may overlap each other to form the first capacitor.

[0017] The light emitting diode display device may further include: an electrode of a second capacitor, the electrode of the second capacitor overlapping the first gate electrode, wherein the first gate electrode and the electrode of the second capacitor form a second capacitor.

[0018] The second electrode of the second transistor may be electrically connected to the second electrode of the first transistor, and the first electrode of the second transistor may be electrically connected to the electrode of the second capacitor.

[0019] The first capacitor and the second capacitor may overlap.

[0020] The light emitting diode display device may further include: a second interlayer insulating film covering an electrode of a second capacitor, wherein the electrode of the second capacitor may be disposed on the first interlayer insulating film.

[0021] The light emitting diode display device may further include: an overlapping layer of a second transistor, the overlapping layer of the second transistor overlapping the oxide semiconductor layer, wherein the overlapping layer of the second transistor may be disposed on the first interlayer insulating film and covered by the second interlayer insulating film.

[0022] An electrode of the second capacitor may be provided on the third interlayer insulating film.

[0023] The light emitting diode display device may further include: an overlapping layer disposed between the substrate and the polycrystalline semiconductor layer.

[0024] The light emitting diode display device may further include: an organic light emitting layer disposed in the second opening of the partition wall; a cathode electrode covering the organic light emitting layer and the partition wall; and an encapsulation layer covering the cathode electrode.

[0025] The second transistor may overlap a polycrystalline semiconductor layer of the first transistor.

[0026] An upper surface of the third interlayer insulating film may be flat.

[0027] An exemplary embodiment of the present invention provides a light-emitting diode display device, which includes: a light-emitting diode, which includes an anode electrode; a first transistor, which is used to provide current to the anode electrode of the light-emitting diode; a first capacitor, which is used to store voltage; a second transistor, which is used to connect the first capacitor to the first transistor so that the voltage stored in the first capacitor is provided to the first transistor; and a second capacitor, which is arranged between a first electrode of the second transistor and a data line and is directly connected to the first electrode of the second transistor and the anode electrode of the light-emitting diode.

[0028] A first electrode of the first transistor may be connected to the driving voltage line, and the second capacitor may be directly connected to a second electrode of the first transistor.

[0029] The first transistor may include a polycrystalline semiconductor layer, and the second transistor may include an oxide semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 An equivalent circuit diagram of a pixel of an organic light emitting diode display device according to an exemplary embodiment of the present invention is shown.

[0031] Figure 2 Shown applied to Figure 1 Waveform diagram of the pixel signal.

[0032] Figure 3 A cross-sectional view illustrating a pixel of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

[0033] Figure 4 The display shows the order according to Figure 3 FIG. 1 is a table of each layer of an organic light emitting diode display device according to an exemplary embodiment.

[0034] Figure 5 A top plan view of an organic light emitting diode display device according to an exemplary embodiment of the present invention is shown.

[0035] Figure 6 A top view of an organic light emitting diode display device according to a comparative example is shown.

[0036] Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 Cross-sectional views of pixels of an organic light emitting diode display device according to an exemplary embodiment of the present invention are respectively shown.

[0037] Fig.12 An equivalent circuit diagram of a pixel of an organic light emitting diode display device according to another exemplary embodiment of the present invention is shown.

[0038] Fig.13 Shown applied to Fig.12 Waveform diagram of the pixel signal. DETAILED DESCRIPTION

[0039] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways and therefore should not be limited to the embodiments set forth herein.

[0040] Like reference numerals may refer to like elements throughout the specification.

[0041] In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity.

[0042] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0043] Furthermore, throughout the specification, the phrase “in a plan view” may mean observing a target portion from the top, and the phrase “in a cross-sectional view” may mean observing a cross section formed by vertically cutting the target portion from the side.

[0044] Now refer to Figure 1 A circuit structure of a pixel according to an exemplary embodiment of the present invention is described.

[0045] Figure 1 An equivalent circuit diagram of a pixel of an organic light emitting diode display device according to an exemplary embodiment of the present invention is shown.

[0046] A pixel of the organic light emitting diode display device according to the present embodiment includes first and second transistors T1 and T2 , a storage capacitor Cst, an input capacitor Cpr, and an organic light emitting diode OLED.

[0047] The first transistor T1 (hereinafter also referred to as the driving transistor T1) receives a driving voltage ELVDD (hereinafter also referred to as the first driving voltage) and transmits an output current to the organic light emitting diode OLED according to the voltage at its gate electrode. The gate electrode of the driving transistor T1 is connected to the first electrode of the storage capacitor Cst, and the output current of the driving transistor T1 is determined according to the voltage stored in the first electrode of the storage capacitor Cst. The driving voltage ELVDD is applied to the first electrode of the driving transistor T1, and the anode electrode of the organic light emitting diode OLED is connected to the second electrode of the driving transistor T1. The second electrode of the driving transistor T1 may also be connected to the first electrode of the input capacitor Cpr and the first electrode of the second transistor T2. The first electrode of the second transistor T2 may also be referred to as the input side electrode hereinafter. The driving transistor T1 may be a p-type transistor and outputs an output current when a low voltage is applied to its gate electrode.

[0048] The second transistor T2 (hereinafter also referred to as a switching transistor) connects the first electrode of the storage capacitor Cst and the first electrode of the input capacitor Cpr, and transmits the voltage of the first electrode of the input capacitor Cpr to the first electrode of the storage capacitor Cst. The gate electrode of the second transistor T2 is connected to the gate line, to which the scan signal GW[n] is applied, the first electrode of the second transistor T2 (for example, the input side electrode) is connected to the first electrode of the input capacitor Cpr, and the second electrode of the second transistor T2 is connected to the first electrode of the storage capacitor Cst. The second electrode of the second transistor T2 may also be referred to as the output side electrode hereinafter. In addition to the first electrode of the input capacitor Cpr, the first electrode of the second transistor T2 may also be connected to the second electrode of the driving transistor T1 and the anode electrode of the organic light emitting diode OLED. In addition, in addition to the first electrode of the storage capacitor Cst, the second electrode of the second transistor T2 is also connected to the gate electrode of the driving transistor T1. Here, the second transistor T2 may be an n-type transistor, and is turned on when a high voltage is applied to its gate electrode. In some exemplary embodiments of the present invention, the second transistor T2 may be a p-type transistor, which will be referred to as the output side electrode. Fig.12 and Fig.13 Describe it.

[0049] The storage capacitor Cst is composed of two storage capacitor electrodes (e.g., a first electrode and a second electrode) and an insulating film disposed therebetween. The storage capacitor Cst stores and maintains a voltage transmitted to the gate electrode of the driving transistor T1 through the second transistor T2. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor T1 and the second electrode (e.g., an output side electrode) of the second transistor T2. The initialization voltage V INIT is applied to the second electrode of the storage capacitor Cst.

[0050] The data line and the pixel (to which the data voltage DATA is applied) are connected through an input capacitor Cpr. The input capacitor Cpr is composed of two input capacitor electrodes (e.g., its first electrode and second electrode) and an insulating film inserted between them. The first electrode of the input capacitor Cpr is connected to the first electrode (e.g., input side electrode) of the second transistor T2, while the second electrode of the input capacitor Cpr is connected to the data line. The first electrode of the input capacitor Cpr may also be connected to the second electrode of the driving transistor T1 and the anode electrode of the organic light emitting diode OLED. When the data voltage DATA applied to the second electrode of the input capacitor Cpr changes, the voltage of the first electrode located on the opposite side thereof also changes, and the changed voltage of the first electrode is applied to the gate electrode of the driving transistor T1 and the first electrode of the storage capacitor Cst through the second transistor T2. In other words, the pixel and the data line are not directly connected, but are connected through the input capacitor Cpr. In this structure, there may be a slight difference between the data voltage DATA applied to the data line and the voltage actually transmitted to the pixel (e.g., the first electrode (input side electrode) of the second transistor T2). Due to this structure, even when leakage occurs at the second transistor T2, the voltage stored in the first electrode of the storage capacitor Cst does not leak through the data line.

[0051] The organic light emitting diode OLED includes an anode electrode, a cathode electrode, and an organic light emitting layer interposed therebetween. The anode electrode is connected to the second electrode of the driving transistor T1, and the cathode electrode receives a driving low voltage ELVSS (hereinafter also referred to as a second driving voltage). The anode electrode of the organic light emitting diode OLED may also be connected to the first electrode of the input capacitor Cpr and the first electrode of the second transistor T2.

[0052] Now refer to Figure 2 Description The above description applies to Figure 1 The signal of the pixel of the structure.

[0053] Figure 2 Shown applied to Figure 1 Waveform diagram of the pixel signal.

[0054] like Figure 2 As shown in , the signal applied to the pixel can be divided into an initialization period (Initial), a compensation period (Vth comp), a programming period (Programming) and an emission period (Emission). Figure 2 In the programming period, an on-bias period (On-bias) and a holding period (Hold and Hold 2) are further included.

[0055] First, the on-bias period will be described. The on-bias period is a period for terminating the emission period, and during this period, a signal for preventing the organic light emitting diode OLED from emitting light is applied. In other words, according to Figure 2 , drives the low voltage ELVSS to a high voltage level, and initializes the voltage V INIT changes to a low voltage level, and then, the initialization voltage V INIT The gate voltage ELVDD is changed to a high voltage level. Other voltages (e.g., the driving voltage ELVDD, the scanning signal GW[n], and the data voltage DATA) do not change during the emission period. In other words, the driving voltage ELVDD is maintained at a high voltage, the scanning signal GW[n] is maintained at a gate-off voltage (e.g., a low voltage), and the data voltage DATA is maintained at a constant voltage corresponding to the ground voltage or the reference voltage.

[0056] In the conduction bias period, the driving low voltage ELVSS is changed to have a high voltage level, thereby reversing the voltage relationship between the driving voltage ELVDD and the driving low voltage ELVSS. For example, the driving voltage ELVDD is set to be higher than the driving low voltage ELVSS so that current flows into the organic light emitting diode OLED; however, when the voltage relationship is reversed, the current does not flow through the organic light emitting diode OLED, so that the emission period can be terminated. In other words, when the anode electrode has a high voltage and the cathode electrode has a low voltage, the current is applied from the anode electrode to the cathode electrode, and thus the organic light emitting diode OLED emits light according to the amount of current. However, when the voltage is changed to the opposite direction, in other words, when the cathode electrode has a high voltage, the organic light emitting diode OLED may not emit light. Therefore, in the conduction bias period, a high voltage is applied as the driving low voltage ELVSS to terminate the emission period of the organic light emitting diode OLED.

[0057] Then, the initialization period is performed. In the initialization period, the driving voltage ELVDD changes to a low voltage level, and the scanning signal GW[n] changes to a high voltage (which is a gate-on voltage). In addition, the initialization voltage V INIT It may be changed to a low voltage as in the on bias period, and then may be changed back to a high voltage level. In this case, the driving low voltage ELVSS is maintained at a high voltage level, and the data voltage DATA is maintained at a constant voltage (eg, a ground voltage or a reference voltage).

[0058] In the initialization period, the gate-on voltage is applied to the scan signal GW[n], so that the second transistor T2 is turned on to electrically connect the gate electrode of the driving transistor T1 to the second electrode of the driving transistor T1. In this case, the turned-on second transistor T2 may act as a resistor so that the voltages at the gate electrode and the second electrode of the driving transistor T1 may be different from each other. In other words, the voltage of the first electrode of the storage capacitor Cst and the voltage of the first electrode of the input capacitor Cpr may be different from each other. In this case, since the driving voltage ELVDD and the initialization voltage V INIT The initialization voltage V is changed to a low voltage, so the voltage of the gate electrode of the driving transistor T1 (for example, the voltage at the first electrode of the storage capacitor Cst) is also changed to a low voltage. Therefore, the voltage at the first electrode of the driving transistor T1 may have a lower voltage than the voltage of the second electrode of the driving transistor T1 (for example, the voltage at the first electrode of the input capacitor Cpr). INIT Change to high voltage again, and the initialization period ends.

[0059] Subsequently, a compensation period is performed, and in this case, the driving voltage ELVDD is changed to a high voltage, and the other voltages are maintained. In other words, the scanning signal GW[n] is maintained at the gate-on voltage (high voltage), the initialization voltage V INIT The driving low voltage ELVSS is maintained at a high voltage, the driving low voltage ELVSS is maintained at a high voltage level, and the data voltage DATA is maintained at a constant voltage (eg, a ground voltage or a reference voltage).

[0060] In the compensation period, according to the difference between the voltage of the gate electrode of the driving transistor T1 set in the initialization period (for example, the voltage at the first electrode of the storage capacitor Cst) and the high voltage of the driving voltage ELVDD, the driving transistor T1 outputs current to its second electrode. However, since the driving low voltage ELVSS has a high voltage, the current does not flow to the organic light emitting diode OLED, and the driving low voltage ELVSS is applied to the gate electrode of the driving transistor T1 (and the first electrode of the storage capacitor Cst) through the turned-on second transistor T2. In this case, when the voltage difference between the gate electrode and the second electrode of the driving transistor T1 is the threshold voltage Vth of the driving transistor T1, the driving transistor T1 does not output current. This is because a channel is not formed at the second electrode side in the semiconductor layer of the driving transistor T1, so that a path through which the current can flow is not formed. In other words, in the compensation period, the driving transistor T1 may initially output current, but after a predetermined time, since the voltage difference between the gate electrode and the second electrode of the driving transistor T1 corresponds to the threshold voltage Vth of the driving transistor T1, no current is output. Therefore, a voltage lower than the voltage of the second electrode of the driving transistor T1 (or the first electrode of the input capacitor Cpr) by the threshold voltage Vth may be stored in the first electrode of the storage capacitor Cst.

[0061] After the driving transistor T1 does not output current, the driving voltage ELVDD changes back to a low voltage, and the scan signal GW[n] changes to a gate-off voltage (eg, a low voltage).

[0062] Then, the programming period is performed. The programming period is a period in which the data voltage DATA is stored in the first electrode of the storage capacitor Cst and the scan signal GW[n] is sequentially applied to the gate line. In addition, according to the timing of applying the scan signal GW[n], the data voltage DATA to be written into the corresponding pixel is applied to the data line. For example, in the programming period, after a predetermined period (e.g., the first hold period Hold) after the drive voltage ELVDD changes to a low voltage, the scan signal GW[n] is sequentially applied to each gate line. In this case, the initialization voltage V INIT The driving voltage ELVDD is maintained at a high voltage, and the driving low voltage ELVSS is also maintained at a high voltage. Therefore, in the first holding period, the driving voltage ELVDD is maintained at a low voltage, the driving low voltage ELVSS is maintained at a high voltage, and the initialization voltage V INIT Maintain high voltage.

[0063] In this case, sequential scan signals GW[n] are applied to the gate lines, and thus, while gate-on voltages, which are high voltages, are sequentially applied to the gate lines, the gate-on voltages may not overlap each other on two or more gate lines.

[0064] When the gate-on voltage is applied to a specific gate line (e.g., the first gate line), the data voltage DATA to be applied to the pixel connected to the first gate line is applied to the data line. When the data voltage DATA changes at the data line, the voltage of the first electrode of the input capacitor Cpr also changes, and in this case, the voltage when the second transistor T2 is turned on is transmitted to the first electrode of the storage capacitor Cst and stored (e.g., written). In other words, Figure 1 In the structure of, since the second transistor T2 is turned on, the voltage of the first electrode of the input capacitor Cpr changed according to the data voltage DATA passes through the second transistor T2, and is then transmitted to the first electrode of the storage capacitor Cst and stored in the first electrode of the storage capacitor Cst. The period of applying the gate-on voltage (e.g., high voltage) to the scan signal GW[n] is called 1H, and the gate-off voltage (e.g., low voltage) is applied before and after 1H. In some exemplary embodiments of the present invention, the gate-on voltage can be changed to a low voltage according to whether the second transistor T2 is a p-type transistor or an n-type transistor. All the second transistors T2 connected to the same gate line are turned on at the same time, and after 1H, the gate-on voltage is applied to the next gate line.

[0065] After the data voltage DATA is stored in the storage capacitor Cst, a second holding period Hold 2 follows. In other words, the voltage stored in the storage capacitor Cst is maintained until the emission period. Although the data voltage DATA applied to the data line changes during the second holding period, the voltage of the first electrode of the storage capacitor Cst remains unchanged because the second transistor T2 is turned off.

[0066] Thereafter, an emission period is performed. In the emission period, the driving voltage ELVDD and the driving low voltage ELVSS are changed to have a voltage relationship in which current can flow to the organic light emitting diode OLED. In other words, the driving voltage ELVDD is changed to a high voltage, and the driving low voltage ELVSS is changed to a low voltage. In this case, the initialization voltage V INIT The data voltage DATA is maintained at a high voltage, a gate-off voltage (eg, a low voltage) is maintained at the gate line, and the data voltage DATA is maintained at a constant voltage (eg, a ground voltage or a reference voltage).

[0067] The amount of current output from the driving transistor T1 is determined by the voltage difference between the high voltage of the driving voltage ELVDD and the voltage of the first electrode of the storage capacitor Cst, in other words, by the voltage difference between the first electrode and the gate electrode of the driving transistor T1, and the current is transmitted to the organic light emitting diode OLED. In this case, since the second transistor T2 is turned off, the output current of the driving transistor T1 is transmitted only to the organic light emitting diode OLED, and the brightness of the light emitted by the organic light emitting diode OLED is determined according to the amount of current.

[0068] In other words, the brightness of the light emitted by the organic light emitting diode OLED is determined according to the amount of current flowing through the organic light emitting diode OLED. Since the current flowing through the organic light emitting diode OLED is the output current of the driving transistor T1, the output current changes according to the voltage of the gate electrode of the driving transistor T1. Therefore, the brightness of the organic light emitting diode OLED can be controlled by adjusting the voltage of the gate electrode of the driving transistor T1. Since the voltage of the gate electrode of the driving transistor T1 is transmitted from the data line through the input capacitor Cpr, the brightness of the organic light emitting diode OLED can be controlled by adjusting the voltage of the data line (e.g., the data voltage DATA).

[0069] After the programming period for all pixels is completed, the emission period can be performed for all pixels at the same time. Therefore, all pixels can emit light at the same time. In some exemplary embodiments of the present invention, the pixels can be divided into two or more groups, and each group can have an emission period.

[0070] The high voltage value and the low voltage value of the driving voltage ELVDD may be different from the high voltage value and the low voltage value of the driving low voltage ELVSS. However, in some exemplary embodiments of the present invention, one high voltage and one low voltage are set, and the driving voltage ELVDD and the driving low voltage ELVSS may be used together with those voltages. In addition, the same initialization voltage V as the high voltage and the low voltage of the driving voltage ELVDD or the driving low voltage ELVSS may also be used. INIT of high voltage and low voltage.

[0071] In some exemplary embodiments of the present invention, the initialization voltage V may be adjusted according to INIT In these embodiments, the voltage V is initialized during the emission period. INIT At the same time as the initialization voltage V changes, the voltage of the first electrode of the storage capacitor Cst changes to set the driving transistor T1 to allow current to flow. In other words, before the emission period, although a voltage that does not allow current to flow in the driving transistor T1 is applied to the gate electrode of the driving transistor T1, as the initialization voltage V INITThe voltage of the first electrode of the storage capacitor Cst can be changed to operate the driving transistor T1. In these embodiments, the initialization voltage V INIT It can be changed to have a lower level than the voltage during the emission period. This further reduces the voltage of the gate electrode of the driving transistor T1 because the driving transistor T1 is a p-type transistor. In this case, the driving voltage ELVDD and the driving low voltage ELVSS can be maintained at a high voltage and a low voltage, respectively.

[0072] In some exemplary embodiments of the present invention, the Figure 2 At least one of the time periods shown in .

[0073] according to Figure 1 In a structure in which a data voltage DATA is applied to a pixel through an input capacitor Cpr, even if leakage current occurs in the second transistor T2, current leaking to the outside of the pixel does not occur. In other words, in a structure in which a data line and a pixel are directly connected, when leakage current occurs in a pixel, current leaking to the outside through the data line occurs. In this case, the pixel includes an additional compensation transistor to prevent this from occurring. However, in the present embodiment, since the pixel has a structure in which the pixel is connected to the data line through an input capacitor Cpr, an additional transistor may not be required, and thus the area occupied by the pixel can be reduced. Therefore, as Figure 1 As shown in , even when only two transistors T1 and T2 are included, one pixel can be operated without the aforementioned current leakage.

[0074] and Figure 1 Different from the embodiment of the present invention, the second electrode of the driving transistor T1 may be connected only to the anode electrode of the organic light emitting diode OLED, and may not be connected to the first electrode of the input capacitor Cpr and the first electrode of the second transistor T2. In this case, an element that can periodically initialize the anode electrode of the organic light emitting diode OLED, such as another transistor, may be further included.

[0075] Now refer to Figure 3 Describe as above Figure 1 The pixel circuit, Figure 3 A specific stacking structure is shown. Figure 1 The pixel circuit may have various stacking structures, and Figure 3 A cross-sectional view showing one of the stacking structures.

[0076] Figure 3 A cross-sectional view illustrating a pixel of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

[0077] The organic light emitting diode display device according to the present embodiment may include a rigid substrate such as glass or a substrate formed of a flexible material such as plastic or polyimide (PI). Figure 3 An example is shown in which the substrate 110 is formed of a flexible material.

[0078] The buffer layer 111 is disposed on the substrate 110. The buffer layer 111 may include an inorganic insulating material, such as silicon oxide, silicon nitride, or aluminum oxide. A barrier layer including an inorganic insulating material or an organic insulating material (such as polyimide) may be further formed between the flexible substrate 110 and the buffer layer 111. In addition, when the flexible substrate 110 is used, two or more substrates 110 may be formed, and in this case, two or more buffer layers 111 or barrier layers may be formed. However, for simplicity, Figure 3 Only one substrate 110 and one buffer layer 111 are shown.

[0079] The semiconductor layer 130 (hereinafter also referred to as a polycrystalline semiconductor layer) included in the driving transistor T1 is formed on the buffer layer 111. The semiconductor layer 130 included in the driving transistor T1 is formed of a polycrystalline semiconductor. The semiconductor layer 130 includes a channel region overlapping with the gate electrode 121 and a first region and a second region located at opposite sides thereof, which will be described later.

[0080] A first gate insulating film 141 covering the polycrystalline semiconductor layer 130 is disposed on the polycrystalline semiconductor layer 130 .

[0081] The gate electrode 121 (hereinafter also referred to as the first gate electrode) of the driving transistor T1 is formed on the first gate insulating film 141. The channel of the driving transistor T1 is located at a region where the gate electrode 121 of the driving transistor T1 overlaps the semiconductor layer 130. The semiconductor layer 130 may be doped except for its channel.

[0082] The gate electrode 121 of the driving transistor T1 also serves as a first electrode of the storage capacitor Cst.

[0083] The first interlayer insulating film 161 is provided to cover the gate electrode 121 of the driving transistor T1 and the exposed first gate insulating film 141 .

[0084] The overlapping layer 126 of the second transistor T2 and the second electrode 122 of the storage capacitor Cst are formed on the first interlayer insulating film 161. The second electrode 122 may also be referred to as an electrode of the storage capacitor Cst hereinafter.

[0085] The second electrode 122 of the storage capacitor Cst and the gate electrode 121 of the driving transistor T1 overlap each other and form the storage capacitor Cst together with the first interlayer insulating film 161 located therebetween. INITis applied to the second electrode 122 of the storage capacitor Cst. In some exemplary embodiments of the present invention, the second electrode 122 of the storage capacitor Cst may be connected to the first electrode 122 of the storage capacitor Cst. INIT The line (eg, initialization line) is formed integrally.

[0086] The overlapping layer 126 of the second transistor T2 is formed at the region where the semiconductor layer 135 of the second transistor T2 is to be formed. In addition, the overlapping layer 126 of the second transistor T2 overlaps the channel of the semiconductor layer 135 of the second transistor T2, and may overlap at least a portion of the first region and the second region located at opposite sides of the channel. In some exemplary embodiments of the present invention, the overlapping layer 126 of the second transistor T2 may receive a voltage of a constant level, may be electrically connected to one electrode of the second transistor T2, may receive a driving voltage ELVDD or a driving low voltage ELVSS, or may float. The overlapping layer 126 of the second transistor T2 is used to ensure the channel characteristics of the second transistor T2 to increase the reliability of the second transistor T2.

[0087] The second interlayer insulating film 162 is positioned on the overlapping layer 126 of the second transistor T2 , the second electrode 122 of the storage capacitor Cst, and the first interlayer insulating film 161 exposed by the overlapping layer 126 and the second electrode 122 .

[0088] On the second interlayer insulating film 162, a semiconductor layer 135 of the second transistor T2, a second gate insulating film 142, a gate electrode 125 of the second transistor T2, and connection portions 176 and 178 are formed. The semiconductor layer 135 may also be referred to as an oxide semiconductor layer, and the gate electrode 125 may also be referred to as a second gate electrode. The gate electrode 125 of the second transistor T2 and the connection portions 176 and 178 may be formed of the same material.

[0089] The semiconductor layer 135 of the second transistor T2 is formed at a region overlapping at least a portion of the overlapping layer 126 of the second transistor T2, and is formed of an oxide semiconductor. The semiconductor layer 135 of the second transistor T2 includes a channel region overlapping the gate electrode 125 of the second transistor T2, which will be described later, and a first region and a second region located at opposite sides thereof. The first region and the second region of the semiconductor layer 135 of the second transistor T2 may be doped. The second transistor T2 including the oxide semiconductor may have the characteristics of an n-type transistor or a p-type transistor by doping.

[0090] By using an oxide semiconductor in the semiconductor layer 135 of the second transistor T2, the leakage current characteristics of the second transistor T2 can be reduced. In other words, in the case of using a polycrystalline semiconductor (such as the driving transistor T1), it may not be easy to maintain the voltage written in the storage capacitor Cst because the leakage current is relatively large. However, by using an oxide semiconductor, it is easy to maintain the voltage of the storage capacitor Cst. Therefore, there is no need to use a structure that uses another transistor to prevent leakage current.

[0091] The second gate insulating film 142 and the gate electrode 125 of the second transistor T2 are sequentially formed on the channel of the semiconductor layer 135 of the second transistor T2. In this embodiment, the second gate insulating film 142 is only located on the channel of the semiconductor layer 135 of the second transistor T2, in other words, only located under the gate electrode 125 of the second transistor T2. Figure 3 In the embodiment of the present invention, when the gate electrode 125 of the second transistor T2 is etched, the second gate insulating film 142 is also etched, so it has the same planar shape as the gate electrode 125 of the second transistor T2. However, in some exemplary embodiments of the present invention, the second gate insulating film 142 may cover the entire semiconductor layer 135 of the second transistor T2 and the entire exposed second interlayer insulating film 162.

[0092] The gate electrode 125 of the second transistor T2 may be electrically connected to a gate line to which the scan signal GW[n] is applied, and may have an integrally formed structure in the present embodiment.

[0093] In addition, two connection portions 176 and 178 are located at an upper portion of the second interlayer insulating film 162 and at a position where the driving transistor T1 is located. The first connection portion 176 is connected to the first region of the semiconductor layer 130 through an opening formed in the first gate insulating film 141, the first interlayer insulating film 161, and the second interlayer insulating film 162. The second connection portion 178 is connected to the second region of the semiconductor layer 130 through an opening formed in the first gate insulating film 141, the first interlayer insulating film 161, and the second interlayer insulating film 162. The two connection portions 176 and 178 are additionally formed to assist the first electrode 175 and the second electrode 177 of the driving transistor T1 in connecting to the first region and the second region of the semiconductor layer 130, respectively, but in some exemplary embodiments of the present invention, they may be omitted. However, in some exemplary embodiments of the present invention, Figure 3Differently, the first electrode 175 and the second electrode 177 of the driving transistor T1 may be connected to the first region and the second region of the semiconductor layer 130, respectively, by including more connection portions. The two connection portions 176 and 178 may overlap at least a portion of an area occupied by an opening 301 formed in a partition wall 300 to be described later, or may be located in the opening 301. This can reduce the area occupied by the pixel.

[0094] The third interlayer insulating film 163 is formed on the semiconductor layer 135 of the second transistor T2, the second gate insulating film 142, the gate electrode 125 of the second transistor T2, the connecting portions 176 and 178, and the exposed second interlayer insulating film 162. The third interlayer insulating film 163 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may be thicker than the first interlayer insulating film 161 and the second interlayer insulating film 162. In some exemplary embodiments of the present invention, the third interlayer insulating film 163 may be formed as a double layer of a silicon nitride film and a silicon oxide film. Since the input capacitor Cpr and the organic light emitting diode OLED will be formed on the third interlayer insulating film 163, a large step may occur due to the structure of the lower electrode and the semiconductor layer under the third interlayer insulating film 163. The large step may cause the electrodes of the input capacitor Cpr and the organic light emitting diode OLED to shift. Therefore, in order to remove the step, the third interlayer insulating film 163 may be formed to be thick and then flattened by chemical mechanical polishing (CMP). In Figure 3 , the third interlayer insulating film 163 having an upper surface planarized by a CMP process is shown, and CMP is shown at its location. Figure 3 As shown in FIG. 1 , since the upper surface of the third interlayer insulating film 163 is planarized, the input capacitor Cpr and the organic light emitting diode OLED can be formed without a step.

[0095] The second electrode 179 of the input capacitor Cpr (hereinafter also referred to as the electrode of the input capacitor Cpr) is formed on the third interlayer insulating film 163. The second electrode 179 of the input capacitor Cpr is electrically connected to the data line to receive the data voltage DATA. In some exemplary embodiments of the present invention, the second electrode 179 may be integrally formed with the data line.

[0096] The fourth interlayer insulating film 164 is located on the second electrode 179 of the input capacitor Cpr and the exposed third interlayer insulating film 163 .

[0097] A first electrode 175 of the driving transistor T1 , a second electrode 177 of the driving transistor T1 , a second electrode 171 of the second transistor T2 , and a first electrode 173 of the second transistor T2 are formed on the fourth interlayer insulating film 164 .

[0098] The first electrode 175 of the driving transistor T1 is connected to the first connection portion 176 through the openings formed in the third interlayer insulating film 163 and the fourth interlayer insulating film 164, and is thus connected to the first region of the semiconductor layer 130. The driving voltage ELVDD may be applied to the first electrode 175 of the driving transistor T1, and the driving transistor T1 may be electrically connected to a wiring (e.g., a driving voltage line) to which the driving voltage ELVDD is applied, or the driving transistor T1 may be integrally formed with the wiring.

[0099] The second electrode 177 of the driving transistor T1 is connected to the second connection portion 178 through the openings formed in the third interlayer insulating film 163 and the fourth interlayer insulating film 164, and is thus connected to the second region of the semiconductor layer 130. In addition, the second electrode 177 of the driving transistor T1 overlaps with the second electrode 179 of the input capacitor Cpr to form the input capacitor Cpr. In addition, referring to Figure 3 The input capacitor Cpr and the storage capacitor Cst formed by overlapping each other overlap each other in the vertical direction. Therefore, the area occupied by the capacitor is reduced.

[0100] The second electrode 171 of the second transistor T2 is connected to the first region of the semiconductor layer 135 of the second transistor T2 through the opening formed in the third interlayer insulating film 163 and the fourth interlayer insulating film 164. Figure 3 The second electrode 171 of the second transistor T2 is shown electrically connected to the first electrode 121 of the storage capacitor Cst through a dotted line Ba.

[0101] The first electrode 173 of the second transistor T2 is connected to the second region of the semiconductor layer 135 of the second transistor T2 through the opening formed in the third interlayer insulating film 163 and the fourth interlayer insulating film 164. Figure 3 It is shown that the first electrode 173 of the second transistor T2 is electrically connected to the second electrode 177 of the driving transistor T1 through a dotted line Bb.

[0102] The passivation film 180 is formed on the first and second electrodes 175 and 177 of the driving transistor T1 , the second and first electrodes 171 and 173 of the second transistor T2 , and the exposed fourth interlayer insulating film 164 .

[0103] The passivation film 180 includes an opening 181 (hereinafter also referred to as a first opening) exposing the second electrode 177 of the driving transistor T1 .

[0104] The anode electrode 191 is formed on the passivation film 180, and the anode electrode 191 is connected to the second electrode 177 of the driving transistor T1 through the opening 181. The anode electrode 191 may include a transparent conductive material or a metal material, and may have a multilayer structure including two or more of the transparent conductive material and the metal material. In some exemplary embodiments of the present invention, the organic light emitting diode OLED including the anode electrode 191 may be formed to have different thicknesses according to the emitted light. In other words, the thickness of the anode electrode 191 included in the red organic light emitting diode OLED, the thickness of the anode electrode 191 included in the green organic light emitting diode OLED, and the thickness of the anode electrode 191 included in the blue organic light emitting diode OLED may be different from each other. In some exemplary embodiments of the present invention, the thickness of the anode electrode 191 included in the red organic light emitting diode OLED may be the thickest, followed by the thickness of the anode electrode 191 included in the blue organic light emitting diode OLED, and then the thickness of the anode electrode 191 included in the green organic light emitting diode OLED. The thickness difference between the respective anode electrodes 191 may be changed by the presence or absence of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) on the metal layer or by controlling the thickness of the transparent conductive material.

[0105] A partition wall 300 having an opening 301 (hereinafter also referred to as a second opening) for partitioning a light emitting region of the organic light emitting diode OLED is formed on the anode electrode 191 and the exposed passivation film 180. The opening 301 exposes a portion of the anode electrode 191, and an organic light emitting layer 350 is formed in the opening 301. In some exemplary embodiments of the present invention, a spacer may be further formed on the partition wall 300 or on the same layer as the partition wall 300.

[0106] The cathode electrode 270 is formed on the partition wall 300 and the organic light emitting layer 350. The cathode electrode 270 receives the driving low voltage ELVSS.

[0107] exist Figure 3 In the embodiment, the opening 301 located in the partition wall 300 and the opening 181 located in the passivation film 180 overlap each other in the vertical direction (hereinafter this is also referred to as a vertical overlapping structure of the openings).

[0108] In addition, the opening 301 in the partition wall 300 and the opening from the second region of the semiconductor layer 130 of the driving transistor T1 to the second electrode 177 overlap each other in the vertical direction. Figure 3 The opening connecting the second region of the semiconductor layer 130 and the second connection portion 178 and the opening connecting the second connection portion 178 and the second electrode 177 are formed in the middle.

[0109] In addition, the second connection portion 178 connecting the second region of the semiconductor layer 130 of the driving transistor T1 and the second electrode 177 is also disposed inside the anode electrode 191. In other words, the anode electrode 191 and the second connection portion 178 overlap in the vertical direction.

[0110] As described above, due to the vertical overlapping structure between the openings 301 and 181, the area occupied by the pixel is reduced.

[0111] In addition, Figure 3 In the embodiment of the present invention, the storage capacitor Cst and the input capacitor Cpr also overlap each other in the vertical direction (hereinafter also referred to as the vertical overlapping structure of the capacitor). In other words, the storage capacitor Cst is formed by overlapping the second electrode 122 of the storage capacitor Cst and the gate electrode 121 of the driving transistor T1. The input capacitor Cpr is formed on the storage capacitor Cst by overlapping the second electrode 179 of the input capacitor Cpr and the second electrode 177 of the driving transistor T1. In this way, the storage capacitor Cst and the input capacitor Cpr exist above and below each other and have overlapping portions. Due to the vertical overlapping structure of the capacitor, the area occupied by the pixel is also reduced.

[0112] The vertical overlapping structure can reduce the area occupied by the pixel. Figure 5 and Figure 6 The area reduction according to the vertical overlapping structure of the openings is further described.

[0113] In addition, an encapsulation layer protecting the organic light emitting diode OLED may be provided on the cathode electrode 270. The encapsulation layer may contact the cathode electrode 270, or may be spaced apart from the cathode electrode 270 due to the additional formation of a cover layer and a functional layer. The encapsulation layer may be a thin film encapsulation layer in which an inorganic film and an organic film are stacked, and may include three layers formed of an inorganic film, an organic film, and an inorganic film.

[0114] In accordance with Figure 1 and Figure 3 In the pixel of the organic light emitting diode display device of the embodiment shown in , since the data voltage DATA is transmitted by the input capacitor Cpr, even if leakage current occurs in the pixel, the leakage current does not leak to the outside through the data line. Therefore, even if the leakage current is not blocked by forming a transistor other than these two transistors, the pixel can be properly operated. In addition, since the second transistor T2 uses an oxide semiconductor to reduce the leakage current, rather than the second transistor T2 using a polycrystalline semiconductor, it is not necessary to further form an additional compensation transistor.

[0115] As described above, no additional compensation transistor is included, and only two transistors are included in the pixel, and thus the area occupied by the pixel can be significantly reduced.

[0116] In addition, refer to Figure 3 , because the opening 181 of the passivation film 180 exposing the anode electrode 191 vertically overlaps with the opening 301 of the partition wall 300 (which is a region in which the organic light emitting diode OLED emits light), the area occupied by the pixel is reduced. In addition, in some exemplary embodiments of the present invention, since the opening and / or the second connection portion 178 connecting the second electrode 177 of the driving transistor T1 and the second region of the semiconductor layer 130 are formed while overlapping with the opening 301 of the partition wall 300, the area occupied by the pixel can be further reduced.

[0117] Therefore, an organic light emitting diode display device having a high pixel number per inch (ppi) can be manufactured. In addition, a high-resolution organic light emitting diode display device can be formed.

[0118] In the following, reference will be made to Figure 4 describe Figure 3 The manufacturing order of each constituent element used in.

[0119] Figure 4 is a table sequentially showing respective layers of an organic light emitting diode display device according to an exemplary embodiment of the present invention.

[0120] exist Figure 4 In the figure, the terms on the left represent the names of the layers in English abbreviations, and the terms on the right represent the names of the layers in English abbreviations. Figure 3 The reference numerals of the constituent elements corresponding to the respective layers in FIG.

[0121] First, Barrier / PI refers to the flexible substrate 110, and means that a layer formed of a flexible material (such as a barrier layer and PI) is located on the substrate 110. In this case, the barrier layer may be formed of various inorganic insulating materials, and may include silicon oxide or silicon nitride, and in some exemplary embodiments of the present invention, it may include an amorphous semiconductor or may be formed as a plurality of layers with an inorganic insulating material. In this article, polyimide (PI) may be formed to have a thickness of 5 μm to 20 μm, and the inorganic insulating material layer or the amorphous semiconductor layer formed therewith may have a thickness of 100 μm to 150 μm. to Thickness.

[0122] The buffer on the barrier / PI refers to the buffer layer 111, and it can be formed of an inorganic insulating material (such as silicon oxide or silicon nitride), and in some exemplary embodiments of the present invention, the inorganic insulating material can be formed into multiple layers. The inorganic insulating material used can be to thick.

[0123] The ACT on the buffer refers to a polycrystalline semiconductor layer, in other words, it refers to the semiconductor layer 130 of the driving transistor T1. A polycrystalline semiconductor can be formed by a crystallization process of an amorphous semiconductor. The polycrystalline semiconductor layer can be formed as to thick.

[0124] The GI on the ACT refers to the first gate insulating film 141, and the first gate insulating film 141 is formed of an inorganic insulating material such as silicon oxide or silicon nitride. The first gate insulating film 141 may have to Thickness.

[0125] GAT1 on GI refers to the first gate conductive layer and includes Figure 3 The first gate conductive layer may be formed of various metals such as molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), and may be formed as a plurality of layers including various metals. The first gate conductive layer may have to Thickness.

[0126] ILD1 on GAT1 refers to a first interlayer insulating film 161 and may be formed of an inorganic insulating material such as silicon oxide or silicon nitride. The first interlayer insulating film 161 may have to Thickness.

[0127] GAT2 on ILD1 refers to a second gate conductive layer and includes Figure 3 The second gate conductive layer may be formed of various metals such as molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), and may be formed as a plurality of layers including various metals. The second gate conductive layer may have to Thickness.

[0128] ILD2 on GAT2 refers to a second interlayer insulating film 162 and may be formed of an inorganic insulating material such as silicon oxide or silicon nitride. The second interlayer insulating film 162 may have to Thickness.

[0129] Oxide on ILD2 refers to an oxide semiconductor layer and includes Figure 3The semiconductor layer 135 of the second transistor T2 in FIG. The oxide semiconductor may include various materials and may be formed of IGZO (Indium Gallium Zinc Oxide). The oxide semiconductor layer may have to Thickness.

[0130] GI2 on Oxide refers to the second gate insulating film 142, and may be formed of an inorganic insulating material such as silicon oxide or silicon nitride. The second gate insulating film 142 may have to Thickness.

[0131] GAT3 above GI2 refers to a third gate conductive layer and includes the gate electrode 125 of the second transistor T2 and the connection portions 176 and 178. The third gate conductive layer may be formed of various metals such as molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), and may be formed as a plurality of layers including various metals. The third gate conductive layer may have to Thickness.

[0132] ILD3 above GAT3 refers to a third interlayer insulating film 163, and may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may be formed in a plurality of layers using the inorganic insulating material. The third interlayer insulating film 163 may have to In some exemplary embodiments of the present invention, the third interlayer insulating film 163 may be formed as a double film of a silicon nitride film and a silicon oxide film. In addition, after the third interlayer insulating film 163 is stacked, a CMP process may be additionally performed to eliminate the step. Through the CMP process, the upper surface of the third interlayer insulating film 163 is planarized, and thus the step due to the electrode and the semiconductor layer located below the third interlayer insulating film 163 is eliminated.

[0133] DAT1 on ILD3 refers to the first data conductive layer and includes Figure 3 The first data conductive layer may be formed of various metals such as molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), and may be formed as a plurality of layers including various metals. The first data conductive layer may have to Thickness.

[0134] ILD4 on DAT1 refers to a fourth interlayer insulating film 164, and may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, and may be formed into a plurality of layers using the inorganic insulating material. The fourth interlayer insulating film 164 may have to Thickness.

[0135] DAT2 on ILD4 refers to a second data conductive layer and includes a first electrode 175 and a second electrode 177 of the driving transistor T1 and a second electrode 171 and a first electrode 173 of the second transistor T2. The second data conductive layer may be formed of various metals such as molybdenum (Mo), titanium (Ti), copper (Cu), and aluminum (Al), and may be formed in a plurality of layers including various metals. The second data conductive layer may have to Thickness.

[0136] VIA on DAT2 refers to a passivation film 180, and the passivation film 180 may be formed to include an organic material, and may be formed of various organic materials such as polyimide (PI). The passivation film 180 may have to Thickness.

[0137] The PXL on VIA refers to the pixel electrode layer and includes Figure 3 The pixel electrode layer may include a transparent conductive material such as ITO, and may be formed to have a multilayer structure including silver (Ag) and various metals such as aluminum (Al), molybdenum (Mo), titanium (Ti), copper (Cu), etc. The pixel electrode layer may have to Thickness.

[0138] The PDL on the PXL refers to the partition wall 300, and the SPC on the PDL may be formed alone or together with the partition wall 300 as a spacer. The partition wall 300 and the spacer may be formed of various organic materials such as polyimide (PI). The partition wall 300 may have to The thickness of the spacer may be to Thickness.

[0139] As described above, the first gate conductive layer, the second gate conductive layer and the third gate conductive layer may include the same material, and the first data conductive layer and the second data conductive layer may also include the same material. In some exemplary embodiments of the present invention, the material included in the gate conductive layer and the material included in the data conductive layer may be different from each other.

[0140] like Figure 4 As shown in FIG. 1 , since the structure of the pixel according to the present embodiment is formed while overlapping in the vertical direction, the area occupied by the pixel is reduced, and thus the number of pixels per inch (ppi) of the pixel is increased. Therefore, the resolution of the organic light emitting diode display device is increased.

[0141] As described above, the area occupied by the pixels formed based on the vertical structure is reduced. Therefore, the ppi increases, which will refer to Figure 5 and Figure 6 Give a description.

[0142] Figure 5 A top view of an organic light emitting diode display device according to an exemplary embodiment of the present invention is shown, and Figure 6 A top view of an organic light emitting diode display device according to a comparative example is shown.

[0143] Corresponding to the comparative example Figure 6 A structure is shown in which the opening 301 of the partition wall 300 and the opening 181 of the passivation film 180 do not vertically overlap. Therefore, it can be seen that the anode electrode 191 is formed wide because the anode electrode 191 has the extended portion 191-1 and connects the two openings 181 and 301.

[0144] In contrast, Figure 5 In the embodiment, the opening 301 of the partition wall 300 and the opening 181 of the passivation film 180 vertically overlap each other, and therefore the anode electrode 191 does not need to be as Figure 6 , further comprising an additional extended portion 191-1. In other words, Figure 5 The anode electrode 191 does not have the same Figure 6 The anode electrode 191 has the same protruding portion. Therefore, Figure 5 The area occupied by the anode electrode 191 is reduced.

[0145] Since a short circuit should not occur between the anode electrodes 191 of adjacent pixels, the adjacent pixels are formed to have a predetermined interval therebetween. Figure 5 In the embodiment, the anode electrodes 191 are formed at intervals of Da.

[0146] In contrast, in the comparative example shown Figure 6 In the embodiment, since the interval Dc is formed so that a short circuit does not occur due to the extended portion 191-1 of the anode electrode 191, the distance between the anode electrodes 191 is formed as an interval Db, which is greater than Figure 5 Therefore, in Figure 5 In, with Figure 6 In comparison, the number of pixels per inch (ppi) has increased further.

[0147] References in this article Figures 7 to 11 A modified embodiment related to the above-described embodiment is described.

[0148] Figures 7 to 11 Cross-sectional views of pixels of an organic light emitting diode display device according to an exemplary embodiment of the present invention are respectively shown.

[0149] First, with Figure 3 different, Figure 7 1 and 2 show an example in which the opening 181 formed in the passivation film 180 is formed completely inside the opening 301 formed in the partition 300. In other words, referring to Figure 3 and Figure 5 , at least a portion of the opening 181 formed in the passivation film 180 may be located outside the opening 301 formed in the partition 300, and referring to Figure 7 , all the openings 181 formed in the passivation film 180 are formed inside the openings 301 formed in the partition wall 300 .

[0150] according to Figure 7 In the embodiment of the present invention, the opening from the second region of the semiconductor layer 130 of the driving transistor T1 to the second electrode 177 is also completely formed inside the opening 301 formed in the partition 300. The opening from the second region of the semiconductor layer 130 of the driving transistor T1 to the second electrode 177 corresponds to the opening in Figure 3 The opening connecting the second region of the semiconductor layer 130 and the second connection portion 178 and the opening connecting the second connection portion 178 and the second electrode 177 are formed in the middle.

[0151] In addition, in addition to the opening 181 formed in the passivation film 180 , the second connection portion 178 connecting the second region of the semiconductor layer 130 of the driving transistor T1 and the second electrode 177 may also be completely disposed in the anode electrode 191 .

[0152] Therefore, with Figure 3 Compared with the implementation method, Figure 7 Embodiments of the present invention may further reduce the area of ​​the anode electrode 191 to form a more compact structure.

[0153] For reference, in Figure 7 In FIG. 1 , the width of the anode electrode 191 is drawn as Figure 3 The width of the anode electrode 191 is wider in order to more clearly show the vertical overlapping structure, but this does not mean that the size of the anode electrode 191 is larger than Figure 3 The size of the anode electrode 191. For example, Figure 7 The anode electrode 191 is simply drawn larger to show the structure of its underlying portion.

[0154] The following will describe Figure 8 implementation method.

[0155] and Figure 3 The implementation methods are different. Figure 8 It is shown that an additional overlapping layer 123 is further included on the substrate 110 below the semiconductor layer 130 of the driving transistor T1.

[0156] The relevant parts will be described as follows.

[0157] exist Figure 8 In the embodiment of the present invention, the barrier layer 112 is located on the flexible substrate 110. The barrier layer 112 may be formed of an inorganic insulating material, or may have a multi-layer structure formed of an inorganic insulating material.

[0158] The additional overlapping layer 123 is disposed on the barrier layer 112. The additional overlapping layer 123 may overlap the channel of the semiconductor layer 130 of the driving transistor T1, and may overlap at least a portion of the first region and the second region of the driving transistor T1.

[0159] The buffer layer 111 is located on the additional overlapping layer 123, and the structure above the buffer layer 111 is connected to the Figure 3 The structure is the same.

[0160] Here, the additional overlapping layer 123 may receive a voltage of a constant level, may be electrically connected to an electrode of the driving transistor T1, may receive a driving voltage ELVDD or a driving low voltage ELVSS, or may be floating. The additional overlapping layer 123 may ensure channel characteristics of the driving transistor T1 to increase reliability of the driving transistor T1.

[0161] The following will describe Fig. 9 implementation method.

[0162] Fig. 9 Shown in Figure 3 An embodiment in which a layer located on the cathode electrode 270 is further formed in the structure and the organic light emitting diode OLED emits white light.

[0163] exist Fig. 9 In an embodiment, the encapsulation layer 400 is located on the cathode electrode 270. The encapsulation layer 400 may contact the cathode electrode 270, or may be spaced apart from the cathode electrode 270 by including a cover layer or a functional layer therebetween. In addition, the encapsulation layer 400 may be a thin film encapsulation layer in which an inorganic film and an organic film are stacked, and may include three layers formed of an inorganic film, an organic film, and an inorganic film. Fig. 9 , the encapsulation layer 400 is shown as being formed only at the upper side of the pixel, but this is because only the cross section of the pixel is shown, and therefore the side surface thereof is not shown. In other words, in addition to the upper side, the encapsulation layer 400 may also be formed on the side surface of the pixel so that oxygen or moisture is not absorbed from the outside into the organic light emitting layer 350.

[0164] The light blocking member 500 and the color filter layer 600 are formed on the encapsulation layer 400. The color filter layer 600 is formed at a position corresponding to the opening 301 of the partition wall 300 so that the light emitted from the organic light emitting diode OLED can be provided to the user. On the other hand, the light blocking member 500 is formed in a region other than above the entire opening 301. When white light is emitted from the organic light emitting diode OLED, the color filter layer 600 transmits only one wavelength of light of the three primary colors to display a specific color. The color filter layer 600 includes at least three different kinds of color filter layers 600 to display colors, and one pixel displays only one color of the three primary colors, so at least three pixels are mixed to display one display color.

[0165] In some exemplary embodiments of the present invention, the organic light emitting diode OLED may emit blue light. In this case, instead of using the color filter layer 600, by forming a color conversion layer including a color conversion material such as quantum dots (QD), three primary colors can be displayed by converting blue light into red light and green light based on blue light.

[0166] The window 700 may be formed on the light blocking member 500 and the color filter layer 600. In some exemplary embodiments of the present invention, a touch sensing element may be formed on an inner surface of the window 700. In this case, since a user may observe wiring of the touch sensing element (e.g., touch wiring), a polarizing layer may be additionally formed to prevent the touch wiring from being observed from the outside.

[0167] The following will describe Fig.10 implementation method.

[0168] exist Fig.10 In the implementation mode, Figure 3 Differently, the storage capacitor Cst and the input capacitor Cpr are not arranged to vertically overlap each other.

[0169] In other words, Fig.10 In the embodiment of FIG. 1 , the second gate conductive layer is removed, and therefore, the second electrode 122 of the storage capacitor Cst and the overlapping layer 126 of the second transistor T2 are removed. In addition, the second interlayer insulating film 162 is also removed.

[0170] exist Fig.10 In the implementation mode, Figure 3 Different from the embodiment of the present invention, the second electrode 122-1 of the storage capacitor Cst is formed in the first data conductive layer. The initialization voltage V INIT is applied to the second electrode 122-1 of the storage capacitor Cst. In some exemplary embodiments of the present invention, the second electrode 122-1 of the storage capacitor Cst may be connected to the first electrode 122-2 of the storage capacitor Cst. INIT The lines (eg, initialization voltage lines) are integrally formed.

[0171] In this case, the second electrode 122 - 1 of the storage capacitor Cst is formed on the same layer (eg, the first data conductive layer) as the second electrode 179 of the input capacitor Cpr.

[0172] The second electrode 122 - 1 of the storage capacitor Cst is covered by the fourth interlayer insulating film 164 .

[0173] The second electrode 171 of the second transistor T2 located on the fourth interlayer insulating film 164 has an extension portion 171-1, and the extension portion 171-1 overlaps the second electrode 122-1 of the storage capacitor Cst. Therefore, the storage capacitor Cst is formed by the extension portion 171-1, the second electrode 122-1 of the storage capacitor Cst, and the fourth interlayer insulating film 164 located therebetween.

[0174] As a result, Fig.10 In the embodiment of the present invention, the number of masks used in the manufacturing is reduced by reducing the number of layers used, but with Figure 3 In comparison, the area of ​​the pixel increases.

[0175] In other words, when the pixel is formed as a whole, such as Fig.10 As shown in , the number of masks can be reduced to reduce manufacturing costs and processing time. Figure 5 The vertical structure between the openings 181 and 301 shown in FIG. 1 includes Fig.10 and therefore, Fig.10 The implementation method and Figure 6 The ppi value can be increased compared to the comparative example.

[0176] The following will describe Fig.11 implementation method.

[0177] exist Fig.11 In the embodiment, the second transistor T2 is located above the semiconductor layer 130 of the driving transistor T1 to minimize the area occupied by the pixel.

[0178] In other words, reference Fig.11 ,lie in Figure 3 The second transistor T2 at the left side of the driving transistor T1 is formed at a position overlapping the semiconductor layer 130 of the driving transistor T1.

[0179] In this case, Fig.11 In the embodiment of the present invention, the first electrode 173 of the second transistor T2 and the second electrode 177 of the driving transistor T1 are not electrically connected via the dotted line Bb but are directly integrally formed.

[0180] exist Fig.11In the embodiment of the present invention, at least a part of the area occupied by the second transistor T2 overlaps with the area of ​​the driving transistor T1, so that the two transistors T1 and T2 also have a vertical structure (also referred to as the vertical structure of the transistor). As a result, the area occupied by the pixel can be the smallest in the embodiment shown.

[0181] In the above mentioned Figures 7 to 11 In the embodiment, the upper surface of the third interlayer insulating film 163 is formed by Figure 3 As a result, the Figures 7 to 11 In the embodiment of the present invention, the input capacitor Cpr and the organic light emitting diode OLED located at the upper portion of the third interlayer insulating film 163 may be formed without a step.

[0182] In the following, reference will be made to Fig.12 and Fig.13 Description and Figure 1 and Figure 2 Different implementations of the method.

[0183] Fig.12 An equivalent circuit diagram of a pixel of an organic light emitting diode display device according to another exemplary embodiment of the present invention is shown, and Fig.13 Shown applied to Fig.12 Waveform diagram of the pixel signal.

[0184] and Figure 1 and Figure 2 Different, in Fig.12 and Fig.13 In the embodiment, the second transistor T2 is a p-type transistor, which is the same type as the driving transistor T1. The semiconductor layer 135 of the p-type transistor is doped with a doping material of a different type from that of the n-type transistor, and therefore, the p-type transistor has a characteristic of being turned on by a low voltage. Fig.12 and Fig.13 In the embodiment of the present invention, the gate-on voltage of the second transistor T2 has a low voltage level.

[0185] Compare Figure 2 and Fig.13 , it can be seen that Fig.13 The scanning signal GW[n] has the same Figure 2 The voltage of the scanning signal GW[n] is opposite to the voltage of the scanning signal GW[n]. In other words, when Figure 2 When the scanning signal GW[n] has a high voltage, Fig.13 The scanning signal GW[n] has a low voltage, and when Figure 2 When the scanning signal GW[n] has a low voltage, Fig.13 The scanning signal GW[n] has a high voltage. All other timings are the same.

[0186] Fig.12 and Fig.13 The operation and Figure 1 and Figure 2 The operation of the embodiments is substantially the same.

[0187] In some exemplary embodiments of the present invention, the type of the driving transistor T1 may also be changed to another type.

[0188] Exemplary embodiments of the present invention provide a light-emitting diode display device that can reduce the area occupied by pixels to increase the number of pixels per inch (ppi) and improve resolution. For example, only two transistors can be used to drive an OLED. In addition, the pixels can have a vertical structure to reduce the area and increase the resolution. In addition, exemplary embodiments of the present invention provide a light-emitting diode display device in which some transistors included in the pixels have increased reliability, while other transistors of the pixels may have eliminated leakage currents, thereby increasing the display quality. Therefore, the display characteristics can be stabilized by using transistors with oxide semiconductors. Although the present invention has been specifically shown and described with reference to exemplary embodiments of the present invention, it should be understood by those skilled in the art that various modifications may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the appended claims.

Claims

1. A light emitting diode display device, comprising: An organic light emitting diode, the organic light emitting diode comprising an anode electrode and a cathode electrode; a first transistor, the first transistor being configured to provide current to the anode electrode of the organic light emitting diode; a second transistor configured to transmit a voltage to a gate electrode of the first transistor; a first capacitor for storing the voltage transmitted to the gate electrode of the first transistor; as well as a second capacitor, the second capacitor being disposed between the first electrode of the second transistor and the data line, wherein the first electrode of the second transistor is directly connected to the anode electrode of the organic light emitting diode, wherein the cathode electrode receives a driving low voltage, The voltage level of the driving low voltage varies during a single frame. wherein the first capacitor comprises a first electrode connected to the gate electrode of the first transistor and a second electrode for receiving an initialization voltage, and In the on-bias period, the initialization voltage changes to a first level and then changes to a second level, and in the initialization period, the initialization voltage changes to the first level and then changes to the second level.

2. The light emitting diode display device according to claim 1, wherein: The second capacitor includes a first electrode connected to the first electrode of the second transistor and a second electrode connected to the data line, and The first electrode of the second capacitor is connected to the anode electrode of the organic light emitting diode.

3. The light emitting diode display device according to claim 1, wherein: The first transistor further includes a first electrode for receiving a driving voltage and a second electrode connected to the anode electrode of the organic light emitting diode.

4. The light emitting diode display device according to claim 3, wherein: The second electrode of the first transistor is connected to the anode electrode, the first electrode of the second capacitor, and the first electrode of the second transistor.

5. The light emitting diode display device according to claim 4, wherein: The driving voltage and the driving low voltage have a high voltage and a low voltage, respectively, in an emission period.

6. A light emitting diode display device, comprising: substrate; a polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer is disposed on the substrate; a first gate insulating film, the first gate insulating film covering the polycrystalline semiconductor layer; a first gate electrode disposed on the first gate insulating film and overlapping a portion of the polycrystalline semiconductor layer; a first interlayer insulating film, the first interlayer insulating film covering the first gate electrode; an oxide semiconductor layer provided on the first interlayer insulating film; a second gate insulating film covering at least a portion of the oxide semiconductor layer; a second gate electrode, the second gate electrode being disposed on the second gate insulating film; a third interlayer insulating film, the third interlayer insulating film covering the second gate electrode; an electrode of a first capacitor, the electrode of the first capacitor being provided on the third interlayer insulating film; a fourth interlayer insulating film, the fourth interlayer insulating film covering the electrode of the first capacitor; a first electrode and a second electrode of a first transistor, the first electrode and the second electrode of the first transistor being disposed on the fourth interlayer insulating film and electrically connected to a first region and a second region of the polycrystalline semiconductor layer, respectively; a first electrode and a second electrode of a second transistor, the first electrode and the second electrode of the second transistor being provided on the fourth interlayer insulating film and electrically connected to the first region and the second region of the oxide semiconductor layer, respectively; a passivation film covering the first electrode and the second electrode of the first transistor and the first electrode and the second electrode of the second transistor, and including a first opening exposing the second electrode of the first transistor; an anode electrode connected to the second electrode of the first transistor through the first opening; as well as a partition wall, the partition wall comprising a second opening, the second opening exposing a portion of the anode electrode, The first opening and the second opening overlap each other in a vertical direction.

7. The light emitting diode display device according to claim 6, wherein: The first opening is disposed in the second opening.

8. The light emitting diode display device according to claim 6, wherein: The electrode of the first capacitor and the second electrode of the first transistor overlap each other to form the first capacitor.

9. The light emitting diode display device according to claim 8, further comprising: an electrode of a second capacitor, the electrode of the second capacitor overlapping the first gate electrode, Wherein the first gate electrode and the electrode of the second capacitor form the second capacitor.

10. The light emitting diode display device according to claim 9, wherein: The second electrode of the second transistor is electrically connected to the second electrode of the first transistor, and The first electrode of the second transistor is electrically connected to the electrode of the second capacitor.

11. The light emitting diode display device according to claim 9, wherein: The first capacitor and the second capacitor overlap.

12. The light emitting diode display device according to claim 9, further comprising: a second interlayer insulating film, the second interlayer insulating film covering the electrode of the second capacitor, The electrode of the second capacitor is provided on the first interlayer insulating film.

13. The light emitting diode display device according to claim 12, further comprising: an overlapping layer of the second transistor, the overlapping layer of the second transistor overlapping the oxide semiconductor layer, The overlapping layer of the second transistor is provided on the first interlayer insulating film and is covered by the second interlayer insulating film.

14. The light emitting diode display device according to claim 9, wherein: The electrode of the second capacitor is provided on the third interlayer insulating film.

15. The light emitting diode display device according to claim 6, further comprising: An overlapping layer is disposed between the substrate and the polycrystalline semiconductor layer.

16. The light emitting diode display device according to claim 6, further comprising: an organic light-emitting layer, wherein the organic light-emitting layer is disposed in the second opening of the partition wall; a cathode electrode, the cathode electrode covering the organic light-emitting layer and the partition wall; as well as A packaging layer covers the cathode electrode.

17. The light emitting diode display device according to claim 6, wherein: The second transistor overlaps the polycrystalline semiconductor layer of the first transistor.

18. The light emitting diode display device according to claim 6, wherein: An upper surface of the third interlayer insulating film is flat.

19. A light emitting diode display device, comprising: A light emitting diode, the light emitting diode comprising an anode electrode and a cathode electrode receiving a driving low voltage; a first transistor, the first transistor being used to provide current to the anode electrode of the light emitting diode; a first capacitor, the first capacitor being used to store a voltage; a second transistor configured to connect the first capacitor to the first transistor so that the voltage stored in the first capacitor is provided to the first transistor; as well as a second capacitor disposed between the first electrode of the second transistor and the data line and directly connected to the first electrode of the second transistor and the anode electrode of the light emitting diode, wherein the voltage level of the driving low voltage varies during a single frame, wherein the first capacitor receives an initialization voltage, and In the on-bias period, the initialization voltage changes to a first level and then changes to a second level, and in the initialization period, the initialization voltage changes to the first level and then changes to the second level. 20 . The light emitting diode display device of claim 19 , wherein a first electrode of the first transistor is connected to a driving voltage line, and the second capacitor is directly connected to a second electrode of the first transistor. 21 . The light emitting diode display device of claim 19 , wherein the first transistor comprises a polycrystalline semiconductor layer, and the second transistor comprises an oxide semiconductor layer.

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