Semiconductor package including embedded semiconductor device

Abstract

A semiconductor package is provided, which includes a package substrate. The package substrate includes a substrate pattern and a substrate insulating layer at least partially surrounding the substrate pattern. The package substrate has a groove. The external connection terminal is arranged below the package substrate. The embedded semiconductor device is arranged in the groove of the package substrate. The embedded semiconductor device includes a first substrate. The first active layer is arranged on the first substrate. The first chip pad is arranged on the first active layer. The buried insulating layer is arranged in the groove of the package substrate, and the buried insulating layer at least partially surrounds at least a portion of the side surface of the embedded semiconductor device. The mounted semiconductor device is arranged on the package substrate and connected to the package substrate and the embedded semiconductor device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0098346 filed on August 12, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including an embedded semiconductor device. Background Art

[0004] Semiconductor devices are required to have high storage capacity, and semiconductor packages including semiconductor devices are required to be light and thin. Research has been conducted on including semiconductor devices having various functions in semiconductor packages and on rapidly driving semiconductor devices. For example, active research has been conducted on the configuration of a semiconductor package in which a second semiconductor device is mounted on a first semiconductor device. Summary of the invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor package including a package substrate is provided. The package substrate includes a substrate pattern and a substrate insulating layer at least partially surrounding the substrate pattern. The package substrate has a groove. The external connection terminal is arranged below the package substrate. The embedded semiconductor device is arranged in the groove of the package substrate. The embedded semiconductor device includes a first substrate. The first active layer is arranged on the first substrate. The first chip pad is arranged on the first active layer. The buried insulating layer is arranged in the groove of the package substrate and at least partially surrounds at least a portion of the side surface of the embedded semiconductor device. The mounted semiconductor device is arranged on the package substrate and connected to the package substrate and the embedded semiconductor device.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package including a package substrate is provided. The package substrate includes a substrate pattern and a substrate insulating layer at least partially surrounding the substrate pattern. The package substrate has an internal space. The external connection terminal is arranged below the package substrate. An embedded semiconductor device is arranged in the internal space of the package substrate and is at least partially surrounded by the package substrate. The embedded semiconductor device includes a first substrate, a first active layer arranged on the first substrate, and a first chip pad arranged on the first active layer. The buried insulating layer at least partially surrounds at least a portion of the side surface of the embedded semiconductor device. A mounted semiconductor device is arranged on the package substrate. The mounted semiconductor device is connected to the package substrate and the embedded semiconductor device. A portion of the lower surface of the mounted semiconductor device overlaps a portion of the upper surface of the embedded semiconductor device including the first active layer in a vertical direction.

[0007] According to an exemplary embodiment of the present invention, a package-on-package (PoP) type semiconductor package is provided, which includes a lower semiconductor package. The upper semiconductor package is arranged on the lower semiconductor package. The lower semiconductor package includes a package substrate, which includes a substrate pattern and a substrate insulating layer that at least partially surrounds the substrate pattern, and has a groove that exposes a portion of the substrate pattern. The external connection terminal is arranged below the package substrate. The embedded semiconductor device is arranged in the groove of the package substrate. The embedded semiconductor device includes a first substrate. The first active layer is arranged on the first substrate. The first chip pad is arranged on the first active layer, and the through electrode penetrates the first substrate and connects the first active layer to the substrate pattern exposed by the groove. The mounted semiconductor device is arranged on the package substrate and connects the package substrate to the embedded semiconductor device. The conductive column is arranged on the package substrate and is electrically connected to the substrate pattern. The molding material is arranged on the package substrate and at least partially surrounds the conductive column and the mounted semiconductor device, and exposes a portion of the conductive column. The insert is arranged on the molding material. The insert includes an insert substrate. The interposer connection terminal is arranged under the interposer substrate and contacts the conductive pillar.

[0008] According to an exemplary embodiment of the present invention, a semiconductor package including a package substrate is provided. The package substrate includes a substrate pattern and a substrate insulating layer at least surrounding the substrate pattern. The package substrate has a groove or an inner space exposing a portion of the substrate pattern. An embedded semiconductor device is arranged in the groove or the inner space of the package substrate. The embedded semiconductor device is electrically connected to the substrate pattern. A molding material is arranged on the package substrate. The molding material includes a groove recessed from the outer surface of the molding material. An insert connection terminal is arranged in the groove recessed from the outer surface of the molding material. A conductive column includes a first end arranged on the substrate pattern and a second end arranged on the lower surface of the insert connection terminal. An upper semiconductor package is arranged on the insert connection terminal. The upper semiconductor package is electrically connected to the substrate pattern through the insert connection terminal and the conductive column. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1 to 4 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present inventive concept;

[0011] Figure 5 and Figure 6 is a lower semiconductor package of a package-on-package (PoP) type semiconductor package according to an exemplary embodiment of the inventive concept;

[0012] Figure 7 and Figure 8 is a PoP type semiconductor package according to an exemplary embodiment of the inventive concept;

[0013] Fig. 9 An operation of attaching a protection substrate to a package substrate according to an exemplary embodiment of the inventive concept is shown;

[0014] Fig.10 An operation of forming a groove in a package substrate according to an exemplary embodiment of the inventive concept is shown;

[0015] Fig.11 An operation of inserting a first embedded semiconductor device into a groove of a package substrate according to an exemplary embodiment of the inventive concept is shown;

[0016] Fig.12 An operation of mounting a mounting type semiconductor device on a package substrate according to an exemplary embodiment of the inventive concept is shown;

[0017] Fig.13 An operation of forming a conductive pillar on a package substrate according to an exemplary embodiment of the inventive concept is shown;

[0018] Fig.14 illustrates an operation of forming a molding material on a package substrate according to an exemplary embodiment of the inventive concept;

[0019] Fig.15 An operation of installing an insert according to an exemplary embodiment of the present inventive concept is illustrated;

[0020] Fig.16 illustrates an operation of mounting an upper semiconductor package on an interposer according to an exemplary embodiment of the inventive concept; and

[0021] Fig.17 An operation of separating a protection substrate from a package substrate according to an exemplary embodiment of the inventive concept is illustrated. DETAILED DESCRIPTION

[0022] Hereinafter, the inventive concept will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown.

[0023] Figure 1 is a cross-sectional view illustrating a semiconductor package 10 according to an exemplary embodiment of the inventive concept.

[0024] Reference Figure 1The semiconductor package 10 may include a package substrate 110 , external connection terminals 120 , a first embedded semiconductor device 130 a , a mounted semiconductor device 140 , a first chip connection terminal 150 a , a second chip connection terminal 150 b , an internal connection terminal 160 , an adhesive layer 170 , and a buried insulating layer 180 .

[0025] The package substrate 110 of the semiconductor package 10 may include a substrate pattern 111 and a substrate insulating layer 112 surrounding the substrate pattern 111. The package substrate 110 may include a printed circuit board (PCB). However, the package substrate 110 is not limited to the PCB, but may include various types of substrates such as a ceramic substrate.

[0026] The substrate pattern 111 may include a plurality of internal wirings extending in a horizontal direction. The horizontal direction may refer to an axis parallel to the upper surface of the package substrate 110. The conductive vias may be provided to connect the internal wirings to each other in a vertical direction. The vertical direction may refer to an axis perpendicular to the upper surface of the package substrate 110 (e.g., a normal axis of the upper surface of the package substrate 110). The substrate pattern 111 may include a metal selected from copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), and / or gold (Au).

[0027] The substrate pattern 111 and its associated vias may be buried in the substrate insulating layer 112. The substrate insulating layer 112 may protect the substrate pattern 111 from external impacts and may prevent electrical short circuits of the substrate pattern 111. For example, the substrate insulating layer 112 may include epoxy resin, polyphenylene ether, polyphenylene oxide, polyimide, and / or liquid crystal polymer. However, the inventive concept is not limited thereto, and the substrate insulating layer 112 may include various insulating materials.

[0028] According to an exemplary embodiment of the inventive concept, the package substrate 110 may include a groove H1 ( Fig.10 For example, a groove H1 facing the mounted semiconductor device 140 may be formed in the package substrate 110 .

[0029] The groove H1 of the package substrate 110 may provide a space in which the first embedded semiconductor device 130a is inserted. The groove H1 of the package substrate 110 may have a larger volume than the first embedded semiconductor device 130a. However, the inventive concept is not limited thereto. For example, the groove H1 of the package substrate 110 may be formed in the package substrate 110 to have a shape substantially the same as that of the first embedded semiconductor device 130a. Although the groove H1 is shown as being recessed from the upper surface of the package substrate 110, the inventive concept is not limited thereto. For example, the groove H1 may be arranged in a recessed side surface of the package substrate 110.

[0030] A portion of the substrate pattern 111 may be exposed through the groove H1 of the package substrate 110. For example, parallel side surfaces of the groove H1 may be arranged on corresponding end surfaces of the first horizontally extending substrate pattern 111, and a lower surface of the groove H1 may be arranged on an exposed upper surface of the second horizontally extending substrate pattern 111. Because the substrate pattern 111 of the package substrate 110 may be exposed through the groove H1, the first active layer 132 of the first embedded semiconductor device 130a may be electrically connected to the substrate pattern 111 through the through electrode 134. The depth of the groove H1 of the package substrate 110 is greater than the thickness (e.g., in the vertical direction) of the first embedded semiconductor device 130a.

[0031] The external connection terminal 120 of the semiconductor package 10 may be a terminal that electrically connects the first embedded semiconductor device 130a and the mounted semiconductor device 140 to an external device. The external connection terminal 120 may be electrically connected to the substrate pattern 111 of the package substrate 110. For example, the external connection terminal 120 may include a conductive ball and / or a solder ball. However, the inventive concept is not limited thereto, and the external connection terminal 120 may include at least one of a conductive bump, a conductive spacer, and a pin grid array.

[0032] The first embedded semiconductor device 130a of the semiconductor package 10 may be inserted into the groove H1 of the package substrate 110. For example, the first embedded semiconductor device 130a may be inserted into the groove H1 of the package substrate 110 and connected to the substrate pattern 111. The first embedded semiconductor device 130a may be inserted into the groove H1 of the package substrate 110 such that the first active layer 132 faces the mounted semiconductor device 140.

[0033] The first embedded semiconductor device 130a may include a memory semiconductor device. For example, the memory semiconductor device may include a volatile memory semiconductor device (such as a dynamic random access memory (DRAM) or a static random access memory (SRAM)), and may include a non-volatile memory semiconductor device (such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). However, the inventive concept is not limited thereto, and the first embedded semiconductor device 130a may include various other types of semiconductor devices.

[0034] The first embedded semiconductor device 130a may include a first substrate 131, a first active layer 132, a first chip pad 133, and a through electrode 134. The first substrate 131 may include a silicon wafer.

[0035] The first active layer 132 may be formed on the first substrate 131 (e.g., formed on the upper surface of the first substrate 131). The first active layer 132 may include a plurality of individual devices of various types. The plurality of individual devices may include various microelectronic devices, for example, metal oxide semiconductor field effect transistors (MOSFETs) (e.g., complementary metal oxide semiconductor (CMOS) transistors), system large scale integration (LSI) devices, image sensors (e.g., CMOS imaging sensors (CIS)), and microelectromechanical systems (MEMS). A protective layer may be formed on the first active layer 132 (e.g., formed on the upper surface of the first active layer 132). The protective layer may cover the surface of the first active layer 132 and may expose the first chip pad 133.

[0036] The first chip pad 133 may be located on the first active layer 132. The first chip pad 133 may be electrically connected to the first active layer 132. The first chip pad 133 may electrically connect the first embedded semiconductor device 130a to the mounted semiconductor device 140. Figure 1 As shown, the first chip pad 133 may overlap the second chip pad 143 a of the mounted semiconductor device 140 in a vertical direction. The first chip pad 133 may have an upper surface substantially coplanar with an upper surface of the package substrate 110 .

[0037] The through electrode 134 may penetrate the upper and lower surfaces of the first substrate 131 and may be electrically connected to the first active layer 132. For example, the through electrode 134 may extend through the inside of the first active layer 132, the side surface of the through electrode 134 may contact the inside of the first active layer 132, and the through electrode 134 may contact the internal connection terminal 160 at a first end and contact the buried insulating layer 180 at a second end spaced apart in a vertical direction. Thus, the through electrode 134 may be electrically connected to the plurality of individual devices of the first active layer 132.

[0038] The through electrode 134 may have a columnar shape. Each of the through electrodes 134 may include a barrier layer formed on at least one surface of the column and a buried conductive layer filling the inside of the barrier layer. The buried conductive layer may include a conductive material, for example, a metal such as copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt) and / or gold (Au). The buried conductive layer may extend to the inside of the first active layer 132.

[0039] According to an exemplary embodiment of the inventive concept, Figure 1As shown, the first embedded semiconductor device 130a may include a first chip pad 133 in a first region and may include a through electrode 134 in a second region spaced apart from the first region (e.g., in a horizontal direction). The first embedded semiconductor device 130a may be inserted into the groove H1 of the package substrate 110 so that the first chip pad 133 is closer to the central portion of the package substrate 110 than the through electrode 134. For example, the first chip pad 133 may overlap with an edge portion of the mounted semiconductor device 140, while the through electrode 134 may not overlap with the mounted semiconductor device 140.

[0040] The internal connection terminal 160 of the semiconductor package 10 may be interposed between the first embedded semiconductor device 130a and the package substrate 110, and thus, the internal connection terminal 160 of the semiconductor package 10 may connect the first embedded semiconductor device 130a to the package substrate 110. For example, the internal connection terminal 160 may be interposed between the first embedded semiconductor device 130a and the lower surface of the groove H1 of the package substrate 110. The internal connection terminal 160 may include a conductive ball and / or a solder ball formed below the through electrode 134, and the internal connection terminal 160 may electrically connect the through electrode 134 to the substrate pattern 111.

[0041] The adhesive layer 170 of the semiconductor package 10 may be interposed between the lower surface of the groove H1 of the package substrate 110 and the first embedded semiconductor device 130a, and may be configured to firmly attach the first embedded semiconductor device 130a to the groove H1 of the package substrate 110. The adhesive layer 170 may be a non-conductive film (NCF), for example, a film formed of an insulating polymer. The adhesive layer 170 may surround the exposed surface of the internal connection terminal 160 and may be located between the package substrate 110 and the first embedded semiconductor device 130a.

[0042] The buried insulating layer 180 of the semiconductor package 10 may fill the space between the inner sidewall of the groove H1 of the package substrate 110 and the side surface of the first embedded semiconductor device 130a. The buried insulating layer 180 may surround the side surface of the first embedded semiconductor device 130a and may cover the upper surface of the first embedded semiconductor device 130a. However, the buried insulating layer 180 may expose the first chip pad 133 of the first embedded semiconductor device 130a by not covering the first chip pad 133. The buried insulating layer 180 may be configured to firmly attach the first embedded semiconductor device 130a to the groove H1 of the package substrate 110. The buried insulating layer 180 may be substantially coplanar with the upper surface of the package substrate 110.

[0043] The buried insulating layer 180 may include an insulating material. For example, the buried insulating layer 180 may include epoxy resin, polybenzoxadiazole (PBO), benzocyclobutene (BCB), polyamide, and / or polyamide derivatives.

[0044] The mounting type semiconductor device 140 may be mounted on the package substrate 110. The mounting type semiconductor device 140 may be connected to the package substrate 110 and the first embedded semiconductor device 130a.

[0045] According to an exemplary embodiment of the inventive concept, the mounting semiconductor device 140 may include a logic semiconductor device, for example, a central processor unit (CPU), a microprocessor unit (MPU), a graphics processor unit (GPU), or an application processor (AP). However, the inventive concept is not limited thereto, and the mounting semiconductor device 140 may include various other types of semiconductor devices.

[0046] The mounted semiconductor device 140 may include a second substrate 141, a second active layer 142, a second chip pad 143a, and a third chip pad 143b. The orientations of the second substrate 141, the second active layer 142, the second chip pad 143a, and the third chip pad 143b of the mounted semiconductor device 140 may be similar to the description of the first embedded semiconductor device 130a and related elements discussed above, and therefore, for the sake of brevity, the description thereof will be omitted.

[0047] According to an exemplary embodiment of the inventive concept, the mounted semiconductor device 140 may be mounted on the package substrate 110 such that the second active layer 142 faces the package substrate 110. Therefore, the second active layer 142 of the mounted semiconductor device 140 may face the first active layer 132 of the first embedded semiconductor device 130a. For example, the second active layer 142 may at least partially overlap the first active layer 132.

[0048] A portion of a lower surface of the mounted semiconductor device 140 may overlap a portion of an upper surface of the first embedded semiconductor device 130 a including the first active layer 132 in a vertical direction.

[0049] The mounted semiconductor device 140 may include a first area A1 and a second area A2. The first area A1 may be an area of ​​the mounted semiconductor device 140 connected to the first embedded semiconductor device 130a, and the second area A2 may be an area of ​​the mounted semiconductor device 140 connected to the package substrate 110. The first area A1 may be an area of ​​the mounted semiconductor device 140 that overlaps with the groove H1 of the package substrate 110 in the vertical direction, and the second area A2 may be an area of ​​the mounted semiconductor device 140 that does not overlap with the groove H1 of the package substrate 110 in the vertical direction. For example, the second area A2 may represent the difference between the total width of the semiconductor device 140 and the first area A1. The first area A1 may be smaller than the second area A2.

[0050] The second chip pad 143a of the mounted semiconductor device 140 may be located in the first area A1 and may be electrically connected to the first chip pad 133 of the first embedded semiconductor device 130a. The third chip pad 143b of the mounted semiconductor device 140 may be located in the second area A2 and may be electrically connected to the substrate pattern 111 of the package substrate 110. For example, the mounted semiconductor device 140 may be connected to the first embedded semiconductor device 130a via the second chip pad 143a. The mounted semiconductor device 140 may be connected to the package substrate 110 via the third chip pad 143b.

[0051] According to an exemplary embodiment of the present invention, the width of a portion of the second chip pad 143a of the second substrate 141 that overlaps with the groove H1 of the package substrate 110 in the vertical direction may be smaller than the width of a portion of the third chip pad 143b of the second substrate 141 that does not overlap with the groove H1 of the package substrate 110 in the vertical direction.

[0052] The first chip connection terminal 150a of the semiconductor package 10 may be interposed between the second chip pad 143a of the mounted semiconductor device 140 and the first chip pad 133 of the first embedded semiconductor device 130a. The first chip connection terminal 150a may electrically connect the first chip pad 133 to the second chip pad 143a. According to an exemplary embodiment of the inventive concept, the first chip connection terminal 150a may overlap the groove H1 of the package substrate 110 in the vertical direction.

[0053] The second chip connection terminal 150b may be interposed between the third chip pad 143b of the mounted semiconductor device 140 and the package substrate 110. The second chip connection terminal 150b may electrically connect the substrate pattern 111 to the third chip pad 143b. According to an exemplary embodiment of the inventive concept, the second chip connection terminal 150b may not overlap the groove H1 of the package substrate 110 in the vertical direction.

[0054] Because the first embedded semiconductor device 130 a and the mounted semiconductor device 140 of the semiconductor package 10 may be electrically connected to each other and may have a short electrical connection path, the first embedded semiconductor device 130 a and the mounted semiconductor device 140 may provide improved driving performance.

[0055] Since the semiconductor package 10 may include the first embedded semiconductor device 130 a inserted into the groove H1 of the package substrate 110 , the semiconductor package 10 may be thin and light.

[0056] Figure 2 is a cross-sectional view of a semiconductor package 20 according to an exemplary embodiment of the inventive concept.

[0057] Reference Figure 2 , the semiconductor package 20 may include a package substrate 110, external connection terminals 120, a second embedded semiconductor device 130b, a mounted semiconductor device 140, a first chip connection terminal 150a, a second chip connection terminal 150b, an adhesive layer 170, and a buried insulating layer 180. The package substrate 110, the external connection terminals 120, the mounted semiconductor device 140, the first chip connection terminal 150a, the second chip connection terminal 150b, the adhesive layer 170, and the buried insulating layer 180 may be the same as those described above with reference to Figure 1 The descriptions provided are similar, and therefore, a detailed description thereof will be omitted for the sake of brevity.

[0058] Reference Figure 2 , the package substrate 110 may include an internal space. The internal space may be buried in the package substrate 110. For example, the package substrate 110 may completely surround the internal space, including the upper surface of the internal space. Therefore, when the package substrate 110 is viewed from the outside, the internal space may not be exposed to the outside.

[0059] As described above, the package substrate 110 may include a substrate pattern 111. Figure 1 , a portion of the substrate pattern 111 covering the upper portion of the inner space may be defined as an upper substrate pattern 111a. For example, the upper substrate pattern 111a may be a portion of the substrate pattern 111 located at a higher level than the inner space. The upper substrate pattern 111a may be spaced apart from the first chip pad 133 (e.g., in a horizontal direction).

[0060] According to an exemplary embodiment of the inventive concept, when the upper substrate patterns 111a are viewed from top to bottom, each of the upper substrate patterns 111a may have a width of about 1 micron to about 7 microns. For example, each of the upper substrate patterns 111a may have a width of about 1 micron to about 5 microns. The distance between the upper substrate patterns 111a may be about 1 micron to about 7 microns. For example, the distance between the upper substrate patterns 111a may be about 1 micron to about 5 microns.

[0061] The second embedded semiconductor device 130b of the semiconductor package 20 may be located in the inner space of the package substrate 110. For example, the second embedded semiconductor device 130b may be located in the inner space of the package substrate 110 so that the first active layer 132 faces the mounted semiconductor device 140. The first active layer 132 of the second embedded semiconductor device 130b may be electrically connected to the upper substrate pattern 111a on the inner space. Therefore, the second embedded semiconductor device 130b may be connected to the external connection terminal 120.

[0062] The second embedded semiconductor device 130b may include a first substrate 131, a first active layer 132, and a first chip pad 133. Figure 1 The first embedded semiconductor device 130a and the second embedded semiconductor device 130b may not include a through electrode. The first substrate 131, the first active layer 132 and the first chip pad 133 of the second embedded semiconductor device 130b may be the same as those described above. Figure 1 The descriptions provided are similar, so a detailed description thereof will be omitted for the sake of brevity.

[0063] The adhesive layer 170 of the semiconductor package 20 may be interposed between the package substrate 110 and the second embedded semiconductor device 130b and may be configured to firmly attach the second embedded semiconductor device 130b to the inner space of the package substrate 110. The adhesive layer 170 may be NCF, for example, a film formed of an insulating polymer.

[0064] The buried insulating layer 180 of the semiconductor package 20 may fill the space between the inner sidewall of the package substrate 110 and the side surface of the second embedded semiconductor device 130b. The buried insulating layer 180 may include an insulating material. For example, the buried insulating layer 180 may include epoxy resin, polybenzodiazole, benzocyclobutene, polyimide and / or a polyimide derivative.

[0065] According to an exemplary embodiment of the inventive concept, the package substrate 110 may cover an upper portion of the second embedded semiconductor device 130b. The upper portion of the second embedded semiconductor device 130b may be a portion of the second embedded semiconductor device 130b in which the first active layer 132 is formed. For example, the substrate insulating layer 112 of the package substrate 110 may cover an upper portion of the second embedded semiconductor device 130b and may still expose a first chip pad 133 of the second embedded semiconductor device 130b. The first chip pad 133 of the second embedded semiconductor device 130b may be electrically connected to a second chip pad 143a of a mounted semiconductor device 140 to be described later.

[0066] The package substrate 110 may include an upper substrate pattern 111a located on an upper portion of the second embedded semiconductor device 130b. The upper substrate pattern 111a may be electrically connected to the substrate pattern 111 located at a lower level than the upper substrate pattern 111a via a conductive via, and may be ultimately electrically connected to the external connection terminal 120. For example, the first active layer 132 of the second embedded semiconductor device 130b may be electrically connected to the external connection terminal 120 via the upper substrate pattern 111a.

[0067] The mounted semiconductor device 140 may include a second substrate 141, a second active layer 142, a second chip pad 143a, and a third chip pad 143b. The mounted semiconductor device 140 may be mounted on the package substrate 110 so that the second active layer 142 faces the package substrate 110. Therefore, the second active layer 142 of the mounted semiconductor device 140 may face the first active layer 132 of the second embedded semiconductor device 130b.

[0068] For example, an edge portion of a lower surface of the mounted semiconductor device 140 may overlap an edge portion of an upper surface of the second embedded semiconductor device 130 b including the first active layer 132 in a vertical direction.

[0069] The mounted semiconductor device 140 may include a first area A1 and a second area A2. The first area A1 may be an area of ​​the mounted semiconductor device 140 connected to the second embedded semiconductor device 130b, and the second area A2 may be an area of ​​the mounted semiconductor device 140 connected to the package substrate 110. The first area A1 may be an area of ​​the mounted semiconductor device 140 that overlaps with the internal space of the package substrate 110 in the vertical direction, and the second area A2 may be an area of ​​the mounted semiconductor device 140 that does not overlap with the internal space of the package substrate 110 in the vertical direction. For example, the second area A2 may represent the difference between the total width of the semiconductor device 140 and the first area A1. The first area A1 may be smaller than the second area A2.

[0070] The second chip pad 143a of the mounted semiconductor device 140 may be located in the first area A1 and may be electrically connected to the first chip pad 133 of the second embedded semiconductor device 130b. The third chip pad 143b of the mounted semiconductor device 140 may be located in the second area A2 and may be electrically connected to the substrate pattern 111 of the package substrate 110. For example, the mounted semiconductor device 140 may be connected to the second embedded semiconductor device 130b via the second chip pad 143a. The mounted semiconductor device 140 may be connected to the package substrate 110 via the third chip pad 143b.

[0071] According to an exemplary embodiment of the present invention, the width of a portion of the second chip pad 143a of the second substrate 141 that overlaps with the internal space of the package substrate 110 in the vertical direction may be smaller than the width of a portion of the third chip pad 143b of the second substrate 141 that does not overlap with the internal space of the package substrate 110 in the vertical direction.

[0072] The first chip connection terminal 150a of the semiconductor package 20 may be interposed between the second chip pad 143a of the mounted semiconductor device 140 and the first chip pad 133 of the second embedded semiconductor device 130b. The first chip connection terminal 150a may electrically connect the first chip pad 133 to the second chip pad 143a. According to an exemplary embodiment of the inventive concept, the first chip connection terminal 150a may overlap with the internal space of the package substrate 110 in the vertical direction.

[0073] The second chip connection terminal 150b may be interposed between the third chip pad 143b of the mounted semiconductor device 140 and the package substrate 110. The second chip connection terminal 150b may electrically connect the substrate pattern 111 to the third chip pad 143b. According to an exemplary embodiment of the inventive concept, the second chip connection terminal 150b may not overlap with the inner space of the package substrate 110 in the vertical direction.

[0074] Because the second embedded semiconductor device 130 b and the mounting semiconductor device 140 of the semiconductor package 20 may be electrically connected to each other and may have a short electrical connection path, the second embedded semiconductor device 130 b and the mounting semiconductor device 140 may provide improved driving performance.

[0075] Since the semiconductor package 20 may include the second embedded semiconductor device 130 b inserted into the inner space of the package substrate 110 , the semiconductor package 20 may be thin and light.

[0076] Figure 3 is a cross-sectional view of a semiconductor package 11 according to an exemplary embodiment of the inventive concept.

[0077] Figure 3 The semiconductor package 11 may include Figure 1 The semiconductor package 10 may further include a molding material 190 and a heat sink 195 .

[0078] According to an exemplary embodiment of the inventive concept, the molding material 190 may be located on the package substrate 110 and at least partially surround the mounted semiconductor device 140. The molding material 190 may be configured to firmly fix the mounted semiconductor device 140 to the package substrate 110. Figure 3 As shown, the molding material 190 may surround at least one side surface of the mounted semiconductor device 140 and at least a portion of the lower surface of the semiconductor device 140, but may not cover the upper surface thereof. However, the inventive concept is not limited thereto, and the molding material 190 may surround both at least one side surface and the upper surface of the mounted semiconductor device 140.

[0079] According to an exemplary embodiment of the inventive concept, the heat sink 195 may be mounted on the molding material 190 and / or the mounted semiconductor device 140. The heat sink 195 may be configured to dissipate heat generated by the mounted semiconductor device 140 and the first embedded semiconductor device 130a to the outside.

[0080] The heat sink 195 may include a metal material having high thermal conductivity. For example, the heat sink 195 may include aluminum (Al), nickel (Ni), copper (Cu), magnesium (Mg) and / or silver (Ag). The heat sink 195 may be attached to the molding material 190 or the mounted semiconductor device 140 through an adhesive film. The adhesive film may be a film having adhesive properties, for example, a double-sided adhesive film.

[0081] Figure 4 is a cross-sectional view of a semiconductor package 21 according to an exemplary embodiment of the inventive concept.

[0082] Figure 4 The semiconductor package 21 may include Figure 2 The semiconductor package 20 may further include a molding material 190 and a heat sink 195. The molding material 190 and the heat sink 195 may be the same as those described above. Figure 3 The descriptions provided are similar, so a detailed description thereof will be omitted for simplicity.

[0083] Figure 5 is a cross-sectional view of a semiconductor package 15 according to an exemplary embodiment of the inventive concept. Figure 5The semiconductor package 15 may be a lower semiconductor package of a package-on-package (PoP) type semiconductor package. The POP type semiconductor package includes a lower semiconductor package and an upper semiconductor package.

[0084] Figure 5 The semiconductor package 15 may include Figure 1 The semiconductor package 10 may further include a conductive pillar 210 , a molding material 190 , and an interposer 30 .

[0085] The conductive pillar 210 of the semiconductor package 15 may be located on the package substrate 110 (e.g., the upper surface) and may be electrically connected to the substrate pattern 111. The conductive pillar 210 may electrically connect the interposer 30 to the package substrate 110. For example, the upper portion of the conductive pillar 210 may be connected to the interposer connection terminal 320, and the lower portion of the conductive pillar 210 may be electrically connected to the substrate pattern 111. The conductive pillar 210 may be arranged adjacent to the side surface of the mounted semiconductor device 140 and may at least partially surround the mounted semiconductor device 140.

[0086] The molding material 190 may be disposed on the package substrate 110 and surround the mounted semiconductor device 140 and the conductive pillar 210. The molding material 190 may include a groove H2 ( Fig.14 ). The conductive pillar 210 exposed through the groove H2 may contact the insert connection terminal 320. For example, the conductive pillar 210 may partially penetrate the molding material 190. The conductive pillar 210 may have an upper end lower than the upper surface of the molding material 190. The lower end of the conductive pillar 210 may be arranged on the substrate pattern 111, and the upper end thereof may be arranged on the lower surface of the groove H2 recessed from the upper surface of the molding material 190.

[0087] The interposer 30 may include an interposer substrate 310 and interposer connection terminals 320 formed under the interposer substrate 310 .

[0088] The interposer substrate 310 may include at least one of a carrier, a PCB, and a wafer. The interposer substrate 310 may include an interposer substrate pattern 311 and an interposer insulating layer 312 at least partially surrounding the interposer substrate pattern 311 .

[0089] The interposer substrate pattern 311 may be electrically connected to the interposer connection terminal 320. The interposer insulating layer 312 may surround the interposer substrate pattern 311. The interposer insulating layer 312 may protect the interposer substrate pattern 311 from external impact and may prevent an electrical short circuit of the interposer substrate pattern 311.

[0090] The interposer connection terminal 320 may be formed under the interposer substrate 310 and may contact the conductive pillar 210. The interposer connection terminal 320 may be electrically connected to the interposer substrate pattern 311. The interposer connection terminal 320 may include a conductive ball and / or a solder ball.

[0091] Figure 6 is a cross-sectional view of a semiconductor package 25 according to an exemplary embodiment of the inventive concept. Figure 6 The semiconductor package 25 may be a lower semiconductor package of a PoP type semiconductor package. The PoP type semiconductor package may include a lower semiconductor package and an upper semiconductor package.

[0092] Figure 6 The semiconductor package 25 may include Figure 2 The semiconductor package 20 may further include a conductive pillar 210, a molding material 190, and an insert 30. The conductive pillar 210, the molding material 190, and the insert 30 may be the same as those described above. Figure 5 The descriptions provided are similar, and therefore, a detailed description thereof will be omitted for the sake of brevity.

[0093] Figure 7 is a cross-sectional view of a semiconductor package 1 according to an exemplary embodiment of the present inventive concept. Figure 7 , the semiconductor package 1 may include Figure 5 The lower semiconductor package 15 and the upper semiconductor package 40 of the PoP type semiconductor package. The lower semiconductor package 15 can be the same as the above reference Figure 5 The descriptions provided are similar.

[0094] According to an exemplary embodiment of the inventive concept, the upper semiconductor package 40 may be mounted on the interposer 30 . The upper semiconductor device 410 of the upper semiconductor package 40 may be connected to the package substrate 110 via the interposer 30 .

[0095] The upper semiconductor package 40 may include an upper semiconductor device 410, an upper package substrate 420, an upper molding material 430, and an upper connection terminal 440. The upper semiconductor device 410 may be a semiconductor device of a different type from the first embedded semiconductor device 130a and the mounted semiconductor device 140. However, the inventive concept is not limited thereto, and the upper semiconductor device 410 may be a semiconductor device of the same type as one of the first embedded semiconductor device 130a and the mounted semiconductor device 140.

[0096] The upper semiconductor device 410 may include a third substrate 411 and a third active layer 412. According to an exemplary embodiment of the inventive concept, the third substrate 411 may include a silicon wafer. The third active layer 412 may be formed on the third substrate 411 and may include a plurality of individual devices of various types. The upper semiconductor device 410 may be mounted on the upper package substrate 420 so that the third active layer 412 faces the upper package substrate 420.

[0097] The upper package substrate 420 may support the upper semiconductor device 410. The upper package substrate 420 may include an upper substrate pattern and an upper substrate insulating layer at least partially surrounding the upper substrate pattern. The upper package substrate 420 may include a PCB. However, the upper package substrate 420 is not limited to the PCB, but may include various substrates such as a ceramic substrate. The upper substrate pattern of the upper package substrate 420 may be electrically connected to the third active layer 412 of the upper semiconductor device 410.

[0098] The upper molding material 430 may be located on the upper package substrate 420 and may at least partially surround the upper semiconductor device 410. The upper molding material 430 may be configured to firmly fix the upper semiconductor device 410 to the upper package substrate 420. The upper molding material 430 may include an insulating polymer and / or an epoxy resin. The upper molding material 430 may at least partially surround the side surface of the upper semiconductor device 410, and may expose the upper surface of the upper semiconductor device 410 to the outside. However, the inventive concept is not limited thereto, and the upper molding material 430 may cover both the side surface and the upper surface of the upper semiconductor device 410, and may not expose the upper surface of the upper semiconductor device 410 to the outside.

[0099] The upper connection terminal 440 may be formed below the upper package substrate 420. For example, the upper connection terminal 440 may be interposed between the upper package substrate 420 and the interposer substrate 310. The upper connection terminal 440 may be electrically connected to the upper substrate pattern of the upper package substrate 420. The upper connection terminal 440 may electrically connect the upper substrate pattern of the upper package substrate 420 to the interposer substrate pattern 311 of the interposer substrate 310.

[0100] The upper semiconductor device 410 of the upper semiconductor package 40 may be connected to the package substrate 110 via the interposer 30 and the conductive pillar 210 .

[0101] Figure 8 is a cross-sectional view of a semiconductor package 2 according to an exemplary embodiment of the present inventive concept. Figure 8 , the semiconductor package 2 may include Figure 6 The lower semiconductor package 25 and the upper semiconductor package 40 of the PoP type semiconductor package. The lower semiconductor package 25 can be the same as the above reference Figure 6The descriptions provided are essentially the same.

[0102] According to an exemplary embodiment of the inventive concept, an upper semiconductor package 40 may be mounted on an interposer 30. An upper semiconductor device 410 of the upper semiconductor package 40 may be connected to a package substrate 110 via the interposer 30. The upper semiconductor package 40 may include an upper semiconductor device 410, an upper package substrate 420, an upper molding material 430, and an upper connection terminal 440. The upper semiconductor package 40 may be similar to the upper semiconductor device 410 of the package substrate 110. Figure 7 The descriptions provided are similar, and therefore, a detailed description thereof will be omitted for the sake of brevity.

[0103] According to an exemplary embodiment of the present inventive concept, the above Figures 1 to 8 The respective connection terminals can be arranged in the grooves.

[0104] Now refer to Figures 9 to 17 A method of manufacturing a semiconductor package according to an exemplary embodiment of the present inventive concept is described. For example, reference will now be made to Figures 9 to 17 Description Manufacturing Figure 7 A method of manufacturing a PoP type semiconductor package.

[0105] Fig. 9 FIG. 1 shows an operation of attaching the protective substrate 109 to the package substrate 110. Referring to FIG. Fig. 9 , a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of attaching a protective substrate 109 to a package substrate 110. The protective substrate 109 may be attached to one surface of the package substrate 110 on which the external connection terminals 120 are formed, and may at least partially surround the external connection terminals 120. In a semiconductor package manufacturing operation to be described later, the protective substrate 109 may protect the external connection terminals 120 from external impacts.

[0106] Fig.10 FIG. 2 shows an operation of forming a groove H1 in the package substrate 110. Referring to FIG. Fig.10 , a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of forming a groove H1 in a package substrate 110. The groove H1 may be formed in the package substrate 110 by, for example, etching or laser drilling. However, the inventive concept is not limited thereto, and the groove H1 may be formed in the package substrate 110 by various other methods.

[0107] According to an exemplary embodiment of the inventive concept, the operation of forming the groove H1 in the package substrate 110 may include an operation of forming the groove H1 in the package substrate 110 so that the substrate pattern 111 is exposed to the outside. The groove H1 of the package substrate 110 may be formed to have a shape corresponding to the shape of the first embedded semiconductor device 130a. The groove H1 of the package substrate 110 may be formed to have a larger volume than the first embedded semiconductor device 130a.

[0108] Fig.11 FIG. 2 shows an operation of inserting the first embedded semiconductor device 130 a into the groove H1 of the package substrate 110 . Fig.11 , a semiconductor package manufacturing method according to an exemplary embodiment of the inventive concept may include an operation of inserting a first embedded semiconductor device 130 a into a groove H1 of a package substrate 110 and an operation of electrically connecting the first embedded semiconductor device 130 a to the package substrate 110 .

[0109] According to an exemplary embodiment of the inventive concept, the first embedded semiconductor device 130a may be inserted into the groove H1 so that the through electrode 134 is electrically connected to the substrate pattern 111 of the package substrate 110. For example, the internal connection terminal 160 formed under the through electrode 134 may be electrically connected to the substrate pattern 111 exposed by the groove H1. The internal connection terminal 160 may be interposed between the through electrode 134 and the substrate pattern 111, and thus the through electrode 134 may be electrically connected to the substrate pattern 111.

[0110] According to an exemplary embodiment of the inventive concept, an adhesive layer 170 may be formed between the package substrate 110 and the first embedded semiconductor device 130a. The adhesive layer 170 may be formed to at least partially surround the internal connection terminal 160. The adhesive layer 170 may firmly attach the first embedded semiconductor device 130a to the groove H1 of the package substrate 110.

[0111] According to an exemplary embodiment of the present inventive concept, a buried insulating layer 180 may be formed in a space between an inner wall of the package substrate 110 and a side surface of the first embedded semiconductor device 130a. The buried insulating layer 180 may at least partially surround the side surface of the first embedded semiconductor device 130a and may cover an upper surface of the first embedded semiconductor device 130a. However, the buried insulating layer 180 may expose the first chip pad 133 of the first embedded semiconductor device 130a to the outside by not covering the first chip pad 133.

[0112] Fig.12An operation of mounting the mount type semiconductor device 140 on the package substrate 110 is shown. A method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of mounting the mount type semiconductor device 140 on the package substrate 110 .

[0113] As described above, the mount type semiconductor device 140 may include a first region A1 vertically overlapping the groove H1 of the package substrate 110 and a second region A2 vertically not overlapping the groove H1 of the package substrate 110. The mount type semiconductor device 140 may include a second chip pad 143a in the first region A1, and may include a third chip pad 143b in the second region A2.

[0114] The first chip connection terminal 150a may be interposed between the first chip pad 133 and the second chip pad 143a, and may electrically connect the first chip pad 133 to the second chip pad 143a. The first chip connection terminal 150a may overlap the groove H1 of the package substrate 110 in a vertical direction. The mounted semiconductor device 140 may be connected to the first embedded semiconductor device 130a via the first chip connection terminal 150a.

[0115] The second chip connection terminal 150b may be interposed between the package substrate 110 and the third chip pad 143b, and may electrically connect the substrate pattern 111 of the package substrate 110 to the third chip pad 143b. The second chip connection terminal 150b may not overlap the groove H1 of the package substrate 110 in the vertical direction. The mounted semiconductor device 140 may be electrically connected to the package substrate 110 via the second chip connection terminal 150b.

[0116] Fig.13 An operation of forming the conductive pillar 210 on the package substrate 110 is illustrated. A method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of forming the conductive pillar 210 on the package substrate 110 .

[0117] The conductive pillar 210 may be formed adjacent to a side surface of the mounted semiconductor device 140. The conductive pillar 210 may at least partially surround the mounted semiconductor device 140. A lower portion of the conductive pillar 210 may contact the substrate pattern 111, and the conductive pillar 210 may be electrically connected to the substrate pattern 111.

[0118] Fig.14 An operation of forming a molding material 190 on a package substrate 110 is shown. A semiconductor package manufacturing method according to an exemplary embodiment of the inventive concept may include an operation of forming a molding material 190 on a package substrate 110 and an operation of forming a groove H2 partially exposing an upper portion of a conductive pillar 210 in the molding material 190.

[0119] According to an exemplary embodiment of the inventive concept, a molding material 190 may be formed on a package substrate 110 to at least partially surround the mounted semiconductor device 140 and the conductive pillar 210. The groove H2 formed in the molding material 190 may partially expose the upper portion of the conductive pillar 210 to the outside. For example, the groove H2 of the molding material 190 may be formed by etching or laser drilling. The conductive pillar 210 exposed through the groove H2 may be connected to the interposer connection terminal 320.

[0120] Fig.15 1 shows an operation of installing the insert 30. The method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of forming the insert 30 on the molding material 190. The insert 30 may be similar to the above-mentioned Figure 5 The descriptions provided are similar.

[0121] According to an exemplary embodiment of the inventive concept, the operation of installing the insert 30 may include connecting the insert connection terminal 320 to the conductive pillar 210. For example, the insert connection terminal 320 may be inserted into the groove H2 formed in the molding material 190 and may contact the conductive pillar 210. According to an exemplary embodiment of the inventive concept, the insert connection terminal 320 may be integrated with the conductive pillar 210 by thermal curing.

[0122] Fig.16 2 shows an operation of mounting the upper semiconductor package 40 on the interposer 30. The method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of mounting the upper semiconductor package 40 on the interposer 30. According to an exemplary embodiment of the inventive concept, the operation of mounting the upper semiconductor package 40 on the interposer 30 may include electrically connecting the interposer 30 to the upper semiconductor package 40. The upper semiconductor package 40 may be connected to the upper semiconductor package 40 as described above with reference to FIG. Figure 7 The descriptions provided are similar.

[0123] For example, the upper connection terminals 440 of the upper semiconductor package 40 may be interposed between the upper package substrate 420 and the interposer substrate 310 , and may be electrically connected to the upper substrate pattern of the upper package substrate 420 .

[0124] Fig.17 1 shows an operation of separating the protective substrate 109 from the package substrate 110. Fig.17 , the method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept may include an operation of separating the protection substrate 109 from the package substrate 110. By separating the protection substrate 109 from the package substrate 110, a PoP type semiconductor package 1 may be manufactured.

[0125] Because the first embedded semiconductor device 130 a and the mounted semiconductor device 140 of the semiconductor package 1 manufactured by the semiconductor package manufacturing method according to the exemplary embodiment of the inventive concept can be electrically connected to each other and can have a short electrical connection path, the first embedded semiconductor device 130 a and the mounted semiconductor device 140 can provide enhanced driving performance.

[0126] Since the semiconductor package 1 manufactured by the semiconductor package manufacturing method according to the exemplary embodiment of the inventive concept may include the first embedded semiconductor device 130 a inserted into the groove H1 of the package substrate 110 , the semiconductor package 1 may be thin and light.

[0127] While exemplary embodiments of the inventive concept have been particularly shown and described above, it should be understood that various changes in form and details may be made in the exemplary embodiments of the inventive concept without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor package, comprising: A package substrate, comprising a substrate pattern and a substrate insulating layer at least partially surrounding the substrate pattern, the package substrate having a groove, the groove exposing a portion of the substrate pattern of the package substrate; External connection terminals arranged below the package substrate; an embedded semiconductor device arranged in the groove of the package substrate, the embedded semiconductor device comprising a first substrate, a first active layer arranged on the first substrate, a first chip pad arranged on the first active layer, and a through electrode penetrating the first substrate and connected to the portion of the substrate pattern; a buried insulating layer disposed in the groove of the package substrate and at least partially surrounding at least a portion of a side surface of the embedded semiconductor device; as well as a mounted semiconductor device disposed on the package substrate and connected to the package substrate and the embedded semiconductor device, The first chip pad overlaps the mounting type semiconductor device in a vertical direction, and the through-electrode does not overlap the mounting type semiconductor device in the vertical direction.

2. The semiconductor package according to claim 1, wherein: The mounted semiconductor device comprises: a second substrate; a second active layer disposed on the second substrate; a second chip pad disposed on the second active layer, the second chip pad being connected to the first chip pad; and a third chip pad disposed on the second active layer, the third chip pad being connected to the substrate pattern, Wherein, the second chip pad overlaps with the groove in the vertical direction.

3. The semiconductor package according to claim 2, wherein: A width of a portion of the second substrate having the second chip pad overlapping the groove in the vertical direction is smaller than a width of a portion of the second substrate having the third chip pad not overlapping the groove in the vertical direction.

4. The semiconductor package according to claim 2, further comprising: a first chip connection terminal disposed between the first chip pad and the second chip pad, the first chip connection terminal electrically connecting the first chip pad to the second chip pad; and a second chip connection terminal disposed between the package substrate and the third chip pad; wherein the second chip connection terminal electrically connects the substrate pattern to the third chip pad, and The embedded semiconductor device is arranged in the groove so that the first active layer faces the mounted semiconductor device.

5. The semiconductor package according to claim 1, further comprising: a molding material disposed on the package substrate, the molding material at least partially surrounding the mounted semiconductor device; as well as A heat sink is arranged on the molding material.

6. The semiconductor package according to claim 1, further comprising: A conductive pillar disposed on the package substrate, the conductive pillar being electrically connected to the substrate pattern; as well as a molding material disposed on the package substrate, the molding material at least partially surrounding the conductive pillar and the mounted semiconductor device, wherein the conductive pillar is formed around the mounted semiconductor device, and The molding material exposes a portion of the conductive column.

7. The semiconductor package according to claim 6, further comprising: an insert arranged on the molding material, wherein The insert comprises: an interposer substrate; and An interposer connection terminal is formed under the interposer substrate and contacts the conductive pillar.

8. A semiconductor package, comprising: a package substrate, comprising a substrate pattern and a substrate insulating layer at least partially surrounding the substrate pattern, the package substrate having an inner space; External connection terminals arranged below the package substrate; an embedded semiconductor device, which is arranged in the inner space of the package substrate and is at least partially surrounded by the package substrate, the embedded semiconductor device comprising a first substrate, a first active layer arranged on the first substrate, and a first chip pad arranged on the first active layer; a buried insulating layer at least partially surrounding at least a portion of a side surface of the embedded semiconductor device; as well as a mounted semiconductor device disposed on the package substrate, the mounted semiconductor device being connected to the package substrate and the embedded semiconductor device, wherein a portion of the lower surface of the mounted semiconductor device overlaps a portion of the upper surface of the embedded semiconductor device including the first active layer in a vertical direction, The substrate insulating layer of the package substrate covers an upper surface of the embedded semiconductor device except an upper surface of the first chip pad of the embedded semiconductor device.

9. The semiconductor package according to claim 8, wherein: A portion of the substrate pattern is arranged over the embedded semiconductor device and overlaps the inner space of the package substrate in the vertical direction, and the portion of the substrate pattern is spaced apart from the first chip pad.

10. The semiconductor package according to claim 8, wherein: The mounted semiconductor device comprises: a second substrate; a second active layer disposed on the second substrate; a second chip pad disposed on the second active layer, the second chip pad being connected to the first chip pad; and a third chip pad disposed on the second active layer, the third chip pad being connected to the substrate pattern, wherein the second chip pad overlaps the internal space in the vertical direction, and Wherein, the third chip pad does not overlap with the internal space in the vertical direction.

11. The semiconductor package according to claim 10, further comprising: a first chip connection terminal disposed between the first chip pad and the second chip pad, the first chip connection terminal electrically connecting the first chip pad to the second chip pad; and a second chip connection terminal disposed between the package substrate and the third chip pad, the second chip connection terminal electrically connecting the substrate pattern to the third chip pad, The embedded semiconductor device is arranged in the inner space so that the first active layer faces the mounted semiconductor device.

12. The semiconductor package according to claim 8, further comprising: A conductive pillar disposed on the package substrate, the conductive pillar being electrically connected to the substrate pattern; a molding material disposed on the package substrate, the molding material at least partially surrounding the conductive pillar and the mounted semiconductor device and exposing a portion of the conductive pillar; as well as an insert, which is arranged on the molding material, Wherein, the insert comprises: an interposer substrate; and An interposer connection terminal is disposed below the interposer substrate and contacts the conductive pillar.

13. A stacked package type semiconductor package, comprising: a lower semiconductor package; as well as an upper semiconductor package disposed on the lower semiconductor package; The lower semiconductor package comprises: a package substrate comprising a substrate pattern and a substrate insulating layer at least partially surrounding the substrate pattern, the package substrate having a groove exposing a portion of the substrate pattern; External connection terminals arranged below the package substrate; an embedded semiconductor device arranged in the groove of the package substrate, the embedded semiconductor device comprising a first substrate, a first active layer arranged on the first substrate, a first chip pad arranged on the first active layer, and a through electrode penetrating the first substrate and connecting the first active layer to the portion of the substrate pattern exposed through the groove; a mounted semiconductor device disposed on the package substrate and connected to the package substrate and the embedded semiconductor device; a conductive pillar disposed on the package substrate and electrically connected to the substrate pattern; a molding material disposed on the package substrate and at least partially surrounding the conductive pillar and the mounted semiconductor device and exposing a portion of the conductive pillar; and an interposer disposed on the molding material, the interposer comprising an interposer substrate and an interposer connection terminal disposed below the interposer substrate and in contact with the conductive pillar, The first chip pad overlaps the mounting type semiconductor device in a vertical direction, and the through-electrode does not overlap the mounting type semiconductor device in the vertical direction.

14. The package-on-package type semiconductor package according to claim 13, wherein: The mounted semiconductor device comprises: a second substrate; a second active layer disposed on the second substrate; a second chip pad disposed on the second active layer and connected to the first chip pad; and a third chip pad disposed on the second active layer and connected to the substrate pattern, wherein the second chip pad overlaps the groove in the vertical direction, and Wherein, the third chip pad does not overlap with the groove in the vertical direction.

15. The package-on-package type semiconductor package according to claim 14, further comprising: a first chip connection terminal disposed between the first chip pad and the second chip pad, the first chip connection terminal electrically connecting the first chip pad to the second chip pad; and a second chip connection terminal disposed between the package substrate and the third chip pad, the second chip connection terminal electrically connecting the substrate pattern to the third chip pad, The embedded semiconductor device is arranged in the groove so that the first active layer faces the mounted semiconductor device.

16. The package-on-package type semiconductor package according to claim 13, further comprising: an internal connection terminal interposed between the through electrode and a lower surface of the groove of the package substrate, the internal connection terminal being configured to electrically connect the through electrode to the substrate pattern; an adhesive layer disposed on the embedded semiconductor device, the adhesive layer at least partially surrounding the internal connection terminal; as well as A buried insulating layer is buried in the groove of the package substrate, and the buried insulating layer at least partially surrounds at least a portion of a side surface of the embedded semiconductor device.

17. The package-on-package type semiconductor package according to claim 16, wherein: The buried insulating layer includes epoxy resin, polybenzoxadiazole, benzocyclobutene, polyamide and / or polyamide derivatives.

18. The package-on-package type semiconductor package according to claim 16, wherein: The buried insulating layer covers an upper surface of the embedded semiconductor device and exposes the first chip pad of the embedded semiconductor device.

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