Method for manufacturing cross-point type semiconductor memory device

Abstract

The present disclosure provides a method for manufacturing a cross-point semiconductor memory device. A method for manufacturing a cross-point semiconductor memory device includes: forming a word line and a cell stack, with a gap between the cell stacks; forming a lower gap filling insulator in the gap; forming an upper gap filling insulator on the lower gap filling insulator; curing the lower gap filling insulator and the upper gap filling insulator to form a gap filling insulator; and forming a bit line on the cell stack and the gap filling insulator. The lower gap filling process can be performed using a first source gas including a first precursor and a second precursor, and the upper gap filling process can be performed using a second source gas including a first precursor and a second precursor, and the volume ratio of the first precursor to the second precursor in the first source gas can be greater than 15:1, and the volume ratio of the first precursor to the second precursor in the second source gas can be less than 15:1.

Description

Technical Field

[0001] Embodiments relate to a cross-point type semiconductor memory device and a method of forming the cross-point type semiconductor memory device using a two-step gap-fill process. Background Art

[0002] As the integration density of semiconductor memory devices increases and patterns become smaller, the aspect ratio of a memory cell stack becomes very large. Summary of the invention

[0003] An embodiment is directed to a method for manufacturing a cross-point type semiconductor memory device, the method comprising: forming a first word line material layer and a first cell stack material layer on an underlayer; patterning the first cell stack material layer and the first word line material layer using a first X-direction trimming process to form a first initial cell stack, a first word line, and a first X-direction gap, wherein the first initial cell stack and the first word line extend in an X-direction, and the first X-direction gap extends in an X-direction between the first initial cell stacks; forming a first lower X-direction gap filling insulator filling the first X-direction gap using a first lower X-direction gap filling process; forming a first upper X-direction gap filling insulator on the first lower X-direction gap filling insulator using a first upper X-direction gap filling process; and forming a first X-direction gap filling insulator by performing a curing process and a planarizing process on the first lower X-direction gap filling insulator and the first upper X-direction gap filling insulator. The first lower X-direction gap-filling process may be performed using a first source gas including a first precursor and a second precursor, the first upper X-direction gap-filling process may be performed using a second source gas including the first precursor and the second precursor, a first volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a second volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.

[0004] Embodiments are also directed to a method for manufacturing a cross-point semiconductor memory device, the method comprising: forming a word line and a cell stack on a base layer, a gap formed between the cell stacks; performing a lower gap filling process to form a lower gap filling insulator in the gap; performing an upper gap filling process to form an upper gap filling insulator on the lower gap filling insulator; curing the lower gap filling insulator and the upper gap filling insulator to form a gap filling insulator; and forming a bit line on the cell stack and the gap filling insulator. The lower gap filling process may be performed using a first source gas including a first precursor and a second precursor, and the upper gap filling process may be performed using a second source gas including a first precursor and a second precursor, the first precursor may include octamethylcyclotetrasiloxane, the second precursor may include at least one of tetramethoxysilane and tetramethyl orthosilicate, a first volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a second volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.

[0005] Embodiments are also directed to a method for manufacturing a cross-point type semiconductor memory device, the method comprising: forming a word line material layer and a cell stack material layer on a base layer; performing an X-direction trimming process to form an initial cell stack and a word line, wherein the initial cell stack and the word line extend in the X-direction, and an X-direction gap extending in the X-direction is formed between the initial cell stacks; forming X-direction spacers on opposite sidewalls of the word line in the X-direction gap and opposite sidewalls of the initial cell stack in the X-direction gap; performing a lower X-direction gap filling process to form a lower X-direction gap filling insulator filling the X-direction gap between the X-direction spacers; performing an upper X-direction gap filling process to form an upper X-direction gap filling insulator on the lower X-direction gap filling insulator; curing and planarizing the lower X-direction gap filling insulator; and The invention relates to a method for forming a cell stack, wherein the cell stack has a column shape and a Y-direction gap extending in the Y direction is formed between the cell stacks; forming a Y-direction spacer on opposite side walls of the cell stack in the Y-direction gap and opposite side walls of the X-direction gap filling insulator in the Y-direction gap; performing a lower Y-direction gap filling process to form a lower Y-direction gap filling insulator filling the Y-direction gap between the Y-direction spacers; performing an upper Y-direction gap filling process to form an upper Y-direction gap filling insulator on the lower Y-direction gap filling insulator; and curing and planarizing the lower Y-direction gap filling insulator and the upper Y-direction gap filling insulator to form a Y-direction gap filling insulator. The lower X-direction gap filling process and the lower Y-direction gap filling process may be performed using a first source gas including a first precursor and a second precursor, the upper X-direction gap filling process and the upper Y-direction gap filling process may be performed using a second source gas including a first precursor and a second precursor, a first volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a second volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become apparent to those skilled in the art by describing in detail example embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1A and Figure 1B A schematic three-dimensional perspective view illustrating a cross-point type semiconductor memory device according to example embodiments.

[0008] Figure 2A and Figure 2B Show Figure 1A The cross-point semiconductor memory devices are respectively along Figure 1A Longitudinal cross-sectional views taken along lines II' and II-II' are shown.

[0009] Figure 3A and Figure 3B Show Figure 1B The cross-point semiconductor memory devices are respectively along Figure 1B Vertical longitudinal cross-sectional views taken along lines III-III' and IV-IV' are shown.

[0010] Figure 4A and FIG. 4B to FIG. 24A and Fig. 24B Shown to form Figures 1A to 3B The stages in the method of a cross-point type semiconductor memory device are shown. DETAILED DESCRIPTION

[0011] Figure 1A and Figure 1B are schematic three-dimensional perspective views of cross-point type semiconductor memory devices 100A and 100B according to example embodiments, respectively.

[0012] Reference Figure 1A , a cross-point type semiconductor memory device 100A according to an example embodiment may include word lines WL extending horizontally and in parallel in an X direction, bit lines BL extending horizontally and in parallel in a Y direction, and a cell stack CS1 disposed at a cross point between the word lines WL and the bit lines BL in a Z direction. The X direction, the Y direction, and the Z direction may be perpendicular to each other.

[0013] The word line WL and the bit line BL may include conductors capable of transmitting electrical signals, respectively. The word line WL may provide a voltage or a current to the cell stack CS1, and the bit line BL may transmit a voltage or a current provided from the word line WL to pass through the cell stack CS1 to an external circuit.

[0014] Each cell stack CS1 may include a memory cell that varies according to a voltage or current supplied from a word line WL. For example, the cell stack CS1 may include a phase change memory cell, a resistance variable memory cell, a magnetoresistive variable memory cell, a conductive bridge memory cell, or various other memory cells.

[0015] Reference Figure 1B , a cross-point type semiconductor memory device 100B according to an example embodiment may include a lower word line WL1 extending horizontally and in parallel in an X direction, a common bit line BLc extending horizontally and in parallel in a Y direction, an upper word line WL2 extending horizontally and in parallel in the X direction, a lower cell stack CS1 disposed at an intersection between the lower word line WL1 and the common bit line BLc in the Z direction, and an upper cell stack CS2 disposed at an intersection between the common bit line BLc and the upper word line WL2 in the Z direction.

[0016] The lower word line WL1, the lower cell stack CS1 and the common bit line BLc may form a lower storage structure, and the upper word line WL2, the upper cell stack CS2 and the common bit line BLc may form an upper storage structure. For example, the lower storage structure and the upper storage structure may have a symmetrical structure sharing the common bit line BLc.

[0017] Figure 2A and Figure 2B The cross-point semiconductor memory device 100A is respectively along Figure 1A Longitudinal cross-sectional views taken along lines II' and II-II' are shown.

[0018] Reference Figure 2A and Figure 2B , the cross-point type semiconductor memory device 100A may include a word line 20 , a cell stack CS1 , and a bit line 50 stacked on a base layer 10 .

[0019] The base layer 10 may include a substrate or an insulator (such as silicon dioxide (SiO 2 ) or silicon nitride (SiN)).

[0020] Each word line 20 may include a word line electrode 22 and a word line barrier 23. The word line electrode 22 may extend in a first horizontal direction (i.e., the X direction). The word line electrode 22 may include, for example, a metal such as tungsten (W), and the word line barrier 23 may include, for example, a barrier material such as titanium nitride (TiN). In an example embodiment, the word line barrier 23 may be inserted between the cell stack CS1 and the word line electrode 22 to form an island shape. In an example embodiment, the word line barrier 23 may extend in a line shape along the word line electrode 22 in the first horizontal direction. For example, the word line barrier 23 may be conformally formed on the word line electrode 22. In an example embodiment, an additional barrier including the same material as the word line barrier 23 may be further formed between the base layer 10 and the word line electrode 22.

[0021] The cell stack CS1 may have a square pillar shape. Each of the cell stacks CS1 may include a switching element 30 , a memory element 40 , and an upper electrode 45 .

[0022] The switching element 30 may include a lower electrode 31, a switch electrode 32, and an intermediate electrode 33. The lower electrode 31 and the intermediate electrode 33 may include a metal, or a non-metal conductor such as N-doped carbon. The switch electrode 32 may include a bidirectional threshold switch (OTS) material. For example, the OTS material may include at least one of various chalcogenide materials, the chalcogenide material including, for example, selenium (Se) and also including at least one of arsenic (As), germanium (Ge), silicon (Si), and indium (In).

[0023] Each storage element 40 may include a lower interface 41, a storage unit 42, and an upper interface 43. The lower interface 41 and the upper interface 43 may include a conductor capable of adjusting a threshold voltage or a work function. For example, the lower interface 41 and the upper interface 43 may include a metal (such as tungsten (W), aluminum (Al), titanium (Ti)), a metal alloy, or a metal compound. The storage unit 42 may include a resistance variable material, a phase change material, a magnetoresistive variable material, a conductive bridge material, or various other variable resistance materials. In an example embodiment, the storage unit 42 may include a phase change material, such as GeSbTe (GST).

[0024] The upper electrode 45 may include a metal, or a non-metal conductor such as N-doped carbon. For example, the upper electrode 45 may include the same material as the lower electrode 31 or the intermediate electrode 33 .

[0025] The bit line 50 may extend in parallel in the second horizontal direction (ie, the Y direction). The first horizontal direction and the second horizontal direction may be perpendicular to each other. The bit line 50 may include a metal, such as tungsten (W). In an example embodiment, an additional barrier material layer may be further formed between the upper electrode 45 and the bit line 50.

[0026] The X-direction spacer Sx1 and the Y-direction spacer Sy1 may be conformally formed on the sidewalls of the word line 20, the sidewalls of the cell stack CS1, and the sidewalls of the bit line 50, respectively. Figure 2A , along the Figure 1A In the longitudinal cross-sectional view taken along line II′ of FIG. 1 , the Y-direction spacer Sy1 may be formed on two or opposite sidewalls of the cell stack CS1 and two or opposite sidewalls of the bit line 50. Figure 2B , along the Figure 1A In the longitudinal cross-sectional view taken along line II-II', the X-direction spacer Sx1 may be conformally formed on two or opposite sidewalls of the word line 20 and two or opposite sidewalls of the cell stack CS1. The X-direction spacer Sx1 and the Y-direction spacer Sy1 may include an insulator such as silicon nitride (SiN).

[0027] The X-direction gap-filling insulator 53x and the Y-direction gap-filling insulator 53y may be formed between the word lines 20, between the cell stacks CS1, and / or between the bit lines 50, for example, between the X-direction spacers Sx1 and between the Y-direction spacers Sy1, respectively. Figure 2A , along the Figure 1A In the longitudinal cross-sectional view taken along line II' of FIG. 1 , the Y-direction gap-filling insulator 53y may be formed between the Y-direction spacers Sy1 on two or opposite sidewalls of the cell stack CS1 and two or opposite sidewalls of the bit line 50. Figure 2B , along the Figure 1AIn the longitudinal cross-sectional view taken along line II-II' of FIG. 1 , the X-direction gap-filling insulator 53x may be formed between the X-direction spacers Sx1 on two or opposite sidewalls of the word line 20 and two or opposite sidewalls of the cell stack CS1. The X-direction gap-filling insulator 53x and the Y-direction gap-filling insulator 53y may include an insulator such as silicon dioxide (SiO 2 ), silicon oxycarbide (SiOC), or silicon hydroxide carbon (SiOHC). In an example embodiment, the X-direction gap-filling insulator 53x and the Y-direction gap-filling insulator 53y may include silicon oxycarbide (SiOC).

[0028] The upper surfaces of the upper electrode 45 of the cell stack CS1, the upper surfaces of the X-direction spacer Sx1, and the upper surfaces of the X-direction gap-filling insulator 53x may be coplanar. The upper surfaces of the bit line 50, the upper surfaces of the Y-direction spacer Sy1, and the upper surfaces of the Y-direction gap-filling insulator 53y may also be coplanar.

[0029] The cross-point semiconductor memory device 100A may further include a cap liner 95 and a cap insulator 96 on the bit line 50. The cap liner 95 may include a barrier material layer or an oxidation-resistant insulator. In an example embodiment, the cap liner 95 may include a conductive barrier material such as titanium nitride (TiN). In an example embodiment, the cap liner 95 may include an insulator such as silicon nitride (SiN). In an example embodiment, the cap liner 95 may be a double layer having a bottom layer and a top layer, the bottom layer including a conductive barrier material, and the top layer including an insulator. In an example embodiment, the cap liner 95 may be formed only on the bit line 50. The cap insulator 96 may include an insulator such as silicon dioxide (SiO 2 ).

[0030] Figure 3A and Figure 3B The cross-point semiconductor memory device 100B is respectively along Figure 1B The vertical longitudinal sectional view taken along the lines III-III' and IV-IV' shown in FIG. Figure 3A and Figure 3B Description and about Figures 15A-24B In the description of Figure 2A and Figure 2B Similar reference numerals will be used in the drawings and “first” and “second” will be used to distinguish between lower and upper elements.

[0031] Reference Figure 3A and Figure 3B, a cross-point type semiconductor memory device 100B according to an example embodiment may include a first word line 20 , a first cell stack CS1 , a common bit line 50 , a second cell stack CS2 , and a second word line 90 stacked on a base layer 10 .

[0032] Each of the first word lines 20 may include a first word line electrode 22 and a first word line barrier 23 .

[0033] Each of the first cell stacks CS1 may include a first switching element 30 , a first memory element 40 , and a first upper electrode 45 .

[0034] The first switching element 30 may include a first lower electrode 31 , a first switching electrode 32 , and a first intermediate electrode 33 .

[0035] The first storage element 40 may include a first lower interface 41 , a first storage unit 42 , and a first upper interface 43 .

[0036] The first X-direction spacer Sx1 and the first Y-direction spacer Sy1 may be conformally formed on both or opposite sidewalls of the first word line 20 , both or opposite sidewalls of the first cell stack CS1 , and both or opposite sidewalls of the common bit line 50 .

[0037] First X-direction gap-filling insulators 53x and first Y-direction gap-filling insulators 53y may be formed between first word lines 20 , between first cell stacks CS1 , and / or between common bit lines 50 , for example, between first X-direction spacers Sx1 and between first Y-direction spacers Sy1 , respectively.

[0038] The base layer 10, the first word line 20, the first cell stack CS1, the common bit line 50, the first X-direction spacer Sx1, the first Y-direction spacer Sy1, the first X-direction gap filling insulator 53x and the first Y-direction gap filling insulator 53y can refer to Figure 2A and Figure 2B understand.

[0039] Each of the second cell stacks CS2 may include a second lower electrode 60 , a second memory element 70 , and a second switching element 80 .

[0040] The second lower electrode 60 may include a metal, or a non-metal conductor such as N-doped carbon. The first upper electrode 45 and the second lower electrode 60 may include the same material.

[0041] The second storage element 70 may include a second lower interface 71 , a second storage unit 72 , and a second upper interface 73 .

[0042] The second lower interface 71 may include the same material as the first upper interface 43, and the second upper interface 73 may include the same material as the first lower interface 41. In an example embodiment, the second lower interface 71 and the second upper interface 73 may include the same material. The second storage unit 72 may include the same material as the first storage unit 42.

[0043] The second switching element 80 may include a second intermediate electrode 81, a second switch electrode 82, and a second upper electrode 83. The second intermediate electrode 81 may include the same material as the first intermediate electrode 33. The second upper electrode 83 may include the same material as the first lower electrode 31. The second switch electrode 82 may include the same material as the first switch electrode 32.

[0044] Each second word line 90 may include a second word line barrier 91 and a second word line electrode 92. The second word line barrier 91 and the second word line electrode 92 may extend in a first horizontal direction (ie, the X direction). The second word line barrier 91 may include the same material as the first word line barrier 23. The second word line electrode 92 may include the same material as the first word line electrode 22.

[0045] The second X-direction spacer Sx2 and the second Y-direction spacer Sy2 may be conformally formed on the sidewalls of the second cell stack CS2 and / or the sidewalls of the second word line 90. Figure 3A , the second Y-direction spacer Sy2 may be conformally formed on two or opposite sidewalls of the second unit stack CS2. Figure 3B , the second X-direction spacer Sx2 may be conformally formed on two or opposite sidewalls of the second cell stack CS2 and two or opposite sidewalls of the second word line 90. The second X-direction spacer Sx2 and the second Y-direction spacer Sy2 may include the same material as the first X-direction spacer Sx1 and the first Y-direction spacer Sy1. The second X-direction gap-filling insulator 57x and the second Y-direction gap-filling insulator 57y may be formed between the second cell stack CS2 and / or between the second word lines 90, for example, between the second X-direction spacers Sx2 and between the second Y-direction spacers Sy2, respectively. The second X-direction gap-filling insulator 57x and the second Y-direction gap-filling insulator 57y may include the same material as the first X-direction gap-filling insulator 53x and the first Y-direction gap-filling insulator 53y.

[0046] The second word line barrier 91 may be disposed between the second word line electrode 92 and the second upper electrode 83 , between the second word line electrode 92 and the second Y-direction spacer Sy2 , and between the second word line electrode 92 and the second Y-direction gap-filling insulator 57 y to extend in the horizontal direction.

[0047] Figure 3A and Figure 3B The first cell stack CS1 and the second cell stack CS2 shown may have a vertically symmetrical structure. For example, the first cell stack CS1 may have a stack structure that is a mirror image of the second cell stack CS2. The first cell stack CS1 may receive an electrical signal from the first word line 20 and provide data information of the first memory cell 42 to the common bit line 50, and the second cell stack CS2 may receive an electrical signal from the second word line 90 and provide data information of the second memory cell 72 to the common bit line 50. The first memory cell 42 may store information of the electrical signal received from the first word line 20, and the second memory cell 72 may store information of the electrical signal received from the second word line 90.

[0048] The cross-point type semiconductor memory device 100B may further include a cap pad 95 and a cap insulator 96 on the second word line 90 .

[0049] Figure 4A and FIG. 4B to FIG. 14A and Fig. 14B It is used to describe the formation Figure 1A , Figure 2A and Figure 2B FIG. 1 is a diagram showing a method of implementing a cross-point type semiconductor memory device 100A.

[0050] Reference Figure 4A and Figure 4B The method of forming the cross-point type semiconductor memory device 100A may include forming a word line material layer 20 a and a cell stack material layer CS1 a on an underlying layer 10 .

[0051] The base layer 10 may include a substrate or an insulating material layer formed on the substrate. For example, the base layer 10 may include a silicon substrate, silicon dioxide (SiO 2 ) layer, silicon nitride (SiN) layer or other insulating material layer.

[0052] Forming the word line material layer 20a may include sequentially performing a deposition process to form a word line electrode material layer 22a and a word line barrier material layer 23a on the base layer 10. The word line barrier material layer 23a may include, for example, a material that prevents atomic diffusion and enhances adhesion to the word line electrode material layer 22a and the cell stack material layer CS1a, such as titanium nitride (TiN). The word line electrode material layer 22a may include a conductor having a low resistivity. For example, the word line electrode material layer 22a may include a metal, such as tungsten (W). In an example embodiment, a barrier material layer having the same material as the word line barrier material layer 23a may be further formed between the base layer 10 and the word line electrode material layer 22a.

[0053] Forming the cell stack material layer CS1a may include forming a switching element material layer 30a, a memory element material layer 40a, and an upper electrode material layer 45a on the word line material layer 20a.

[0054] Forming the switching element material layer 30a may include performing a deposition process to sequentially form a lower electrode material layer 31a, a switch electrode material layer 32a, and an intermediate electrode material layer 33a on the word line material layer 20a. For example, the lower electrode material layer 31a and the intermediate electrode material layer 33a may include a non-metallic material, such as carbon. In an example embodiment, the lower electrode material layer 31a and the intermediate electrode material layer 33a may include N-doped carbon. For example, the N-doped carbon may include n-type impurities, such as phosphorus (P), arsenic (As), and / or antimony (Sb). The switch electrode material layer 32a may include a bidirectional threshold switch (OTS) material.

[0055] Forming the storage element material layer 40a may include performing a deposition process to sequentially form a lower interface material layer 41a, a storage cell material layer 42a, and an upper interface material layer 43a. Forming the lower interface material layer 41a and the upper interface material layer 43a may include performing a deposition process to form a metal layer, such as tungsten (W). Forming the storage cell material layer 42a may include performing a deposition process to form a resistance variable material, a phase change material, a magnetoresistive variable material, a conductive bridge material, or various other variable resistance materials. Forming the upper electrode material layer 45a may include performing a deposition process to form a non-metallic material layer including a material such as carbon. The upper electrode material layer 45a may include the same material as the lower electrode material layer 31a or the intermediate electrode material layer 33a.

[0056] Reference Figure 5A and Figure 5B , the method may include patterning the cell stack material layer CS1a and the word line material layer 20a by performing an X-direction trimming process to form an initial cell stack CS1p and a word line 20. The initial cell stack CS1p may include an initial switching element 30b, an initial storage element 40b, and an initial upper electrode 45b. The initial switching element 30b may include an initial lower electrode 31b, an initial switching electrode 32b, and an initial intermediate electrode 33b. The initial storage element 40b may include an initial lower interface 41b, an initial storage cell 42b, and an initial upper interface 43b. The word line 20 may include a word line electrode 22 and a word line barrier 23. The initial cell stack CS1p may have a dam or wall shape extending in the X direction. The word line 20 may extend horizontally in the X direction. An X-direction gap Gx1 having a groove shape extending in the X direction may be formed between the initial cell stacks CS1p to selectively expose the surface of the underlying layer 10.

[0057] Reference Fig. 6A and Figure 6BThe method may include conformally forming an X-direction spacer Sx1 on two or opposite sidewalls of the word line 20 and two or opposite sidewalls of the initial cell stack CS1p. The X-direction spacer Sx1 may extend in the X-direction along the word line 20 and the initial cell stack CS1p. The X-direction spacer Sx1 may include an insulating material such as silicon nitride (SiN).

[0058] Reference Fig. 7A and Figure 7B , the method may include performing a lower X-direction gap-filling process to form a lower X-direction gap-filling insulator 51 x filling the X-direction gap Gx1 .

[0059] The lower X-direction gap filling process may be performed using a first source gas. The first source gas may include a first precursor and a second precursor. The first precursor may be suitable for forming a layer of a gap filling material having relatively good flowability or low viscosity, and the second precursor may be suitable for forming a layer of a gap filling material having relatively low flowability or good viscosity. The first precursor may include, for example, octamethylcyclotetrasiloxane (OMCTS), and the second precursor may include, for example, tetramethoxysilane and / or tetramethyl orthosilicate (TMOS).

[0060] In the first source gas, the volume ratio of the first precursor to the second precursor may be greater than 15:1. For example, the volume ratio of the first precursor to the second precursor may be about 20:1 to 50:1. The lower X-direction gap filling insulator 51x formed by the lower X-direction gap filling process may have excellent flowability and an appropriate amount of the second precursor. Therefore, the lower X-direction gap filling insulator 51x may be formed before leaking to the peripheral area PA (see Figure 7C ) before fully filling the cell area CA (see Figure 7C ) in the X-direction gap Gx1 between the initial unit stacks CS1p.

[0061] Reference Figure 7C , the lower X-direction gap-filling insulator 51x may fill the X-direction gap Gx1 in the cell area CA and may be formed slightly thin on the base layer 10 in the peripheral area PA. For example, the top surface of the lower X-direction gap-filling insulator 51x may be coplanar with or slightly higher than the top surface of the initial upper electrode 45b of the initial cell stack CS1p. In the present example embodiment, the top surface of the lower X-direction gap-filling insulator 51x is shown to be located at a level slightly higher than the top surface of the initial upper electrode 45b.

[0062] In the lower X-direction gap-filling process, the word line 20 and the initial cell stack CS1p may have a dam shape extending in the X-direction. Therefore, the lower X-direction gap-filling insulator 51x may quickly fill the X-direction gap Gx1 in the cell area CA. The lower X-direction gap-filling insulator 51x may be formed faster in the cell area CA than in the peripheral area PA.

[0063] In the first source gas, when the volume ratio of the first precursor is too high, the lower X-direction gap filling insulator 51x may leak into the peripheral area PA before filling the X-direction gap Gx1. If the volume ratio of the first precursor is not high enough, the lower X-direction gap filling insulator 51x cannot sufficiently fill the X-direction gap Gx1, and a gap or a void may be generated at the top position of the initial cell stack CS1p and an over-hang shape may be formed.

[0064] Reference Fig. 8A and Figure 8B , the method may include performing an upper X-direction gap filling process to form an upper X-direction gap filling insulator 52x on the lower X-direction gap filling insulator 51x. The upper X-direction gap filling process may be performed using a second source gas. The second source gas may also include a first precursor and a second precursor. In the second source gas, a volume ratio of the first precursor to the second precursor may be less than 15:1, for example, a volume ratio of the first precursor to the second precursor may be about 1:1 to 10:1, and in an example embodiment, the second source gas includes a higher volume ratio of the second precursor than the first source gas.

[0065] Reference Figure 8C , the upper X-direction gap filling insulator 52x may have good uniformity overall. For example, the upper X-direction gap filling insulator 52x may be formed to have substantially uniform or similar thickness in the cell area CA and the peripheral area PA. The upper X-direction gap filling insulator 52x may have a sufficiently thick thickness.

[0066] According to the present example embodiment, the second source gas includes a second precursor having a higher volume ratio than the first source gas. Therefore, the upper X-direction gap filling insulator 52x may have a relatively better consistency than the lower X-direction gap filling insulator 51x. Therefore, the upper X-direction gap filling insulator 52x may be formed to a sufficient thickness on the lower X-direction gap filling insulator 51x in the cell area CA. In the present example embodiment, the upper X-direction gap filling insulator 52x substantially covers the lower X-direction gap filling insulator 51x without filling the X-direction gap Gx1, but it may be referred to as a gap filling insulator rather than a covering insulator.

[0067] In an example embodiment, when the curing process is performed, the volume of the lower X-direction gap-filling insulator 51 x is reduced. Therefore, the upper X-direction gap-filling insulator 52 x may partially fill the inside of the X-direction gap Gx1.

[0068] Reference Fig.9A and Fig. 9B The method may include curing and planarizing the lower X-direction gap filling insulator 51x and the upper X-direction gap filling insulator 52x by performing a curing process and a planarizing process to form an X-direction gap filling insulator 53x. The curing process may include a UV curing process using ultraviolet (UV) light. 3 Compared with the UV curing process and the thermal curing process, the UV curing process can more effectively discharge the internal moisture or solvent components to the outside in a shorter time. The planarization process may include a chemical mechanical polishing (CMP) process.

[0069] Refer again Figure 8C , the upper X-direction gap filling insulator 52x is formed thick enough to compensate for the volume reduction during the curing of the lower X-direction gap filling insulator 51x and the upper X-direction gap filling insulator 52x. If the upper X-direction gap filling insulator 52x is not sufficiently formed on the lower X-direction gap filling insulator 51x, the X-direction gap filling insulator 53x may not sufficiently fill the X-direction gap Gx1, or a gap or a void may be formed in the X-direction gap Gx1.

[0070] Refer again Fig.9A and Fig. 9B In this process, the top surface of the X-direction gap-filling insulator 53 x and the top surface of the preliminary upper electrode 45 b may be coplanar.

[0071] Reference Fig. 10A and Fig. 10B The method may include performing a deposition process to form a bit line material layer 50a on the initial upper electrode 45b, the X-direction spacer Sx1, and the X-direction gap filling insulator 53x. The bit line material layer 50a may include a conductive material. In an example embodiment, the bit line material layer 50a may include a metal such as tungsten (W).

[0072] Reference Fig.11A and Fig. 11B, the method may include selectively removing the bit line material layer 50a, the initial cell stack CS1p, the X-direction spacer Sx1, and the X-direction gap filling insulator 53x by performing a Y-direction trimming process to form the bit line 50 and the cell stack CS1. The bit line 50 may extend horizontally and in parallel in the Y direction. The cell stack CS1 may have a column shape. A Y-direction gap Gy1 having a groove shape extending in the Y direction may be formed between the cell stacks CS1 and between the bit lines 50 to selectively expose the surface of the word line 20.

[0073] Reference Fig. 12A and Fig. 12B , the method may include conformally forming a Y-direction spacer Sy1 on two or opposite sidewalls of the bit line 50, two or opposite sidewalls of the cell stack CS1, two or opposite sidewalls of the X-direction spacer Sx1, and two or opposite sidewalls of the X-direction gap-filling insulator 53x. The Y-direction spacer Sy1 may extend in the Y direction along the cell stack CS1, the bit line 50, the X-direction spacer Sx1, and the X-direction gap-filling insulator 53x. The Y-direction spacer Sy1 may include an insulating material such as silicon nitride (SiN).

[0074] Reference Fig.13A and Fig. 13B , the method may include performing a lower Y-direction gap filling process for forming a lower Y-direction gap filling insulator 51y filling the Y-direction gap Gy1 and an upper Y-direction gap filling process for forming an upper Y-direction gap filling insulator 52y on the lower Y-direction gap filling insulator 51y. The lower Y-direction gap filling process may be performed under process conditions substantially the same as or similar to the above-described lower X-direction gap filling process. For example, the lower Y-direction gap filling process may be performed using a third source gas substantially the same as the first source gas. Reference may be made to Figure 7C Understand the profile of the Y-direction gap-filling insulator 51y.

[0075] For example, the lower Y-direction gap filling insulator 51y may fill the Y-direction gap Gy1 in the cell area CA and may be thinly formed in the peripheral area PA. The top surface of the lower Y-direction gap filling insulator 51y may be coplanar with the top surface of the bit line 50 or slightly higher than the top surface of the bit line 50. In this embodiment, the top surface of the lower Y-direction gap filling insulator 51y is shown to be located at a level slightly higher than the top surface of the bit line 50.

[0076] The upper Y-direction gap-filling process may be performed under substantially the same process conditions as the upper X-direction gap-filling process described above. For example, the upper Y-direction gap-filling process may be performed using a fourth source gas substantially the same as the second source gas.

[0077] You can refer to Figure 8C Understand the profile of the upper Y-direction gap filling insulator 52y. The upper Y-direction gap filling insulator 52y can have good consistency overall. The upper Y-direction gap filling insulator 52y can be thick enough.

[0078] Reference Fig.14A and Fig. 14B The method may include curing and planarizing the lower Y-direction gap filling insulator 51y and the upper Y-direction gap filling insulator 52y by performing a curing process and a planarizing process to form a Y-direction gap filling insulator 53y. In this process, the upper surface of the Y-direction spacer Sy1, the upper surface of the Y-direction gap filling insulator 53y, and the upper surface of the bit line 50 may be coplanar.

[0079] Then, refer again Figure 2A and Figure 2B , the method may further include forming a cap liner 95 and a cap insulator 96 on the planarized Y-direction gap filling insulator 53y, the Y-direction spacer Sy1, and the bit line 50. Forming the cap liner 95 may include performing a deposition process to conformally form an insulator on the Y-direction gap filling insulator 53y, the Y-direction spacer Sy1, and the bit line 50. For example, the cap liner 95 may include silicon nitride (SiN), which may be denser than the X-direction gap filling insulator 53x and the Y-direction gap filling insulator 53y. Forming the cap insulator 96 may include performing a deposition process to form an insulator layer thicker than the cap liner 95. For example, the cap insulator 96 may include silicon dioxide (SiO 2 ), which may be softer than the cover liner 95.

[0080] Fig.15A and FIG. 15B to FIG. 24A and Fig. 24B is a diagram for describing a method of forming a cross-point type semiconductor memory device 100B according to an example embodiment. Figure 4A and Figure 4B Initially referring briefly again to the above-described processes, the formation of the second unit stack according to the present example embodiment will then be described.

[0081] In this example embodiment, the method may include executing the above reference Figure 4A and Figure 4BThe process described is to form a first word line material layer 20a and a first cell stack material layer CS1a on the base layer 10. Forming the first word line material layer 20a may include forming a first word line electrode material layer 22a and a first word line barrier material layer 23a. Forming the first cell stack material layer CS1a may include forming a first switching element material layer 30a, a first storage element material layer 40a, and a first upper electrode material layer 45a on the first word line material layer 20a. Forming the first switching element material layer 30a may include performing a deposition process to sequentially form a first lower electrode material layer 31a, a first switch electrode material layer 32a, and a first intermediate electrode material layer 33a. Forming the first storage element material layer 40a may include performing a deposition process to sequentially form a first lower interface material layer 41a, a first storage cell material layer 42a, and a first upper interface material layer 43a.

[0082] The method may then include:

[0083] By executing the reference Figure 5A and Figure 5B The described first X-direction trimming process patterns the first cell stack material layer CS1a and the first word line material layer 20a to form a first initial cell stack CS1p, a first word line 20 and a first X-direction gap Gx1;

[0084] By executing the reference Fig. 6A and Figure 6B The described process conformally forms a first X-direction spacer Sx1 on two or opposite sidewalls of the first initial cell stack CS1p;

[0085] By executing the reference 7A to 7C The described process forms a first lower X-direction gap filling insulator 51x filling the first X-direction gap Gx1;

[0086] By executing the reference FIG. 8A to FIG. 8C The first upper X-direction gap-filling process described above forms a first upper X-direction gap-filling insulator 52x on the first lower X-direction gap-filling insulator 51x;

[0087] By executing the reference Fig.9A and Fig. 9B The described process forms a first X-direction gap-filling insulator 53x;

[0088] By executing the reference Fig. 10A and Fig. 10B According to the described process, a common bit line material layer 50a is formed on the first preliminary upper electrode 45b of the first preliminary cell stack CSlp, the first X-direction spacer Sx1 and the first X-direction gap-filling insulator 53x;

[0089] By executing the reference Fig.11A and Fig. 11B The first Y-direction trimming process described above is used to pattern the common bit line material layer 50a, the first initial cell stack CSlp, the first X-direction spacer Sxl and the first X-direction gap filling insulator 53x to form the common bit line 50, the first cell stack CSl and the first Y-direction gap Gyl;

[0090] By executing the reference Fig. 12A and Fig. 12B The described process conformally forms a first Y-direction spacer Sy1 on two or opposite sidewalls of the first cell stack CS1, two or opposite sidewalls of the first X-direction spacer Sx1, two or opposite sidewalls of the first X-direction gap-filling insulator 53x, and two or opposite sidewalls of the common bit line 50;

[0091] By executing the reference Fig.13A and Fig. 13B The process described above forms a first lower Y-direction gap-filling insulator 51y and a first upper Y-direction gap-filling insulator 52y; and

[0092] By executing the reference Fig.14A and Fig. 14B The first Y-direction gap-filling insulator 53 y is formed by the process described above.

[0093] In this example implementation, refer to Fig.15A and Fig. 15B, the method may include sequentially forming a second cell stack material layer CS2a on the common bit line 50, the first Y-direction spacer Sy1, and the first Y-direction gap filling insulator 53y by performing a deposition process. The second cell stack material layer CS2a may include a second lower electrode material layer 60a, a second storage element material layer 70a, and a second switching element material layer 80a. The second storage element material layer 70a may include a second lower interface material layer 71a, a second storage cell material layer 72a, and a second upper interface material layer 73a. The second switching element material layer 80a may include a second intermediate electrode material layer 81a, a second switch electrode material layer 82a, and a second upper electrode material layer 83a. The second lower electrode material layer 60a may include the same material as the first upper electrode material layer 45a, the second lower interface material layer 71a may include the same material as the first upper interface material layer 43a, the second storage cell material layer 72a may include the same material as the first storage cell material layer 42a, the second upper interface material layer 73a may include the same material as the first lower interface material layer 41a, the second intermediate electrode material layer 81a may include the same material as the first intermediate electrode material layer 33a, the second switch electrode material layer 82a may include the same material as the first switch electrode material layer 32a, and the second upper electrode material layer 83a may include the same material as the first lower electrode material layer 31a.

[0094] Reference Fig.16A and Fig. 16B , the method may include forming a second initial cell stack CS2p by performing a second Y-direction trimming process. A second Y-direction gap Gy2 may be formed between the second initial cell stacks CS2p. Each second initial cell stack CS2p may include a second initial lower electrode 60b, a second initial storage element 70b, and a second initial switching element 80b. The second initial storage element 70b may include a second initial lower interface 71b, a second initial storage cell 72b, and a second initial upper interface 73b. The second initial switching element 80b may include a second initial intermediate electrode 81b, a second initial storage cell 82b, and a second initial upper electrode 83b.

[0095] Reference Fig.17A and Fig. 17B , the method may include conformally forming a second Y-direction spacer Sy2 on both or opposite sidewalls of the second preliminary cell stack CS2p.

[0096] Reference Fig.18A and Fig.18B The method may include forming a second lower Y-direction gap filling insulator 55y and a second upper Y-direction gap filling insulator 56y to fill the second Y-direction gap Gy2. This process may refer to 7A to 7C and FIG. 8A to FIG. 8C Understand in more detail.

[0097] For example, the second lower Y-direction gap filling insulator 55y can be formed by a second lower Y-direction gap filling process using a fifth source gas substantially the same as the first source gas, and the second upper Y-direction gap filling insulator 56y can be formed by a second upper Y-direction gap filling process using a sixth source gas substantially the same as the second source gas.

[0098] Reference Fig.19A and Fig.19B The method may include forming a second Y-direction gap-filling insulator 57y by performing a curing process and a planarizing process to cure and planarize the second lower Y-direction gap-filling insulator 55y and the second upper Y-direction gap-filling insulator 56y.

[0099] Reference Fig. 20A and Fig. 20B , the method may include forming a second word line material layer 90a on the second initial cell stack CS2p, the second Y-direction spacer Sy2, and the second Y-direction gap-filling insulator 57y. Forming the second word line material layer 90a may include forming a second word line barrier material layer 91a and a second word line electrode material layer 92a. The second word line barrier material layer 91a may include the same material as the first word line barrier material layer 23a, and the second word line electrode material layer 92a may include the same material as the first word line electrode material layer 22a.

[0100] Reference Fig.21A and Fig. 21B The method may include forming second word lines 90 and second cell stacks CS2 by performing a second X-direction trimming process. A second X-direction gap Gx2 may be formed between the second cell stacks CS2 and between the second word lines 90. The second word line 90 may include a second word line barrier 91 and a second word line electrode 92.

[0101] Reference Fig.22A and Fig. 22B The method may include conformally forming a second X-direction spacer Sx2 on two or opposite sidewalls of the second cell stack CS2 and two or opposite sidewalls of the second word line 90 .

[0102] Reference Fig.23A and Fig. 23B The method may include forming a second lower X-direction gap filling insulator 55x and a second upper X-direction gap filling insulator 56x to fill the second X-direction gap Gx2. This process may refer to 7A to 7C and FIG. 8A to FIG. 8C Understand in more detail.

[0103] The second lower X-direction gap-filling insulator 55x may be formed by a second lower X-direction gap-filling process using a seventh source gas substantially the same as the first source gas, and the second upper X-direction gap-filling insulator 56x may be formed by a second upper X-direction gap-filling process using an eighth source gas substantially the same as the second source gas.

[0104] Reference Fig.24A and Fig. 24B The method may include forming a second X-direction gap-filling insulator 57x by performing a curing process and a planarizing process to cure and planarize the second lower X-direction gap-filling insulator 55x and the second upper X-direction gap-filling insulator 56x.

[0105] Then, refer to Figure 3A and Figure 3B The method may further include forming a capping pad 95 and a capping insulator 96 on the planarized second X-direction gap-filling insulator 57 x , the second X-direction spacer Sx2 , and the second word line 90 .

[0106] By way of summary and review, as the aspect ratio of the gap between cell stacks increases, it becomes increasingly challenging to perform a process of filling the gap with a gap-fill insulator in the gap such that no seams or voids are formed in the gap between cell stacks.

[0107] As described above, embodiments may provide a process for filling a gap-fill insulator in which a seam or void in a gap between cell stacks is reduced or eliminated, and a block-level step difference is reduced or eliminated.

[0108] As described above, the gap filling insulator can be filled in the gap with a large aspect ratio between the cell stacks without gaps or voids, and the structural stability of the cell stack can be improved. The gap filling insulator can be formed using a two-step gap filling process. The two-step gap filling process may include a first step gap filling process for forming a lower gap filling insulator in the gap and a second step gap filling process for forming an upper gap filling insulator on the lower gap filling insulator. The first step gap filling process may use a high-flowability insulator, and the second step gap filling process may use a high-viscosity insulator. In the gap filling process for filling the space with a high aspect ratio between the cell stacks, the gap filling capability can be improved at the bottom of the cell stack, and a conformal insulating layer can be provided at the top of the cell stack, which can reduce the step difference in the block unit.

[0109] Example embodiments have been disclosed herein, and although specific terms are used, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as of the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0110] Korean Patent Application No. 10-2019-0098185, filed on August 12, 2019 in the Korean Intellectual Property Office and entitled “Method of Manufacturing a Semiconductor Device Using a Two-Step Gap-Fill Process” is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a cross-point semiconductor memory device, the method comprising: forming a first word line material layer and a first unit stack material layer on the base layer, patterning the first cell stack material layer and the first word line material layer using a first X-direction trimming process to form a first initial cell stack, a first word line, and a first X-direction gap, wherein the first initial cell stack and the first word line extend in an X-direction, and the first X-direction gap extends between the first initial cell stacks in the X-direction, forming a first lower X-direction gap-filling insulator filling the first X-direction gap using a first lower X-direction gap-filling process, forming a first upper X-direction gap-filling insulator on the first lower X-direction gap-filling insulator using a first upper X-direction gap-filling process, and forming a first X-direction gap-filling insulator by performing a curing process and a planarizing process on the first lower X-direction gap-filling insulator and the first upper X-direction gap-filling insulator, in: The first lower X-direction gap-filling process is performed using a first source gas including a first precursor and a second precursor, and The first upper X-direction gap-filling process is performed using a second source gas including the first precursor and the second precursor, The gap-fill material formed from the first precursor has a higher flowability or a lower viscosity than the gap-fill material formed from the second precursor, A first volume ratio of the first precursor to the second precursor in the first source gas is greater than 15:1 and a second volume ratio of the first precursor to the second precursor in the second source gas is less than 15:1, so that the first lower X-direction gap-filling insulator has a higher flowability or a lower viscosity than the first upper X-direction gap-filling insulator. 2 . The method of claim 1 , wherein the first precursor comprises octamethylcyclotetrasiloxane. 3 . The method of claim 1 , wherein the second precursor comprises at least one of tetramethoxysilane and tetramethyl orthosilicate.

4. The method according to claim 1, wherein: The first volume ratio of the first precursor to the second precursor in the first source gas is 20:1 to 50:1, and The second volume ratio of the first precursor to the second precursor in the second source gas is 1:1 to 10:

1.

5. The method according to claim 1, further comprising: forming a bit line material layer on the first initial cell stack and the first X-direction gap-fill insulator, The bit line material layer and the first initial cell stack are patterned by using a first Y-direction trimming process to form a first cell stack, a bit line, and a first Y-direction gap, wherein the first cell stack has a pillar shape, the bit line extends in the Y-direction, and the first Y-direction gap extends in the Y-direction between the first cell stacks, Using a first lower Y-direction gap filling process to form a first lower Y-direction gap filling insulator filling the first Y-direction gap, forming a first upper Y-direction gap-filling insulator on the first lower Y-direction gap-filling insulator using a first upper Y-direction gap-filling process, and forming a first Y-direction gap-filling insulator by performing a curing process and a planarizing process on the first lower Y-direction gap-filling insulator and the first upper Y-direction gap-filling insulator, in: The first lower Y-direction gap-filling process is performed using a third source gas including the first precursor and the second precursor, and The first upper Y-direction gap-filling process is performed using a fourth source gas including the first precursor and the second precursor, A third volume ratio of the first precursor to the second precursor in the third source gas is greater than 15:1, and A fourth volume ratio of the first precursor to the second precursor in the fourth source gas is less than 15:

1.

6. The method according to claim 5, wherein: Each of the first cell stacks includes a first switching element, a first storage element and a first upper electrode, The first switching element includes a first lower electrode, a first switching electrode and a first intermediate electrode, and The first storage element includes a first storage cell.

7. The method according to claim 6, wherein: The first switch electrode comprises a bidirectional threshold switch material, and The first memory cell includes a variable resistance material.

8. The method of claim 6, wherein the first lower electrode, the first intermediate electrode, and the first upper electrode comprise a non-metallic conductor.

9. The method of claim 8, wherein the non-metallic conductor comprises N-doped carbon.

10. The method of claim 6, wherein the first memory element comprises a first lower interface between the first switching element and the first memory cell and a first upper interface between the first memory cell and the first upper electrode, each of the first lower interface and the first upper interface comprising metal.

11. The method according to claim 5, wherein: The curing process includes an ultraviolet curing process, and The planarization process includes a chemical mechanical polishing process.

12. The method according to claim 5, further comprising: forming an X-direction spacer on a sidewall of the first initial cell stack in the first X-direction gap and a sidewall of the first word line in the first X-direction gap, and Y-direction spacers are formed on sidewalls of the first cell stack in the first Y-direction gap and sidewalls of the bit line in the first Y-direction gap.

13. The method according to claim 5, further comprising: forming a second unit stack material layer on the bit line and the first Y-direction gap-filling insulator, The second unit stack material layer is patterned by using a second Y-direction trimming process to form a second initial unit stack, and a second Y-direction gap is formed between the second initial unit stacks. Using a second lower Y-direction gap filling process to form a second lower Y-direction gap filling insulator filling the second Y-direction gap, forming a second upper Y-direction gap-filling insulator on the second lower Y-direction insulator using a second upper Y-direction gap-filling process, and By curing and planarizing the second lower Y-direction gap-filling insulator and the second upper Y-direction gap-filling insulator, a second Y-direction gap-filling insulator is formed, in: The second lower Y-direction gap-filling process is performed using a fifth source gas including the first precursor and the second precursor, and The second upper Y-direction gap-filling process is performed using a sixth source gas including the first precursor and the second precursor, A fifth volume ratio of the first precursor to the second precursor in the fifth source gas is greater than 15:1, and A sixth volume ratio of the first precursor to the second precursor in the sixth source gas is less than 15:

1.

14. The method according to claim 13, further comprising: forming a second word line material layer on the second initial cell stack and the second Y-direction gap-fill insulator, forming a second word line and a second cell stack by patterning the second word line material layer and the second initial cell stack using a second X-direction trimming process, wherein a second X-direction gap is formed between the second cell stacks, forming a second lower X-direction gap-filling insulator filling the second X-direction gap using a second lower X-direction gap-filling process, forming a second upper X-direction gap-filling insulator on the second lower X-direction gap-filling insulator using a second upper X-direction gap-filling process, and forming a second X-direction gap-filling insulator by curing and planarizing the second lower X-direction gap-filling insulator and the second upper X-direction gap-filling insulator, in: The second lower X-direction gap-filling process is performed using a seventh source gas including the first precursor and the second precursor, and the second upper X-direction gap-filling process is performed using an eighth source gas including the first precursor and the second precursor, A seventh volume ratio of the first precursor to the second precursor in the seventh source gas is greater than 15:1, and An eighth volume ratio of the first precursor to the second precursor in the eighth source gas is less than 15:

1.

15. The method according to claim 14, further comprising: forming a Y-direction spacer on a sidewall of the second initial unit stack in the second Y-direction gap, and X-direction spacers are formed on sidewalls of the second cell stack in the second X-direction gap and sidewalls of the second word line in the second X-direction gap.

16. A method for manufacturing a cross-point semiconductor memory device, the method comprising: forming word lines and cell stacks on a base layer, with gaps formed between the cell stacks, performing a lower gap-filling process to form a lower gap-filling insulator in the gap, performing an upper gap-filling process to form an upper gap-filling insulator on the lower gap-filling insulator, curing the lower gap-filling insulator and the upper gap-filling insulator to form a gap-filling insulator, and forming a bit line on the cell stack and the gap-fill insulator, in: The lower gap filling process is performed using a first source gas including a first precursor and a second precursor, and the upper gap-filling process is performed using a second source gas including the first precursor and the second precursor, The first precursor includes octamethylcyclotetrasiloxane, The second precursor includes at least one of tetramethoxysilane and tetramethyl orthosilicate, A first volume ratio of the first precursor to the second precursor in the first source gas is greater than 15:1, and A second volume ratio of the first precursor to the second precursor in the second source gas is less than 15:

1.

17. The method according to claim 16, The lower gap filling process includes a lower first direction gap filling process and a lower second direction gap filling process, the upper gap filling process includes an upper first direction gap filling process and an upper second direction gap filling process, and Wherein forming the unit stack comprises: Forming a unit stack material layer, The unit stack material layer is patterned using a first direction trimming process to form an initial unit stack, and a first direction gap is formed between the initial unit stacks. performing a lower first direction gap filling process to form a lower first direction gap filling insulator filling the first direction gap, performing an upper first direction gap filling process to form an upper first direction gap filling insulator on the lower first direction gap filling insulator, curing the lower first direction gap filling insulator and the upper first direction gap filling insulator to form a first direction gap filling insulator, patterning the initial cell stack using a second direction trimming process to form the cell stack, with second direction gaps formed between the cell stacks, performing a lower second direction gap filling process to form a lower second direction gap filling insulator filling the second direction gap, performing an upper second direction gap-filling process to form an upper second direction gap-filling insulator on the lower second direction gap-filling insulator, and A second direction gap-filling insulator is formed by curing the lower second direction gap-filling insulator and the upper second direction gap-filling insulator.

18. The method of claim 17, wherein: The first volume ratio of the first precursor to the second precursor in the first source gas is 20:1 to 50:1, and The second volume ratio of the first precursor to the second precursor in the second source gas is 1:1 to 10:

1.

19. A method for manufacturing a cross-point semiconductor memory device, the method comprising: forming a word line material layer and a cell stack material layer on the base layer, performing an X-direction trimming process to form initial cell stacks and word lines, wherein the initial cell stacks and the word lines extend in an X-direction, and an X-direction gap extending in the X-direction is formed between the initial cell stacks, forming X-direction spacers on opposite sidewalls of the word line in the X-direction gap and opposite sidewalls of the initial cell stack in the X-direction gap, performing a lower X-direction gap filling process to form a lower X-direction gap filling insulator filling the X-direction gaps between the X-direction spacers, performing an upper X-direction gap-filling process to form an upper X-direction gap-filling insulator on the lower X-direction gap-filling insulator, curing and planarizing the lower X-direction gap-filling insulator and the upper X-direction gap-filling insulator to form an X-direction gap-filling insulator, performing a Y-direction trimming process to form cell stacks, wherein the cell stacks have a column shape and a Y-direction gap extending in the Y-direction is formed between the cell stacks; forming Y-direction spacers on opposite sidewalls of the cell stack in the Y-direction gap and opposite sidewalls of the X-direction gap-filling insulator in the Y-direction gap, performing a lower Y-direction gap filling process to form a lower Y-direction gap filling insulator filling the Y-direction gap between the Y-direction spacers, performing an upper Y-direction gap-filling process to form an upper Y-direction gap-filling insulator on the lower Y-direction gap-filling insulator, and curing and planarizing the lower Y-direction gap-filling insulator and the upper Y-direction gap-filling insulator to form a Y-direction gap-filling insulator, in: The lower X-direction gap-filling process and the lower Y-direction gap-filling process are performed using a first source gas including a first precursor and a second precursor, and The upper X-direction gap-filling process and the upper Y-direction gap-filling process are performed using a second source gas including the first precursor and the second precursor, The gap-fill material formed from the first precursor has a higher flowability or a lower viscosity than the gap-fill material formed from the second precursor, A first volume ratio of the first precursor to the second precursor in the first source gas is greater than 15:1 and a second volume ratio of the first precursor to the second precursor in the second source gas is less than 15:1, so that the lower X-direction gap-filling insulator has a higher flowability or a lower viscosity than the upper X-direction gap-filling insulator, and the lower Y-direction gap-filling insulator has a higher flowability or a lower viscosity than the upper Y-direction gap-filling insulator.

20. The method of claim 19, wherein: Each of the cell stacks includes a switching element, a storage element and an upper electrode, The switch element comprises a lower electrode, a switch electrode and an intermediate electrode, The storage element comprises a lower interface, a storage unit and an upper interface, The switch electrode includes a bidirectional threshold switch material, The memory cell includes a variable resistance material, Each of the lower electrode, the intermediate electrode, and the upper electrode includes N-doped carbon, and Each of the lower interface and the upper interface includes metal.

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