Watchdog for resolving deadlock conditions

Abstract

Embodiments of the present disclosure generally relate to a watchdog for resolving a deadlock condition. The described techniques resolve a deadlock problem associated with interconnected hardware devices that share a bus line associated with a digital communication interface. A watchdog-based solution is described that can be implemented internally within the interconnected hardware device, or alternatively, can be implemented as an external component. A watchdog circuit device can monitor the logic state of one or more internal connections of a hardware device, and when a deadlock condition is detected using this internal monitoring, cause one or more portions of the hardware device to reset.

Description

Technical Field

[0001] Various aspects described herein relate generally to resolving hardware deadlock conditions, and more particularly to resolving deadlock conditions using a watchdog circuit arrangement. Background Art

[0002] Hardware systems often use components that are interconnected to a collection of common bus lines. In such systems, various hardware components may share access to these bus lines in a time-division multiplexed manner, where the hardware devices assert the shared bus lines at different times based on the desired communication timing. Therefore, in the event of one of the interconnect failures, the state of the shared bus lines may become "deadlocked" in the same logical state. The deadlock state may prevent other interconnected devices from asserting the bus lines until the deadlock problem is resolved. Current solutions to resolve this deadlock problem are not adequate. Summary of the invention

[0003] Modern hardware design usually implements interconnection devices, which are coupled to various buses and share access with them, and these various bus lines can include data bus lines and clock bus lines. These bus lines can form a part of, for example, a digital communication interface, which enables the interconnection hardware devices to communicate with each other and / or with other external components. This interconnection design is prone to deadlock problems, and as the number of interconnection devices increases, the risk of suffering from deadlock problems also increases. In other words, the failure of any interconnection hardware device in the interconnection hardware device may cause one or more bus lines to be stuck in the same logical state, thereby cannot be used by other hardware components.

[0004] The traditional solution to resolve deadlocks involves resetting the failed hardware device by toggling its supply voltage, which generates an internal reset and restores the logic of the deadlocked bus line to a default logic state or a pre-deadlocked logic state. However, this solution is costly because it requires an external supply voltage switch and other additional components dedicated to this purpose. This solution also introduces additional design complexity because software-based components are also required to ensure that the failed hardware device is correctly identified and reset correctly.

[0005] Therefore, the embodiments described herein use a watchdog-based solution to solve the deadlock problem. As explained in further detail below, this may include using a watchdog circuit device that is integrated as part of the same chip as the monitored hardware device or integrated externally to the monitored hardware device. Moreover, compared to conventional techniques that monitor a shared external bus line, the watchdog circuit device may monitor the logic state of one or more internal connections of the hardware device.

[0006] The embodiments described herein advantageously do not require additional components or design work as described above to resolve deadlock scenarios. Also, because the watchdog circuit device does not need to monitor external bus lines, the watchdog timing can be designed independently of the bus line timing, and instead can depend only on the timing of the monitored hardware device. From a design point of view, it is easier to determine these internal hardware device timings for the purpose of issuing a hardware component reset. Further, the use of internal device timing can advantageously enable the watchdog circuit device to be implemented using an oscillator and / or a different power supply from other parts of the monitored hardware device. Doing so can also improve the robustness of the watchdog circuit device, so that in the case of a deadlock problem caused by such a clock failure or power failure, the watchdog circuit device can still reset the monitored hardware device (or its various parts) that has failed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the various aspects and to enable those skilled in the art to make and use the various aspects.

[0008] Figure 1 A conventional system including a master device and slave devices communicating via a digital interface is illustrated.

[0009] Figure 2 A conventional reset circuit for resolving bus line deadlock is shown.

[0010] Figure 3 A system including a first device and a second device communicating with each other via a digital interface according to an embodiment of the present disclosure is illustrated.

[0011] Figure 4A A timing diagram is illustrated in accordance with an embodiment of the present disclosure in which internal control lines associated with a device remain at the same logic state for a duration that is less than a watchdog timeout threshold.

[0012] Figure 4B A timing diagram is illustrated in which internal control lines associated with a device remain at the same logic state for a duration exceeding a watchdog timeout threshold in accordance with an embodiment of the present disclosure.

[0013] Figure 4C A timing diagram is illustrated in accordance with an embodiment of the present disclosure wherein an internal control line associated with the device is not asserted and the watchdog counter is not enabled.

[0014] Figure 5 The diagram illustrates a method flow according to an embodiment of the present disclosure.

[0015] Example aspects of the disclosure are described with reference to the accompanying drawings. The drawing in which an element first appears is generally indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0016] In the following description, many specific details are set forth in order to provide a thorough understanding of various aspects of the present disclosure. However, it will be apparent to those skilled in the art that various aspects including structures, systems, and methods may be practiced without these specific details. The descriptions and representations herein are common means for those skilled in the art to most effectively communicate the essence of their work to other persons skilled in the art. In other instances, known methods, processes, components, and circuit arrangements have not yet been described in detail to avoid unnecessarily obscuring various aspects of the present disclosure.

[0017] Figure 1 The figure shows a conventional system including a master device and a slave device communicating via a digital interface. Figure 1 As shown, the conventional system 100 includes a microcontroller used as a master device 102, and a slave device 104 coupled to the master device 102 via a digital interface 103. The digital interface 103 can facilitate bidirectional digital communication between the master device 102 and the slave device 104 and synchronization of communication between the master device 102 and the slave device 104. Therefore, the digital interface 103 can implement the following functions: Figure 1 Several bus lines are shown, one of which is a clock (CLK) line. When communicating with each other, the master device 102 and the slave device 104 may each assert the CLK line at different times.

[0018] like Figure 1 As shown, slave device 104 may include logic circuitry 106 configured to perform processing operations and communication operations for slave device 104; a Schmitt trigger for debouncing a CLK signal received via a CLK line; and a transistor 110 coupled to the CLK line. The gate of transistor 110 is also connected to a control line of logic circuitry 106 and receives a control signal via the control line. Therefore, the CLK line is typically pulled up to a power supply voltage V via a pull-up resistor 108. DD, and when the slave device 104 asserts the CLK line (e.g., when transmitting data to the master device 102), the logic circuit device 106 can assert the control line by outputting a control signal with appropriate logic at the gate of the transistor 110, so that the transistor 110 is turned on and the CLK line is pulled to ground (GND). In this way, the logic circuit device 106 can modulate the CLK line via the switch of the transistor 110 as needed. However, in the event of a failure of the slave device 104, the control signal can be fixed in an asserted logic high state, which causes the CLK line to be stuck or deadlocked in a low logic state. In this deadlocked state, the master device 102 (and any other device connected to the CLK line) can no longer utilize the CLK line.

[0019] To remedy the deadlock condition, conventional solutions include using an additional reset circuit such as Figure 2 As shown coupled to Figure 1 The slave device 102 is shown. Figure 2 The reset circuit 200 shown includes a master general purpose input / output (GPIO) device 201 and an external power supply 205, which are coupled to the slave device 104 via a voltage switch configuration, which includes a transistor 220, resistors 222, 224, 226, and a capacitor C. The conventional solution is used to monitor the CLK line and trigger the power supply voltage V of the slave device 104. DD , which generates an internal reset in the slave device 104 to resolve the Figure 1 However, again, this conventional solution of external reset and dedicated reset switching adds a significant amount of cost to the system design and requires additional design work in terms of implementing these additional components, solder joints, PCB layout and space, and software design performed by the master GPIO 201. Further complicating this problem, in the case where the slave device 104 consumes very low current from the power supply line, an additional pull-down transistor is required to discharge the power supply voltage pin of the slave device 104 in a reasonable time.

[0020] As discussed further below, embodiments presented in the present disclosure eliminate the need for external reset circuits and dedicated reset circuits, but instead aim to resolve deadlock by monitoring control signals generated by the device itself that may be malfunctioning.

[0021] Figure 3 300 is a diagram illustrating a system including a first device and a second device communicating with each other via a digital interface according to an embodiment of the present disclosure. Figure 3304. The embodiment includes a system 300 that implements any suitable number of first devices 302 and / or second devices 304, which may be interconnected via one or more bus lines included in the digital interface 303.

[0022] For convenience, embodiments are described herein in the singular with reference to the first device 302 and the second device 304. However, the embodiments described herein with reference to the second device 304 can be extended to any number of interconnected devices within the system 300. For example, the embodiments described herein with reference to the watchdog circuit arrangement of the second device 304 can additionally or alternatively be implemented as part of the first device 302. As another example, the embodiments described herein with reference to the watchdog circuit arrangement of the second device 304 can additionally or alternatively be implemented as part of an additional device configured in a similar manner to the second device 304, which can be configured to additionally communicate with the first device 302.

[0023] Furthermore, although the embodiments discussed herein are about monitoring of CLK lines, deadlock states are not unique to the type of clock lines, and other bus lines may also be deadlocked in the event of a hardware device failure. Therefore, the embodiments described herein should not be interpreted as being applicable only to preventing the deadlock state of the CLK line. On the contrary, the concepts described herein can be extended to include any suitable type of internal monitoring of logic signals, which affect the logic state of external bus lines that can be shared by other interconnected hardware devices in the system. For example, this may include: monitoring an internal logic signal that causes the assertion of a data bus line, and when the monitored signal remains at the same logic state of the external bus line that causes the deadlock, one or more parts of the device are reset. In addition to or as an alternative to monitoring the CLK line, the embodiments described herein may include monitoring the deadlock state of other bus lines. For example, the second device 304 may include a watchdog circuit device 308 and an appropriate connection to the logic circuit device 306 to monitor the logic state of one or more other signals used by the logic circuit device 306, which control the state of one or more (or all) logic circuits. Thus, embodiments include any number of interconnected devices within the system 300 that implement the watchdog techniques described herein to prevent deadlock issues for any number of bus lines included in the digital interface 303 described herein.

[0024] In one embodiment, the first device 302 and the second device 304 may be implemented as any suitable type of device configured to bidirectionally communicate with each other using the digital interface 303. These communications may occur according to any suitable type of communication protocol that facilitates the first device 302 and the second device 304 to establish a connection with each other to exchange data. Some examples of suitable communication protocols may include an inter-integrated circuit (I2C) protocol, a serial peripheral interface (SPI) protocol, a controller area network (CAN) protocol, a 1-Wire protocol, etc. Thus, the digital interface 303 may include any suitable number of bus lines to facilitate a particular type of communication protocol implemented for a particular application.

[0025] In one embodiment, the first device 302 and the second device 304 can each communicate with each other as part of a master / slave relationship using one or more bus lines in the digital interface 303, as referred to herein. Figure 1 In this case, for example, the first device 302 can be implemented as any suitable type of master device, such as, for example, a microcontroller. The second device 304 can be implemented as any suitable type of slave device, such as, for example, another microcontroller, a sensor device configured to measure a physical property, an analog-to-digital converter, etc.

[0026] To facilitate bidirectional communication, each of the first device 302 and the second device 304 may assert the CLK line (and Figure 3 To avoid bus contention, the first device 302 and the second device 304 can each use the CLK line to send a signal to the other device indicating that the sending device will drive the bus line so that the receiving device will not attempt to drive the bus line within a future time window that can be established by the communication protocol.

[0027] The second device 304 may include a Schmitt trigger or other suitable device to de-jitter the CLK signal received from the first device 302. The logic circuit device 306 may include any suitable hardware configuration to facilitate the second device 304 to process data, transmit data to the first device 302, and receive data from the first device 302. The logic circuit device may be integrated as part of the same chip (i.e., die) as the second device 304, so that the logic circuit device 306 is internal to the second device 304. The logic circuit device 306 may manage the data processing and timing functions of the second device 304, and may be implemented as a sub-circuit of the second device 304, for example. As an example, the logic circuit device 306 may be implemented as a system on a chip (SoC) with suitable complementary metal oxide semiconductor (CMOS) circuit devices to implement data processing and communication functions associated with the second device 304.

[0028] Further, the second device 304 can include any suitable type of driver configuration coupled to the logic circuit device 306 and the CLK line to enable the second device 304 to control the logic state of the CLK line when the second device 304 needs to assert the CLK line to communicate with the first device 302. For example, the second device 304 can include a transistor 310 coupled to the logic circuit device 306 and the CLK line in an open drain configuration. In this configuration, the transistor 301 can have a gate terminal coupled to the logic circuit device 306 via a control line 309, such as Figure 3 As shown. The logic circuit device 306 can have an output terminal, which is also coupled to the control line 309, and the logic circuit device 306 can be configured to output a control signal on the control line 309. In one embodiment, the control signal can be an interrupt signal or another suitable signal, which signals the occurrence of a specific event to other interconnected devices (e.g., the first device 302) depending on the specific implementation of the second device 302. For example, the interrupt signal can indicate to the first device 302 that there is a new measurement result, or that there is new data available for the first device 302 to obtain (e.g., read out from the memory of the second device 304 or another suitable device).

[0029] As another example, the control signal may be a "clock stretching" signal used according to various data communication protocols (such as, I2C). Continuing with this example, the second device 304 may use the control signal as a clock stretching signal to delay ongoing communication with the first device 302 via the digital interface 303. This may be applicable to various scenarios, one example being when the first device 302 has an outstanding requested operation (e.g., sensor data measurement) and new data is not yet ready to be read.

[0030] In other words, according to the communication protocol, the control signal can be used as a clock stretching signal to prevent the first device 302 from communicating with the second device 304 too quickly. In other words, the use of the clock stretching signal can prevent the first device 302 from communicating with the second device 304 according to a threshold communication rate, which may be a predetermined communication rate, a ratio of a communication rate used according to a specific communication protocol, a communication rate adjusted according to an original communication rate or a default communication rate, etc. The threshold communication rate may include a non-periodic communication rate and a periodic communication rate, wherein the non-periodic communication rate includes the aforementioned waiting period associated with the first device 302 completing a specific event.

[0031] Transistor 310 may also have a drain terminal coupled to the CLK line, which is pulled up to the supply voltage V via resistor 308. DD, and the source terminal of transistor 308 can be coupled to the ground reference. Therefore, in this open-drain configuration, when transistor 310 is not conducting, the CLK line can be pulled high (to a logic high state) via resistor 308. When transistor 308 is conducting, the CLK line can be driven to a logic low state (GND), which may be Figure 3 This occurs when logic circuitry 306 in the illustrated configuration asserts the control signal to a logic high.

[0032] Despite Figure 3 304 is shown as an n-type field effect transistor (FET), but embodiments include implementing the second device 304 of any suitable type of transistor 310. Examples of such transistors may include, for example, bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), etc. Moreover, the implementation of a single transistor 310 may include, for example, Figure 3 The exemplary driver configuration shown is only one example of a driver configuration that the second device 304 may use to assert the CLK line. Although for the sake of brevity, Figure 3 Not shown, but another example of a driver stage may alternatively implement a push-pull output transistor configuration with three states. Figure 3 The transistor 310 shown may be replaced with any suitable transistor configuration to enable the CLK line to be driven to a logic high state or a logic low state depending on the output of a push-pull transistor configuration provided in response to a control signal output by logic circuitry 306 .

[0033] In any case, embodiments include second device 304 asserting the CLK signal in response to the control signal output by logic circuit device 306. Likewise, in the event of a failure of logic circuit device 306, the control line may continue to be asserted and cause the CLK line to be in a deadlocked state. Therefore, to avoid these deadlock issues, embodiments include second device 304 implementing watchdog circuit device 308, which can monitor the internal control signal provided by logic circuit device 306. When the control signal remains at a specific logic state (e.g., logic high in this example) for more than a watchdog timeout threshold, watchdog circuit device 308 can reset one or more portions of second device 304 to resolve the deadlocked state by causing the control signal to return to a default state or a pre-asserted state (logic low in this example).

[0034] To this end, the embodiment includes a watchdog circuit device 308, which is coupled to the logic circuit device 306 via a monitoring line 307 and a timeout line 311, such as Figure 3As shown. Monitoring line 307 can be coupled directly to logic circuit device 306, directly to transistor 310, or coupled in any suitable manner so that watchdog circuit device 308 can accurately monitor the logic state of the control signal provided to transistor 310 (or other suitable driver configuration, as the case may be). For example, monitoring line 307 can include additional buffers, couplers, etc. to provide isolation between watchdog circuit device 308 and other components of second device 304 if desired. Similarly, watchdog circuit device 308 can be coupled to logic circuit device 306 directly or indirectly (e.g., using a buffer, driver, etc.) via timeout line 311.

[0035] The watchdog circuit device 308 can be configured as an integrated part of the second device 304 and can be formed as part of the same chip (i.e., die) as the second device 304 along with other components of the second device 304 (such as transistor 310, logic circuit device 306, etc.). When implemented on the same die, the watchdog circuit device 308 can be internal to the second device 304, although the embodiments are not limited to this particular implementation. Instead, alternative embodiments include the watchdog circuit device 308 implemented as one or more components that are coupled to the logic circuit device 306 in any suitable manner to monitor the logic state of the control signal and reset one or more parts of the second device 304 when a deadlock condition is detected.

[0036] The watchdog circuit device 308 can be implemented according to any suitable type of architecture that outputs a timeout signal to the logic circuit device 306 based on the monitored state of the control signal. Although the embodiments are not limited to these examples, the examples of the watchdog circuit device 308 described herein refer to a timeout watchdog architecture. For example, the watchdog circuit 308 can alternatively be implemented as another type of watchdog architecture, such as a multi-level watchdog architecture, which triggers the generation of a timeout signal after the expiration of several time periods.

[0037] In other words, in the example described in further detail below, the watchdog circuit device 308 is described as generating a timeout signal once the control signal remains at a specific logic state for more than the watchdog timeout threshold. According to such an embodiment, when the watchdog timeout threshold condition is met, the timeout signal can be generated immediately, except for other system delays such as the response time of the circuit component or the overall system latency. However, the embodiments are not limited to this specific example, and once the deadlock condition is detected (i.e., once the watchdog timeout threshold is exceeded), the timeout signal can be generated according to any suitable schedule. For example, once it is determined that the control signal has remained at a specific logic state for more than the watchdog timeout threshold, the timeout signal can be generated with a fixed delay or an adjustable delay as to when the timeout signal is output to the logic circuit device 306.

[0038] As discussed above with respect to the generation of the timeout signal, the watchdog circuit device 308 can be implemented according to various architectures, so that when the watchdog circuit device 308 detects a change in the logic state of the control signal output by the logic circuit device 306, the watchdog counter can be started immediately, except for other system delays such as the response time of the watchdog circuit device 308 and other system wait times. Alternatively, the watchdog circuit device 308 can delay starting the watchdog counter for a period of time, which period of time can be fixed or adjustable. Further, the watchdog timeout threshold itself can be fixed or adjustable and can be configured based on the specific application in which the watchdog circuit device 308 is implemented. For example, the watchdog timeout threshold can be established (fixed or adjusted) based on the clock speed or other suitable parameters used by the digital interface 300.

[0039] Additionally, the watchdog circuit device 308 can be implemented within the second device 304 and / or as an external component. In various embodiments, the watchdog circuit device 308 can also use one or more dedicated components that are different from the components used by the second device 304. For example, the watchdog circuit device 308 can implement an oscillator, logic, and / or power supply voltage V that is different from the oscillator, logic, and / or power supply voltage implemented by the second device 304 or other devices within the system 300. DD For example, these different components can be dedicated to the watchdog circuit device 308, or shared with components other than the second device 304 within the system 300 (e.g., shared between each watchdog circuit device within the system 300). In this way, because failures of the second device 304 caused by oscillators, voltage supplies, logic, etc. do not affect the watchdog circuit device 308, the embodiments described herein ensure robust operation of the watchdog circuit device 308. Therefore, the watchdog circuit device 308 can continue to monitor the state of the control signal and generate a timeout signal in the event of these failures.

[0040] Again, if Figure 3 As shown, watchdog circuit device 308 monitors the logic state of control line 309, which is used by logic circuit device 306 to output a control signal. This is done via monitoring line 307, which couples watchdog circuit device 308 to control line 309. Now, turning to Figure 4A , the monitoring function of the watchdog circuit device 308 is explained in more detail. Figure 3 , Figure 4A The timing diagrams 400 are shown for the CLK signal carried via the CLK line of the digital interface 303, the control signal carried by the control line 309, and the watchdog counter timing implemented by the watchdog circuit device 308. Each of these timing diagrams 400 is shown in time scale. Figure 4A As shown, the first device 302 drives the CLK line during time period 402 , while the second device 304 drives the CLK line during time period 404 .

[0041] To drive the CLK line, in this example, the logic circuit device 306 outputs a control signal having a logic high state, which in turn turns on the transistor 310 and causes the CLK signal to change from the logic high state to the logic low state, as shown during the time period 404. In one embodiment, the watchdog circuit device 308 detects the change in the logic state of the control line 309 via the monitoring line 307, which can be detected according to edge-sensitive logic (e.g., detecting a rising edge of the control signal) or level-sensitive logic (e.g., detecting that the control signal is now in a different logic state than the default state). Regardless, upon detecting a change in the logic state of the control signal output by the logic circuit device 306, an embodiment includes the watchdog circuit device 308 starting a counter (e.g., a timer) that continues to run until a subsequent change in the logic state of the control signal is detected (which can also be detected via edge-sensitive logic or level-sensitive logic).

[0042] like Figure 4A As shown, the control signal returns to the previous logic low state at the end of time period 404, thereby giving up control of the CLK line. As a result, the watchdog counter implemented via the watchdog circuit device 308 is stopped and reset (i.e., "kicked") at the end of time period 404. In this example, no deadlock condition occurs, and time period 404 is shown as being less than the watchdog timeout threshold period. Therefore, the operation of the system 300 continues, wherein the watchdog counter is started and reset in this manner while the watchdog circuit device 308 continues to monitor the control signal output by the logic circuit device 306 via the monitoring line 307.

[0043] Figure 4BThe diagram shows Figure 4A The same timing diagram as shown in the timing diagram continues to refer to Figure 3 .picture Figure 4A Like the timing diagram 400 shown in FIG. Figure 4B The timing diagram 425 shown also shows that the first device 302 drives the CLK line during the time period 402 and the second device 304 drives the CLK line during the time period 404. Figure 4B In the example timing diagram 425 shown, the second device 304 fails and causes the CLK line to be in a deadlock state. Figure 4B As shown, the watchdog circuit device 308 starts the watchdog counter upon detecting that the logic state of the control signal changes from a logic low state to a logic high state, which causes the CLK line to be driven to a logic low state.

[0044] In such Figure 4B In the example timing diagram 425 shown, the control signal remains at a logic high state, thereby asserting the CLK line low for a time period 404. In this example, the time period 404 during which the control signal remains at a logic high state exceeds the watchdog timeout threshold as shown. In this example, once the control signal remains at the same logic state for longer than the watchdog timeout threshold, the watchdog circuit device 308, which is coupled to the logic circuit device 306 via the timeout line 311, generates a timeout signal.

[0045] The timeout signal generated by the watchdog circuit device 308 can be configured to reset one or more parts of the second device 304. For example, this can be achieved by resetting the logic circuit device 306 or various parts of the logic circuit device 306. As an illustrative example, the timeout signal can reset the second device part by resetting the logic of the logic circuit device 306 associated with the communication interface, while other parts of the second device 304 maintain their current state. As another example, the timeout signal can be coupled to the appropriate terminal of the logic circuit device 306 via the timeout line 311, which resets the logic circuit device 306 and can optionally reset other parts of the second device 304 (or the entire second device 304).

[0046] The timeout signal can be configured in different ways depending on the architecture of the watchdog circuit device 308, the implementation of the logic circuit device 306, and the specific implementation of the second device 304. For example, the timeout signal can be generated in the form of a timing pulse according to a maskable interrupt, a non-maskable interrupt, or a combination thereof. The timeout signal can have a fixed format or an adjustable format in terms of data and / or logic timing. In an alternative embodiment, instead of being directly coupled to the logic circuit device via the timeout line 311, the watchdog circuit device 308 can be coupled to another device (not shown) inside or outside the second device 304. In this case, the watchdog circuit device 308 can provide a timeout signal to one or more of these (multiple) other components, which in turn can generate the necessary reset signal and provide it to the logic circuit device 306.

[0047] In any case, as described above, generating a timeout signal may cause one or more portions of second device 304 and / or logic circuit arrangement 306 to be reset. In one embodiment, after second device 304 and / or logic circuit arrangement 306 is reset, the control signal may be restored to an unasserted default logic state. For example, Figure 4B As shown, when the watchdog circuit device 308 generates a timeout signal, the second device 304 and / or the logic circuit device 306 are reset so that the control signal is restored to a logic low state, thereby resolving the deadlock state and giving up the control of the CLK line over the first device 302 (or other devices in the system 300, as the case may be).

[0048] In one embodiment, the operation of the watchdog circuit device 308 can be transparent to the rest of the system 300 during normal operation. Figure 4C The diagram shows the continued reference Figure 3 and Figure 4A The timing diagram is the same as the timing diagram shown. Figure 4A As shown in the timing diagram 400, Figure 4C The timing diagram 450 shown may also represent the CLK signal carried via the CLK line of the digital interface 303, the control signal carried via the control line 309, and the watchdog counter timing implemented by the watchdog circuit device 308. Figure 4A and Figure 4B The timing diagrams 400, 425 shown respectively are different. Figure 4C The timing diagram 450 shown indicates that the second device 304 does not assert the CLK line. Instead, as shown, the first device 302 drives the CLK line exclusively during the entire time period 402. As a result, the control signal does not change state from a logic low state, and the watchdog counter does not start.

[0049] The logic states described above and elsewhere throughout this disclosure are based on implementing transistor 310 in an open drain configuration. Figure 3 The illustrated driver configurations are examples of use, and other embodiments may use alternative logic states based on other driver configurations. More generally, embodiments include watchdog circuitry 308 initiating a watchdog timer based on detecting a change in logic state of a control signal from one logic state associated with not asserting a particular bus line (e.g., a CLK line) to another logic state associated with asserting the same bus line.

[0050] Figure 5 500 may begin when a control signal having a particular logic state is output (block 502). This may include, for example, the logic circuit device 306 of the second device 304 outputting a control signal at a logic state indicating that a particular event has occurred (e.g., as an interrupt signal), or preventing communication with the first device 302 from occurring too quickly (e.g., as a clock stretching signal). Again, assertion of a control signal in this manner may in turn assert a particular bus line, such as, for example, Figure 3 CLK line shown.

[0051] Method 500 may include deviating the logic state of the control signal from a default state so that the bus line (e.g., Figure 3 CLK line shown) changes (block 504) the logic state so that the bus line is asserted. For example, this may include Figure 4B The change of the CLK signal is shown in response to the control signal being output in a logic high state causing the CLK line to change to a logic low state via the conduction of transistor 310 .

[0052] The method 500 may include starting a watchdog counter (block 506) when the watchdog circuit detects a change in the logic state of the control signal (block 502). This may include, for example, the watchdog circuit device 308 via Figure 3 The monitoring circuit 309 shown monitors the output signal and, upon detecting that the control signal is driven to a specific logic state, starts a watchdog counter (eg, a timer), as described herein with reference to Figure 4B discussed.

[0053] The method 500 may include determining (block 508) whether the control signal has changed logic state or whether the control signal remains at the same logic state. This may be done, for example, via Figure 3The method 500 may be performed by the watchdog circuit device 308 shown. For example, the determination (block 508) may be repeated each time the watchdog counter is incremented or according to any suitable sampling schedule. In the event that the logic state of the control signal has changed (e.g., restored to a default logic state or restored to a logic state before changing (block 504) the logic state of the bus line) (block 508—YES branch), the method 500 may include stopping and / or resetting (block 509) the watchdog counter. In the event that the control signal remains at the same logic state, the method 500 continues (block 508—NO branch).

[0054] Whenever the second device 304 outputs another control signal to assert the bus line, Figure 5 The process shown is repeated as follows: outputting (block 502) a control signal, changing (block 504) the logic state of the bus line in response to the control signal, starting (block 506) a watchdog counter, and determining (block 508) whether the control signal has returned to a default logic state.

[0055] When the control signal remains at the same logic state (block 508—NO branch), the method 500 may further include determining (block 510) whether the watchdog counter has reached the watchdog timeout threshold. If not, the watchdog counter may continue to run while the control signal remains at the same logic state (block 510—NO branch).

[0056] Therefore, as long as the control signal remains at the same logic state until the watchdog counter reaches the watchdog timeout threshold (block 510—YES branch), the Figure 5 The process shown in the repetition is continued as follows: continue to increment the watchdog counter (block 506), determine (block 508) whether the watchdog counter has been restored to the default logic state, and determine whether the watchdog counter has reached the watchdog timeout threshold (block 510). When the watchdog counter reaches the watchdog timeout threshold (block 510-YES branch), the watchdog circuit device 308 can output (block 511) a timeout signal. As discussed herein, the timeout signal can cause one or more parts of the second device 304 to reset, thereby resetting the logic state of the control signal to its default state and resetting the watchdog counter. However, after the reset is completed, as discussed herein, the method 500 (block 502) can be repeated each time another control signal is output to assert the bus line.

[0057] The technology of the present disclosure may also be described in the following examples.

[0058] Example 1. A device comprising a transistor coupled to a bus line external to the device and a logic circuit device internal to the device, the transistor being configured to change a logic state of the bus line from a first logic state to a second logic state in response to a control signal received from the logic circuit device; and a watchdog circuit device internal to the device, the watchdog circuit device being configured to provide a timeout signal to the logic circuit device when the control signal remains at the same logic state for more than a threshold timeout period.

[0059] Example 2. The device of Example 1, wherein the transistor is coupled to the bus line in an open-drain configuration or a push-pull configuration.

[0060] Example 3. A device of any combination of Examples 1-2, wherein the bus line is a clock line connected to the device and the second device.

[0061] Example 4. The device of any combination of Examples 1 to 3, wherein the clock line is used according to an I2C communication protocol to enable the device and the second device to communicate with each other.

[0062] Example 5. The device of any combination of Examples 1 to 4, wherein a timeout signal provided by the watchdog circuit device causes one or more portions of the device to reset.

[0063] Example 6. The device of any combination of Examples 1 to 5, wherein when one or more portions of the device are reset, the control signal changes to a different logic state than the same logic state that the control signal remained in for more than a threshold timeout period.

[0064] Example 7. The apparatus of any combination of Examples 1 to 6, wherein the watchdog circuit device is configured to start a timer based on detecting a change in the logic state of the control signal.

[0065] Example 8. The apparatus of any combination of Examples 1 to 7, wherein the watchdog circuit device is configured to operate using at least one of a different oscillator or a different power supply than the logic circuit device.

[0066] Example 9. The apparatus of any combination of Examples 1 to 8, wherein the transistor, the watchdog circuit device, and the logic circuit device are implemented on the same semiconductor chip.

[0067] Example 10. The apparatus of any combination of Examples 1-9, wherein the transistor receives a control signal from the logic circuitry via a control line, and wherein the watchdog circuitry is connected to the control line via a monitoring line.

[0068] Example 11. A system comprising a first device configured to selectively drive a bus line; and a second device coupled to the first device via the bus line, the second device configured to selectively drive the bus line and comprising a transistor coupled to the bus line and a logic circuit device inside the second device, the transistor configured to change a logic state of the bus line from a first logic state to a second logic state in response to a control signal received from the logic circuit device, the control signal indicating that the second device is to drive the bus line; and a watchdog circuit device inside the second device, the watchdog circuit device configured to monitor the logic state of the control signal and provide a timeout signal to the logic circuit device when the control signal remains at the same logic state for more than a threshold timeout period.

[0069] Example 12. The system of Example 11, wherein the first device is a master device, and wherein the second device is a slave device.

[0070] Example 13. A system of any combination of Examples 11 to 12, wherein the control signal is one of: (i) an interrupt signal that signals an event to the master device, or (ii) a clock stretching signal that prevents the master device from communicating with the slave device beyond a threshold communication rate.

[0071] Example 14. A method comprising: in response to a control signal received from a logic circuit device inside a first device, changing a logic state of a bus line from a first logic state to a second logic state via a transistor, the transistor being coupled to (i) a bus line outside the first device, and (ii) the logic circuit device; and when the control signal remains at the same logic state for more than a threshold timeout period, outputting a timeout signal via a watchdog circuit device inside the first device.

[0072] Example 15. The method of Example 14, further comprising: coupling the transistor to the bus line in an open-drain configuration or a push-pull configuration.

[0073] Example 16. The method of any combination of Examples 14-15, further comprising: coupling the bus line to the second device as a clock line coupled to the first device and the second device.

[0074] Example 17. The method of any combination of Examples 14 to 16, further comprising: asserting, via a logic circuit device, a control signal as one of: (i) an interrupt signal when the first device signals an event to the second device, or (ii) a clock stretching signal that prevents the second device from communicating with the first device at a rate exceeding a threshold communication rate.

[0075] Example 18. The method of any combination of Examples 14 to 17, wherein the timeout signal provided by the watchdog circuit device causes one or more portions of the first device to reset, thereby changing the control signal to a logic state different from the same logic state that the control signal remained in for more than a threshold timeout period.

[0076] Example 19. The method of any combination of Examples 14 to 18, further comprising: starting a timer via the watchdog circuit device based on detecting a change in the logic state of the control signal.

[0077] Example 20. The method of any combination of Examples 14 to 19, further comprising: coupling the watchdog circuit device to at least one of a different oscillator or a different power supply than the logic circuit device.

[0078] in conclusion

[0079] Although specific embodiments have been illustrated and described herein, it should be appreciated that any device calculated to achieve the same purpose may be substituted for the specific embodiments shown. The present disclosure is intended to cover any and all adaptations or variations of the various embodiments. Combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art upon reading the above description.

[0080] It should also be noted that the specific terms used in the specification and claims can be interpreted in a very broad sense. For example, the term "circuit" or "circuit device" used herein is to be interpreted in a sense that includes not only hardware but also software, firmware or any combination thereof. The term "data" can be interpreted as including any form of representation data. In addition to any form of digital information, the term "information" can also include other forms of representation information. In an embodiment, the term "entity" or "unit" can include any device, device circuit, hardware, software, firmware, chip, or other semiconductor, and a logical unit or physical implementation of a protocol layer, etc. Further, the term "coupling" or "connection" can be interpreted in a broad sense, which not only covers direct coupling, but also includes indirect coupling.

[0081] It should also be pointed out that the methods disclosed in the specification or claims may be implemented by an apparatus having means for performing each of the individual steps of these methods.

[0082] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that a variety of alternative implementations and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. The present disclosure is intended to cover any adaptation or variation of the specific embodiments discussed herein.

Claims

1. A device comprising: a transistor coupled to a bus line external to the device and to a logic circuit device internal to the device, the transistor being configured to change a logic state of the bus line from a first logic state to a second logic state in response to a control signal received from the logic circuit device; as well as A watchdog circuit arrangement is internal to the device, the watchdog circuit arrangement being configured to provide a timeout signal to the logic circuit arrangement when the control signal remains at the same logic state for more than a threshold timeout period. 2 . The apparatus of claim 1 , wherein the transistor is coupled to the bus line in an open-drain configuration or a push-pull configuration.

3. The device of claim 1, wherein the bus line is a clock line connected to the device and a second device. 4 . The device of claim 3 , wherein the clock line is used according to an I2C communication protocol to enable the device and the second device to communicate with each other.

5. The apparatus of claim 1, wherein the timeout signal provided by the watchdog circuitry causes one or more portions of the apparatus to reset. 6 . The device of claim 5 , wherein when the one or more portions of the device are reset, the control signal changes to a logic state that is different from the same logic state that the control signal remained in for exceeding the threshold timeout period. 7 . The apparatus of claim 1 , wherein the watchdog circuitry is configured to start a timer based on detecting a change in the logic state of the control signal.

8. The apparatus of claim 1, wherein the watchdog circuitry is configured to operate using at least one of a different oscillator or a different power supply than the logic circuitry.

9. The apparatus of claim 1, wherein the transistor, the watchdog circuitry, and the logic circuitry are implemented on a same semiconductor chip.

10. The apparatus of claim 1, wherein the transistor receives the control signal from the logic circuit device via a control line, and The watchdog circuit device is connected to the control circuit via a monitoring circuit.

11. A system comprising: a first device configured to selectively drive a bus line; as well as a second device coupled to the first device via the bus line, the second device being configured to selectively drive the bus line and comprising: a transistor coupled to the bus line and to logic circuitry within the second device, the transistor configured to change a logic state of the bus line from a first logic state to a second logic state in response to a control signal received from the logic circuitry, the control signal instructing the second device to drive the bus line; as well as A watchdog circuit arrangement is internal to the second device, the watchdog circuit arrangement being configured to monitor a logic state of the control signal and to provide a timeout signal to the logic circuit arrangement when the control signal remains at the same logic state for more than a threshold timeout period.

12. The system of claim 11, wherein the first device is a master device, and The second device is a slave device.

13. The system of claim 12, wherein the control signal is one of: (i) an interrupt signal that signals an event to the master device, or (ii) a clock stretching signal that prevents the master device from communicating with the slave device beyond a threshold communication rate.

14. A method comprising: responsive to a control signal received from a logic circuit arrangement internal to a first device, changing a logic state of a bus line from a first logic state to a second logic state via a transistor coupled to (i) a bus line external to the first device and (ii) the logic circuit arrangement; as well as When the control signal remains at the same logic state for more than a threshold timeout period, a timeout signal is output via a watchdog circuit arrangement internal to the first device.

15. The method according to claim 14, further comprising: The transistor is coupled to the bus line in an open drain configuration or a push-pull configuration.

16. The method according to claim 14, further comprising: The bus line is coupled to a second device as a clock line coupled to the first device and the second device.

17. The method according to claim 16, further comprising: The control signal is asserted via the logic circuit device as one of: (i) an interrupt signal when the first device signals an event to the second device, or (ii) a clock stretching signal that prevents the second device from communicating with the first device exceeding a threshold communication rate.

18. The method of claim 14, wherein the timeout signal provided by the watchdog circuit device causes one or more portions of the first device to reset, thereby changing the control signal to a logic state different from the same logic state in which the control signal remained for exceeding the threshold timeout period.

19. The method according to claim 14, further comprising: Based on detecting a change in the logic state of the control signal, a timer is started via the watchdog circuit device.

20. The method of claim 14, further comprising: The watchdog circuit arrangement is coupled to at least one of a different oscillator or a different power supply than the logic circuit arrangement.

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