Display device having pixels

Abstract

A display device having pixels is disclosed. The display device includes pixels, at least one of the pixels includes: a light emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light emitting element and controlling a driving current flowing through the light emitting element in response to a voltage of a first node; a switch transistor connected to the first node and including an active layer, the active layer including a first conductive region and a second conductive region separated from each other, a first channel region and a second channel region disposed between the first conductive region and the second conductive region, and a common conductive region disposed between the first channel region and the second channel region; and a conductive pattern overlapped with the active layer to face the common conductive region.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0101682 filed on August 20, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments relate to a pixel and a display device having the pixel. Background Art

[0003] The display device displays an image using pixels arranged in a display area. The pixels may be connected to corresponding scan lines and data lines and may include transistors. For example, a pixel of an active light emitting display device may include a light emitting element, a driving transistor, and at least one switching transistor.

[0004] In order to express the desired brightness in the pixel during the light-emitting period of each frame, it is necessary to stably maintain the gate voltage of the driving transistor. However, due to the characteristics of the transistor, leakage current will appear in the pixel. The leakage current may cause the change of the gate voltage of the driving transistor. Therefore, the desired brightness may not be fully expressed in the pixel.

[0005] It will be understood that this background technology of the technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology of the technology section may also include ideas, concepts or realizations that were not part of what was known or appreciated by a person skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0006] Embodiments of a pixel capable of effectively reducing or preventing leakage current and a display device having the pixel are provided.

[0007] The display device according to the embodiment may include a pixel arranged in a display area. The pixel may include: a light emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light emitting element and controlling a driving current flowing through the light emitting element in response to a voltage of a first node; a switching transistor connected to the first node and including an active layer. The active layer may include a first conductive region and a second conductive region separated from each other, a first channel region and a second channel region arranged between the first conductive region and the second conductive region, and a common conductive region arranged between the first channel region and the second channel region. The pixel may include a conductive pattern superimposed with the active layer to face the common conductive region.

[0008] In an embodiment, a conductive pattern may be disposed under the active layer to overlap the common conductive region.

[0009] In an embodiment, the conductive pattern may be disposed not to overlap the first conductive region and the second conductive region.

[0010] In an embodiment, the conductive pattern may be disposed not to overlap at least one of the first channel region and the second channel region.

[0011] In an embodiment, the switch transistor may include a sub-transistor including a first sub-transistor and a second sub-transistor connected to each other in series.

[0012] In an embodiment, the first sub-transistor may include a first conductive region, a first channel region, a common conductive region, and a first gate electrode overlapping the first channel region, and the second sub-transistor may include a second conductive region, a second channel region, a common conductive region, and a second gate electrode overlapping the second channel region and connected to the first gate electrode.

[0013] In an embodiment, the switch transistor may include at least three sub-transistors connected to each other in series.

[0014] In an embodiment, the active layer may include at least two common conductive regions disposed between the active layers of the at least three sub-transistors, and the pixel may include at least two conductive patterns respectively overlapping the at least two common conductive regions and spaced apart from each other.

[0015] In an embodiment, the conductive pattern may have a substantially symmetrical shape with respect to the common conductive region on a line connecting the first conductive region and the second conductive region.

[0016] In an embodiment, the conductive patterns may be electrically isolated.

[0017] In an embodiment, the conductive pattern may be connected to a gate electrode of the switching transistor.

[0018] In an embodiment, the conductive pattern may be connected to a source electrode of the switching transistor.

[0019] In an embodiment, the conductive pattern may be connected to a power source.

[0020] In an embodiment, the switching transistor may include at least one of a second transistor, a third transistor, and a fourth transistor, the second transistor being connected between the first electrode of the first transistor and the data line and including a gate electrode connected to the scan line, the third transistor being connected between the second electrode of the first transistor and the first node and including a gate electrode connected to the scan line, and the fourth transistor being connected between the first node and the initialization power supply and including a gate electrode connected to the first control line.

[0021] In an embodiment, the third transistor may include a common conductive region, and the conductive pattern may be disposed under the active layer of the third transistor to overlap the common conductive region.

[0022] In an embodiment, the fourth transistor may include a common conductive region, and the conductive pattern may be disposed under the active layer of the fourth transistor to overlap the common conductive region.

[0023] In an embodiment, a pixel may include multiple switching transistors, a predetermined number of switching transistors may be constructed by a multi-structure transistor including a first channel region and a second channel region and a common conductive region, and a conductive pattern may be disposed under the common conductive region of each of the multi-structure transistors.

[0024] According to an embodiment, a pixel may include: a light emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light emitting element and controlling a driving current flowing through the light emitting element in response to a voltage of a first node; a switching transistor connected to the first node and including an active layer, the active layer may include a first conductive region and a second conductive region separated from each other, a first channel region and a second channel region disposed between the first conductive region and the second conductive region, and a common conductive region disposed between the first channel region and the second channel region; and a conductive pattern overlapped with the active layer to face the common conductive region.

[0025] In embodiments, the conductive pattern may be disposed under the active layer to be electrically isolated.

[0026] In an embodiment, the conductive pattern may be connected to a gate electrode or a source electrode of the switching transistor or a power source.

[0027] A multi-structure switching transistor for a display device may include an active layer and a conductive pattern, the active layer may include a first conductive region and a second conductive region separated from each other, a first channel region and a second channel region arranged between the first conductive region and the second conductive region, and a common conductive region arranged between the first channel region and the second channel region, and the conductive pattern is overlapped with the active layer to face the common conductive region.

[0028] The length of the conductive pattern may be smaller than that of the active layer. The common conductive region may be disposed at a substantially central region of the active layer. The conductive pattern may be disposed to overlap the active layer and face the common conductive region.

[0029] According to the pixel and the display device having the same according to the embodiment, leakage current that may occur in the switching transistor of the pixel can be effectively reduced or prevented. Therefore, the grayscale expression of the pixel can be increased, and the image quality of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other features of the embodiments of the present disclosure will become more apparent by further describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0031] Figure 1illustrating a display area DA and a driving circuit of a display device according to an embodiment;

[0032] Figure 2 shows a pixel PXL according to an embodiment;

[0033] Figure 3 is a graphical view of signals showing a driving method of a pixel PXL according to an embodiment;

[0034] FIG. 4A to FIG. 4D Pixels PXL according to the embodiment are shown respectively;

[0035] FIG. 5A to FIG. 5D Pixels PXL according to the embodiment are shown respectively;

[0036] FIG. 6A to FIG. 6D Pixels PXL according to the embodiment are shown respectively;

[0037] 7A to 7D Pixels PXL according to the embodiment are shown respectively;

[0038] Figure 8 and Fig. 9 Schematic cross-sectional structures of a multi-structure switching transistor Tsw according to an embodiment are respectively shown;

[0039] FIG. 10A to FIG. 10D 1 and 2 respectively show the planar structures of the multi-structured switching transistor Tsw according to the embodiment; and

[0040] Fig.11 A schematic cross-sectional structure of a pixel PXL according to an embodiment is shown. DETAILED DESCRIPTION

[0041] The disclosure may be modified in various ways and may have various forms, and embodiments will be shown in the drawings and described in detail herein.In the following description, a singular form also includes a plural form unless the context clearly includes the singular.

[0042] The disclosure is not limited to the embodiments disclosed below and may be modified in various forms and may be implemented in various ways. Each of the embodiments disclosed below may be implemented alone or in combination with at least one of any or all other embodiments.

[0043] In the drawings, some components that are not directly related to the disclosed features may be omitted to clearly represent the disclosure. In addition, some components in the drawings may be shown as exaggerated in size or proportion to clarify and facilitate the description thereof. Throughout the drawings, even though components may be shown in different drawings, the same or similar components will be given by the same reference numerals and symbols as much as possible, and repeated descriptions will be omitted within the scope of the description already provided. The specification should be interpreted as including all changes, equivalents and substitutions included in the spirit and scope of the disclosure.

[0044] Furthermore, in the specification, the phrase "in a plan view" means when the target portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the target portion is viewed from the side.

[0045] In addition, the term "overlay" or its variants means that the first target can be above or below or on the side of the second target, and vice versa. In addition, the term "overlay" can include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where the third element is inserted between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, although still facing each other. When an element is described as "not" "overlaying" or "not overlapping" another element with another element, this can include elements being separated from each other, offset from each other or separated from each other or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0046] When a layer, film, zone, substrate or region is referred to as "on" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly on the other layer, film, zone, substrate or region, or there may be an intermediate layer, film, zone, substrate or region between them. On the contrary, when a layer, film, zone, substrate or region is referred to as "directly on" another layer, film, zone, substrate or region, there may not be an intermediate layer, film, zone, substrate or region between them. In addition, when a layer, film, zone, substrate or region is referred to as "below" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly below the other layer, film, zone, substrate or region, or there may be an intermediate layer, film, zone, substrate or region between them. On the contrary, when a layer, film, zone, substrate or region is referred to as "directly on" another layer, film, zone, substrate or region, there may not be an intermediate layer, film, zone, substrate or region between them. Furthermore, "above" or "over" may include positioning above or below a target and does not necessarily imply a direction based on gravity.

[0047] For ease of description, spatially relative terms such as "below", "under", "lower", "above", "on", etc. may be used herein to describe the relationship between one element or component and another (other) element or component as shown in the figure. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the figure. For example, in a case where the device shown in the accompanying drawings is flipped, a device positioned "below" or "below" another device may be placed "above" the other device. Therefore, the illustrative term "below" may include both a lower position and an upper position. The device may also be positioned in other directions, so the spatially relative terms may be interpreted differently depending on the orientation.

[0048] Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element with one or more intermediate elements interposed therebetween. It will also be understood that when the terms "comprises," "comprising," and / or variations thereof are used in this specification, they or it may specify the presence of stated features, wholes, steps, operations, elements, components, and / or any combination thereof, but do not exclude the presence or addition of other features, wholes, steps, operations, elements, components, and / or any combination thereof.

[0049] In the specification and claims, for the purpose of the meaning and interpretation of the term "and / or", the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a connected or separate sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of the meaning and interpretation of the phrase "at least one of...", the phrase "at least one of..." is intended to include the meaning of "at least one of the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0050] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element to facilitate description and explanation thereof. For example, when a "first element" is discussed in the description, it may be named "second element" or "third element," and the "second element" and "third element" may be named in a similar manner without departing from the teachings herein.

[0051] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the referenced measurements and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the stated value.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0053] Figure 1 1 and 2 show a display area DA and a driving circuit of a display device according to an embodiment. Figure 1 A light-emitting display device having a light-emitting element is illustrated as an example of the display device, but the display device is not limited thereto and may include any display device within the spirit and scope of the disclosure.

[0054] Reference Figure 1 The display device according to the embodiment includes a display area DA in which pixels PXL are disposed and a driving circuit for driving the pixels PXL. The driving circuit may include a scan driver SD, a light emission control driver ED, a data driver DD, and a timing controller TCON.

[0055] The display area DA includes scan lines S1 to Sn, light emission control lines E1 to En, and data lines D1 to Dm. When describing the embodiments, the term "connection" can comprehensively represent electrical connection and / or physical connection. For example, the pixel PXL can be electrically connected to the scan lines S1 to Sn, the light emission control lines E1 to En, and the data lines D1 to Dm.

[0056] The light emission control lines E1 to En may be selected according to the structure and / or driving method of the pixel PXL. In an embodiment, the light emission control lines E1 to En may be omitted. In the case where the light emission control lines E1 to En are omitted, the display device may not include a light emission control driver ED.

[0057] According to an embodiment, the pixel PXL may be further connected to at least one other control line (not shown). In this case, the operation of the pixel PXL may be controlled by a control signal supplied from the control line. The driving circuit may include a control line driver for driving the control line.

[0058] The pixel PXL may receive scan signals from scan lines S1 to Sn, light emission control signals from light emission control lines E1 to En, and data signals from data lines D1 to Dm, respectively. The pixel PXL may be connected to a first power source ELVDD and a second power source ELVSS to receive operating power. The pixel PXL may be connected to another power source (e.g., an initialization power source) according to a structure and / or a driving method of the pixel PXL.

[0059] When corresponding scan signals are supplied from the scan lines S1 to Sn, the pixels PXL receive corresponding data signals from the data lines D1 to Dm and emit light at brightness corresponding to the data signals. Thus, an image corresponding to the data signal of each frame can be displayed in the display area DA.

[0060] Each pixel PXL may include a light emitting element and a pixel circuit for driving the light emitting element. The pixel circuit controls a driving current flowing from the first power source ELVDD to the second power source ELVSS corresponding to a data signal. To this end, the pixel circuit may include a driving transistor and at least one switching transistor.

[0061] The scan driver SD receives the scan drive control signal SCS from the timing controller TCON and supplies the scan signal to the scan lines S1 to Sn corresponding to the scan drive control signal SCS. For example, the scan driver SD may sequentially supply the scan signal to the scan lines S1 to Sn corresponding to the scan drive control signal SCS. When the corresponding scan signal is supplied to the scan lines S1 to Sn, the pixels PXL connected to the corresponding scan lines S1 to Sn may be selected by the scan signal.

[0062] According to an embodiment, a scan signal may be used to select a pixel PXL in a horizontal line unit. For example, the scan signal may have a gate-on voltage (e.g., a low voltage), at which a transistor (e.g., at least one switching transistor) of each pixel PXL connected to the data lines D1 to Dm may be turned on, and the scan signal may be supplied to the pixel PXL of the horizontal line corresponding to each horizontal period. The pixel PXL receiving the scan signal may be connected to the data lines D1 to Dm during a period in which the scan signal is supplied to receive a corresponding data signal.

[0063] The light emitting control driver ED receives the light emitting drive control signal ECS from the timing controller TCON, and supplies the light emitting control signal to the light emitting control lines E1 to En corresponding to the light emitting drive control signal ECS. For example, the light emitting control driver ED may sequentially supply the light emitting control signal to the light emitting control lines E1 to En corresponding to the light emitting drive control signal ECS. The light emitting control driver ED may be selected according to the structure and / or driving method of the pixel PXL, and may be omitted according to an embodiment.

[0064] The light-emitting control signal can be used to control the light-emitting period (e.g., light-emitting timing and / or light-emitting duration) of the pixel PXL. For example, the light-emitting control signal may have a gate cut-off voltage (e.g., a high voltage), at which at least one switch transistor positioned on the current path of each of the pixels PXL may be turned off. In this case, the pixel PXL may be set to a non-light-emitting state during a period in which the light-emitting control signal is supplied, and may be set to a light-emitting state during other periods. When a data signal corresponding to a black grayscale is supplied to at least one pixel PXL, even if a light-emitting control signal of a gate cut-off voltage is not supplied, the pixel PXL may remain in a non-light-emitting state during a corresponding frame period corresponding to the data signal.

[0065] The data driver DD receives a data driving control signal DCS and image data RGB from the timing controller TCON and supplies data signals to the data lines D1 to Dm corresponding to the data driving control signal DCS and the image data RGB. The data signals supplied to the data lines D1 to Dm may be supplied to pixels PXL selected by corresponding scan signals.

[0066] The timing controller TCON receives various timing control signals (e.g., vertical synchronization signal / horizontal synchronization signal, main clock signal, etc.) from the outside (e.g., a main processor within the spirit and scope of the disclosure, etc.), and generates a scan drive control signal SCS, a light emitting drive control signal ECS, and a data drive control signal DCS. The scan drive control signal SCS, the light emitting drive control signal ECS, and the data drive control signal DCS can be supplied to the scan driver SD, the light emitting control driver ED, and the data driver DD, respectively.

[0067] The scan drive control signal SCS includes a first start pulse (e.g., a scan start pulse) and a first clock signal (e.g., at least one scan clock signal). The first start pulse can control the output timing of the first scan signal (e.g., the scan signal supplied to the first scan line S1), and the first clock signal can be used to sequentially shift the first start pulse.

[0068] The light-emitting driving control signal ECS includes a second start pulse (e.g., a light-emitting start pulse) and a second clock signal (e.g., at least one light-emitting clock signal). The second start pulse can control the output timing of the first light-emitting control signal (e.g., the light-emitting control signal supplied to the first light-emitting control line E1), and the second clock signal can be used to sequentially shift the second start pulse.

[0069] The data driving control signal DCS includes a source sampling pulse, a source sampling clock and a source output enable signal. The data driving control signal DCS can control the sampling operation of data.

[0070] The timing controller TCON receives input image data from the outside and rearranges the input image data to generate image data RGB. For example, the timing controller TCON may rearrange the input image data from the outside according to the specification of the data driver DD and supply the rearranged image data RGB to the data driver DD. The image data RGB supplied to the data driver DD may be used to generate a data signal.

[0071] Figure 2 Pixel PXL according to an embodiment is shown. For example, Figure 2 Shows that it can be set Figure 1 The pixels PXL disposed in the display area DA may all have substantially the same structure.

[0072] For ease of description, Figure 2 , a pixel PXL disposed at the i-th (where i represents a natural number) pixel row (e.g., the i-th horizontal line) and the j-th (where j represents a natural number) pixel column (e.g., the j-th vertical line) in the display area DA is shown. In an embodiment, the pixel PXL may be connected to the i-th scan line Si, the i-th emission control line Ei, and the j-th data line Dj. For example, the pixel PXL may be connected to at least one other control line. For example, the pixel PXL may be connected to the i-th first control line CL1i and the i-th second control line CL2i. For ease of description, in the description Figure 2 In the embodiment of the present invention, the “i-th scan line Si”, the “i-th light-emitting control line Ei” and the “j-th data line Dj” may be respectively referred to as the “scan line Si”, the “light-emitting control line Ei” and the “data line Dj”, and the i-th first control line CL1i and the i-th second control line CL2i may be respectively referred to as the “first control line CL1i” and the “second control line CL2i”.

[0073] Reference Figure 2 According to the embodiment, the pixel PXL may include a light emitting element EL and a pixel circuit PXC for driving the light emitting element EL. In the embodiment, the light emitting element EL may be connected between the pixel circuit PXC and the second power source ELVSS, but the position of the light emitting element EL is not limited thereto. For example, in the embodiment, the light emitting element EL may be connected between the first power source ELVDD and the pixel circuit PXC.

[0074] The light emitting element EL may be connected between the first power source ELVDD and the second power source ELVSS. For example, the anode electrode of the light emitting element EL may be connected to the first power source ELVDD through the pixel circuit PXC, and the cathode electrode of the light emitting element EL may be connected to the second power source ELVSS. When the driving current is supplied from the first transistor T1, the light emitting element EL may generate light of a brightness corresponding to the driving current.

[0075] In an embodiment, the light emitting element EL may be an organic light emitting diode (OLED) including an organic light emitting layer, but is not limited thereto. For example, in an embodiment, an ultra-small inorganic light emitting element as small as nanometer to micrometer may constitute the light source of each pixel PXL.

[0076] The first power source ELVDD and the second power source ELVSS may have a potential difference that allows the light emitting element EL to emit light. For example, the first power source ELVDD may be a high potential pixel power source, and the second power source ELVSS may be a low potential pixel power source having a potential smaller than the potential of the first power source ELVDD by a threshold voltage of the light emitting element EL or greater.

[0077] The pixel circuit PXC may include a driving transistor, a switching transistor, and a storage capacitor Cst. In an embodiment, the pixel circuit PXC may include one or more (or at least one) switching transistors. For example, the pixel circuit PXC may include a first transistor T1 as a driving transistor, at least one switching transistor (e.g., a second transistor T2, a third transistor T3, and / or a fourth transistor T4), and a storage capacitor Cst, the first transistor T1 controlling the driving current corresponding to the voltage of the first node N1, and at least one switching transistor (e.g., a second transistor T2, a third transistor T3, and / or a fourth transistor T4) directly or indirectly connected to the first node N1 to transmit the voltage of the data signal or the initialization power supply Vint to the first node N1.

[0078] In an embodiment, the pixel circuit PXC may include additional switch transistors. For example, the pixel circuit PXC may include a fifth transistor T5 and / or a sixth transistor T6 and a seventh transistor T7, wherein the fifth transistor T5 and / or the sixth transistor T6 are positioned on the current path of the driving current to control the light emission period of the pixel PXL, and the seventh transistor T7 is used to transmit the voltage of the initialization power supply Vint to one electrode of the light emitting element EL.

[0079] The structure of the pixel circuit PXC may be variously changed in different embodiments. The pixel PXL may include a pixel circuit PXC having various structures and / or operating in various driving methods.

[0080] In an embodiment, each of the first transistor T1 to the seventh transistor T7 may be a P-type transistor. However, the disclosure is not limited thereto. For example, in another embodiment, each of the first transistor T1 to the seventh transistor T7 may be an N-type transistor. In other embodiments, some of the first transistor T1 to the seventh transistor T7 may be P-type transistors, and the others may be N-type transistors. In this case, the gate turn-on voltage for turning on the N-type transistor may be a high voltage.

[0081] The voltage of the data signal may be determined according to the type of the first transistor T1. For example, when the first transistor T1 is a P-type transistor, since the grayscale to be expressed is high, a data signal with a lower voltage may be supplied to each pixel PXL, and when the first transistor T1 is an N-type transistor, since the grayscale to be expressed is high, a data signal with a higher voltage may be supplied to each pixel PXL.

[0082] Types of transistors configuring the pixel PXL and voltage levels of various control signals (eg, scan signals, data signals, first control signals, second control signals, and / or light emission control signals) for controlling the transistors may be variously changed according to embodiments.

[0083] The first transistor T1 may be connected between the first power source ELVDD and the second power source ELVSS to be positioned on the current path of the driving current. For example, the first transistor T1 may be connected between the first power source ELVDD and the light emitting element EL. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power source ELVDD through the fifth transistor T5, and the second electrode (e.g., drain electrode) of the first transistor T1 may be connected to the light emitting element EL through the sixth transistor T6. The gate electrode of the first transistor T1 may be connected to the first node N1.

[0084] The first transistor T1 may be a driving transistor that controls a driving current flowing through the light emitting element EL corresponding to a gate voltage (i.e., a voltage of the first node N1). For example, during a light emitting period of each frame, the first transistor T1 may control a driving current flowing from the first power source ELVDD through the light emitting element EL to the second power source ELVSS corresponding to the voltage of the first node N1.

[0085] The second transistor T2 may be connected between the data line Dj and the first electrode of the first transistor T1. A gate electrode of the second transistor T2 may be connected to the scan line Si.

[0086] When a scan signal of a gate-on voltage (e.g., a low voltage) is supplied to the scan line Si, the second transistor T2 may be turned on to connect the data line Dj to the first electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal from the data line Dj may be transmitted to the first electrode of the first transistor T1. During the period in which the second transistor T2 is turned on by the scan signal, the third transistor T3 is also turned on by the scan signal, and the first transistor T1 is turned on in the form of a diode connection through the third transistor T3. Therefore, the data signal from the data line Dj may be transmitted to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3. Therefore, the storage capacitor Cst may be charged with or store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0087] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be connected to the scan line Si. When a scan signal of a gate-on voltage is supplied to the scan line Si, the third transistor T3 may be turned on to connect the second electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 may be connected in the form of a diode.

[0088] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be connected to the first control line CL1i. According to an embodiment, the first control line CL1i may be an initialization control line for initializing the pixels PXL of the i-th horizontal line, and may receive the initialization control signal of the gate-on voltage during a previous initialization period before the scan signal of the gate-on voltage is supplied to each scan line Si.

[0089] In an embodiment, the first control line CL1i may be any one of the previous scan lines for selecting the pixels PXL of the previous horizontal line, for example, the i-1th scan line Si-1 for selecting the pixels PXL of the immediately previous horizontal line. In this case, the i-1th scan signal supplied to the i-1th scan line Si-1 may also be supplied to the first control line CL1i of the i-th horizontal line and used as an initialization control signal. In an embodiment, the first control line CL1i may be a control line formed separately from the scan lines S1 to Sn of the pixels PXL.

[0090] When a scan signal of a gate-on voltage is supplied to the first control line CL1i, the fourth transistor T4 may be turned on. When the fourth transistor T4 is turned on, the voltage of the initialization power source Vint is transmitted to the first node N1, and thus the voltage of the first node N1 is initialized to the voltage of the initialization power source Vint.

[0091] According to an embodiment, the voltage of the initialization power supply Vint may be set to a voltage equal to or less than the voltage of the data signal. For example, the voltage of the initialization power supply Vint may be set to a voltage equal to or less than the lowest voltage of the data signal. When the voltage of the first node N1 is initialized to the voltage of the initialization power supply Vint before the data signal of the current frame is transmitted to each pixel PXL, the first transistor T1 may be diode-connected in the forward direction during the scanning period of each horizontal line (i.e., the period in which the scanning signal is supplied to each scanning line Si), regardless of the data signal of the previous frame. Therefore, the data signal of the current frame can be stably transmitted to the first node N1, regardless of the data signal of the previous frame.

[0092] The fifth transistor T5 may be connected between the first power source ELVDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the light emission control line Ei. The fifth transistor T5 may be turned off when a light emission control signal of a gate-off voltage (e.g., a high voltage) is supplied to the light emission control line Ei, and may be turned on in other cases.

[0093] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element EL. The gate electrode of the sixth transistor T6 may be connected to the light emitting control line Ei. The sixth transistor T6 may be turned off when a light emitting control signal of a gate-off voltage is supplied to the light emitting control line Ei, and may be turned on in other cases.

[0094] For example, the fifth transistor T5 and the sixth transistor T6 can be turned on or off simultaneously by the light emission control signal to control the light emission period of the pixel PXL. When the fifth transistor T5 and the sixth transistor T6 are turned on, a current path through which a driving current can flow can be formed in the pixel PXL. Therefore, the pixel PXL can emit light with a brightness corresponding to the voltage of the first node N1. On the contrary, when the fifth transistor T5 and the sixth transistor T6 are turned off, the current path can be blocked and the pixel PXL may not emit light.

[0095] According to an embodiment, a light emitting control signal may be supplied as a gate-off voltage to turn off the fifth transistor T5 and the sixth transistor T6 during an initialization period and a data programming period (e.g., a scanning period) of the pixel PXL. For example, during a period in which each of the scanning signal, the first control signal, and the second control signal has a gate-on voltage, a light emitting control signal of the gate-off voltage may be supplied to overlap with the scanning signal, the first control signal, and the second control signal. After the voltages of the scanning signal, the first control signal, and the second control signal are changed to the gate-off voltage, the light emitting period of each frame may be started while the voltage of the light emitting control signal is changed to the gate-on voltage. When the light emitting period of the pixel PXL is controlled by using the light emitting control signal, the pixel PXL may emit light at a brightness corresponding to the data signal after the data signal is stably stored in the pixel PXL.

[0096] The seventh transistor T7 may be connected between the initialization power supply Vint and one electrode (e.g., an anode electrode) of the light emitting element EL. The gate electrode of the seventh transistor T7 may be connected to the second control line CL2i. According to an embodiment, the second control line CL2i may be a bypass control line for initializing a voltage charged in an organic capacitor (a parasitic capacitor generated due to the structure of the light emitting element EL) formed in the pixel PXL located at the i-th horizontal line, and may receive a bypass control signal of a gate-on voltage before each light emitting period.

[0097] In an embodiment, the second control line CL2i may be any one of the next scan lines for selecting the pixel PXL of the next horizontal line, for example, the i+1th scan line Si+1 for selecting the pixel PXL of the i+1th horizontal line, but is not limited thereto. For example, in another embodiment, the second control line CL2i may be the current scan line (i.e., the scan line Si) of each pixel PXL, or may be a control line formed separately from the scan lines S1 to Sn of the pixel PXL.

[0098] When the second control signal of the gate-on voltage is supplied to the second control line CL2i before the light-emitting period of each frame, the seventh transistor T7 may be turned on. When the seventh transistor T7 is turned on, the voltage of the initialization power supply Vint may be transmitted to one electrode of the light-emitting element EL. Therefore, when the charges charged in the parasitic capacitor formed in the light-emitting element EL are uniformly initialized, the pixel PXL may exhibit more uniform brightness characteristics corresponding to each data signal during the light-emitting period of each frame.

[0099] The storage capacitor Cst may be connected between the first power source ELVDD and the first node N1. The storage capacitor Cst may charge or store a voltage corresponding to the data signal and the threshold voltage of the first transistor T1.

[0100] In the pixel PXL according to the embodiment, the switch transistor may be formed by a dual or multi-structure transistor (hereinafter, referred to as a "multi-structure transistor"). For example, in the case where the pixel PXL includes one or more switch transistors, at least one switch transistor directly connected to the first node N1 (for example, the third transistor T3 or the fourth transistor T4 or both) may be at least one multi-structure transistor including at least two sub-transistors. The remaining switch transistors (that is, the switch transistors other than the at least one multi-structure transistor) (for example, the second transistor T2 and the fifth transistor T5 to the seventh transistor T7) may be constructed by a single-structure transistor (hereinafter, referred to as a "single-structure transistor").

[0101] For example, the third transistor T3 may include or be constructed of sub-transistors connected in series to reduce leakage current. A common conductive region CSDR (eg, a common source / drain region between two adjacent sub-transistors) may be positioned between the sub-transistors.

[0102] For example, the third transistor T3 may include or be constructed of a double transistor including a 3_1 transistor T3_1 (a first sub-transistor of the third transistor T3) and a 3_2 transistor T3_2 (a second sub-transistor of the third transistor T3) connected in series between the first node N1 and the second electrode of the first transistor T1. The common conductive region CSDR may be positioned between the 3_1 transistor T3_1 and the 3_2 transistor T3_2. For example, the 3_1 transistor T3_1 and the 3_2 transistor T3_2 may be connected integrally or non-integrally through the common conductive region CSDR.

[0103] Gate electrodes of the 3_1st transistor T3_1 and the 3_2nd transistor T3_2 may be commonly connected to the scan line Si. Therefore, the 3_1st transistor T3_1 and the 3_2nd transistor T3_2 may be simultaneously turned on or off corresponding to the scan signal.

[0104] Similarly, the fourth transistor T4 may include or be constructed of sub-transistors connected in series to each other to reduce leakage current. The common conductive region CSDR may be positioned between the sub-transistors.

[0105] For example, the fourth transistor T4 may include or be constructed of a double transistor, the double transistor including a 4_1 transistor T4_1 (a first sub-transistor of the fourth transistor T4) and a 4_2 transistor T4_2 (a second sub-transistor of the fourth transistor T4) connected in series between the first node N1 and the initialization power supply Vint. The common conductive region CSDR may be positioned between the 4_1 transistor T4_1 and the 4_2 transistor T4_2. For example, the 4_1 transistor T4_1 and the 4_2 transistor T4_2 may be connected integrally or non-integrally through the common conductive region CSDR.

[0106] Gate electrodes of the 4_1st transistor T4_1 and the 4_2nd transistor T4_2 may be commonly connected to the first control line CL1i. Therefore, the 4_1st transistor T4_1 and the 4_2nd transistor T4_2 may be simultaneously turned on or off corresponding to the first control signal (eg, the previous scan signal).

[0107] In an embodiment, each of the third transistor T3 and the fourth transistor T4 may be constructed by a dual-structure transistor, but the disclosure is not limited thereto. For example, in other embodiments, the third transistor T3 and / or the fourth transistor T4 may be constructed by a multi-structure transistor, and the number of sub-transistors that construct each of the third transistor T3 and the fourth transistor T4 may be variously changed according to the embodiment. For example, the third transistor T3 or the fourth transistor T4 or both of them may include three or more sub-transistors connected in series to each other and having a gate electrode commonly connected to the same node or signal line or may be constructed by three or more sub-transistors connected in series to each other and having a gate electrode commonly connected to the same node or signal line.

[0108] In an embodiment, only one of the third transistor T3 and the fourth transistor T4 (e.g., the third transistor T3) may be formed of a multi-structure transistor, and the other transistor (e.g., the fourth transistor T4) may be formed as a single-structure transistor. According to an embodiment, a switching transistor other than the third transistor T3 and the fourth transistor T4 (e.g., the second transistor T2 and at least one of the fifth transistor T5 to the seventh transistor T7 (e.g., the second transistor T2)) may also be formed of a multi-structure transistor including sub-transistors connected in series with each other.

[0109] The pixel PXL according to the embodiment may include at least one switching transistor, and at least one switching transistor includes a sub-transistor or is constructed by a sub-transistor. According to the embodiment, when at least one of the third transistor T3 and the fourth transistor T4 connected to the first node N1 is constructed by a double or multi-structure transistor, the leakage current of each multi-structure transistor (i.e., the third transistor T3 and / or the fourth transistor T4) can be reduced or prevented. Therefore, during the period in which each of the third transistor T3 and the fourth transistor T4 is cut off by the scan signal and the first control signal, the leakage current through the third transistor T3 and the fourth transistor T4 can be reduced or prevented. In this case, the voltage of the first node N1 can be stably maintained. Therefore, the grayscale expression of the pixel PXL can be improved, and the image quality of the display device can be improved.

[0110] However, even if at least one of the third transistor T3 and the fourth transistor T4 can be formed by a dual or multi-structure transistor, it is difficult to completely block the leakage current flowing through the third transistor T3 and / or the fourth transistor T4. For example, when the voltage of the scan line Si connected to the gate electrode of the third transistor T3 changes, the transient current Ioff_T3 flows through the third transistor T3 in both directions. Similarly, when the voltage of the first control line CL1i connected to the gate electrode of the fourth transistor T4 changes, the transient current Ioff_T4 flows through the fourth transistor T4 in both directions. A detailed description thereof will be described later.

[0111] Figure 3 is a graphical view of signals showing a driving method of the pixel PXL according to an embodiment. For example, Figure 3 The corresponding signal lines connected to the pixels PXL are shown to drive Figure 2 The waveform of the driving signal of the pixel PXL. Figure 3 , a voltage change of the common conductive region CSDR of the third transistor T3 and the fourth transistor T4 is also shown.

[0112] Reference Figure 2 and Figure 3 , one frame 1F may include a non-light-emitting period NEP and a light-emitting period EP.

[0113] The non-light-emitting period NEP of each frame 1F is a period during which a light-emitting control signal of a gate-off voltage is supplied to the light-emitting control line Ei of each pixel PXL. A scan signal may be supplied to a scan line connected to the pixel PXL during the non-light-emitting period NEP. Figure 2In an example of a driving method of a pixel PXL of an i-th horizontal line, a first control signal of a gate-on voltage (e.g., a previous scan signal), a scan signal (i.e., a current scan signal), and a second control signal of a gate-on voltage (e.g., a next scan signal) may be sequentially supplied to a first control line CL1i (e.g., an i-1th scan line Si-1), an i-th scan line Si, and a second control line CL2i (e.g., an i+1th scan line Si+1) during a non-light emitting period NEP of each frame 1F. Hereinafter, the method according to which the first control line CL1i and the second control line CL2i are respectively the i-1th scan line Si-1 and the i+1th scan line Si+1 will be described. Figure 2 An operating process of a pixel PXL of an embodiment.

[0114] When the light emission control signal of the gate-off voltage is supplied to the light emission control line Ei, the fifth transistor T5 and the sixth transistor T6 may be turned off. Therefore, the current path of the driving current may be blocked, and thus the pixel PXL may maintain a non-light emission state.

[0115] When a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on. Therefore, the first node N1 may be initialized to a voltage of an initialization power source Vint.

[0116] When a scan signal of a gate-on voltage is supplied to the i-th scan line Si, the second transistor T2 and the third transistor T3 may be turned on. The first transistor T1 may be turned on in the form of a diode connection through the third transistor T3. Therefore, the data signal from the data line Dj may be sequentially transmitted to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3. At this time, a voltage corresponding to the data signal and the threshold voltage of the first transistor T1 (for example, a difference voltage between the voltage of the data signal and the threshold voltage of the first transistor T1) may be transmitted to the first node N1, and the voltage transmitted to the first node N1 may be stored in the storage capacitor Cst.

[0117] When the scanning signal of the gate-on voltage is supplied to the i+1 scanning line Si+1, the seventh transistor T7 can be turned on. Therefore, the voltage of the initialization power supply Vint can be transmitted to the anode electrode of the light emitting element EL, thereby initializing the charge charged in the parasitic capacitor of the light emitting element EL during the previous frame period.

[0118] When the voltage of the light emitting control line Ei is changed to the gate-on voltage, the non-light emitting period NEP may end, and the light emitting period EP may start after the non-light emitting period NEP. During the light emitting period EP of each frame 1F, the voltage of the light emitting control line Ei may be maintained at the gate-on voltage. Therefore, the fifth transistor T5 and the sixth transistor T6 may be turned on, and thus a current path through which the driving current may flow may be formed in the pixel PXL.

[0119] During the light emitting period EP of each frame 1F, the first transistor T1 may generate a driving current corresponding to the voltage of the first node N1. The driving current may flow from the first power source ELVDD to the second power source ELVSS through the fifth transistor T5, the first transistor T1, the sixth transistor T6, and the light emitting element EL in sequence. Therefore, the light emitting element EL may emit light at a brightness corresponding to the driving current.

[0120] However, during the non-light-emitting period NEP of each frame 1F, for example, during a period in which a scan signal of a gate-on voltage is supplied to the i-th scan line Si, when a data signal corresponding to a black grayscale is supplied to the data line Dj, the first transistor T1 may not generate a driving current. In this case, the pixel PXL may maintain a non-light-emitting state and may express a black grayscale even in the light-emitting period EP of the corresponding frame.

[0121] In the above method, the pixel PXL may express the brightness corresponding to the data signal of each frame 1F.

[0122] In an embodiment, at least one switch transistor (eg, the third transistor T3 or the fourth transistor T4 or both) connected to the first node N1 may be formed as a dual or multi-structure transistor. Therefore, the leakage current of the pixel PXL may be reduced to some extent.

[0123] However, even if at least one of the third transistor T3 and the fourth transistor T4 is formed of a multi-structure transistor, it is difficult to completely block the leakage current flowing through the third transistor T3 and / or the fourth transistor T4. For example, in at least one of the third transistor T3 and the fourth transistor T4, since the common conductive region CSDR between the corresponding sub-transistors is in a floating state, a transient current may occur when each gate voltage changes.

[0124] For example, since the supply of the scan signal to the i-1 scan line Si-1 is stopped at time t1 and the voltage of the i-1 scan line Si-1 increases, the voltage V[CSDR_T4] of the common conductive region CSDR of the fourth transistor T4 increases. In this case, the transient current Ioff_T4 flows through the fourth transistor T4 in two directions. For example, in the fourth transistor T4, a first transient current Ioff1 (also referred to as a "main transient current") with a larger current amount flows in a direction toward the initialization power supply Vint, and a second transient current Ioff2 (also referred to as a "sub-transient current") with a smaller current amount flows in a direction toward the first node N1.

[0125] Similarly, since the supply of the scan signal to the i-th scan line Si is stopped at time t2 and the voltage of the i-th scan line Si is increased, the voltage V[CSDR_T3] of the common conductive region CSDR of the third transistor T3 will increase. In this case, the transient current Ioff_T3 will flow through the third transistor T3 in two directions. For example, in the third transistor T3, the first transient current Ioff1 with a larger current amount will flow in the direction toward the first node N1, and the second transient current Ioff2 with a smaller current amount will flow in the direction toward the first transistor T1. Here, the first transient current Ioff1 and the second transient current Ioff2 may refer to the main transient current and the sub-transient current of the transient currents in two directions generated in a given transistor (e.g., the third transistor T3 and / or the fourth transistor T4), respectively. According to an embodiment, the first transient current Ioff1 and the second transient current Ioff2 flowing through the third transistor T3 may be the same as or different from the first transient current Ioff1 and the second transient current Ioff2 flowing through the fourth transistor T4.

[0126] When transient currents Ioff_T3 and Ioff_T4 occur in at least one of the third transistor T3 and the fourth transistor T4 connected to the first node N1, the voltage of the first node N1 may be changed. Therefore, each pixel PXL may not fully express brightness corresponding to the data signal of each frame.

[0127] For example, in a low frequency mode in which the pixel PXL is driven at a low frequency lower than the reference frequency (e.g., at about 60H), as each frame 1F lasts longer, a voltage change (e.g., a voltage increase) of the first node N1 may be enhanced. In this case, a greater image quality degradation may occur in the display device, such as the occurrence of flickering that a user may recognize, than in a high frequency mode.

[0128] Therefore, in an embodiment, a structure capable of reducing or preventing leakage current that may occur in at least one switching transistor provided in the pixel PXL is disclosed. For example, in an embodiment to be described below, a structure of a pixel PXL capable of reducing or blocking transient currents Ioff_T3 and Ioff_T4 that may occur in at least one of the third transistor T3 and the fourth transistor T4 connected to the first node N1 is disclosed.

[0129] FIG. 4A to FIG. 4D Pixels PXL according to the embodiment are shown respectively. For example, FIG. 4A to FIG. 4D Shows that it can be set in Figure 1 In describing different embodiments of the pixel PXL in the display area DA. FIG. 4A to FIG. 4D In the embodiment, the above embodiment (for example, Figure 2 The same or similar components as those of the embodiment of the pixel PXL) are denoted by the same reference numerals, and detailed description about the same features previously described above will be omitted.

[0130] Reference Figure 4A , the third transistor T3 may be formed of a dual or multi-structure transistor and may include a common conductive region CSDR between the 3_1st transistor T3_1 and the 3_2nd transistor T3_2. The pixel PXL may include a conductive pattern CDP disposed to overlap with the common conductive region CSDR of the third transistor T3. For example, the conductive pattern CDP may be disposed below the active layer of the third transistor T3 to overlap with the common conductive region CSDR of the third transistor T3. According to an embodiment, the conductive pattern CDP may be regarded as a component of the third transistor T3 or may be regarded as a component of the pixel PXL that is separate from the third transistor T3.

[0131] In addition, the numbering of transistors can be arbitrary, so the third transistor T3 can be any designated number. For example, without departing from the spirit and scope of the disclosure, the third transistor T3 can be labeled as a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, etc. The identification of transistors is for ease of description and is not limited thereto.

[0132] The conductive pattern CDP may have conductivity by including at least one conductive material. The conductive pattern CDP may be transparent, opaque, or translucent. For example, the conductive pattern CDP may be a light-shielding pattern formed of a light-shielding metal, but is not limited thereto.

[0133] In an embodiment, the conductive pattern CDP may be electrically isolated. For example, the conductive pattern CDP may be insulated from other circuit elements near the conductive pattern CDP and / or float.

[0134] When the conductive pattern CDP is arranged to overlap with the common conductive region CSDR of the third transistor T3 (for example, below the common conductive region CSDR), the potential of the common conductive region CSDR can be stabilized. For example, when the conductive pattern CDP is formed of metal, since the metal itself has a work function, the potential of the common conductive region CSDR can be stabilized even if the conductive pattern CDP is electrically isolated.

[0135] According to the above-described embodiment, even if the gate voltage of the third transistor T3 is changed, the voltage change of the common conductive region CSDR between the sub-transistors configuring the third transistor T3 can be reduced or minimized. Therefore, by effectively reducing or preventing the leakage current (specifically, the transient current Ioff_T3) generated in the third transistor T3, the unexpected voltage change of the first node N1 can be reduced or minimized, and the operating characteristics of the pixel PXL can be stabilized.

[0136] Reference Figure 4B , the fourth transistor T4 may be formed of a dual or multi-structure transistor and may include a common conductive region CSDR between the 4_1st transistor T4_1 and the 4_2nd transistor T4_2. The pixel PXL may include a conductive pattern CDP disposed to overlap with the common conductive region CSDR of the fourth transistor T4. For example, the conductive pattern CDP may be disposed below the active layer of the fourth transistor T4 to overlap with the common conductive region CSDR of the fourth transistor T4. According to an embodiment, the conductive pattern CDP may be regarded as a component of the fourth transistor T4 or may be regarded as a component of the pixel PXL that is separate from the fourth transistor T4.

[0137] The conductive pattern CDP may have conductivity by including at least one conductive material. The conductive pattern CDP may be transparent, opaque, or translucent. For example, the conductive pattern CDP may be a light-shielding pattern formed of a light-shielding metal, but is not limited thereto.

[0138] In an embodiment, the conductive pattern CDP may be electrically isolated. For example, the conductive pattern CDP may be insulated from other circuit elements near the conductive pattern CDP and / or floated. When the conductive pattern CDP is arranged to overlap with the common conductive region CSDR of the fourth transistor T4 (for example, below the common conductive region CSDR), the potential of the common conductive region CSDR may be stabilized.

[0139] According to the above-described embodiment, even if the gate voltage of the fourth transistor T4 is changed, the voltage change of the common conductive region CSDR between the sub-transistors configuring the fourth transistor T4 can be reduced or minimized. Therefore, by effectively reducing or preventing the leakage current (specifically, the transient current Ioff_T4) generated in the fourth transistor T4, the unexpected voltage change of the first node N1 can be reduced or minimized, and the operating characteristics of the pixel PXL can be stabilized.

[0140] Reference Figure 4C , the pixel PXL may include a conductive pattern CDP disposed to overlap the common conductive region CSDR of each of the third transistor T3 and the fourth transistor T4. Therefore, even if the gate voltage of each of the third transistor T3 and the fourth transistor T4 is changed, the leakage current (specifically, the transient current Ioff_T3 and Ioff_T4) generated in each of the third transistor T3 and the fourth transistor T4 can be effectively reduced or prevented, and the operating characteristics of the pixel PXL can be stabilized.

[0141] Reference Figure 4D , at least one switching transistor included in the pixel PXL may include a multi-structure transistor including at least three sub-transistors. For example, the third transistor T3 may be constructed by a multi-structure transistor (e.g., a triple structure), the multi-structure transistor (e.g., a triple structure) including a 3_1st transistor T3_1, a 3_2nd transistor T3_2, and a 3_3rd transistor T3_3 connected in series to each other, and the fourth transistor T4 may be constructed by a multi-structure transistor (e.g., a triple structure), the multi-structure transistor (e.g., a triple structure) including a 4_1st transistor T4_1, a 4_2nd transistor T4_2, and a 4_3rd transistor T4_3 connected in series to each other.

[0142] In this case, each of the third transistor T3 and the fourth transistor T4 may include at least two common conductive regions CSDR positioned between two adjacent sub-transistors. For example, the active layer of each of the third transistor T3 and the fourth transistor T4 may include at least two common conductive regions CSDR inserted or disposed between the active layers of at least three sub-transistors.

[0143] In an embodiment, the pixel PXL may include a conductive pattern CDP overlapping each of the common conductive regions CSDR. For example, the pixel PXL may include a conductive pattern CDP overlapping each of the common conductive regions CSDR of the third transistor T3 (e.g., two conductive patterns CDP) and a conductive pattern CDP overlapping each of the common conductive regions CSDR of the fourth transistor T4 (e.g., two conductive patterns CDP).

[0144] In another embodiment, only one transistor (e.g., the third transistor T3 or the fourth transistor T4) of the switch transistors of the pixel PXL may be formed by a multi-structure transistor including at least three sub-transistors, and each of the remaining switch transistors may be formed by a single-structure transistor. In this case, the pixel PXL may include at least two conductive patterns CDP, and the at least two conductive patterns CDP overlap each of the at least two common conductive regions CSDR formed in the active layer of any one of the switch transistors.

[0145] The conductive pattern CDP may overlap or partially overlap the active layer of each of the third transistor T3 and / or the fourth transistor T4 to overlap each common conductive region CSDR. For example, the conductive patterns CDP may be spaced apart from each other and individually disposed under each common conductive region CSDR.

[0146] As in the above-described embodiment, the pixel PXL according to the embodiment includes a switching transistor, and at least one of the switching transistors may be constructed by a multi-structure transistor including at least one common conductive region CSDR. For example, at least one of the third transistor T3 and the fourth transistor T4 directly connected to the first node N1 may be constructed as a multi-structure transistor. The pixel PXL may include at least one conductive pattern CDP superimposed or partially superimposed with the active layer of at least one of the third transistor T3 and the fourth transistor T4. For example, the pixel PXL may include at least one conductive pattern CDP disposed under each common conductive region CSDR.

[0147] According to the above-described embodiment, even if the gate voltage of at least one of the third transistor T3 and the fourth transistor T4 is changed, by reducing the voltage change of the common conductive region CSDR between the sub-transistors configuring at least one of the third transistor T3 and the fourth transistor T4 or minimizing the voltage change of the common conductive region CSDR between the sub-transistors configuring at least one of the third transistor T3 and the fourth transistor T4, the leakage current (specifically, transient currents Ioff_T3 and Ioff_T4) generated in at least one of the third transistor T3 and the fourth transistor T4 can be effectively reduced or prevented. Therefore, the unexpected voltage change of the first node N1 can be reduced or minimized, and the operating characteristics of the pixel PXL can be stabilized. For example, even in the low-frequency mode, the brightness change of the pixel PXL caused by the leakage current can be reduced or minimized. Therefore, the image quality of the display device can be improved, such as preventing flicker.

[0148] According to the above-described embodiment, the conductive pattern CDP may be formed to correspond to each common conductive region CSDR, and thus the leakage current of at least one of the third transistor T3 and the fourth transistor T4 may be reduced without forming a low-density doped region (also referred to as a "lightly doped drain (LDD) region"). Therefore, the manufacturing process of the pixel PXL and the display device having the pixel PXL may be further simplified, and the image quality of the display device may be further improved by reducing the characteristic deviation of the pixel PXL caused by the process deviation.

[0149] FIG. 5A to FIG. 5D Pixels PXL according to the embodiment are shown respectively. For example, FIG. 5A to FIG. 5D Shown according to FIG. 4A to FIG. 4D A modified embodiment of the pixel PXL of the embodiment. FIG. 5A to FIG. 5D When describing an embodiment of the present invention, components that are the same as or similar to those of the above-described embodiment are denoted by the same reference numerals, and detailed description of the same features previously described above will be omitted.

[0150] Reference FIG. 4A to FIG. 4D and FIG. 5A to FIG. 5D Each conductive pattern CDP may be connected to a gate electrode of a corresponding switching transistor. In this case, the conductive pattern CDP may be one of components of a multi-structured switching transistor and may be formed in a gate-sink structure.

[0151] For example, the conductive pattern CDP overlapping the common conductive region CSDR of the third transistor T3 may be connected to the i-th scan line Si together with the gate electrodes of the 3_1st transistor T3_1, the 3_2nd transistor T3_2, and / or the 3_3rd transistor T3_3 configuring the third transistor T3. Similarly, the conductive pattern CDP overlapping the common conductive region CSDR of the fourth transistor T4 may be connected to the i-th first control line CL1i together with the gate electrodes of the 4_1st transistor T4_1, the 4_2nd transistor T4_2, and / or the 4_3rd transistor T4_3 configuring the fourth transistor T4.

[0152] In the above-described embodiment, the potential of the common conductive region CSDR overlapping each conductive pattern CDP can be stabilized. For example, by setting the voltage of the conductive pattern CDP to the voltage of the signal supplied to the signal line (e.g., the i-th scan line Si and / or the i-th first control line CL1i), the potential of the common conductive region CSDR overlapping the conductive pattern CDP can be stabilized. Therefore, the operating characteristics of the pixel PXL can be stabilized, and the image quality of the display device can be improved.

[0153] FIG. 6A to FIG. 6D Pixels PXL according to the embodiment are shown respectively. For example, FIG. 6A to FIG. 6D Shown according to FIG. 4A to FIG. 4D A modified embodiment of the pixel PXL of the embodiment. FIG. 6A to FIG. 6D When describing an embodiment of the present invention, components that are the same as or similar to those of the above-described embodiment are denoted by the same reference numerals, and detailed description of the same features previously described above will be omitted.

[0154] Reference FIG. 4A to FIG. 4D and FIG. 6A to FIG. 6D , each conductive pattern CDP may be connected to a source electrode of a corresponding switching transistor. In this case, the conductive pattern CDP may be one of the components of a multi-structured switching transistor and may be formed in a source-sink structure.

[0155] For example, the conductive pattern CDP overlapping the common conductive region CSDR of the third transistor T3 may be connected to the source electrode of the third transistor T3 (e.g., a node between the first transistor T1 and the third transistor T3). Similarly, the conductive pattern CDP overlapping the common conductive region CSDR of the fourth transistor T4 may be connected to the source electrode of the fourth transistor T4 (e.g., one electrode of the fourth transistor T4 connected to the first node N1).

[0156] In the above-described embodiment, the potential of the common conductive region CSDR overlapping each conductive pattern CDP can be stabilized. For example, by setting the voltage of the conductive pattern CDP to the voltage of the signal supplied to the source electrode of the switching transistor corresponding to each conductive pattern CDP, the potential of the common conductive region CSDR overlapping the conductive pattern CDP can be stabilized. Therefore, the operating characteristics of the pixel PXL can be stabilized, and the image quality of the display device can be improved.

[0157] 7A to 7D Pixels PXL according to the embodiment are shown respectively. For example, 7A to 7D Show according to FIG. 4A to FIG. 4D A modified embodiment of the pixel PXL of the embodiment. 7A to 7D When describing an embodiment of the present invention, components that are the same as or similar to those of the above-described embodiment are denoted by the same reference numerals, and detailed description of the same features previously described above will be omitted.

[0158] Reference FIG. 4A to FIG. 4D and 7A to 7D, each conductive pattern CDP may be connected to a power source Vs. In an embodiment, the power source Vs may be an operating power source supplied to the pixel PXL and / or the driving circuit. For example, the power source Vs may be a high potential pixel power source (i.e., a first power source ELVDD) supplied to the pixel PXL, or a high potential operating power source (e.g., a first driving power source for supplying a gate high voltage (VGH) as a gate cut-off voltage). For example, the power source Vs may be an operating power source of various types and / or levels.

[0159] In the above-described embodiment, the potential of the common conductive region CSDR overlapping each conductive pattern CDP can be stabilized. For example, by setting the voltage of the conductive pattern CDP to the voltage of the power supply Vs, the potential of the common conductive region CSDR overlapping the conductive pattern CDP can be stabilized. Therefore, the operating characteristics of the pixel PXL can be stabilized, and the image quality of the display device can be improved.

[0160] Figure 8 and Fig. 9 Schematic cross-sectional structures of the switching transistor Tsw of the multi-structure according to the embodiment are shown respectively. Figure 8 and Fig. 9 In the present invention, a double transistor will be disclosed as an example of a multi-structure switching transistor Tsw.

[0161] According to the embodiment, according to Figure 8 and Fig. 9 Each of the switching transistors Tsw of the embodiment may be arranged in accordance with FIG. 4A to FIG. 7D For example, the pixel PXL may include a switching transistor, at least one of which may be constructed of a multi-structure transistor including a first channel region CHR1 and a second channel region CHR2 and a common conductive region CSDR between the first channel region CHR1 and the second channel region CHR2.

[0162] according to Figure 8 and Fig. 9 Each of the switching transistors Tsw of the embodiment may represent a switch that may be set according to FIG. 4A to FIG. 7D For example, according to the multi-structure transistor in the pixel PXL of the embodiment of FIG. 4A to FIG. 7D At least one of the third transistor T3 and the fourth transistor T4 of the embodiment may be formed according to Figure 8 or Fig. 9 The structure of the switching transistor Tsw of the embodiment is formed.

[0163] Reference Figure 8 and Fig. 9According to the embodiment, the switching transistor Tsw may include an active layer ACT, a gate electrode GE, and a first electrode ET1 and a second electrode ET2, the active layer ACT being disposed on a surface of a base layer BSL on which a buffer layer BFL may be formed, the gate electrode GE being overlapped with the surface of the active layer ACT and a gate insulating film GI being inserted or disposed between the gate electrode GE and the active layer ACT, the first electrode ET1 and the second electrode ET2 being separated from the active layer ACT and connected to different regions of the active layer ACT. The conductive pattern CDP may be disposed under a region (e.g., a common conductive region CSDR) of the switching transistor Tsw. The conductive pattern CDP may be regarded as a component of the switching transistor Tsw.

[0164] According to an embodiment, the switch transistor Tsw may include a channel region for forming a channel of each sub-transistor. For example, the active layer ACT of the switch transistor Tsw may include a first channel region CHR1 and a second channel region CHR2 separated from each other, and a common conductive region CSDR is inserted or disposed between the first channel region CHR1 and the second channel region CHR2. According to an embodiment, the first channel region CHR1 may form a channel of a first sub-transistor (e.g., a 3_1 transistor T3_1 or a 4_1 transistor T4_1), and the second channel region CHR2 may form a channel of a second sub-transistor (e.g., a 3_2 transistor T3_2 or a 4_2 transistor T4_2).

[0165] Will be described from the bottom Figure 8 and Fig. 9 The base layer BSL may be a base member for forming a display panel. According to an embodiment, the base layer BSL may be a rigid or flexible substrate or film, and the material or physical properties of the base layer BLS are not particularly limited. For example, the base layer BSL may be a rigid substrate formed of glass or tempered glass, a flexible substrate (or film) of a plastic or metal material, or an insulating film of at least one layer, and the material and / or physical properties of the base layer BSL are not particularly limited. The base layer BSL may be transparent, but is not limited thereto. For example, the base layer BSL may be formed of a transparent, translucent, opaque, or reflective base member.

[0166] The conductive pattern CDP may be disposed on a surface of the base layer BSL.

[0167] The conductive pattern CDP may be disposed under the active layer ACT to overlap the active layer ACT of the switching transistor Tsw. For example, the conductive pattern CDP may be disposed under the active layer ACT to overlap the common conductive region CSDR. Therefore, the potential of the common conductive region CSDR may be stabilized.

[0168] According to an embodiment, the conductive pattern CDP may overlap the active layer ACT around the common conductive region CSDR, and may overlap or partially overlap the active layer ACT. Figure 8 In the schematic cross-sectional view shown in FIG. 1 , the conductive pattern CDP may have a width or length greater than that of the common conductive region CSDR. Fig. 9 In the schematic cross-sectional view shown in , the conductive pattern CDP may have a width or length that is smaller than that of the common conductive region CSDR. For example, the conductive pattern CDP may partially overlap the active layer ACT to have a substantially symmetrical shape relative to the common conductive region CSDR on a line connecting the first conductive region CDR1 and the second conductive region CDR2 positioned at the end of the active layer ACT. In other words, the common conductive region CSDR may be disposed at a substantially central area of ​​the active layer ACT so that the active layer ACT may be substantially symmetrical relative to the common conductive region CSDR, and the conductive pattern CDP is disposed to correspond to or face the common conductive region CSDR. In this case, on the line connecting the first conductive region CDR1 and the second conductive region CDR2, when the active layer ACT has a first length L1, the conductive pattern CDP may have a second length L2 that is shorter than the first length L1.

[0169] The structure, shape and size of the conductive pattern CDP and the common conductive region CSDR are not limited to the structure, shape and size shown in the figure, and may include any structure or shape or size within the spirit and scope of the disclosure. For example, in the schematic cross-sectional view, the conductive pattern CDP may have a substantially trapezoidal shape, and the common conductive region CSDR may have a substantially parallelogram, rhombus or rectangular shape. The thickness of the conductive pattern CDP and the common conductive region CSDR is not limited and may include any thickness within the spirit and scope of the disclosure to achieve stability of the common conductive region CSDR and reduction of crosstalk and flicker.

[0170] Similarly, the materials of the conductive pattern CDP and the common conductive region CSDR are not limited and may include any material within the spirit and scope of the disclosure to achieve stabilization of the common conductive region CSDR and reduction of crosstalk and flicker.

[0171] In at least Figure 8 and Fig. 9 In the embodiment shown in FIG. 4 , the conductive pattern CDP and the common conductive region CSDR may be disposed or substantially located between the first gate electrode GE1 and the second gate electrode GE2 of the gate electrodes GE.

[0172] In at least Figure 8 and Fig. 9In the embodiment shown in , the conductive pattern CDP and the common conductive region CSDR may be disposed or substantially located between the upper electrode GE1_2 and the lower electrode GE1_1 of the first gate electrode GE1 and the upper electrode GE2_2 and the lower electrode GE2_1 of the second gate electrode GE2.

[0173] In an embodiment, the conductive pattern CDP may be disposed not to overlap at least one region of the first and second channel regions CHR1 and CHR2. For example, the conductive pattern CDP may be disposed not to completely cover lower portions of the first and second channel regions CHR1 and CHR2.

[0174] For example, Figure 8 As shown in , the conductive pattern CDP may overlap or partially overlap the first channel region CHR1 and / or the second channel region CHR2 adjacent to the common conductive region CSDR. Fig. 9 As shown in , the conductive pattern CDP may be formed to have a smaller area that does not overlap the first and second channel regions CHR1 and CHR2 .

[0175] In this case, parasitic capacitance that may be generated by the conductive pattern CDP may be reduced or minimized. Therefore, operation characteristics (eg, operation speed, etc.) of the switching transistor Tsw may be ensured, and crosstalk may be prevented.

[0176] The buffer layer BFL may be disposed on the surface of the base layer BSL including the conductive pattern CDP.

[0177] The buffer layer BFL may be formed on the surface of the base layer BSL, and may prevent impurities from diffusing into a circuit element (e.g., a switching transistor Tsw) to be formed thereon by forming the buffer layer BFL. The buffer layer BFL may be constructed of a single layer, but may also be constructed of a multilayer of at least two layers. When the buffer layer BFL is configured as a multilayer, each layer may be formed of the same or similar material or a different material. For example, the buffer layer BFL may be formed of a silicon nitride film (SiN x ) and silicon oxide film (SiO x ) is formed by multiple layers.

[0178] The active layer ACT may be disposed on a surface of the base layer BSL including the buffer layer BFL.

[0179] The active layer ACT may include a first conductive region CDR1 and a second conductive region CDR2 separated from each other, a first channel region CHR1 and a second channel region CHR2 inserted or disposed between the first conductive region CDR1 and the second conductive region CDR2, and a common conductive region CSDR inserted or disposed between the first channel region CHR1 and the second channel region CHR2. According to an embodiment, the active layer ACT may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, or the like. For example, one region of the active layer ACT may be an intrinsic semiconductor region in which impurities may not be doped, and another region of the active layer ACT may be a conductive region in which impurities are doped. For example, the first channel region CHR1 and the second channel region CHR2 may be intrinsic semiconductor regions, and the first conductive region CDR1 and the second conductive region CDR2 and the common conductive region CSDR may be conductive regions in which impurities such as N-type or P-type impurities may be doped.

[0180] According to an embodiment, the first channel region CHR1 and the first conductive region CDR1 and the common conductive region CSDR positioned at both sides of the first channel region CHR1 may constitute an active layer of a first sub-transistor. The second channel region CHR2 and the common conductive region CSDR and the second conductive region CDR2 positioned at both sides of the second channel region CHR2 may constitute an active layer of a second sub-transistor.

[0181] According to an embodiment, the first conductive region CDR1 and the common conductive region CSDR may be the source region and the drain region of the first sub-transistor. For example, when the first conductive region CDR1 is the source region of the first sub-transistor, the common conductive region CSDR may be the drain region of the first sub-transistor.

[0182] Similarly, the common conductive region CSDR and the second conductive region CDR2 may be the source region and the drain region of the second sub-transistor. For example, when the common conductive region CSDR is the source region of the second sub-transistor, the second conductive region CDR2 may be the drain region of the second sub-transistor.

[0183] The gate insulating film GI may be disposed on the surface of the base layer BSL including the active layer ACT.

[0184] The gate insulating film GI may be disposed on the active layer ACT to cover the active layer ACT. The gate insulating film GI may be inserted or disposed between the active layer ACT and the gate electrode GE. According to an embodiment, the gate insulating film GI may be formed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the gate insulating film GI may include various types of organic / inorganic insulating materials, and the inorganic insulating material includes silicon nitride (SiN x ) and / or silicon oxide (SiO x ) etc., the structure and / or construction material of the gate insulating film GI are not particularly limited thereto.

[0185] The gate electrode GE may be provided on the surface of the base layer BSL including the gate insulating film GI.

[0186] The gate electrode GE may be constructed of a sub-gate electrode overlapping the corresponding channel region, and the gate insulating film GI is inserted or disposed between the sub-gate electrode and the corresponding channel region, and the sub-gate electrodes may be connected to each other integrally or non-integrally. For example, the gate electrode GE may include a first gate electrode GE1 overlapping the first channel region CHR1 and a second gate electrode GE2 connected to the first gate electrode GE1 and overlapping the second channel region CHR2. According to an embodiment, the first gate electrode GE1 may construct a gate electrode of a first sub-transistor, and the second gate electrode GE2 may construct a gate electrode of a second sub-transistor.

[0187] In an embodiment, the gate electrode GE may be constructed of multiple layers. For example, the first gate electrode GE1 may include a lower electrode GE1_1 disposed on the gate insulating film GI and an upper electrode GE1_2 disposed on the interlayer insulating film ILD and connected to the lower electrode GE1_1. Similarly, the second gate electrode GE2 may include a lower electrode GE2_1 disposed on the gate insulating film GI and an upper electrode GE2_2 disposed on the interlayer insulating film ILD and connected to the lower electrode GE2_1.

[0188] In an embodiment, the gate electrode GE may be configured by a single layer. For example, the first gate electrode GE1 and the second gate electrode GE2 may be formed of only each of the lower electrodes GE1_1 and GE2_1 disposed on the gate insulating film GI.

[0189] An interlayer insulating film ILD may be disposed on a surface of the base layer BSL including the lower electrode GE1_1 of the corresponding first gate electrode GE1 and the lower electrode GE2_1 of the second gate electrode GE2 .

[0190] The interlayer insulating film ILD may be constructed of a single layer or multiple layers, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the interlayer insulating film ILD may include various types of organic / inorganic insulating materials, and the inorganic insulating material may include silicon nitride (SiN x ) and / or silicon oxide (SiO x ) etc., and the structure and / or construction material of the interlayer insulating film ILD are not particularly limited thereto.

[0191] The first electrode ET1 and the second electrode ET2 of the switching transistor Tsw may be disposed on a surface of the base layer BSL including the interlayer insulating film ILD. For example, when the first gate electrode GE1 and / or the second gate electrode GE2 are formed of multiple layers, the upper electrode GE1_2 of the first gate electrode GE1 and / or the upper electrode GE2_2 of the second gate electrode GE2 may be further disposed on the interlayer insulating film ILD accordingly.

[0192] The first electrode ET1 and the second electrode ET2 may be connected to different regions of the active layer ACT. For example, the first electrode ET1 may be connected to the first conductive region CDR1 through the first contact hole CH1, and the second electrode ET2 may be connected to the second conductive region CDR2 through the second contact hole CH2.

[0193] According to an embodiment, the first electrode ET1 may be any one of the source electrode SE and the drain electrode DE of the switching transistor Tsw, and the second electrode ET2 may be the other of the source electrode SE and the drain electrode DE. For example, when the first electrode ET1 is the source electrode SE of the switching transistor Tsw, the second electrode ET2 may be the drain electrode DE of the switching transistor Tsw. Conversely, when the first electrode ET1 is the drain electrode DE of the switching transistor Tsw, the second electrode ET2 may be the source electrode SE of the switching transistor Tsw.

[0194] In the disclosure, the positions of the first electrode ET1 and the second electrode ET2 are not particularly limited and may be variously changed according to the embodiment. According to the embodiment, at least one of the first electrode ET1 and the second electrode ET2 may be omitted.

[0195] For example, when the switch transistor Tsw is directly connected to another circuit element (eg, at least one other transistor and / or capacitor, etc.) through the first conductive region CDR1, the first electrode ET1 may be omitted. The first conductive region CDR1 may be a source electrode SE or a drain electrode DE of the switch transistor Tsw.

[0196] Similarly, when the switch transistor Tsw is directly connected to another circuit element through the second conductive region CDR2, the second electrode ET2 may be omitted. The second conductive region CDR2 may be the source electrode SE or the drain electrode DE of the switch transistor Tsw.

[0197] Alternatively, the first conductive region CDR1 and / or the second conductive region CDR2 may be regarded as a source electrode SE and / or a drain electrode DE of the switching transistor Tsw. The first electrode ET1 and / or the second electrode ET2 may be regarded as a wiring or electrode of another circuit element connected to one electrode of the switching transistor Tsw.

[0198] As in the above-described embodiments, at least one switching transistor Tsw included in the pixel PXL may be configured as a dual or multi-structure transistor. For example, the switching transistor Tsw may include a first sub-transistor and a second sub-transistor connected through a common conductive region CSDR.

[0199] According to an embodiment, the first sub-transistor may include a first active layer including a first channel region CHR1 and a first gate electrode GE1 overlapping the first channel region CHR1. The first sub-transistor may include at least one electrode (eg, first electrode ET1) connected to one region of the first active layer.

[0200] The first active layer may include a first conductive region CDR1 and a common conductive region CSDR positioned at both sides of the first channel region CHR1 and the first channel region CHR1. The first conductive region CDR1 and the common conductive region CSDR may configure a source region and a drain region of the first sub-transistor.

[0201] Similarly, the second sub-transistor may include a second active layer including a second channel region CHR2 and a second gate electrode GE2 overlapping the second channel region CHR2. The second sub-transistor may include at least one electrode (eg, second electrode ET2) connected to one region of the second active layer.

[0202] The second active layer may include common conductive regions CSDR and second conductive regions CDR2 positioned at both sides of the second channel region CHR2 and the second channel region CHR2. The common conductive regions CSDR and second conductive regions CDR2 may configure source and drain regions of the second sub-transistor.

[0203] The conductive pattern CDP may be disposed under the common conductive region CSDR between the sub-transistors configuring the switch transistor Tsw of the above-described embodiment to overlap or partially overlap with the active layer ACT. Therefore, while stabilizing the potential of the common conductive region CSDR to reduce transient current, the operating characteristics (e.g., high operating speed) of the switch transistor Tsw may be ensured, and crosstalk may be prevented.

[0204] When the conductive pattern CDP is regarded as a component of the switch transistor Tsw, adjacent sub-transistors may share one conductive pattern CDP. FIG. 4A to FIG. 7D The 3_1st transistor T3_1 and / or the 4_1st transistor T4_1) and the last sub-transistor (e.g., the 3_2nd transistor T3_2 or the 3_3rd transistor T3_3 and / or the 4_2nd transistor T4_2 or the 4_3rd transistor T4_3) may include a conductive pattern CDP positioned only at one side of each channel region. Therefore, each of the first sub-transistor and the last sub-transistor may have an asymmetric cross-sectional structure.

[0205] FIG. 10A to FIG. 10D 1 and 2 show the planar structures of the switch transistor Tsw for multiple structures according to the embodiments. Fig. 10A and Fig. 10B They are shown respectively according to Figure 8 and Fig. 9 The switching transistor Tsw of the embodiment corresponds to an embodiment of a planar structure. Fig. 10C and Fig. 10D Shown according to Fig. 10A and Fig. 10B A modified embodiment of the switching transistor Tsw of the embodiment.

[0206] Reference Fig. 10A and Fig. 10B , the switching transistor Tsw may include an active layer ACT, first and second gate electrodes GE1 and GE2 overlapping different regions of the active layer ACT, and first and second electrodes ET1 and ET2 connected to both ends of the active layer ACT. According to an embodiment, the first and second gate electrodes GE1 and GE2 may be commonly connected to the same gate line GL. For example, the first and second gate electrodes GE1 and GE2 may be integrally connected to the gate line GL.

[0207] In an embodiment, the switching transistor Tsw may be the third transistor T3 and / or the fourth transistor T4 connected to the first node N1 at each pixel PXL according to the above-described embodiment. When the switching transistor Tsw is the third transistor T3, the gate line GL may be the i-th scan line Si. On the other hand, when the switching transistor Tsw is the fourth transistor T4, the gate line GL may be the i-th first control line CL1i.

[0208] The conductive pattern CDP may be disposed under the active layer ACT of the switching transistor Tsw to overlap one region of the active layer ACT.

[0209] In an embodiment, the conductive pattern CDP may be as follows Fig. 10A The conductive pattern CDP may overlap or partially overlap the first gate electrode GE1 and / or the second gate electrode GE2 as shown in FIG. The first channel region CHR1 and the second channel region CHR2 of the active layer ACT may be disposed in a region overlapping the first gate electrode GE1 and / or the second gate electrode GE2. For example, according to an embodiment, the conductive pattern CDP may overlap a region of the first channel region CHR1 and / or the second channel region CHR2.

[0210] In an embodiment, the conductive pattern CDP may be as follows Fig. 10B , and does not overlap the first gate electrode GE1 and / or the second gate electrode GE2. For example, according to an embodiment, the conductive pattern CDP may have a Fig. 10AThe area shown in FIG. 1 has a smaller area (eg, a smaller width and / or length) so as not to overlap with the first channel region CHR1 and the second channel region CHR2.

[0211] Reference Fig. 10C and Fig. 10D , at least one end of the active layer ACT may be directly connected to other circuit elements (eg, an active layer of another adjacent transistor) and / or wiring in the vicinity thereof. In this case, the first electrode ET1 and / or the second electrode ET2 may be omitted.

[0212] The planar structure of the switching transistor Tsw is not limited to the above-described embodiments. For example, in an embodiment, the area of ​​the conductive pattern CDP may be extended so that the conductive pattern CDP may overlap with the gate line GL (or gate electrode GE), the first electrode ET1 or the second electrode ET2, or the power line. The signal or voltage of the power supply may be supplied to the conductive pattern CDP by connecting the conductive pattern CDP to the gate line GL, the first electrode ET1 or the second electrode ET2, or the power line.

[0213] Fig.11 Schematic cross-sectional structure of a pixel PXL according to an embodiment is shown. For example, Fig.11 Shown according to Figure 8 A schematic cross section of a pixel PXL of an embodiment including a switching transistor Tsw and a region of a conductive pattern CDP. Fig.11 When describing an embodiment of the present invention, a detailed description of the above-mentioned switching transistor Tsw and the conductive pattern CDP regarding the same features as previously described above will be omitted.

[0214] Reference Figures 1 to 11 , the pixel PXL may include a circuit element including a switching transistor Tsw and a storage capacitor Cst, and a light-emitting element EL. For example, the pixel PXL and the display panel including the pixel PXL may include a backplane layer BPL (also referred to as a "circuit element layer" or "circuit layer") in which the circuit element of each pixel PXL and wiring connected to the circuit element are disposed, and a display element layer DPL disposed on the backplane layer BPL and having a region in which the light-emitting element EL of each pixel PXL may be disposed.

[0215] According to an embodiment, the storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2, respectively disposed on the same or different layers as any one electrode of the switching transistor Tsw. For example, the first capacitor electrode CE1 may be disposed on the gate insulating film GI together with the lower electrode GE1_1 of the first gate electrode GE1 and the lower electrode GE2_1 of the second gate electrode GE2, and the second capacitor electrode CE2 may be disposed on a layer different from that of the electrode of the switching transistor Tsw.

[0216] For example, the interlayer insulating film ILD may be formed in a multi-layer structure including a first interlayer insulating film ILD1 and a second interlayer insulating film ILD2. The second capacitor electrode CE2 may be provided between the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2.

[0217] In an embodiment, the upper electrode GE1_2 of the first gate electrode GE1 and the upper electrode GE2_2 of the second gate electrode GE2 may be disposed on the interlayer insulating film ILD together with the first electrode ET1 and the second electrode ET2 of the switching transistor Tsw. However, the positions of the first gate electrode GE1 and the second gate electrode GE2 may be changed. For example, in an embodiment, the upper electrode GE1_2 of the first gate electrode GE1 and the upper electrode GE2_2 of the second gate electrode GE2 may be disposed between the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2 together with the second capacitor electrode CE2. In an embodiment, the first gate electrode GE1 and the second gate electrode GE2 may be formed by electrodes of a single layer including only the lower electrodes GE1_1 and GE2_1 formed on the gate insulating film GI.

[0218] In other words, the structures, positions, etc. of various circuit elements, wirings, and insulating films formed on the back plane layer BPL may be variously changed according to the embodiment. A passivation film PSV may be provided on the circuit elements and wirings.

[0219] The passivation film PSV may be constructed of a single layer or multiple layers. When the passivation film PSV is provided as multiple layers, each layer may be formed of the same or similar material or different materials. For example, the passivation film PSV may be composed of multiple layers, the multiple layers including a first passivation film constructed of at least one layer of an inorganic insulating film and a second passivation film constructed of at least one layer of an organic insulating film. When the passivation film PSV includes at least one layer of an organic insulating film, the surface of the backplane layer BPL may be substantially flat.

[0220] The display element layer DPL may include the light emitting element EL, and may include a levee structure for defining a light emitting region in which each light emitting element EL may be disposed (e.g., a light emitting region of each pixel PXL), such as a pixel defining film PDL, etc. A protective film PTL may be disposed on the light emitting element EL and the pixel defining film PDL.

[0221] The light emitting element EL may include a first electrode ELE1, a light emitting layer EML, and a second electrode ELE2 sequentially stacked on the passivation film PSV. According to an embodiment, one of the first electrode ELE1 and the second electrode ELE2 of the light emitting element EL may be an anode electrode, and the other may be a cathode electrode. For example, when the first electrode ELE1 is an anode electrode, the second electrode ELE2 may be a cathode electrode.

[0222] The first electrode ELE1 of the light emitting element EL may be disposed on the passivation film PSV and may be connected to at least one circuit element configuring each pixel circuit PXC through a contact hole not shown. For example, the first electrode ELE1 may be connected to one electrode of the sixth transistor T6 and the seventh transistor T7 through a contact hole or a through hole passing through the passivation film PSV.

[0223] In each pixel region in which the first electrode ELE1 may be formed, a pixel defining film PDL that divides the light emitting region of the corresponding pixel PXL may be formed. The pixel defining film PDL may be disposed between the light emitting regions of the pixels PXL and may have an opening portion that exposes the first electrode ELE1 in the light emitting region of each pixel PXL. For example, the pixel defining film PDL may protrude upward from the surface of the base layer BSL on which the first electrode ELE1 or the like is formed or disposed, along the outer circumference of the light emitting region of each pixel PXL.

[0224] The light emitting layer EML may be formed or disposed in each light emitting region surrounded by the pixel defining film PDL. For example, the light emitting layer EML may be disposed on the exposed surface of the first electrode ELE1. The light emitting layer EML may include at least a light generating layer, and may include at least one command layer other than the light generating layer. For example, the light emitting layer EML may have a multilayer thin film structure including a light generating layer.

[0225] For example, the light emitting layer EML may include a light generating layer that emits color light, a first common layer disposed between the light generating layer and the first electrode ELE1, and a second common layer disposed between the light generating layer and the second electrode ELE2. According to an embodiment, the first common layer may include at least one of a hole injection layer and a hole transport layer. According to an embodiment, the second common layer may include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer. According to an embodiment, the light generating layer may be patterned individually corresponding to each light emitting region. The first common layer and the second common layer may be completely formed in the display area DA in which the pixel PXL may be disposed.

[0226] The second electrode ELE2 of the light emitting element EL may be formed on the light emitting layer EML. According to an embodiment, the second electrode ELE2 may be entirely formed in the display area DA, but is not limited thereto.

[0227] A protective film PTL covering the second electrode ELE2 of the light emitting element EL may be formed on the light emitting element EL. According to an embodiment, the protective film PTL may include an encapsulation layer or an encapsulation substrate provided on a region (e.g., at least the display region DA) of the display panel in which the pixel PXL may be provided to seal the pixel PXL. For example, the protective film PTL may include a thin film encapsulation layer (TFE). When the thin film encapsulation layer is formed to seal the display region DA, the thickness of the display panel may be reduced, and flexibility may be ensured while protecting the pixel PXL.

[0228] According to the embodiment, the protective film PTL may be formed of a single layer or a multilayer structure. For example, the protective film PTL may be constructed of a plurality of films including at least two inorganic films stacked on each other and at least one organic film inserted or disposed between the inorganic films. However, the structure, material, etc. of the protective film PTL may be variously changed according to the embodiment.

[0229] In the disclosure, the structure of the pixel PXL and the display panel including the same is not limited to Fig.11 For example, the type and / or structure of the pixel PXL and the display panel including the pixel PXL may be variously changed according to the embodiment.

[0230] Although the disclosed spirit and scope have been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description rather than limitation. In addition, it can be understood by those skilled in the art that various modifications within the disclosed spirit and scope are possible.

[0231] The scope of the disclosure is not limited to the details described in the detailed description of the specification, but should be defined by the claims. In addition, it should be interpreted that all changes or modifications derived from the meaning and scope of the claims and their equivalent embodiments are included in and / or within the scope of the disclosure.

Claims

1. A display device, comprising pixels arranged in a display area, wherein the pixels include: A light emitting element connected between the first power source and the second power source; a first transistor connected between the first power source and the light emitting element and controlling a driving current flowing through the light emitting element in response to a voltage of a first node; a switch transistor connected to the first node and comprising an active layer, the active layer comprising a first conductive region and a second conductive region separated from each other, a first channel region and a second channel region disposed between the first conductive region and the second conductive region, and a common conductive region disposed between the first channel region and the second channel region; as well as A conductive pattern is disposed below the active layer and overlaps a central area of ​​the common conductive region of the active layer.

2. The display device according to claim 1, in, The switch transistor includes a plurality of sub-transistors including a first sub-transistor and a second sub-transistor connected in series to each other.

3. The display device according to claim 2, in, The first sub-transistor includes the first conductive region, the first channel region, the common conductive region, and a first gate electrode overlapping the first channel region, and The second sub-transistor includes the second conductive region, the second channel region, the common conductive region, and a second gate electrode overlapping the second channel region and connected to the first gate electrode.

4. The display device according to claim 2, in, The switching transistor includes at least three sub-transistors connected in series to each other.

5. The display device according to claim 4, in, The active layer includes at least two common conductive regions disposed between the active layers of the at least three sub-transistors, and The pixel includes at least two conductive patterns respectively overlapping the at least two common conductive regions and spaced apart from each other.

6. The display device according to claim 1, in, The conductive pattern is connected to a gate electrode of the switching transistor.

7. The display device according to claim 1, in, The switching transistor includes at least one of a second transistor, a third transistor and a fourth transistor, the second transistor is connected between the first electrode of the first transistor and the data line and includes a gate electrode connected to the scan line, the third transistor is connected between the second electrode of the first transistor and the first node and includes a gate electrode connected to the scan line, and the fourth transistor is connected between the first node and an initialization power supply and includes a gate electrode connected to the first control line.

8. The display device according to claim 7, in, The third transistor includes the common conductive region, and The conductive pattern is disposed under the active layer of the third transistor to overlap the common conductive region.

9. The display device according to claim 7, in, The fourth transistor includes the common conductive region, and The conductive pattern is disposed under the active layer of the fourth transistor to overlap the common conductive region.

10. The display device according to claim 1, in, The pixel includes a plurality of switching transistors, A predetermined number of the switch transistors are constructed by multi-structure transistors each including the first channel region, the second channel region and the common conductive region, and The conductive pattern is disposed under the common conductive region of each of the multi-structure transistors.

Images