Semiconductor device and method of forming the same

Abstract

Embodiments of the invention disclose a semiconductor device and a method of forming the same. A nanocrystal high-k film can be deposited as an amorphous matrix layer of dielectric material, and self-contained nanocrystal regions can be formed suspended within the amorphous matrix layer. In this way, the amorphous matrix layer material separates the self-contained nanocrystal regions from one another, thereby avoiding the formation of grain boundaries within the dielectric layer as a path for leakage and / or oxidation. Doping can be implanted into the dielectric material, and the crystalline phase of the self-contained nanocrystal regions can be modified to change one or more of the dielectric constant of the high-k dielectric material and / or the ferroelectric properties of the dielectric material.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a method for forming a nanocrystalline high dielectric constant thin film in a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, which allows more components to be integrated within a given area. However, as the minimum feature size shrinks, additional problems also arise that need to be addressed. Summary of the Invention

[0004] The purpose of this invention is to provide a method for forming a semiconductor device to solve at least one of the above-mentioned problems.

[0005] This invention provides a method for forming a semiconductor device. The method includes: first, depositing a dielectric layer on a fin in a channel region of the semiconductor device; then performing a first annealing process on the dielectric layer to form multiple nanocrystalline regions, which are suspended within an amorphous matrix layer of the dielectric layer and separated by the amorphous matrix layer; and finally, depositing a metal layer on the dielectric layer in the channel region of the semiconductor device.

[0006] This invention provides a method for forming a semiconductor device. The method includes: first, forming a gate dielectric layer in a fin field-effect transistor (FFET) of the semiconductor device, the gate dielectric layer comprising a dielectric material; next, forming a plurality of self-contained crystalline regions in the dielectric material of the gate dielectric layer, the plurality of self-contained crystalline regions comprising a plurality of crystalline / amorphous interfaces, wherein the plurality of self-contained crystalline regions are separated from each other by the dielectric material of an amorphous matrix layer of the gate dielectric layer; and then, depositing a metal gate structure on the gate dielectric layer of the fin field-effect transistor of the semiconductor device.

[0007] This invention provides a semiconductor device comprising: a fin of a field-effect transistor; a gate dielectric layer deposited on the fin, the gate dielectric layer comprising a plurality of self-contained nanocrystal regions, the nanocrystal regions comprising a plurality of crystalline / amorphous interfaces, wherein the self-contained crystalline regions are separated from each other by an amorphous matrix dielectric material of the gate dielectric layer; and a metal gate electrode deposited on the gate dielectric layer. Attached Figure Description

[0008] The best way to understand the various aspects of this disclosure is to read the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0009] Figure 1 The steps in the process of forming a fin field-effect transistor device are shown according to some embodiments.

[0010] Figure 2 The formation of the source / drain regions and the interlayer dielectric (ILD) layer is illustrated according to some embodiments.

[0011] Figures 3A-3C The formation of the first dielectric layer is illustrated in three related views according to some embodiments.

[0012] Figure 4 An optional first annealing process is shown according to some embodiments.

[0013] Figure 5 The formation of the capping layer is illustrated according to some embodiments.

[0014] Figures 6A-6B An optional second annealing process is illustrated in two related views according to some embodiments.

[0015] Figures 7A-7B The formation of a nanocrystalline high dielectric constant material layer is illustrated according to some embodiments.

[0016] Figures 8A-8B The formation of the gate electrode structure is illustrated in two related views according to some embodiments.

[0017] The attached figures are labeled as follows:

[0018] 100: Semiconductor devices

[0019] 101:Substrate

[0020] 103: First trench

[0021] 105: First Quarantine Zone

[0022] 107: Fins

[0023] 109: Dummy gate dielectric

[0024] 111: Dummy gate electrode

[0025] 113: First spacer

[0026] 115: Virtual Stack

[0027] 203: Interlayer dielectric layer

[0028] 207: Opening

[0029] 211: First dielectric layer

[0030] 401: Post-deposition annealing process

[0031] 411: Simple Nanocrystalline Thin Film

[0032] 501,807: Cap layer

[0033] 601: Top cover post-annealing process

[0034] 611: Compound Nanocrystalline Thin Film

[0035] 700, 750: Layered stacked materials

[0036] 701: Interface Layer

[0037] 703: Amorphous matrix layer

[0038] 705, 715: Nanocrystalline region

[0039] 707, 717: Integrated Interface

[0040] 709: Cap layer

[0041] 801: First metal layer

[0042] 803: Third Metallic Material

[0043] 805: Gate Stack

[0044] 809: First Etching Stop Layer

[0045] CS1, CS2: Crystal sizes

[0046] A-A', B-B', C-C': Cutting lines

[0047] T1, T2: Thickness

[0048] H1, H2: Height

[0049] D1: Distance Detailed Implementation

[0050] The following embodiments provide many different embodiments or examples for implementing various features of the invention. Specific examples of the components and their configurations are described below to simplify the description of the embodiments of the invention. Of course, these are merely examples and are not intended to be limiting. For example, if the description refers to a first component forming on or over a second component, it may include embodiments where the formed first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference numerals and / or letters in different examples. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0051] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0052] Reference Figure 1 This image shows a cross-sectional view of a semiconductor device 100 (e.g., a fin field-effect transistor device). In one embodiment, the fin field-effect transistor device 100 includes a substrate 101 and a first trench 103 formed therein. The substrate 101 may be a silicon substrate, although other substrates may also be used, such as semiconductor-on-insulator (SOI), strained SOI, and silicon-germanium-on-insulator. The substrate 101 may be a p-type semiconductor, although in other embodiments it may be an n-type semiconductor.

[0053] A first trench 103 can be formed as a starting step for the final formation of the first isolation region 105. This can be achieved through a mask layer (in...) Figure 1 (Not shown separately) and a suitable etching process are used to form the first trench 103. For example, the mask layer can be a hard mask including silicon nitride formed by chemical vapor deposition (CVD), although other materials such as oxides, oxide oxynitrides, silicon carbide, combinations thereof, or similar materials can also be used, as well as other processes such as plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or even silicon oxide followed by nitriding. Once formed, the mask layer can be patterned using a suitable photolithography process to expose the portions of the substrate 101 that will be removed to form the first trench 103.

[0054] However, as those skilled in the art to which this invention pertains will know, the aforementioned mask layer forming process and materials are not the only methods for protecting portions of the substrate 101 when other portions of the substrate 101 are exposed to form the first trench 103. The portions of the substrate 101 to be removed to form the first trench 103 can be exposed by any suitable process (e.g., patterning and developing photoresist). The scope of this embodiment is fully intended to encompass all such methods.

[0055] Once the mask layer is formed and patterned, a first trench 103 is formed in the substrate 101. The exposed substrate 101 can be removed by a suitable process (e.g., reactive ion etching, RIE) to form the first trench 103 in the substrate 101, although any suitable process may be used. In one embodiment, the first trench 103 may be formed with a first depth of less than about 5000 angstroms from the surface of the substrate 101, for example, about 2500 angstroms.

[0056] However, those skilled in the art will understand that the above-described process for forming the first trench 103 is merely a possible process and is not intended to be the only embodiment. Rather, any suitable process for forming the first trench 103 can be utilized, and any suitable process including any number of masking and removal steps can be used.

[0057] In addition to forming the first trench 103, the masking and etching processes further form fins 107 from the remaining portions of the substrate 101 that have not been removed. For simplicity, the fins 107 shown in the figures are separated from the substrate 101 by dashed lines and different patterns, although physical representations of separation may or may not be shown. As discussed below, the fins 107 can be used to form the channel regions of multi-gate fin field-effect transistors. Although Figure 1 Only three fins 107 formed from the substrate 101 are shown, but any number of fins 107 can be used.

[0058] Fins 107 can be formed such that their width on the surface of substrate 101 is between about 5 nanometers and about 80 nanometers, such as about 30 nanometers. Furthermore, fins 107 can be spaced apart from each other at a distance between about 10 nanometers and about 100 nanometers, such as about 50 nanometers. By spacing the fins 107 apart in this way, each fin 107 can form a separate channel region, while still being close enough to share a common gate.

[0059] Once the first trench 103 and fin 107 are formed, the first trench 103 can be filled with a dielectric material, and the dielectric material in the first trench can be etched to form a first isolation region 105. The dielectric material can be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material can be formed using chemical vapor deposition (CVD) methods (e.g., high-aspect-ratio process, HARP), high-density plasma CVD methods, or other suitable methods known in the art to which this invention pertains, after optionally cleaning or lining the first trench 103.

[0060] The first trench 103 can be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material, followed by removing the excess material outside the first trench 103 and the fin 107 using a suitable process such as chemical mechanical polishing (CMP), etching, or a combination thereof. In one embodiment, the removal process also removes any dielectric material above the fin 107, thus exposing the surface of the fin 107 for further processing steps.

[0061] Once the first trench 103 is filled with a dielectric material, the dielectric material can then be etched away from the surface of the fin 107. The etching step can be performed to expose at least a portion of the sidewalls of the fin 107 adjacent to the top surface. The dielectric material can be etched by wet etching, which involves immersing the top surface of the fin 107 in an etchant such as HF, although other etchants (e.g., H2) and other methods, such as reactive ion etching, dry etching using etchants like NH3 / NF3, chemical oxide removal, or dry chemical clean, can also be used. The dielectric material can be etched to a distance between about 50 angstroms and about 500 angstroms from the fin 107, for example, about 400 angstroms. Furthermore, the etching step can also be used to remove any remaining dielectric material above the fin 107 to ensure that the fin 107 is exposed for further processing.

[0062] However, those skilled in the art will understand that the above steps are only part of the overall process for filling and etching the dielectric material. For example, the first trench 103 can be formed and filled with dielectric material using a lining step, a cleaning step, an annealing step, a gap filling step, combinations thereof, and the like. The scope of this embodiment is fully intended to include all possible process steps.

[0063] After the first isolation region 105 is formed, a dummy gate dielectric 109, a dummy gate electrode 111 above the dummy gate dielectric 109, and a first spacer 113 may be formed on each fin 107. In one embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art to which this invention pertains. Depending on the technique used to form the gate dielectric, the thickness of the dummy gate dielectric 109 on the top of the fin 107 may differ from its thickness on the sidewalls of the fin 107.

[0064] The dummy gate dielectric 109 may comprise a material such as silicon dioxide or silicon oxynitride, with a thickness ranging from about 3 angstroms to about 100 angstroms, for example, about 10 angstroms. The dummy gate dielectric 109 may be formed of a high dielectric constant (high k-value) material (e.g., a relative dielectric constant greater than about 5), such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or zirconium oxide (ZrO₂), or a combination thereof, with an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, for example, about 10 angstroms or less. Furthermore, any combination of silicon dioxide, silicon oxynitride, and / or high dielectric constant materials may also be used for the dummy gate dielectric 109.

[0065] The dummy gate electrode 111 may comprise a conductive material, and is selected from the group consisting of W, Al, Cu, AlCu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or similar materials. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art to which this invention pertains for depositing conductive materials. The thickness of the dummy gate electrode 111 may range from about 5 angstroms to about 200 angstroms. The dummy gate electrode 111 may have a non-planar top surface and may be planarized before patterning the dummy gate electrode 111 or before etching the gate. Ions may or may not be introduced at this time. Ions may be introduced by ion implantation techniques.

[0066] Once formed, the dummy gate dielectric 109 and dummy gate electrode 111 can be patterned to form a series of dummy stacks 115 on the fin 107. The dummy stacks 115 define multiple channel regions on each side of the fin 107 adjacent to the dummy gate dielectric 109. The gate mask (not shown) on the dummy gate electrode 111 can be deposited and patterned using deposition and photolithography techniques known in, for example, the art to which this invention pertains. Figure 1(Shown separately) to form the dummy stack 115. The gate mask may combine commonly used mask and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC and / or silicon nitride, and may be deposited to a thickness between about 5 angstroms and about 200 angstroms. The dummy gate electrode 111 and the dummy gate dielectric 109 may be etched by a dry etching process to form the patterned gate stack 115.

[0067] Once the dummy stack 115 is patterned, a first spacer 113 can be formed. The first spacer 113 can be formed on the opposite side of the dummy stack 115. The first spacer 113 is typically formed by depositing a spacer layer (not on) a blanket deposition on the previously formed structure. Figure 1 (Shown separately) to form. The spacer layer may include SiN, oxide nitride, SiC, SiON, SiOCN, SiOC, oxides, and the like, and may be formed by methods used to form such a film, such as chemical vapor deposition (CVD), plasma-assisted CVD, sputtering, and other methods known in the art to which this invention pertains. The spacer layer may include different materials with different etching properties, or the same material as the dielectric material in the first isolation region 105. The first spacer 113 may then be patterned, such as by removing the spacer layer from the horizontal surface of the structure through one or more etching processes to form the first spacer 113.

[0068] In one embodiment, the first spacer 113 may be formed with a first thickness T1 between about 5 angstroms and about 500 angstroms, for example, 50 angstroms. Furthermore, once the first spacer 113 is formed, a first spacer 113 adjacent to one stack 115 may be separated from a first spacer adjacent to another stack 115 by a distance D1 between about 5 nanometers and about 200 nanometers, for example, about 20 nanometers. However, any suitable thickness and distance may be used.

[0069] Figure 2 The source / drain region 201 of the semiconductor device 100 is shown. Figure 2 Further illustration shows the removal of the gate stack 115 to form an opening 207 between the first spacers 113, and the exposure of the fins 107 in the channel region of the semiconductor device 100 for further processing.

[0070] According to some embodiments, removal is as follows Figure 1The portion of fin 107 shown is not protected by the dummy stack 115 and is not protected by the first spacer 113. Once these regions of fin 107 are removed, the source / drain regions 201 are regrown. The step of removing the regions of fin 107 not protected by the dummy stack 115 and the first spacer 113 can be performed by reactive ion etching (RIE) using the dummy stack 115 and the first spacer 113 as hard masks, or by any suitable removal process. The removal process can continue until the fin 107 is flush with or below the surface of the first spacer region 105.

[0071] Once these portions of fin 107 are removed, a hard mask is placed and patterned to cover the dummy gate electrode 111 to prevent its growth, and the source / drain regions 201 can be regrowed while in contact with each fin 107 in the channel region located beneath the dummy stack 115. In one embodiment, the source / drain regions 201 can be regrowed, and in some embodiments, the source / drain regions 201 can be regrowed to form stress sources that apply stress to the channel region of the fin 107 located beneath the dummy stack 115. In one embodiment, the fin 107 comprises silicon and the fin field-effect transistor is a p-type device. The source / drain regions 201 can be regrowed using selective epitaxial processes and materials such as silicon, or materials having a different lattice constant than the channel region, such as silicon-germanium. In other embodiments, the material of the source / drain region 201 may include, for example, GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, combinations thereof, or similar. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, etc., and may be sustained between about 5 minutes and about 120 minutes (e.g., about 30 minutes).

[0072] In one embodiment, the source / drain region 201 may be formed with a thickness between about 5 angstroms and about 1000 angstroms, and may have a first height H1 between about 10 angstroms and about 500 angstroms, for example about 200 angstroms, on the first isolation region 105. However, any suitable height may be used.

[0073] Once the source / drain region 201 is formed, the doping in the fins 107 located below the dummy stack 115 can be supplemented by implanting appropriate dopants into the source / drain region 201. For example, p-type dopants such as boron, gallium, indium, or the like can be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, or the like can be implanted to form an NMOS device. The dummy stack 115 and the first spacer 113 can be used as a mask for implanting these dopants. It should be noted that those skilled in the art will appreciate that many other processes, steps, or the like can be used for doping. For example, those skilled in the art will appreciate that various combinations of spacers and liners can be used to perform multiple implantation processes to form source / drain regions with a specific shape or characteristics suitable for a particular purpose. Any of these processes can be used for doping, and the above description is not intended to limit the invention to the steps described above.

[0074] Figure 2 Also shown is the interlayer dielectric (ILD) layer 203 located above the dummy stack 115 and above the source / drain region 201. Figure 2 The formation of the interlayer dielectric layer 203 (shown in dashed lines to more clearly illustrate the structure below) may be described. The interlayer dielectric layer 203 may comprise a material such as boron phosphorous silicate glass (BPSG), although any suitable dielectric may be used. The interlayer dielectric layer 203 may be formed using a process such as PECVD, although other processes such as LPVCD may be used alternatively. The interlayer dielectric layer 203 may be formed to have a thickness T2 between approximately 100 angstroms and approximately 3000 angstroms. Once formed, the interlayer dielectric layer 203 may be planarized flush with the dummy stack 115 and the first spacer 113 using a planarization process such as chemical mechanical polishing, although any suitable process may be used.

[0075] After forming the interlayer dielectric layer 203, the dummy gate electrode 111 and dummy gate dielectric 109 of the dummy stack 115 can be removed to provide an opening 207 between the first spacers and expose the fins 107 in the channel region of the semiconductor device 100. In one embodiment, the dummy gate electrode 111 and dummy gate dielectric 109 can be removed, for example, by one or more dry etching processes, wherein the etchant used in the dry etching process is selective for the materials of the dummy gate electrode 111 and dummy gate dielectric 109 of the dummy stack 115. However, any suitable removal process can be used. Once the dummy gate electrode 111 and dummy gate dielectric 109 of the dummy stack 115 have been removed, the remaining opening 207 can be used to form a metal gate stack structure therein, which will be discussed in detail below.

[0076] Reference Figure 3A The accompanying drawings illustrate the deposition of a first dielectric layer 211 on the semiconductor device 100 after the dummy gate electrode 111 and dummy gate dielectric 109 of the dummy stack 115 have been removed. In some embodiments, the first dielectric layer 211 is deposited as an amorphous matrix layer using a high dielectric constant material (e.g., a relative permittivity greater than about 5), including hafnium oxide (HfO2), zirconium oxide (ZrO2), combinations thereof, or the like. According to some embodiments, the first dielectric layer 211 is deposited to a thickness between about 1 nanometer and about 3 nanometers, for example, about 1.5 nanometers, using a process such as atomic layer deposition (ALD) or the like. However, the first dielectric layer 211 can be formed using any suitable material, any suitable deposition process, and any suitable thickness.

[0077] In one embodiment, the atomic layer deposition process can be performed using a series of cyclical steps, which may involve introducing a first precursor for a first self-limiting reaction, purging the first precursor, introducing a second precursor for a second self-limiting reaction, and purging the second precursor to complete a first cycle. Once the first cycle is completed, the first cycle can be repeated to perform a second cycle, with each cycle depositing a monolayer of the desired material. For example, in an embodiment where the first dielectric layer 211 is hafnium oxide, a first precursor such as hafnium chloride may be introduced and then purged, and a second precursor such as oxygen or ozone may be introduced to form a single monolayer of hafnium oxide.

[0078] Furthermore, in some embodiments where atomic layer deposition (ALD) is used to form initial crystals rather than fully amorphous materials, the first dielectric layer 211 can be deposited via high-temperature ALD at temperatures above about 300°C (e.g., about 350°C) and at periods between about 300 seconds and about 1800 seconds (e.g., about 600 seconds). In this way, the first dielectric layer 211 is deposited as a nanocrystalline film of a high dielectric constant material, comprising multiple self-contained nanocrystallite regions suspended within the amorphous matrix layer. The nanocrystalline regions and the amorphous matrix layer will be discussed in more detail below.

[0079] Figure 3B Show along line B-B' Figure 3A A cross-sectional view. Specifically, Figure 3BThe deposition of the first dielectric layer 211 is shown, wherein the first dielectric layer 211 is conformally deposited on the upper surface and sidewalls of the planarized first spacer 113, on the surface exposed at the bottom of the opening 207 formed between the first spacers 113 in the channel region of the semiconductor device, and on the surface exposed on the interlayer dielectric layer 203 in the source / drain region 201 of the semiconductor device 100.

[0080] Figure 3C Shown along line C-C' Figure 3A A cross-sectional view. Specifically, Figure 3C The deposition of a first dielectric layer 211 is shown, wherein the first dielectric layer 211 is conformally deposited on the exposed surface of the fin 107 in the channel region of the semiconductor device, the exposed surface being formed in the opening 207 between the sidewalls of the first spacer 113.

[0081] Figure 4 According to some embodiments, an optional post-deposit anneal (PDA) process is shown (in... Figure 4 (This is indicated by the arrow marked 401). For example, in embodiments where the deposition process has not formed initial crystals or provided a minimum amount of crystals, once the first dielectric layer 211 is deposited, an optional post-deposition annealing process can be performed to anneal the first dielectric layer 211, causing a plurality of first-type nanocrystal regions to form in the amorphous matrix layer and / or further crystallizing any first-type nanocrystal regions formed in the amorphous matrix layer. In this way, a simple nanocrystal thin film 411 is formed from the first dielectric layer 211 and disposed on the fin 107 of the channel region of the semiconductor device 100. The nanocrystal regions and the amorphous matrix layer will be discussed in more detail below.

[0082] In one embodiment, an optional post-deposition annealing (PDA) process can be performed as a low-temperature soak anneal process at a temperature below about 700°C (e.g., about 500°C) and at a period between about 5 seconds and about 1800 seconds (e.g., about 300 seconds). In other embodiments, an optional PDA process can be performed at a temperature above about 800°C (e.g., about 1100°C) and at a period of less than 100 milliseconds (e.g., about 3 milliseconds). In yet another embodiment, an optional PDA process can be performed as a spike anneal process at a temperature between about 700°C and about 1000°C (e.g., about 850°C) and at a period of greater than 0.5 seconds (e.g., about 1.5 seconds). However, any suitable temperature and any suitable period can be used to perform any low-temperature PDA process, high-temperature PDA process, and PDA process.

[0083] Figure 5 The deposition process of capping layer 501 on semiconductor device 100 is illustrated. In some embodiments, capping layer 501 may be formed on... Figure 2 On the first dielectric layer 211; and in some embodiments, the capping layer 501 may be formed on Figure 4 The capping layer 501 is deposited on a first-type nanocrystalline thin film 411. The capping layer 501 can be deposited as a single-layer or double-layer film using one or more materials, including, for example, TiN, TaN, or W; amorphous silicon (e.g., a-Si); high-dielectric-constant dielectrics such as Al₂O₃, ZrO₂, and TiO₂; compounds of the above or similar. The capping layer 501 can be deposited to a thickness between about 1 nanometer and about 50 nanometers, for example, about 2 nanometers, using processes such as atomic layer deposition (ALD) or similar methods. Although any suitable material, any suitable deposition process, and any suitable thickness can be used to form the capping layer 501.

[0084] Figure 6A According to some embodiments, an optional post-capping anneal (PCA) process is shown (in... Figure 6A (This is indicated by the arrow marked 601). Based on the material composition used to form the high-dielectric-constant dielectric material 211 and / or based on the material composition used to form the capping layer 501, in some embodiments, an optional capping post-annealing (PCA) process may be performed separately from post-deposition annealing (PDA). In other embodiments, based on the material composition used to form the high-dielectric-constant dielectric material 211 and / or based on the material composition used to form the capping layer 501, an optional capping post-annealing (PCA) process may be performed in conjunction with post-deposition annealing (PDA).

[0085] For example, according to some embodiments, after depositing a capping layer on the first dielectric layer 211, the first dielectric layer 211 can be pre-annealed using an optional capping-after-annealing (PCA) process without performing a PDA process, and a first-type nanocrystalline region can be preliminarily formed within an amorphous matrix layer of a high-dielectric-constant material. In this way, a simple nanocrystalline thin film 411 is formed from the first dielectric layer 211 and disposed on the fins 107 in the channel region.

[0086] In other embodiments, after depositing a capping layer 501 on the simple nanocrystalline film 411 formed, for example by an optional post-deposition annealing (PDA) process, an optional top cap post-annealing (PCA) process can be used to further crystallize any first-type nanocrystalline regions previously formed in the amorphous high-dielectric-constant material of the simple nanocrystalline film 411, and / or initially form second-type nanocrystalline regions in the amorphous high-dielectric-constant material. In this way, a compound nanocrystalline film 611 is formed from the first dielectric layer 211 and disposed on the fins 107 of the channel region.

[0087] In one embodiment, optional post-metallization annealing (PMA) and / or optional cap post-annealing (PCA) processes can be performed as a spike annealing process at a temperature between about 700°C and about 1000°C (e.g., about 850°C) and at a cycle greater than 0.5 seconds (e.g., about 1.5 seconds). However, any suitable temperature and any suitable cycle can be used to perform the optional PMA and / or optional cap post-annealing (PCA) processes.

[0088] Although the embodiments disclosed herein pertain to the deposition and annealing process of a high-dielectric-constant material thin film on the channel region of the fin 107 of a semiconductor device 100, the deposition and annealing process of a high-dielectric-constant material thin film can be used in other applications without departing from the spirit of the invention and is considered to fall within the scope of the embodiments disclosed herein. Furthermore, the examples provided herein pertain to a high-dielectric-constant material thin film having a thickness of less than about 2.5 nanometers and a film composition including materials such as HfO2; other suitable regions, other semiconductor devices, other suitable thicknesses, and other suitable materials can be used and are considered to fall within the scope of the embodiments disclosed herein. In this way, the thermal budget can be varied according to the film thickness and film composition without departing from the spirit of the disclosed embodiments.

[0089] Figure 6B Along line B-B', it is shown in the sedimentary cap layer 501 and in Figure 6AThe optional top cover post-annealing process shown Figure 3A A cross-sectional view. Specifically, Figure 6B A capping layer 501 is shown conformally disposed on the surface of a compound nanocrystal thin film 611 of a semiconductor device 100. In this manner, the capping layer 501 is conformally disposed along the compound nanocrystal thin film 611, which is disposed along the sides and sidewalls of the upper surface of the planarized first spacer 113, along the surface of the fins 107 in the channel region at the bottom of the opening 207, and along the surface of the interlayer dielectric layer 203 on the source / drain region 201.

[0090] Figure 7A The formation of multiple nanocrystal regions 705, for example, in a simple nanocrystal thin film 411 is shown in more detail. Figure 7A A portion of a layered stacked material 700 is shown, such as a simple nanocrystalline film 411 comprising a portion of the material above a fin 107 in a channel region of a semiconductor device 100. In some embodiments, the layered stacked material 700 includes an interface layer 701 disposed between the upper surface of the fin 107 in the channel region of the semiconductor device and the simple nanocrystalline film 411. In other embodiments, the simple nanocrystalline film 411 may be disposed above and in contact with the upper surface of the fin 107. In some embodiments, the layered stacked material 700 includes a capping layer 709 disposed above the simple nanocrystalline film 411.

[0091] In one embodiment, the interface layer 701 may be a material such as silicon dioxide, formed by a process such as in-situ steam generation (ISSG). However, any suitable material or formation process may be used.

[0092] The simple nanocrystalline thin film 411 can be formed from the first dielectric layer 211, and through the above-mentioned... Figures 3A-3C and Figure 4 Annealing is performed using one or more deposition and annealing processes. According to some embodiments, the simplified nanocrystalline film 411 can be formed by one or more crystallization processes (e.g., HT-ALD, LT-PDA, HT-PDA, and / or PDA / PMA) as discussed in detail above. In this way, the simplified nanocrystalline film 411 is formed as a high-dielectric-constant dielectric layer having multiple nanocrystalline regions 705 suspended in an amorphous matrix layer 703.

[0093] Figure 7AFurther illustration shows that the nanocrystalline region 705 is formed as a plurality of self-contained crystalline materials including coherence interfaces 707, which include multiple crystalline / amorphous interfaces between the self-contained crystalline material of the nanocrystalline region 705 and the amorphous material of the amorphous matrix layer 703. The amorphous material of the amorphous matrix layer 703 effectively separates the grain boundaries of the nanocrystalline region 705. In this way, by forming a simple nanocrystalline thin film 411, leakage paths and oxidant paths can be completely avoided and / or minimized. Therefore, defects can be minimized and / or avoided during the manufacture of the semiconductor device 100, resulting in increased yield, improved performance, and increased reliability of the semiconductor device 100.

[0094] The crystallization region ratio of the simplified nanocrystalline film 411 is defined as the percentage of the volume of the plurality of nanocrystalline regions 705 relative to the total volume of the simplified nanocrystalline film 411. According to some embodiments, the crystallization region ratio of the simplified nanocrystalline film 411 may be between about 10 volume percentage and about 80 volume percentage, for example, between about 30 volume percentage and about 50 volume percentage. The plurality of nanocrystalline regions 705 may be formed to have a crystallite size (CS1) (e.g., one or more cross-sectional diameters) between about 0.5 nanometers and about 10 nanometers, for example, about 3 nanometers. However, any suitable crystallization region ratio and any suitable crystal size may be used.

[0095] Furthermore, the dielectric material of the simplified nanocrystalline thin film 411 may be doped or undoped. In some embodiments, the dielectric material of the simplified nanocrystalline thin film 411 may be doped with, for example, silicon (Si), lanthanum (La), yttrium (Y), nitrogen (N), scandium (Sc), gadolinium (Gd), combinations thereof, or similar materials. However, any other suitable dopant may be used. Based on the dopant used and / or the process control used (e.g., thickness, thermal budget, annealing rise and fall rates), the crystal phase of the nanocrystalline region 705 may be modified (e.g., tetragonal, cubic, orthorhombic, rhombohedral, etc.). In this way, the physical properties of the simplified nanocrystalline thin film 411 may be modified to provide a higher dielectric constant and / or stronger ferroelectric properties compared to the amorphous matrix layer 703 alone. Furthermore, the modified physical properties of the simple nanocrystalline film 411 can be maintained by controlling one or more phase boundary parameters, including: the proportion of crystalline regions, temperature, and / or morphotropic phase boundaries of the respective crystalline phases remaining in the material of the simple nanocrystalline film 411 due to phase separation caused by doping.

[0096] For example, compared to a standalone amorphous matrix layer 703, the tetragonal and cubic phase modifications based on the nanocrystalline region 705 result in an enhanced high dielectric constant value for the simplified nanocrystalline film 411. According to some embodiments, the tetragonal phase modification of the nanocrystalline region 705 provides a dielectric constant between about 25 and about 70 (e.g., about 40), and the cubic phase modification of the nanocrystalline region 705 provides a high dielectric constant value between about 20 and about 40 (e.g., about 30).

[0097] As with other examples, based on the orthorhombic and rhombohedral phase modifications of the nanocrystalline region 705, the simplified nanocrystalline film 411 exhibits enhanced ferroelectric properties, such as polarization coercivity and polarization retentivity, compared to the standalone amorphous matrix layer 703. According to some embodiments, the orthorhombic phase modification of the nanocrystalline region 705 provides a value between approximately 0.1 μC / cm². 2 (microcoulombs / cm²) and approximately 15 uC / cm² 2 The residual polarization between them, for example, is about 0.5 uC / cm. 2 Furthermore, it provides a modifier of the rhombohedral phase in the nanocrystalline region 705 with a value between approximately 0.1 μC / cm². 2 and approximately 15uC / cm2 Residual polarization between them, for example, about 0.5 uC / cm 2 .

[0098] Figure 7B A plurality of nanocrystal regions 715, including an integrated interface 717, are shown in more detail, for example, in a compound nanocrystal thin film 611. Figure 7B A portion of a layered stacked material 750 is shown, which includes, for example, a compound nanocrystal film 611 on a fin 107 in a channel region of a semiconductor device 100. In some embodiments, the layered stacked material 750 includes an interface layer 701 disposed between the upper surface of the fin 107 in the channel region of the semiconductor device and the compound nanocrystal film 611. In other embodiments, the compound nanocrystal film 611 may be disposed above and in contact with the upper surface of the fin 107. In some embodiments, the layered stacked material 750 includes a capping layer 709 disposed above the compound nanocrystal film 611.

[0099] The compound nanocrystalline thin film 611 can be formed as an amorphous high-dielectric-constant layer 211, and through the above-mentioned... Figures 3A-3C Figures 4-5 and Figures 6A-6B Annealing is performed using one or more deposition and annealing processes. According to some embodiments, the compound nanocrystal film 611 is formed of one or more dielectric materials, including HfO2, ZrO2, the aforementioned alloys, and the like, and may be doped or undoped. However, any suitable material may be used for the compound nanocrystal film 611. In some embodiments, the dielectric material of the compound nanocrystal film 611 may be doped with one or more materials, such as silicon (Si), lanthanum (La), yttrium (Y), nitrogen (N), scandium (Sc), gadolinium (Gd), combinations thereof, or the like. However, any other suitable dopant may be used. Thus, the compound nanocrystal film 611 includes a plurality of compound nanocrystal regions 715 in an amorphous matrix layer 703.

[0100] According to some embodiments, the compound nanocrystal region 715 may include... Figure 7A Multiple nanocrystalline regions 705 have undergone further processing. For example, it is possible to... Figure 7A The simplified nanocrystalline film 411 undergoes a second annealing process (e.g., post-cap annealing (PCA)). In this way, for example, the compound nanocrystalline region 715 can be crystallized to have a second crystal size (CS2) larger than the first crystal size (CS1) (e.g., one or more cross-sectional diameters). According to some embodiments, the second crystal size (CS2) is between about 0.5 nanometers and about 10 nanometers, for example, about 5 nanometers. However, any suitable proportion of crystalline regions and any suitable crystal size can be used.

[0101] Furthermore, in some embodiments, the implanted doped compound nanocrystal region 715 may have a different composition than the amorphous matrix layer 703. For example, in one embodiment, the nanocrystal region 715 may have a doping concentration between about 1 atomic percentage and about 50 atomic percentage, such as about 4 atomic percentage, while the amorphous matrix layer 703 may have a smaller doping concentration, between about 0.1 atomic percentage and about 10 atomic percentage, such as about 0.4 atomic percentage. However, any suitable doping concentration may be used.

[0102] The crystalline region ratio of the compound nanocrystal film 611 is defined as the percentage of the volume of the plurality of nanocrystal regions 715 relative to the total volume of the compound nanocrystal film 611. According to some embodiments, the crystalline region ratio of the compound nanocrystal film 611 may be between about 10 volume percentage and about 80 volume percentage, for example, between about 30 volume percentage and about 50 volume percentage.

[0103] Figure 8A and Figure 8B According to some embodiments, a metal gate electrode structure is shown in two views. Once the capping layer 501 is as... Figure 6B As shown, a series of metal layers can be deposited on the capping layer 501. According to some embodiments, a first metal layer 801 can be formed adjacent to the capping layer 501 and can be formed of a first metallic material, such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar. The first metallic material of the first metal layer 801 can be deposited to a thickness between about 5 Å and about 200 Å by deposition processes such as atomic layer deposition, chemical vapor deposition, sputtering, or similar methods, although any suitable deposition process or thickness can be used.

[0104] In some embodiments, the first metal layer 801 may be a compound metal layer comprising a second metal material formed adjacent to the first metal material, and in a particular embodiment, the second metal material may be similar to the first metal material. For example, the second metal material may be formed from second metal materials such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar second metal materials. Furthermore, the second metal material of the first metal layer 801 may be deposited to a thickness between about 5 Å and about 200 Å using deposition processes such as atomic layer deposition, chemical vapor deposition, sputtering, or similar methods, although any suitable deposition process or thickness may be used.

[0105] A third metal material 803 fills the remaining portion of the opening 207 left by removing the dummy gate electrode 111. In one embodiment, the third metal material 803 may be formed of, for example, W, Al, AlCu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or similar third metal materials, and may be used to fill or overfill the opening 207 left by removing the dummy gate electrode 111 by, for example, atomic layer deposition, chemical vapor deposition, sputtering, or similar deposition processes. In a particular embodiment, the third metal material 803 may be deposited to a thickness between about 5 angstroms and about 500 angstroms, although any suitable material, deposition process, or thickness may be used.

[0106] Once the opening 207 left by removing the dummy gate electrode 111 is filled, a gate stack 805 can be formed from the material filling the opening 207, wherein any excess material outside the opening 207 is removed by planarizing the material. In a particular embodiment, the removal process can be performed by a planarization process such as chemical mechanical polishing (CMP). However, any suitable planarization and removal processes can be used.

[0107] After the material of the gate stack 805 is formed and planarized, the material of the gate stack 805 may be etched and capped with a capping layer 807. In one embodiment, the material of the gate stack 805 may be etched by, for example, a wet or dry etching process using an etchant selective for the material of the gate stack 805. In one embodiment, the material of the gate stack 805 may be etched at a distance between about 5 nanometers and about 150 nanometers, for example, about 120 nanometers. However, any suitable process and distance may be used.

[0108] Once the material of the gate stack 805 is etched, a capping layer 807 can be deposited and flush with the first spacer 113. In one embodiment, the material of the capping layer 807 is, for example, SiN, SiON, SiCON, SiC, SiOC, combinations thereof, or the like, and is deposited by deposition processes such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. The capping layer 807 can be deposited to a thickness between about 5 angstroms and about 200 angstroms, and is then planarized by a planarization process such as chemical mechanical polishing, so that the capping layer 807 is flush with the first spacer 113.

[0109] Figure 8A and Figure 8B Additionally, a first etch stop layer 809 is shown formed on the gate stack 805. In one embodiment, the first etch stop layer 809 can be formed from silicon nitride by plasma-assisted chemical vapor deposition (PECVD), although other materials such as SiON, SiCON, SiC, SiOC, and SiC2 can be used. x N y SiO x Other dielectrics, combinations thereof, or similar materials may be used, and alternative techniques for forming the first etch stop layer 809, such as low-pressure CVD (LPCVD), PVD, or similar methods, may be employed. The first etch stop layer 809 may be formed to a thickness between about 5 Å and about 200 Å, or between about 5 Å and about 50 Å.

[0110] Figure 8B This is a perspective view of a semiconductor device 100 after the deposition of a first etch stop layer 809. Figure 8B The cutting line B-B' is further shown, where Figure 8A This line shows a cross-sectional view.

[0111] The advanced photolithography processes, methods, and materials described above can be used in any application, including fin field-effect transistors (FinFETs). For example, patterned fins can create relatively tight spacing between components, which is well-suited for the embodiments of the invention described above. Furthermore, the spacers used to form the fins of the fin field-effect transistors can be processed according to the embodiments of the invention described above.

[0112] Furthermore, fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes, including dual or multiple patterning. Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to create patterns with pitches, for example, smaller than those achievable using a single, directional photolithography process. For instance, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0113] According to embodiments of the present invention, the simplified nanocrystalline film 411 and the compound nanocrystalline film 611 can be formed as dielectric layers of pure HfO2, ZrO2, and alloys thereof, the dielectric layer comprising a plurality of self-contained nanocrystalline regions 705 suspended in an amorphous material of an amorphous matrix layer 703. The dielectric layer can be doped or undoped with one or more of Si, La, Y, N, Sc, Gd, or the like, and the crystal phase (e.g., tetragonal, cubic, orthorhombic, rhombohedral, and the like) of the nanocrystalline regions 705 can be modified during deposition or annealing. Based on the doping used and process control, the dielectric constant and / or ferroelectric properties (e.g., polarization coercivity and polarization retention) of the high-dielectric-constant dielectric material can be improved. Furthermore, these modifications can be maintained by controlling the process to keep the process within the morphotropic phase boundary of the high-dielectric-constant dielectric material. In this way, leakage paths and oxidant paths can be completely blocked and / or minimized by the simplified nanocrystalline film 411 and the compound nanocrystalline film 611. Therefore, defects can be minimized and / or avoided during the manufacture of semiconductor device 100, thereby increasing the yield, performance and reliability of semiconductor device 100.

[0114] In one embodiment, a method includes: depositing a dielectric layer on a fin in a channel region of a semiconductor device; performing a first annealing process on the dielectric layer to form a plurality of nanocrystalline regions, the plurality of nanocrystalline regions being suspended within and separated by an amorphous matrix layer of the dielectric layer; and depositing a metal layer on the dielectric layer in the channel region of the semiconductor device. In one embodiment, the step of forming the nanocrystalline regions includes doping the dielectric layer with a first doping. In one embodiment, the step of forming the nanocrystalline regions further includes maintaining the proportion of crystalline regions of the dielectric layer greater than or equal to 10 volume percentage and less than or equal to 80 volume percentage. In one embodiment, the step of forming the nanocrystalline regions includes modifying the crystal phase of the nanocrystalline regions. In one embodiment, the method further includes forming a capping layer on the dielectric layer. In one embodiment, an annealing process on the dielectric layer is performed after the capping layer is formed. In one embodiment, the method further includes performing a second annealing process on the dielectric layer, wherein the first annealing process is performed on the dielectric layer before the capping layer is formed, and wherein the second annealing process is performed on the dielectric layer after the capping layer is formed.

[0115] In one embodiment, a method includes: forming a gate dielectric layer in a fin field-effect transistor of a semiconductor device, the gate dielectric layer comprising a dielectric material; forming a plurality of self-contained crystal regions in the dielectric material of the gate dielectric layer, wherein the plurality of self-contained crystal regions include a plurality of crystalline / amorphous interfaces and wherein the plurality of self-contained crystal regions are separated from each other by dielectric material of an amorphous matrix layer of the gate dielectric layer; and depositing a metal gate structure on the gate dielectric layer of the fin field-effect transistor of the semiconductor device. In one embodiment, the method further includes implanting a first dopant material into the dielectric material. In one embodiment, the method further includes performing an annealing process to crystallize the dielectric material implanted with the first dopant material into a plurality of first self-contained crystal regions. In one embodiment, the first dopant material is gadolinium. In one embodiment, the method further includes: depositing a capping layer on the dielectric material; and performing a second annealing process after depositing the capping layer, the second annealing process modifying the crystal structure of the dielectric material. In one embodiment, the dielectric material is hafnium oxide. In one embodiment, the self-contained crystal regions have a first composition, and the amorphous matrix layer has a second composition different from the first composition. In one embodiment, the gate dielectric layer has a thickness of no more than 2.5 nm. In another embodiment, the method further includes: performing an annealing process to crystallize the dielectric material; and depositing a capping layer on the dielectric material, wherein the annealing process is performed prior to depositing the capping layer.

[0116] In one embodiment, a semiconductor device includes: a fin of a field-effect transistor; a gate dielectric layer deposited on the fin, the gate dielectric layer including a plurality of self-contained nanocrystalline regions, the nanocrystalline regions including a plurality of crystalline / amorphous interfaces, wherein the self-contained crystalline regions are separated from each other by an amorphous matrix dielectric material of the gate dielectric layer; and a metal gate electrode deposited on the gate dielectric layer. In one embodiment, the thickness of the gate dielectric layer is less than 2.5 nm. In one embodiment, the semiconductor device further includes a plurality of dopants in the self-contained crystalline regions. In one embodiment, the proportion of crystalline regions in the gate dielectric layer is greater than or equal to 10 volume percentage and less than or equal to 80 volume percentage.

[0117] The components of several embodiments have been outlined above to facilitate a better understanding of the ideas presented herein by those skilled in the art. Those skilled in the art will understand that they can design or modify other processes and structures based on this disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent processes and structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A dielectric layer is deposited on a fin in a channel region of a semiconductor device, wherein the dielectric layer includes a nanocrystalline film comprising a plurality of nanocrystalline regions suspended within an amorphous matrix layer of the dielectric layer and separated by the amorphous matrix layer. A first annealing process is performed on the dielectric layer to further crystallize the plurality of nanocrystalline regions, wherein the plurality of nanocrystalline regions include a first material, and wherein the amorphous matrix layer includes the first material, wherein the doping concentration of the plurality of nanocrystalline regions is greater than the doping concentration of the amorphous matrix layer; and A metal layer is deposited on the dielectric layer of the channel region in the semiconductor device.

2. The method for forming a semiconductor device as claimed in claim 1, wherein the step of further crystallizing the plurality of nanocrystal regions further includes maintaining the proportion of the crystalline region of the dielectric layer greater than or equal to 10 volume percentage and less than or equal to 80 volume percentage.

3. The method for forming a semiconductor device as claimed in claim 2, wherein the step of further crystallizing the plurality of nanocrystal regions modifies the crystal phase of the plurality of nanocrystal regions.

4. The method for forming a semiconductor device as claimed in claim 1, further comprising forming a capping layer on the dielectric layer.

5. The method of forming a semiconductor device as claimed in claim 4, wherein an annealing process is performed on the dielectric layer after the capping layer is formed.

6. The method of forming a semiconductor device as claimed in claim 4, further comprising performing a second annealing process on the dielectric layer, wherein a first annealing process is performed on the dielectric layer before forming the capping layer, and wherein a second annealing process is performed on the dielectric layer after forming the capping layer.

7. A method for forming a semiconductor device, comprising: A gate dielectric layer is formed in a fin field-effect transistor in a semiconductor device, and the gate dielectric layer includes a dielectric material. A first dopant material is implanted into the dielectric material; Multiple self-contained crystal regions are formed in the dielectric material of the gate dielectric layer, wherein the multiple self-contained crystal regions include multiple crystalline / amorphous interfaces, and wherein the multiple self-contained crystal regions are separated from each other by the dielectric material of an amorphous matrix layer of the gate dielectric layer, wherein the doping concentration of the multiple self-contained crystal regions is greater than the doping concentration of the amorphous matrix layer. A metal gate structure is deposited on the gate dielectric layer of the fin field-effect transistor in the semiconductor device; A capping layer is deposited on the dielectric material; and After the capping layer is deposited, a second annealing process is performed, which modifies the crystal structure of the dielectric material.

8. The method of forming a semiconductor device as claimed in claim 7, further comprising performing an annealing process to crystallize the dielectric material implanted with the first doped material into a plurality of first self-contained crystal regions.

9. The method of forming a semiconductor device as claimed in claim 8, wherein the first doping material is gadolinium.

10. The method of forming a semiconductor device as claimed in claim 7, wherein the dielectric material is hafnium oxide.

11. The method of forming a semiconductor device as claimed in claim 7, wherein the gate dielectric layer has a thickness of not more than 2.5 nm.

12. The method of forming a semiconductor device as claimed in claim 7, further comprising: An annealing process is performed to crystallize the dielectric material. as well as The capping layer is deposited on the dielectric material, wherein the annealing process is performed prior to the deposition of the capping layer.

13. A semiconductor device, comprising: A fin of a field-effect transistor; A gate dielectric layer is located on the fin, the gate dielectric layer comprising a plurality of self-contained nanocrystal regions, the plurality of self-contained nanocrystal regions comprising a plurality of crystalline / amorphous interfaces, wherein the plurality of crystalline / amorphous interfaces are integrated interfaces, wherein the plurality of self-contained nanocrystal regions are separated from each other by an amorphous matrix dielectric material of the gate dielectric layer, wherein the entire gate dielectric layer comprises a first material, and wherein the doping concentration of the plurality of self-contained nanocrystal regions is greater than the doping concentration of the amorphous matrix layer; and A metal gate electrode is located on the gate dielectric layer.

14. The semiconductor device of claim 13, wherein the thickness of the gate dielectric layer is less than 2.5 nm.

15. The semiconductor device of claim 13, wherein the proportion of the crystalline region of the gate dielectric layer is greater than or equal to 10% by volume and less than or equal to 80% by volume.

16. A method for forming a semiconductor device, comprising: A gate dielectric layer is formed on a channel region of a semiconductor fin, wherein the gate dielectric layer includes a plurality of nanocrystalline regions separated by an amorphous matrix material; A first dopant is implanted into the gate dielectric layer; A first annealing process is performed to modify a first crystal structure of the gate dielectric layer into a second crystal structure, wherein the crystal size of each nanocrystal region after the first annealing process has a first profile diameter. A second annealing process is performed to modify the second crystal structure of the gate dielectric layer into a third crystal structure, wherein the crystal size of each nanocrystal region after the second annealing process has a second profile diameter, wherein the second profile diameter is larger than the first profile diameter. A second dopant is implanted into the gate dielectric layer, wherein after the second dopant is implanted, a first doping concentration in the nanocrystalline region is greater than a second doping concentration in the amorphous matrix material.

17. The method of forming a semiconductor device as claimed in claim 16, wherein the diameter of the second cross-section is 0.5 nm to 10 nm.

18. The method of forming a semiconductor device as claimed in claim 16, further comprising: A capping layer is deposited on the gate dielectric layer after the first annealing process and before the second annealing process.

19. The method of forming a semiconductor device as claimed in claim 16, wherein the first doping concentration is 1% to 50%, and the second doping concentration is 0.1% to 10%.

20. The method of forming a semiconductor device as claimed in claim 16, wherein the proportion of the crystalline region of the third crystal structure of the gate dielectric layer is from 10% to 80% by volume.

21. A method for forming a semiconductor device, comprising: A gate dielectric layer of a fin field-effect transistor is deposited, wherein the gate dielectric layer includes a nanocrystalline film, which includes a plurality of nanocrystalline regions suspended in an amorphous matrix layer and separated by the amorphous matrix layer. Deposit a capping layer on the gate dielectric layer; and A dopant is implanted into the gate dielectric layer, wherein a first doping concentration of the plurality of nanocrystalline regions after implantation is greater than a second doping concentration of the amorphous matrix layer.

22. The method of forming a semiconductor device as claimed in claim 21, wherein the plurality of nanocrystalline regions and the amorphous matrix layer comprise the same material.

23. The method of forming a semiconductor device as claimed in claim 21, further comprising: A first annealing process is performed before the deposition of the capping layer to further crystallize the plurality of nanocrystal regions, wherein the crystal size of each plurality of nanocrystal regions after the first annealing process has a first profile diameter.

24. The method of forming a semiconductor device as claimed in claim 23, further comprising: After the capping layer is deposited, a second annealing process is performed, wherein each of the plurality of nanocrystal regions after the second annealing process has a crystal size with a second profile diameter, and the second profile diameter is larger than the first profile diameter.

25. The method of forming a semiconductor device as claimed in claim 23, wherein the plurality of nanocrystal regions following the first annealing process include a plurality of crystalline / amorphous interfaces, and the plurality of crystalline / amorphous interfaces include an integrated interface.

26. The method of forming a semiconductor device as claimed in claim 21, wherein the step of implanting the doped layer into the gate dielectric layer includes doping the gate dielectric layer with lanthanum, gadolinium, scandium, or a combination thereof.

27. A semiconductor device, comprising: A fin protrudes from a substrate; A gate dielectric layer is located on the sidewall and upper surface of the fin, wherein the gate dielectric layer includes a plurality of nanocrystalline regions in an amorphous matrix layer, wherein the plurality of nanocrystalline regions and the amorphous matrix layer are made of the same material, and wherein the doping concentration of the plurality of nanocrystalline regions is greater than the doping concentration of the amorphous matrix layer. A capping layer is located on the gate dielectric layer; and A gate electrode is located on the capping layer.

28. The semiconductor device of claim 27, wherein the relative permittivity of the material of the plurality of nanocrystalline regions with respect to the amorphous matrix layer is greater than 5.

29. The semiconductor device of claim 27, wherein the doping concentration of the plurality of nanocrystal regions is from 1% to 50%, and the doping concentration of the amorphous matrix layer is from 0.1% to 10%.

30. The semiconductor device of claim 29, wherein the doping of the plurality of nanocrystalline regions and the amorphous matrix layer comprises lanthanum, gadolinium, scandium, or a combination thereof.

31. The semiconductor device of claim 27, wherein the crystalline region of the gate dielectric layer accounts for 10% to 80% by volume.

32. The semiconductor device of claim 27, wherein the crystal size of each plurality of nanocrystal regions includes at least one cross-sectional diameter of 0.5 nm to 10 nm.

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