Simulation method of DC output characteristic model of van der waals bipolar junction transistor
By constructing a DC output characteristic model of a van der Waals bipolar junction transistor and performing simulation calculations, the problem of the lack of dedicated models in EDA tools is solved, enabling accurate simulation of device characteristics and support for circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUN YAT SEN UNIV
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-26
Smart Images
Figure CN122287518A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a simulation method for a van der Waals bipolar junction transistor DC output characteristic model. Background Technology
[0002] With the rapid development of integrated circuit technology and industry, the feature size of transistors continues to shrink, and the performance improvement of traditional silicon-based devices is gradually approaching the physical limit. Two-dimensional atomic crystal materials, with their smooth surfaces, atomic-level thickness, and rich electrical and optical properties, have become important candidate materials for breaking through the size limitations of traditional silicon-based devices. In recent years, bipolar junction transistors with van der Waals structures formed by vertically stacking two-dimensional atomic crystal materials have shown promising applications in amplifier circuits, photoelectric detection, and gas sensing.
[0003] However, to truly bring this novel device to practical circuit design and large-scale system integration, accurate quantitative analysis and simulation evaluation of its electrical behavior and device characteristics are essential. Through device characteristic simulation, designers can effectively predict and optimize the device's operating state and circuit performance under different bias conditions before actual tape-out manufacturing, thereby significantly reducing R&D costs and shortening the design cycle.
[0004] Currently, mainstream electronic design automation (EDA) tools (such as PSpice) have integrated a large number of mature traditional semiconductor device models, such as traditional silicon-based bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), which can support the design of traditional silicon-based integrated circuits. However, due to the fundamental physical differences between van der Waals BJTs and traditional bulk silicon-based devices in terms of charge transport mechanisms and interface characteristics, traditional device models cannot be directly applied to accurately describe their unique operating states.
[0005] Currently, mainstream EDA tools generally lack dedicated characteristic models and effective simulation methods for this novel van der Waals bipolar junction transistor (VBT). This lack of simulation capabilities prevents developers from directly utilizing existing mature EDA environments to accurately design and verify the performance of circuits based on this device. This has become one of the bottlenecks hindering the development of VBTs towards functional circuit optimization and complex system integration. Summary of the Invention
[0006] To overcome the lack of simulation methods for van der Waals bipolar junction transistor (VJT) characteristic models, this invention provides a simulation method for the DC output characteristic model of VJTs.
[0007] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: This invention provides a simulation method for a van der Waals bipolar junction transistor (VJT) DC output characteristic model, comprising: Obtain the target van der Waals bipolar junction transistor and experimentally measure the output characteristic curve of the target van der Waals bipolar junction transistor; Based on the output characteristic curve, construct a DC output characteristic model of the target van der Waals bipolar junction transistor and obtain the initial parameters of the DC output characteristic model; The initial parameters are iteratively optimized using existing mathematical software to obtain the optimized parameters. A simulation module is constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. The simulation module is used to perform simulation calculations, and the simulation data and simulation curves of the target van der Waals bipolar junction transistor are obtained, thus completing the simulation.
[0008] Preferably, obtaining the target van der Waals bipolar junction transistor includes: A substrate is obtained, wherein the substrate material is Si / SiO2 and the thickness is 300 nm; MoS2, WSe2, and MoS2 are sequentially stacked on the substrate using a dry transfer process to form a collector region, a base region, and an emitter region, respectively. The thickness of the collector region is 15nm≤d1≤30nm, the thickness of the base region is 4nm≤d2≤10nm, and the thickness of the emitter region is 15nm≤d3≤30nm. Cr / Au with a thickness of 10nm / 100nm is deposited on the surfaces of the collector region, base region, and emitter region to form the collector, base, and emitter, respectively, thereby obtaining the target van der Waals bipolar junction transistor.
[0009] Preferably, the output characteristic curve of the target van der Waals bipolar junction transistor is measured experimentally, including: By applying different bias voltages and measuring the corresponding output currents in common-base and common-emitter operating modes, the output characteristic curves of the target van der Waals bipolar junction transistor are obtained.
[0010] Preferably, in the common-base operating mode, the base of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0.1V≤ V BE ≤1V, step size 0.1V, collector-base bias voltage V CB The range is 1V≤ V CB ≤3V, step size is 0.04V.
[0011] Preferably, in the common-emitter operating mode, the emitter of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0≤ V BE ≤5V, step size 1V, collector-emitter bias voltage V CE The range is 0≤ V CE ≤6V, with a step size of 0.06V.
[0012] Preferably, constructing a DC output characteristic model of the target van der Waals bipolar junction transistor based on the output characteristic curve includes: The expression for the DC output characteristic model is as follows:
[0013] in, I C Represents the collector output current. V BE Represents the base-emitter voltage. V CE Represents the collector-emitter voltage. V offset Represents offset voltage. l Representative base width modulation effect parameters, A n , N and m For the fitting parameters, k The order of the predefined polynomial function is given.
[0014] Preferably, the offset voltage is calculated as follows:
[0015] in, K For the fitting parameters, V 0 represents V BE The offset voltage when it is 0.
[0016] Preferably, the base region width modulation effect parameter is calculated as follows:
[0017] in, m For the fitting parameters, l 0 represents V BE The base width modulation effect parameter when it is 0.
[0018] Preferably, obtaining the initial parameters of the DC output characteristic model includes: Extract different V CE Down I C Open instantly V CE As V offset And extract based on curve fitting method K and V 0; Select V CE The data range >2.5V was extracted using a curve fitting method. A n , m and l 0; Extract K , V 0、 A n , m and l Substituting 0 into the DC output characteristic model, extract N and m .
[0019] Preferably, the initial parameters are iteratively optimized using existing mathematical software to obtain optimized parameters, including: Select the collector output current I in the output characteristic curve C The portion greater than 0 is used as the experimental dataset; The existing mathematical software is 1stopt software; The initial parameters 、 The experimental dataset and DC output characteristic model were written into the 1stopt software; The initial parameters were optimized using the 1stopt software, with the optimization conditions set as follows: the optimization algorithm was set to Levenberg. Marquardt optimization algorithm, with a tolerance of 10. 10 The maximum number of iterations is 1000. When the maximum number of convergences or the preset convergence criterion is reached, the iteration stops, and the optimized parameters are finally obtained.
[0020] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: This invention provides a simulation method for the DC output characteristic model of a van der Waals bipolar junction transistor (VJT). First, a target VJT is obtained, and its output characteristic curve is experimentally measured. Based on the output characteristic curve, a DC output characteristic model of the target VJT is constructed, and initial parameters of the model are obtained. These initial parameters are iteratively optimized using existing mathematical software to obtain optimized parameters. A simulation module is constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. Finally, the simulation module is used to perform simulation calculations, obtaining simulation data and curves for the target VJT, thus completing the simulation. This invention enables rapid judgment of the characteristics of the target VJT by constructing a simulation module for the target VJT and using this module for simulation calculations to obtain simulation data and curves. Attached Figure Description
[0021] Figure 1 This is a flowchart illustrating the simulation method for a van der Waals bipolar junction transistor DC output characteristic model in Example 1. Figure 2 This is a schematic diagram of the van der Waals bipolar junction transistor in Example 2; Figure 3 The figures show the simulation and experimental data of the common base working mode in Example 3; Figure 4 The figure shows the simulation data and experimental data of the common emitter working mode in Example 3. Detailed Implementation
[0022] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent. To better illustrate this embodiment, some parts in the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions; It will be understood by those skilled in the art that certain well-known structures and their descriptions may be omitted in the accompanying drawings.
[0023] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.
[0024] Example 1 This embodiment provides a simulation method for a van der Waals bipolar junction transistor (VJT) DC output characteristic model, such as... Figure 1 As shown, it includes: Obtain the target van der Waals bipolar junction transistor and experimentally measure the output characteristic curve of the target van der Waals bipolar junction transistor; Based on the output characteristic curve, construct a DC output characteristic model of the target van der Waals bipolar junction transistor and obtain the initial parameters of the DC output characteristic model; The initial parameters are iteratively optimized using existing mathematical software to obtain the optimized parameters. A simulation module is constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. The simulation module is used to perform simulation calculations, and the simulation data and simulation curves of the target van der Waals bipolar junction transistor are obtained, thus completing the simulation.
[0025] In its specific implementation, this invention first obtains the target van der Waals bipolar junction transistor (VJT) and experimentally measures its output characteristic curve. Next, it constructs a DC output characteristic model of the VJT based on the output characteristic curve and obtains the initial parameters of the DC output characteristic model. Then, iteratively optimizes the initial parameters using existing mathematical software to obtain optimized parameters. A simulation module is then constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. Finally, the simulation module is used to perform simulation calculations, obtaining the simulation data and simulation curves of the target VJT, thus completing the simulation.
[0026] Example 2 This embodiment provides a simulation method for a van der Waals bipolar junction transistor (VJT) DC output characteristic model, including: Obtain the target van der Waals bipolar junction transistor and experimentally measure the output characteristic curve of the target van der Waals bipolar junction transistor; Based on the output characteristic curve, construct a DC output characteristic model of the target van der Waals bipolar junction transistor and obtain the initial parameters of the DC output characteristic model; The initial parameters are iteratively optimized using existing mathematical software to obtain the optimized parameters. A simulation module is constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. The simulation module is used to perform simulation calculations, and the simulation data and simulation curves of the target van der Waals bipolar junction transistor are obtained, thus completing the simulation.
[0027] It should be noted that, in this embodiment, the target van der Waals bipolar junction transistor is obtained, such as... Figure 2 As shown, it includes: A substrate is obtained, wherein the substrate material is Si / SiO2 and the thickness is 300 nm; MoS2, WSe2, and MoS2 are sequentially stacked on the substrate using a dry transfer process to form a collector region, a base region, and an emitter region, respectively. The thickness of the collector region is 15nm≤d1≤30nm, the thickness of the base region is 4nm≤d2≤10nm, and the thickness of the emitter region is 15nm≤d3≤30nm. Cr / Au with a thickness of 10nm / 100nm is deposited on the surfaces of the collector region, base region, and emitter region to form the collector, base, and emitter, respectively, thereby obtaining the target van der Waals bipolar junction transistor.
[0028] It should be noted that, in this embodiment, the output characteristic curve of the target van der Waals bipolar junction transistor is measured experimentally, including: By applying different bias voltages and measuring the corresponding output currents in common-base and common-emitter operating modes, the output characteristic curves of the target van der Waals bipolar junction transistor are obtained.
[0029] It should be noted that, in this embodiment, in the common-base operating mode, the base of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0.1V≤ V BE ≤1V, step size 0.1V, collector-base bias voltage V CB The range is 1V≤ V CB ≤3V, step size is 0.04V.
[0030] It should be noted that, in this embodiment, in the common-emitter operating mode, the emitter of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0≤ V BE ≤5V, step size 1V, collector-emitter bias voltage V CE The range is 0≤ V CE ≤6V, with a step size of 0.06V.
[0031] It should be noted that, in this embodiment, constructing the DC output characteristic model of the target van der Waals bipolar junction transistor based on the output characteristic curve includes: The expression for the DC output characteristic model is as follows:
[0032] in, IC Represents the collector output current. V BE Represents the base-emitter voltage. V CE Represents the collector-emitter voltage. V offset Represents offset voltage. l Representative base width modulation effect parameters, A n , N and m For the fitting parameters, k The order of the predefined polynomial function is given.
[0033] It should be noted that, in this embodiment, the offset voltage is calculated as follows:
[0034] in, K For the fitting parameters, V 0 represents V BE The offset voltage when it is 0.
[0035] It should be noted that, in this embodiment, the base region width modulation effect parameter is calculated as follows:
[0036] in, m For the fitting parameters, l 0 represents V BE The base width modulation effect parameter when it is 0.
[0037] It should be noted that, in this embodiment, obtaining the initial parameters of the DC output characteristic model includes: Extract different V CE Down I C Open instantly V CE As V offset And extract based on curve fitting method K and V 0; Select V CE The data range >2.5V was extracted using a curve fitting method. A n , m and l 0; Extract K ,V 0、 A n , m and l Substituting 0 into the DC output characteristic model, extract N and m .
[0038] It should be noted that, in this embodiment, the initial parameters are iteratively optimized using existing mathematical software to obtain optimized parameters, including: Select the collector output current I in the output characteristic curve C The portion greater than 0 is used as the experimental dataset; The existing mathematical software is 1stopt software; The initial parameters 、 The experimental dataset and DC output characteristic model were written into the 1stopt software; The initial parameters were optimized using the 1stopt software, with the optimization conditions set as follows: the optimization algorithm was set to Levenberg. Marquardt optimization algorithm, with a tolerance of 10. 10 The maximum number of iterations is 1000. When the maximum number of convergences or the preset convergence criterion is reached, the iteration stops, and the optimized parameters are finally obtained.
[0039] Example 3 This embodiment provides a simulation method for a van der Waals bipolar junction transistor (VJT) DC output characteristic model, including: Obtain the target van der Waals bipolar junction transistor and experimentally measure the output characteristic curve of the target van der Waals bipolar junction transistor; Based on the output characteristic curve, construct a DC output characteristic model of the target van der Waals bipolar junction transistor and obtain the initial parameters of the DC output characteristic model; The initial parameters are iteratively optimized using existing mathematical software to obtain the optimized parameters. A simulation module is constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. The simulation module is used to perform simulation calculations, and the simulation data and simulation curves of the target van der Waals bipolar junction transistor are obtained, thus completing the simulation.
[0040] It should be noted that, in this embodiment, obtaining the target van der Waals bipolar junction transistor includes: A substrate is obtained, wherein the substrate material is Si / SiO2 and the thickness is 300 nm; MoS2, WSe2, and MoS2 are sequentially stacked on the substrate using a dry transfer process to form a collector region, a base region, and an emitter region, respectively. The thickness of the collector region is 15nm≤d1≤30nm, the thickness of the base region is 4nm≤d2≤10nm, and the thickness of the emitter region is 15nm≤d3≤30nm. Cr / Au with a thickness of 10nm / 100nm is deposited on the surfaces of the collector region, base region, and emitter region to form the collector, base, and emitter, respectively, thereby obtaining the target van der Waals bipolar junction transistor.
[0041] It should be noted that, in this embodiment, the output characteristic curve of the target van der Waals bipolar junction transistor is measured experimentally, including: By applying different bias voltages and measuring the corresponding output currents in common-base and common-emitter operating modes, the output characteristic curves of the target van der Waals bipolar junction transistor are obtained.
[0042] It should be noted that, in this embodiment, in the common-base operating mode, the base of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0.1V≤ V BE ≤1V, step size 0.1V, collector-base bias voltage V CB The range is 1V≤ V CB ≤3V, step size is 0.04V.
[0043] It should be noted that, in this embodiment, in the common-emitter operating mode, the emitter of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0≤ V BE ≤5V, step size 1V, collector-emitter bias voltage V CE The range is 0≤ V CE ≤6V, with a step size of 0.06V.
[0044] It should be noted that, in this embodiment, constructing the DC output characteristic model of the target van der Waals bipolar junction transistor based on the output characteristic curve includes: The expression for the DC output characteristic model is as follows:
[0045] in, IC Represents the collector output current. V BE Represents the base-emitter voltage. V CE Represents the collector-emitter voltage. V offset Represents offset voltage. l Representative base width modulation effect parameters, A n , N and m For the fitting parameters, k The order of the predefined polynomial function is given.
[0046] It should be noted that, in this embodiment, the offset voltage is calculated as follows:
[0047] in, K For the fitting parameters, V 0 represents V BE The offset voltage when it is 0.
[0048] It should be noted that, in this embodiment, the base region width modulation effect parameter is calculated as follows:
[0049] in, m For the fitting parameters, l 0 represents V BE The base width modulation effect parameter when it is 0.
[0050] It should be noted that, in this embodiment, obtaining the initial parameters of the DC output characteristic model includes: Extract different V CE Down I C Open instantly V CE As V offset And extract based on curve fitting method K and V 0; Select V CE The data range >2.5V was extracted using a curve fitting method. A n , m and l 0; Extract K ,V 0、 A n , m and l Substituting 0 into the DC output characteristic model, extract N and m .
[0051] It should be noted that, in this embodiment, the initial parameters are iteratively optimized using existing mathematical software to obtain optimized parameters, including: Select the collector output current I in the output characteristic curve C The portion greater than 0 is used as the experimental dataset; The existing mathematical software is 1stopt software; The initial parameters 、 The experimental dataset and DC output characteristic model were written into the 1stopt software; The initial parameters were optimized using the 1stopt software, with the optimization conditions set as follows: the optimization algorithm was set to Levenberg. Marquardt optimization algorithm, with a tolerance of 10. 10 The maximum number of iterations is 1000. When the maximum number of convergences or the preset convergence criterion is reached, the iteration stops, and the optimized parameters are finally obtained.
[0052] In practical applications, the thickness of the collector region is 20nm, the thickness of the base region is 6nm, and the thickness of the emitter region is 20nm. In the common-base operating mode, the base of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The collector-base bias voltage is 0.5V with a step size of 0.1V. V CB The voltage is 1V, and the step size is 0.04V.
[0053] In the common-emitter operating mode, the emitter of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The collector-emitter bias voltage is 2.5V with a step size of 1V. V CE The voltage is 3V, with a step size of 0.06V.
[0054] A simulation module is constructed based on the DC output characteristic model. This simulation module includes simulation modules for both common-base and common-emitter operating modes. Simulation calculations are performed on this module to obtain experimental graphs of the simulation data and experimental data, including experimental graphs for both common-base and common-emitter operating modes. The experimental graph for the common-base operating mode is shown below. Figure 3 As shown, the experimental diagram in the common-emitter operating mode is as follows: Figure 4 As shown in the figure. The experiment shows that the simulation curve coincides with the test curve, verifying the effectiveness and accuracy of the simulation method.
[0055] The same or similar labels correspond to the same or similar parts; The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent. Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A simulation method for a van der Waals bipolar junction transistor DC output characteristic model, characterized in that, include: Obtain the target van der Waals bipolar junction transistor and experimentally measure the output characteristic curve of the target van der Waals bipolar junction transistor; Based on the output characteristic curve, construct a DC output characteristic model of the target van der Waals bipolar junction transistor and obtain the initial parameters of the DC output characteristic model; The initial parameters are iteratively optimized using existing mathematical software to obtain the optimized parameters. A simulation module is constructed based on the DC output characteristic model, and simulation parameters are set based on the optimized parameters. The simulation module is used to perform simulation calculations, and the simulation data and simulation curves of the target van der Waals bipolar junction transistor are obtained, thus completing the simulation.
2. The simulation method for the DC output characteristic model of a van der Waals bipolar junction transistor according to claim 1, characterized in that, Obtaining the target van der Waals bipolar junction transistor includes: A substrate is obtained, wherein the substrate material is Si / SiO2 and the thickness is 300 nm; MoS2, WSe2, and MoS2 are sequentially stacked on the substrate using a dry transfer process to form a collector region, a base region, and an emitter region, respectively. The thickness of the collector region is 15nm≤d1≤30nm, the thickness of the base region is 4nm≤d2≤10nm, and the thickness of the emitter region is 15nm≤d3≤30nm. Cr / Au with a thickness of 10nm / 100nm is deposited on the surfaces of the collector region, base region, and emitter region to form the collector, base, and emitter, respectively, thereby obtaining the target van der Waals bipolar junction transistor.
3. The simulation method for a van der Waals bipolar junction transistor DC output characteristic model according to claim 1, characterized in that, The output characteristic curve of the target van der Waals bipolar junction transistor was measured experimentally, including: By applying different bias voltages and measuring the corresponding output currents in common-base and common-emitter operating modes, the output characteristic curves of the target van der Waals bipolar junction transistor are obtained.
4. The simulation method for the DC output characteristic model of a van der Waals bipolar junction transistor according to claim 3, characterized in that, In the common-base operating mode, the base of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0.1V≤ V BE ≤1V, step size 0.1V, collector-base bias voltage V CB The range is 1V≤ V CB ≤3V, with a step size of 0.04V.
5. The simulation method for the DC output characteristic model of a van der Waals bipolar junction transistor according to claim 3, characterized in that, In the common-emitter operating mode, the emitter of the van der Waals bipolar junction transistor is grounded, and the base-emitter bias voltage is... V BE The range is 0≤ V BE ≤5V, step size 1V, collector-emitter bias voltage V CE The range is 0≤ V CE ≤6V, with a step size of 0.06V.
6. The simulation method for the DC output characteristic model of a van der Waals bipolar junction transistor according to claim 1, characterized in that, Based on the output characteristic curve, a DC output characteristic model of the target van der Waals bipolar junction transistor is constructed, including: The expression for the DC output characteristic model is as follows: in, I C Represents the collector output current. V BE Represents the base-emitter voltage. V CE Represents the collector-emitter voltage. V offset Represents offset voltage. λ Representative base width modulation effect parameters, A n , N and m For the fitting parameters, k The order of the predefined polynomial function is given.
7. The simulation method for a van der Waals bipolar junction transistor DC output characteristic model according to claim 6, characterized in that, The offset voltage is calculated as follows: in, K For the fitting parameters, V 0 represents V BE The offset voltage when it is 0.
8. The simulation method for the DC output characteristic model of a van der Waals bipolar junction transistor according to claim 7, characterized in that, The base region width modulation effect parameter is calculated as follows: in, μ For the fitting parameters, λ 0 represents V BE The base width modulation effect parameter when it is 0.
9. The simulation method for a van der Waals bipolar junction transistor DC output characteristic model according to claim 8, characterized in that, Obtaining the initial parameters of the DC output characteristic model includes: Extract different V CE Down I C Open instantly V CE As V offset And extract based on curve fitting method K and V 0; Select V CE The data range >2.5V was extracted using a curve fitting method. A n , μ and λ 0; Extract K , V 0、 A n , μ and λ Substituting 0 into the DC output characteristic model, extract N and m .
10. The simulation method for a van der Waals bipolar junction transistor DC output characteristic model according to claim 1, characterized in that, The initial parameters are iteratively optimized using existing mathematical software to obtain optimized parameters, including: Select the collector output current I in the output characteristic curve C The portion greater than 0 is used as the experimental dataset; The existing mathematical software is 1stopt software; The initial parameters 、 The experimental dataset and DC output characteristic model were written into the 1stopt software; The initial parameters were optimized using the 1stopt software, with the optimization conditions set as follows: the optimization algorithm was set to Levenberg. Marquardt optimization algorithm, with a tolerance of 10. 10 The maximum number of iterations is 1000. When the maximum number of convergences or the preset convergence criterion is reached, the iteration stops, and the optimized parameters are finally obtained.