Semiconductor device having multiple stacked passive devices

Abstract

The present invention relates to a semiconductor device. In one embodiment, the semiconductor device includes a first-layer passive device comprising a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, and one or more second-layer passive devices disposed on the first-layer passive device. Each of the one or more second-layer passive devices comprises a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, and a set of through-substrate vias (TSVs) passing through the corresponding substrate portion and electrically coupled to the corresponding metallization portion. The semiconductor device comprises a passive component including a passive device portion of the first-layer passive device electrically coupled to one or more passive device portions of the one or more second-layer passive devices through the first-layer passive device and the metallization portions of the one or more second-layer passive devices.

Description

Technical Field

[0001]

[0001] This disclosure relates to semiconductor devices, and more particularly to semiconductor devices having a plurality of stacked passive devices.

Background Art

[0002]

[0002] Integrated circuit (IC) technology has achieved great progress in improving computing power through miniaturization of electrical components. An IC device can be implemented in the form of an IC chip having a set of circuits integrated thereon, including a plurality of active components (e.g., transistors) and passive components (e.g., diodes, capacitors, inductors, and / or resistors), and a layer of contacts and interconnects above the active and passive components. In some implementations, one or more IC chips can be physically carried and protected by an IC package based on a packaging substrate.

[0003]

[0003] In some implementations, embedded passive devices such as deep trench capacitors are incorporated into IC packaging for performance improvement and package size reduction. One factor driving the use of such embedded passive devices is the desire to obtain small form factor products with electrical performance equivalent to or better than that of their larger passive device counterparts. In some implementations, depending on the size and / or thickness of the packaging substrate and the process for embedding passive devices in the packaging substrate, the size of the passive device may need to match the thickness of the core of the packaging substrate, and the electrical characteristics of the passive device may be limited. In some implementations, passive devices embedded in the packaging substrate may not include an electrostatic discharge (ESD) protection circuit provided therein.

[0004]

[0004] Therefore, there is a need for a semiconductor device (which can be embedded in a packaging substrate as an embedded passive device) and a method for manufacturing such a semiconductor device. [Overview of the Initiative]

[0005]

[0005] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, the following overview should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope associated with any particular embodiment. Accordingly, the sole purpose of the following overview is to provide, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0006]

[0006] In one embodiment, the semiconductor device is a first-tier passive device comprising a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, and one or more second-tier passive devices disposed on the first-tier passive device, wherein each of the one or more second-tier passive devices comprises a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, and through-substrate vias passing through the corresponding substrate portion and electrically coupled to the corresponding metallization portion. A passive component comprising one or more second-layer passive devices, including a set of vias (TSVs), and a passive component comprising a metallization portion of a first-layer passive device, one or more sets of TSVs of one or more second-layer passive devices, and a passive component of a first-layer passive device electrically coupled to one or more passive component portions of one or more second-layer passive devices through one or more metallization portions of one or more second-layer passive devices.

[0007]

[0007] In one embodiment, a method for manufacturing a semiconductor device is to provide a first layer passive device, wherein the first layer passive device includes a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, the passive device portion being located between the substrate portion and the metallization portion, and to form a semiconductor device, one or more second layer passive devices are stacked on the first layer passive device, each of the one or more second layer passive devices includes a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, the passive device portion being located between the substrate portion and the metallization portion The passive component includes a substrate portion, a passive device portion, and a metallization portion disposed between the substrate and the metallization portion, and a set of through-substrate vias (TSVs) passing through the corresponding substrate portion and electrically coupled to the corresponding metallization portion, and forming a passive component including a metallization portion of a first-layer passive device, one or more sets of TSVs of one or more second-layer passive devices, and a passive device portion of a first-layer passive device electrically coupled to one or more passive device portions of one or more second-layer passive devices through one or more metallization portions of one or more second-layer passive devices.

[0008]

[0008] In one embodiment, the electronic device includes an integrated circuit device including a semiconductor device, the semiconductor device being a first layer passive device including a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, and one or more second layer passive devices disposed on the first layer passive device, wherein each of the one or more second layer passive devices is a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion The passive device comprises one or more second-layer passive devices, each including a substrate portion, a passive device portion, and a metallization portion, and a set of through-substrate vias (TSVs) passing through the corresponding substrate portion and electrically coupled to the corresponding metallization portion; and a passive component including a metallization portion of a first-layer passive device, one or more sets of TSVs of one or more second-layer passive devices, and a passive device portion of a first-layer passive device electrically coupled to one or more passive device portions of one or more second-layer passive devices through one or more metallization portions of one or more second-layer passive devices.

[0009]

[0009] Other purposes and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. [Brief explanation of the drawing]

[0010]

[0010] A more complete understanding of many aspects of this disclosure and their associated advantages will be easier to obtain if they are examined together with the accompanying drawings, which are presented not to limit this disclosure but merely to illustrate it, by referring to the following detailed description. [Figure 1]

[0011] This is a cross-sectional view of an exemplary packaging substrate in which a semiconductor device is embedded, according to an aspect of the present disclosure. [Figure 2]

[0012] This is a cross-sectional view of an exemplary deep trench capacitor (DTC) according to an aspect of the present disclosure. [Figure 3]

[0013] This is a cross-sectional view of an exemplary semiconductor device configured without a plurality of stacked passive devices, according to an aspect of the present disclosure. [Figure 4]

[0014] This is a cross-sectional view of a first exemplary semiconductor device comprising a plurality of stacked passive devices according to an aspect of the present disclosure. [Figure 5AB]

[0015] Figure 4 shows the structure at various stages in the manufacturing of the semiconductor device according to aspects of this disclosure. [Figure 5CD] Figure 4 shows the structure at various stages in the manufacturing of the semiconductor device according to aspects of this disclosure. [Figure 5EF] Figure 4 shows the structure at various stages in the manufacturing of the semiconductor device according to aspects of this disclosure. [Figure 6]

[0016] This is a cross-sectional view of a second exemplary semiconductor device comprising a plurality of stacked passive devices according to an aspect of the present disclosure. [Figure 7AB]

[0017] Figure 6 shows the structure at various stages of manufacturing the semiconductor device according to aspects of this disclosure. [Figure 7CD] Figure 6 shows the structure at various stages of manufacturing the semiconductor device according to aspects of this disclosure. [Figure 7EF] Figure 6 shows the structure at various stages of manufacturing the semiconductor device according to aspects of this disclosure. [Figure 7G] Figure 6 shows the structure at various stages of manufacturing the semiconductor device according to aspects of this disclosure. [Figure 8]

[0018] This disclosure describes a method for manufacturing a semiconductor device according to the embodiments of this disclosure. [Figure 9]

[0019] A side view of a package including a surface mount substrate and an integrated device according to an aspect of the present disclosure is shown. [Figure 10]

[0020] An exemplary flow diagram of a method for manufacturing a package including a substrate, an integrated device, and an integrated passive device is shown. [Figure 11]

[0021] The figures show various electronic devices that can integrate the electronic components, electronic circuits, integrated devices, integrated passive devices, passive components, packages, and / or device packages described herein.

[0011]

[0022] In accordance with convention, the features shown in the drawings may not be drawn to scale. Accordingly, the dimensions of the features shown may be arbitrarily enlarged or reduced for clarity. In accordance with convention, some of the drawings are simplified for clarity. Thus, the drawings may not depict all of the components of a particular apparatus or method. Further, like reference numerals indicate like features throughout this specification and the figures.

DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0023] Aspects of the present disclosure are provided in the following description and associated drawings directed to various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of the present disclosure. Additionally, well-known elements of the present disclosure are not described in detail or are omitted so as not to obscure the relevant details of the present disclosure.

[0013]

[0024] Various aspects generally relate to semiconductor devices having a plurality of stacked passive devices and manufacturing methods for fabricating semiconductor devices. Some aspects more particularly relate to semiconductor devices based on a first layer passive device and one or more second layer passive devices stacked on the first layer passive device.

[0014]

[0025] Certain aspects of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In some examples, by forming a semiconductor device having a plurality of stacked passive devices, the thickness of the semiconductor device can be adjusted to match the thickness of the core for a particular packaging task. The first layer passive device of the semiconductor device can further include an ESD protection circuit. Also, based on the combined effect of the stacked passive devices, the electrical characteristics of the resulting passive components can be improved or enhanced.

[0015]

[0026] As used herein, the terms “exemplary” and / or “example” are used to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” should not necessarily be construed as preferred or advantageous over other aspects. Similarly, the term “aspects of the present disclosure” does not necessarily require that all aspects of the present disclosure include the discussed features, advantages, or modes of operation.

[0016]

[0027] Those skilled in the art will understand that the information and signals described below can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the following description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof, depending in part on a particular application, desired design, corresponding technology, etc.

[0017]

[0028] Furthermore, many embodiments are described, for example, in terms of sequences of actions to be performed by elements of a computing device. It will be recognized that the various actions described herein can be performed by specific circuits (e.g., application-specific integrated circuits, ASICs), by program instructions executed by one or more processors, or a combination of both. In addition, the sequence(s) of actions described herein, when executed, can be considered to be fully embodied in any form of non-temporary computer-readable storage medium that stores a corresponding set of computer instructions that cause or instruct the relevant processors of the device to perform the functions described herein. Thus, the various embodiments of this disclosure can be embodied in several different forms, all of which are intended to fall within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, any corresponding form of such embodiment may be described herein, for example, as “logic configured to perform” the described actions.

[0018]

[0029] Figure 1 is a cross-sectional view of an exemplary packaging substrate 100 in which a semiconductor device 106 is embedded, according to an aspect of the present disclosure. In this example, the packaging substrate 100 includes a core 102, the core 102 having a cavity 104 extending completely through the core 102. The semiconductor device 106 is disposed within the cavity 104. The semiconductor device 106 has a top surface 108 having metal terminals 110 that provide electrical connections to passive components (e.g., capacitors) configured within the semiconductor device 106.

[0019]

[0030] The packaging substrate 100 further includes a plurality of dielectric layers 112 covering the upper surface 116 of the core 102 and corresponding patterned metallization layers 114. The patterned metallization layers 118 are disposed on the upper surface 116 of the core 102 to provide electrical connections between the metal terminals 110 of the semiconductor device 106 and the patterned metallization layers 114. In one embodiment, the same dielectric resin material used to form the plurality of dielectric layers 112 may be used in the gap region 109 of the cavity 104, between the sidewall of the semiconductor device 106 and the sidewall of the cavity 104. Applying the dielectric resin to the semiconductor device 106 and into the gap region 109 helps to fix the semiconductor device 106 in the cavity 104 so that, once the dielectric resin has cured, the metal terminals 110 maintain electrical contact with the corresponding portions of the patterned metallization layers 118.

[0020]

[0031] In one embodiment, the uppermost patterned metallization layer 114 on the top surface 120 of the packaging substrate 100 is connected to a plurality of metal terminals 122. The patterned metallization layer 114 provides a conductive path between the metal terminals 110 and 122 of the semiconductor device 106. In one embodiment, the plurality of metal terminals 122 may be configured to connect to an electronic package of a surface mount device (not shown in Figure 1).

[0021]

[0032] In one embodiment, a further plurality of dielectric layers 132 and corresponding patterned metallization layers 134 cover the bottom surface 136 of the core 102. Here, a patterned metallization layer 138 is positioned on the bottom surface 136 of the core 102. The bottommost patterned metallization layer 134 on the bottom surface 140 of the packaging substrate 100 is connected to a plurality of metal terminals 142. The patterned metallization layer 134 provides a conductive path to the metal terminals 142. In one embodiment, the plurality of metal terminals 142 may be configured to connect to an electronic package of a further surface mount device (not shown in Figure 1) or to a circuit board for connection to other devices.

[0022]

[0033] In Figure 1, the semiconductor device 106 has a height H1 that is substantially the same as the thickness H2 of the core 102. During the manufacturing of the packaging substrate 100, the semiconductor device 106 is inserted into the cavity 104 before dielectric resin is injected to fill the gap region 109 between the cavity 104 and the semiconductor device 106. During insertion, the semiconductor device 106 is carefully aligned within the cavity 104 to ensure that the metal terminals 110 make proper contact with and electrically bond to the corresponding portions of the patterned metallization layer 118. In addition, the injection of dielectric resin into the gap region 109 should be carried out with care not to disturb the initial alignment of the semiconductor device 106. In one embodiment, once the dielectric resin has cured, it fixes the semiconductor device 106 in its proper position within the cavity 104.

[0023]

[0034] In a scenario where the height H1 of the semiconductor device 106 and the thickness H2 of the core 102 are substantially the same, the insertion of the semiconductor device 106 into the cavity 104, and the subsequent injection and curing of the dielectric resin, can be achieved using processing techniques as described with reference to Figure 1.

[0024]

[0035] In some embodiments, the thickness H2 of the core 102 may be about 760 micrometers or less. In some embodiments, the recent trend is to have a thicker core to address issues such as substrate warping control, and the thickness H2 of the core 102 may be greater than about 760 micrometers (μm), and may even be in the range of 1.2 millimeters (mm) to 1.8 mm.

[0025]

[0036] However, according to some current designs, the height H1 of a semiconductor device 106 consisting of a single passive device can be in the range of 20 μm to 780 μm. In some embodiments, according to this application, a semiconductor device having a plurality of stacked passive devices may have a height that can be adjusted to match the thickness of the core for a particular packaging task.

[0026]

[0037] In some embodiments, the passive devices described herein may be capacitors, inductors, resistors, or combinations thereof. Figure 2 is a cross-sectional view of an exemplary deep trench capacitor 200 according to an embodiment of this disclosure. In some embodiments, the passive devices usable on the packaging substrate 100 of Figure 1 may be capacitors configured based on the deep trench capacitor 200.

[0027]

[0038] In Figure 2, the deep trench capacitive structure 210 is disposed in trenches 220 of an insulator 204 on a substrate 202. The deep trench capacitive structure 210 may include a conductive layer 212, a dielectric layer 214, and a conductive layer 216. The dielectric layer 214 separates the conductive layer 212 from the conductive layer 216. The conductive layers 212 and 216 of the deep trench capacitive structure 210 form electrodes of a capacitor 200, which may be connected, for example, to terminals on the surface of the resulting passive device (e.g., the top surface 108 with metal terminals 110 of the semiconductor device 106 shown in Figure 1). In some scenarios, multiple capacitive structures may be formed from an array of deep trenches in the substrate, with the spaces between the electrode layers filled with an electrical insulator (e.g., a dielectric).

[0028]

[0039] In some embodiments, the conductive layer 212 and / or conductive layer 216 may include copper, tungsten, aluminum, or a combination thereof. In some embodiments, the conductive layer 212 and / or conductive layer 216 may include polysilicon, doped silicon, or a combination thereof. In some embodiments, the dielectric layer 214 may include silicon oxide, a high-k material (having a relative permittivity (k) greater than that of silicon dioxide), or a combination thereof.

[0029]

[0040] Figure 3 is a cross-sectional view of an exemplary semiconductor device 300 configured without stacked passive devices, according to an aspect of the present disclosure. In some aspects, the semiconductor device 300 may be used as the semiconductor device 106 shown in Figure 1. The semiconductor device 300 includes a substrate portion 310, a passive device portion 320, and a metallization portion 330 arranged in a stacked configuration, with the passive device portion 320 disposed between the substrate portion 310 and the metallization portion 330. In some aspects, the metallization portion 330 may be manufactured based on a back end of line (BEOL) process. In some aspects, the passive device portion 320 may be manufactured based on a front end of line (FEOL) process or a middle of line (MOL) process.

[0030]

[0041] The semiconductor device 300 includes a passivation layer 340 on top of the metallization portion 330. The semiconductor device 300 further includes electrical terminal structures 352, 354, 356, and 358 which may correspond to the metal terminals 110 shown in Figure 1. In some embodiments, the electrical terminal structures 352, 354, 356, and 358 may include copper pillars, conductive pads, solder, or a combination thereof.

[0031]

[0042] In some embodiments, the substrate portion 310 may include silicon, germanium, and / or gallium arsenide. In some embodiments, the substrate portion 310 may correspond to the substrate 202 shown in Figure 2. In some embodiments, the passivation layer 340 may include an oxide material (e.g., silicon dioxide) or a nitride material (e.g., silicon nitride).

[0032]

[0043] In some embodiments, the passive device portion 320 includes deep trench capacitive structures 321, 323, 325, 327, and 329, each of which may have a configuration corresponding to the deep trench capacitive structure 210 shown in Figure 2. In some embodiments, the metallization portion 330 may include an interlayer dielectric layer and a conductive layer (unlabeled). In some embodiments, the metallization portion 330 may electrically couple the deep trench capacitive structures 321, 323, 325, 327, and 329 in series or parallel to electrical terminal structures 352, 354, 356, and 358 to form one or more passive components. In some embodiments, the deep trench capacitive structures 321, 323, 325, 327, and 329 may be configured as a single capacitor, and the electrical terminal structures 352, 354, 356, and 358 may be divided into two subsets as separate electrical terminals of the resulting capacitor. In some embodiments, the deep trench capacitive structures 321, 323, 325, 327, and 329 may be configured as two capacitors, two of the electrical terminal structures 352, 354, 356, and 358 may be configured as electrical terminals of a first resulting capacitor, and the other two of the electrical terminal structures 352, 354, 356, and 358 may be configured as electrical terminals of a second resulting capacitor.

[0033]

[0044] In some embodiments, the height H3 of a semiconductor device 300 consisting of a single passive device may be in the range of 20 μm to 780 μm. In some embodiments, when the core thickness of the packaging substrate is much greater than 780 μm, the semiconductor device 300 may not be embedded in such a packaging substrate based on the packaging scheme shown in Figure 1 (for example, it may be inserted into a through-cavity of the core).

[0034]

[0045] Figure 4 is a cross-sectional view of a first exemplary semiconductor device 400 comprising a plurality of stacked passive devices according to an aspect of the present disclosure. In some aspects, the semiconductor device 400 may be called a hybrid junction multi-stacking semiconductor device. In some aspects, the semiconductor device 400 may be used as the semiconductor device 106 in Figure 1.

[0035]

[0046] The semiconductor device 400 includes a first-layer passive device 410 and one or more second-layer passive devices 430a and 430b disposed on the first-layer passive device 410. The example shown in Figure 4 shows two second-layer passive devices 430a and 430b on the first-layer passive device 410, but in some embodiments, there may be only one second-layer passive device or three or more second-layer passive devices stacked on the first-layer passive device 410.

[0036]

[0047] The first layer passive device 410 includes a substrate portion 412, a passive device portion 414, and a metallization portion 416 arranged in a stacked configuration. In some embodiments, the passive device portion 414 may be disposed between the substrate portion 412 and the metallization portion 416. In this example, the passive device portion 414 of the first layer passive device 410 is disposed on top of the substrate portion 412 of the first layer passive device 410. The first layer passive device 410 further includes a passivation layer 418 and an electrical terminal structure 422 on top of the metallization portion 416. In some embodiments, the substrate portion 412, the passive device portion 414, the metallization portion 416, the passivation layer 418, and the electrical terminal structure 422 may correspond to the substrate portion 310, the passive device portion 320, the metallization portion 330, the passivation layer 340, and the electrical terminal structures 352-358 in Figure 3, and a detailed description of these may be omitted.

[0037]

[0048] In some embodiments, the deep trench capacitive structure is shown in this disclosure as a passive element disposed within a passive device portion, the passive device portion may include a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof. In some embodiments, the passive device portion may include a capacitor, an inductor, a resistor, or a combination thereof.

[0038]

[0049] In some embodiments, the first layer passive device 410 may further include one or more electrostatic discharge (ESD) protection circuits 424 and 426 disposed in the substrate portion 412 of the first layer passive device 410 and electrically coupled to the passive device portion 414 of the first layer passive device 410. In some embodiments, one or more ESD protection circuits 424 and 426 may include diodes (considered as passive components in this disclosure) configured to provide ESD protection to the resulting passive components of the semiconductor device 400.

[0039]

[0050] Furthermore, each of the one or more second-layer passive devices 430a and 430b includes a substrate portion 432a / 432b, a passive device portion 434a / 434b, and a metallization portion 416a / 416b arranged in a stacked configuration, wherein the passive device portion 434a / 434b is disposed between the substrate portion 432a / 432b and the metallization portion 436a / 436b. Each of the one or more second-layer passive devices 430a and 430b may include a set of through-substrate vias (TSVs) 444a / 444b that pass through the corresponding substrate portion 432a / 432b and are electrically coupled to the corresponding metallization portion 436a / 436b.

[0040]

[0051] In this example, the substrate portion 432a of the second layer passive device 430a is disposed on the passive device portion 434a of the second layer passive device 430a, and the substrate portion 432b of the second layer passive device 430b is disposed on the passive device portion 434b of the second layer passive device 430b. In addition, one or more second layer passive devices 430a and 430b may each include a passivation layer 438a and an electrical terminal structure 442a / 442b adjacent to the metallization portion 436a / 436b. The second layer passive device 430a may further include an etch stop layer 452a adjacent to the substrate portion 432a, and a passivation layer 454a and an electrical terminal structure 456a above the etch stop layer 452a. The second layer passive device 430b may further include an etch stop layer 452b adjacent to the substrate portion 432b. The semiconductor device 400 may also include electrical terminal structures 462, 464, 466, and 468 above the etch stop layer 452b.

[0041]

[0052] Various parts of the second layer passive devices 430a and 430b are shown as non-limiting examples. In some embodiments, different parts within each of the second layer passive devices 430a / 430b may be individually configured to be stacked in the same or reverse order as shown in Figure 4.

[0042]

[0053] In some embodiments, the semiconductor device 400 includes a passive component, which further includes a metallization portion 416 of a first-layer passive device 410, one or more sets of TSVs 444a / 444b of one or more second-layer passive devices 430a / 430b, and a passive component 414 of a first-layer passive device 410 electrically coupled to one or more passive component portions 434a / 434b of one or more second-layer passive devices 430a / 430b through one or more metallization portions 436a / 436b of one or more second-layer passive devices 430a / 430b. In some embodiments, at least two of the electrical terminal structures 462, 464, 466, and 468 disposed on the upper surface of the uppermost second-layer passive device (for example, second-layer passive device 430b) among one or more second-layer passive devices 430a / 430b may be configured as electrical terminals of the semiconductor device 400, and the resulting passive components.

[0043]

[0054] In some embodiments, the electrical terminal structure 422 may be a first conductive structure in the form of a conductive pad, and the electrical terminal structure 442a may be a second conductive structure in the form of a conductive pad bonded to the first conductive structure. In some embodiments, the first conductive structure may be connected to the second conductive structure based on fusion bonding or hybrid bonding. In some embodiments, the electrical terminal structure 456a may be a third conductive structure in the form of a conductive pad, and the electrical terminal structure 442b may be a fourth conductive structure in the form of a conductive pad bonded to the third conductive structure. In some embodiments, the third conductive structure may be connected to the fourth conductive structure based on fusion bonding or hybrid bonding.

[0044]

[0055] In some embodiments, the substrate portion 432a of the second layer passive device 430a is located on top of the passive device portion 434a of the second layer passive device 430a, as shown in Figure 4. In this scenario, the second conductive structure (e.g., electrical terminal structure 442a) to be bonded to the first layer passive device 410 is located on the underside of the second layer passive device 430a and adjacent to the metallization portion 436a of the second layer passive device 430a. In some embodiments, the passive device portion 434a of the second layer passive device 430a may be located on top of the substrate portion 432a of the second layer passive device 430a (e.g., by inverting the second layer passive device 430a upside down, as shown in Figure 4). In this scenario, the second conductive structure to be joined to the first layer passive device 410 (for example, the electrical terminal structure 456a after inverting the second layer passive device 430a shown in Figure 4) may be located on the underside of the second layer passive device 430a and connected to the set of TSVs 444a of the second layer passive device 430a.

[0045]

[0056] In some embodiments, the substrate portion 412 of the first layer passive device 410 may not be further trimmed, and thus the thickness of the wafer substrate for manufacturing the first layer passive device 410 can be substantially maintained. In some embodiments, the thickness H4 of the first layer passive device 410 may be similar to the thickness H3 of the semiconductor device 300, and may be in the range of 20 μm to 780 μm. In some embodiments, the substrate portions 432a / 432a of the second layer passive devices 430a / 430b may be further trimmed, and thus may have a thickness smaller than the thickness of the wafer substrate for manufacturing the second layer passive devices 430a / 430b. Therefore, the thickness of the substrate portion 412 of the first layer passive device 410 may be greater than the thickness of the substrate portions 432a / 432b of one or more second layer passive devices 430a / 430b. In some embodiments, the thickness H4a / H4b of the second layer passive device 430a / 430b may be in the range of 20 μm to 100 μm.

[0046]

[0057] In some embodiments, the total thickness of the semiconductor device 400 can be adjusted based on the number of second-layer passive devices and the thickness of the second-layer passive devices (one or more) to match the core thickness for a particular packaging task. For example, if the first-layer passive device 410 has a thickness H4 of 780 μm and each of the second-layer passive devices 430a / 430b has a thickness H5a / H5b of 50 μm, the total thickness of stacking N second-layer passive devices will be (780 + 50 × N) μm. In some embodiments, the overall thickness of the semiconductor device 400 may be in the range of 1.2 mm to 1.8 mm.

[0047]

[0058] Furthermore, the resulting passive components of the semiconductor device 400 may have electrical properties based on the combined effects of at least the passive device portions 414, 434a, and / or 434b. In one example, the resulting passive component may be a capacitor, and its capacitance may be a combination of the capacitive elements of the passive device portions 414, 434a, and / or 434b. In another example, the resulting passive component may be an inductor, and its inductance may be a combination of the inductive elements of the passive device portions 414, 434a, and / or 434b. Thus, by stacking multiple passive devices, larger capacitances or inductances can be implemented within the same footprint as the semiconductor device 300.

[0048]

[0059] Figures 5A to 5F show the structures at various stages of manufacturing the semiconductor device 400 of Figure 4 according to embodiments of this disclosure. Among the elements shown in Figures 5A to 5F, elements that are the same as or similar to those in the semiconductor device 400 of Figure 4 are given the same reference numerals, and their detailed descriptions may be omitted.

[0049]

[0060] As shown in Figure 5A, a structure 500A is provided. Structure 500A includes a first layer passive device 410. In some embodiments, the first layer passive device 410 includes a substrate portion 412, a passive device portion 414, and a metallization portion 416 arranged in a stacked configuration. The first layer passive device 410 further includes a passivation layer 418 and an electrical terminal structure 422 on the metallization portion 416. In some embodiments, the first layer passive device 410 may further include one or more ESD protection circuits 424 and 426 disposed in the substrate portion 412 of the first layer passive device 410 and electrically coupled to the passive device portion 414 of the first layer passive device 410.

[0050]

[0061] In some embodiments, the electrical terminal structure 422 may be a conductive structure in the form of a conductive pad and may contain copper. In some embodiments, after forming the electrical terminal structure 422 on the metallization portion 416, a passivation layer 418 may be formed by depositing a passivation material (e.g., an oxide material or a nitride material), and the upper surface of the first layer passive device 410 may be prepared based on a chemical-mechanical polishing (CMP) process followed by a surface cleaning process (e.g., a surface plasma cleaning process).

[0051]

[0062] As shown in Figure 5B, the second layer passive device 530a is added to the first layer passive device 410 to form structure 500B based on structure 500A. The second layer passive device 530a may include a substrate portion 532a, a passive device portion 434a, and a metallization portion 436a arranged in a stacked configuration. The second layer passive device 530a may include a set of TSVs 534a connected to the metallization portion 436a and extending into the substrate portion 532a. The second layer passive device 530a may further include a passivation layer 438a and an electrical terminal structure 442a adjacent to the metallization portion 436a.

[0052]

[0063] In some embodiments, the second layer passive device 530a may be manufactured in a similar manner to the first layer passive device 410 (except for the formation of TSVs in the substrate portion and the absence of ESD protection circuits), and then inverted upside down. The electrical terminal structure 442a may be a conductive structure in the form of a conductive pad, and the electrical terminal structures 422 and 442a may be joined by performing a fusion bonding process or a hybrid bonding process. In some embodiments, the electrical terminal structures 422 and 442a may be joined by other bonding processes, such as those based on soldering.

[0053]

[0064] As shown in Figure 5C, structure 500C is formed based on structure 500B by forming a second layer passive device 540a based on a second layer passive device 530a. In some embodiments, a portion of the substrate portion 532a of the second layer passive device 530a may be concave (e.g., based on a CMP process) to become a trimmed substrate portion 432a. A layer of etch-stop material (e.g., silicon nitride) may be deposited on the substrate portion 432a (e.g., based on a chemical vapor deposition (CVD) process), followed by a polishing process (e.g., based on a CMP process) to reduce the thickness of the etch-stop material layer to become an etch-stop layer 452a, and a set of TSV 534a is trimmed and exposed to become a set of TSV 444a.

[0054]

[0065] As shown in Figure 5D, structure 500D is formed based on structure 500C by forming a second layer passive device 430a based on a second layer passive device 540a. In some embodiments, a passivation layer 454a and an electrical terminal structure 456a may be formed above the etch stop layer 452a.

[0055]

[0066] As shown in Figure 5E, structure 500E is formed based on structure 500D by stacking another second-layer passive device 430b on top of the second-layer passive device 430a, based on the same operation as described with reference to Figures 5B and 5C.

[0056]

[0067] As shown in Figure 5F, structure 500F is formed based on structure 500E by forming electrical terminal structures 462, 464, 466, and 468 on the upper surface of the uppermost second layer passive device 430b. In some embodiments, the electrical terminal structures 462, 464, 466, and 468 may include copper pillars, conductive pads, solder, or a combination thereof.

[0057]

[0068] Figure 6 is a cross-sectional view of a second exemplary semiconductor device 600 comprising a plurality of stacked passive devices according to an aspect of the present disclosure. In some aspects, the semiconductor device 600 may be called a chip-on-wafer stacking semiconductor device. In some aspects, the semiconductor device 600 may be used as the semiconductor device 106 in Figure 1.

[0058]

[0069] The semiconductor device 600 includes a first-layer passive device 610 and one or more second-layer passive devices 630a and 630b disposed on the first-layer passive device 610. The example shown in Figure 6 shows two second-layer passive devices 630a and 630b on the first-layer passive device 610, but in some embodiments, there may be only one second-layer passive device or three or more second-layer passive devices stacked on the first-layer passive device 610.

[0059]

[0070] The first layer passive device 610 includes a substrate portion 612, a passive device portion 614, and a metallization portion 616 arranged in a stacked configuration. In some embodiments, the passive device portion 614 may be disposed between the substrate portion 612 and the metallization portion 616. In this example, the passive device portion 614 of the first layer passive device 610 is disposed on top of the substrate portion 612 of the first layer passive device 610. The first layer passive device 610 further includes a passivation layer 618 and an electrical terminal structure 622 on top of the metallization portion 616. In some embodiments, the substrate portion 612, the passive device portion 614, the metallization portion 616, the passivation layer 618, and the electrical terminal structure 622 may correspond to the substrate portion 310, the passive device portion 320, the metallization portion 330, the passivation layer 340, and the electrical terminal structures 352-358 in Figure 3, and a detailed description of these may be omitted.

[0060]

[0071] In some embodiments, the deep trench capacitive structure is shown in this disclosure as a passive element disposed within a passive device portion, the passive device portion may include a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof. In some embodiments, the passive device portion may include a capacitor, an inductor, a resistor, or a combination thereof.

[0061]

[0072] In some embodiments, the first layer passive device 610 may further include one or more ESD protection circuits 624 and 626 disposed in the substrate portion 612 of the first layer passive device 610 and electrically coupled to the passive device portion 614 of the first layer passive device 610. In some embodiments, one or more ESD protection circuits 624 and 626 may include diodes (considered as passive components in this disclosure) configured to provide ESD protection to the resulting passive components of the semiconductor device 600.

[0062]

[0073] Furthermore, each of the one or more second-layer passive devices 630a and 630b may include a substrate portion 632a / 632b, a passive device portion 634a / 634b, and a metallization portion 616a / 616b arranged in a stacked configuration, wherein the passive device portion 634a / 634b is disposed between the substrate portion 632a / 632b and the metallization portion 636a / 636b. Each of the one or more second-layer passive devices 630a and 630b may include a set of through-substrate vias (TSVs) 644a / 644b that pass through the corresponding substrate portion 632a / 632b and are electrically coupled to the corresponding metallization portion 636a / 636b. Furthermore, each of the one or more second-layer passive devices 630a and 630b includes a passivation layer 638a / 638b and an electrical terminal structure 642a / 642b adjacent to the metallization portion 636a / 636b. The second-layer passive device 630a may further include an etch-stop layer 652a adjacent to the substrate portion 632a and an electrical terminal structure 656a above the etch-stop layer 652a. The second-layer passive device 630b may further include an etch-stop layer 652b adjacent to the substrate portion 632b.

[0063]

[0074] In some embodiments, the semiconductor device 600 includes a sealing structure 670 formed on a molding material on a first layer passive device 610 and surrounding one or more second layer passive devices 630a / 630b. The semiconductor device 600 may also include electrical terminal structures 662, 664, 666, and 668 above the etch stop layer 652b and the sealing structure 670.

[0064]

[0075] Various parts of the second layer passive devices 630a and 630b are shown as non-limiting examples. In some embodiments, different parts within each of the second layer passive devices 630a / 630b may be individually configured to be stacked in the same or reverse order as shown in Figure 6.

[0065]

[0076] In some embodiments, the semiconductor device 600 includes a passive component, which further includes a metallization portion 616 of a first-layer passive device 610, one or more sets of TSVs 644a / 644b of one or more second-layer passive devices 630a / 630b, and a passive component 614 of a first-layer passive device 610 electrically coupled to one or more passive device portions 634a / 634b of one or more second-layer passive devices 630a / 630b through one or more metallization portions 636a / 636b of one or more second-layer passive devices 630a / 630b. In some embodiments, at least two of the electrical terminal structures 662, 664, 666, and 668 disposed on the upper surface of the uppermost second-layer passive device (for example, second-layer passive device 630b) among one or more second-layer passive devices 630a / 630b may be configured as electrical terminals of the semiconductor device 600, and the resulting passive components.

[0066]

[0077] In some embodiments, the electrical terminal structure 622 may be a first conductive structure in the form of a conductive pad, and the electrical terminal structure 642a may be a second conductive structure in the form of a conductive pillar bonded to the first conductive structure. In some embodiments, the first conductive structure may be connected to the second conductive structure by a solder joint (for example, the solder joint may not be labeled and shown as a block connecting the electrical terminal structures 622 and 642a, respectively). In some embodiments, the electrical terminal structure 656a may be a third conductive structure in the form of a conductive pad, and the electrical terminal structure 642b may be a fourth conductive structure in the form of a conductive pillar bonded to the third conductive structure. In some embodiments, the third conductive structure may be connected to the fourth conductive structure by a solder joint (for example, the solder joint may not be labeled and shown as a block connecting the electrical terminal structures 656a and 642b, respectively).

[0067]

[0078] In some embodiments, the substrate portion 612 of the first layer passive device 610 may not be further trimmed, and thus the thickness of the wafer substrate for manufacturing the first layer passive device 610 can be substantially maintained. In some embodiments, the substrate portions 632a / 632a of the second layer passive devices 630a / 630b may be further trimmed, and thus they may have a thickness smaller than the thickness of the wafer substrate for manufacturing the second layer passive devices 630a / 630b. Therefore, the thickness of the substrate portion 612 of the first layer passive device 610 may be greater than the thickness of the substrate portions 632a / 632b of one or more second layer passive devices 630a / 630b.

[0068]

[0079] In some embodiments, similar to semiconductor device 400, the total thickness of semiconductor device 600 may be adjusted based on adjusting the number of second-layer passive devices and the thickness of the second-layer passive devices (one or more) to match the core thickness for a particular packaging task. In some embodiments, the overall thickness of semiconductor device 600 may be in the range of 1.2 mm to 1.8 mm. Furthermore, similar to semiconductor device 400, the resulting passive components of semiconductor device 600 may have electrical properties based on the combined effect of at least the passive device portions 614, 634a, and / or 634b. Thus, by stacking multiple passive devices, greater capacitance or inductance can be implemented within the same footprint as semiconductor device 300.

[0069]

[0080] Figures 7A to 7F show the structures at various stages of manufacturing the semiconductor device 600 of Figure 6 according to embodiments of this disclosure. Among the elements shown in Figures 7A to 7F, elements that are the same as or similar to those in the semiconductor device 600 of Figure 6 are given the same reference numerals, and their detailed descriptions may be omitted.

[0070]

[0081] As shown in Figure 7A, a structure 700A is provided. Structure 700A includes a first-layer passive device 610. In some embodiments, the first-layer passive device 610 includes a substrate portion 612, a passive device portion 614, and a metallization portion 616 arranged in a stacked configuration. The first-layer passive device 610 further includes a passivation layer 618 and an electrical terminal structure 622 on the metallization portion 616. In some embodiments, the first-layer passive device 610 may further include one or more ESD protection circuits 624 and 626 disposed in the substrate portion 612 of the first-layer passive device 610 and electrically coupled to the passive device portion 614 of the first-layer passive device 610. In some embodiments, structure 700A further includes a soldering structure 702 formed on the electrical terminal structure 622.

[0071]

[0082] In some embodiments, the electrical terminal structure 622 may be a conductive pad and may contain copper. In some embodiments, after forming the electrical terminal structure 622 on the metallization portion 616, a passivation layer 618 may be formed by depositing a passivation material (e.g., an oxide material or a nitride material), and the upper surface of the first layer passive device 610 may be prepared based on a chemical mechanical polishing (CMP) process followed by a surface cleaning process (e.g., a surface plasma cleaning process). Soldering material may then be deposited on the electrical terminal structure 622 to form a soldering structure 702.

[0072]

[0083] As shown in Figure 7B, structure 700B is formed based on structure 700A by attaching the second layer passive device 630a to the first layer passive device 610. The second layer passive device 630a may be a die manufactured and prepared to be stacked according to the present disclosure. In some embodiments, the electrical terminal structures 622 and 642a may be joined based on solder joints by solder joint structures 702. In some embodiments, if the second layer passive device 630a is not the top second layer passive device, the electrical terminal structure 656a may have a solder joint structure 704 stacked on top of it.

[0073]

[0084] As shown in Figure 7C, structure 700C is formed based on structure 700B by stacking all other second-layer passive devices (e.g., second-layer passive devices 630b) on the second-layer passive device 630a, based on the same operation as described with reference to Figure 7B.

[0074]

[0085] As shown in Figure 7D, structure 700D is formed based on structure 700C by arranging a molding material 710 on a first layer passive device 610 and surrounding one or more second layer passive devices 630a / 630b. In some embodiments, the molding material may include a resin. In some embodiments, the molding material may be deposited based on a molded underfill (MUF) process.

[0075]

[0086] As shown in Figure 7E, structure 700E is formed based on structure 700D by grinding the molding material 710 so that it becomes a sealing structure 670 and exposes the electrical terminal structures 662, 664, 666, and 668. In some embodiments, if the first layer passive device 610 in Figure 7A is an independent die, structure 700E may correspond to the semiconductor device 600.

[0076]

[0087] As shown in Figure 7F, if the first layer passive device 610 in Figure 7A is not a standalone die but part of the bottom wafer, a wafer dicing process can be performed, as shown in Figure 7F, which includes mounting the bottom wafer onto a dicing tape 720 and then cutting the bottom wafer based on a dicing saw or dicing laser 730 to separate structures 700F and 700F'. Each of structures 700F and 700F' may correspond to structure 700E.

[0077]

[0088] As shown in Figure 7G, structure 700G can be formed based on structure 700E or semiconductor device 600 by forming bump structures 742, 744, 746, and 748 on electrical terminal structures 662, 664, 666, and 668. In some embodiments, the bump structures 742, 744, 746, and 748 may be copper pillar bumps, solder bumps, or solder balls. In some embodiments, structure 700G may be an optional variation of structure 700E. In some embodiments, if the resulting semiconductor device is used inside a substrate core region, larger copper pads (e.g., electrical terminal structures 662, 664, 666, and 668) may be used for routing and connecting the substrate, and bump structures 742, 744, 746, and 748 as shown in Figure 7G may not be necessary.

[0078]

[0089] Figure 8 shows a method 800 for manufacturing semiconductor devices (such as semiconductor devices 400 and 600) according to an aspect of the present disclosure.

[0079]

[0090] In operation 810, a first layer passive device (e.g., first layer passive device 410 or 610) is provided. In some embodiments, the first layer passive device may include a substrate portion (e.g., substrate portion 412 or 612), a passive device portion (e.g., passive device portion 414 or 614), and a metallization portion (e.g., metallization portion 416 or 616), arranged in a stacked configuration. In some embodiments, the passive device portion may be disposed between the substrate portion and the metallization portion.

[0080]

[0091] In operation 820, one or more second-layer passive devices (e.g., second-layer passive devices 430a / 430b or 630a / 630b) may be stacked on top of a first-layer passive device (e.g., first-layer passive device 410 or 610) to form a semiconductor device (e.g., semiconductor device 400 or 600). In some embodiments, each of the one or more second-layer passive devices may include a substrate portion (e.g., substrate portions 432a / 432b or 632a / 632b), a passive device portion (e.g., passive device portion 434a / 434b or 634a / 634b), and a metallization portion (e.g., passive device portion 436a / 436b or 636a / 636b) arranged in a stacked configuration, wherein the passive device portion may be disposed between the substrate portion and the metallization portion.

[0081]

[0092] In operation 830, a passive component may be formed, the passive component including a metallization portion of a first layer passive device, one or more sets of TSVs of one or more second layer passive devices, and a passive component of a first layer passive device electrically coupled to one or more passive component portions of one or more second layer passive devices through one or more metallization portions of one or more second layer passive devices.

[0082]

[0093] In some embodiments, operation 820 may include mounting a first second layer passive device (e.g., second layer passive device 430a or 630a) of one or more second layer passive devices onto the upper surface of a first layer passive device (e.g., first layer passive device 410 or 610). In some embodiments, the first layer passive device may further include a first conductive structure disposed on the upper surface of the first layer passive device, the first second layer passive device may include a second conductive structure, and the first conductive structure may be bonded to the second conductive structure.

[0083]

[0094] In some embodiments, operation 820 may include performing a fusion bond or hybrid bond to connect the first conductive structure to the second conductive structure. In some embodiments, operation 820 may include forming a soldered structure that connects the first conductive structure to the second conductive structure.

[0084]

[0095] In some embodiments, operation 820 may include making a portion of the substrate of the first second layer passive device concave, and the substrate portion of the first second layer passive device may be disposed on top of the passive device portion of the first second layer passive device. In some embodiments, operation 820 may include forming a third conductive structure disposed on the upper surface of the first second layer passive device and connected to a set of TSVs of the first second layer passive device.

[0085]

[0096] In some embodiments, Method 800 may further include forming electrically coupled ESD protection circuits (e.g., ESD protection circuits 424 / 426 or 624 / 626) in the substrate portion of the first layer passive device, or in the passive device portion of the first layer passive device. In some embodiments, Method 800 may further include forming at least two electrical terminal structures (e.g., electrical terminal structures 462, 464, 466, and 468, or 662, 664, 666, and 668) on the upper surface of the uppermost second layer passive device (e.g., second layer passive device 430b or 630b) of one or more second layer passive devices, wherein at least two electrical terminal structures may be configured as electrical terminals of the passive components.

[0086]

[0097] In some embodiments, method 800 may further include arranging a molding material on a first layer passive device to form a sealing structure, surrounding one or more second layer passive devices.

[0087]

[0098] In some embodiments, Method 800 may further include forming a passive device portion of a first layer passive device and one or more passive device portions of one or more second layer passive devices, including a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof.

[0088]

[0099] The technical advantage of Method 800 is that, with respect to the formation of a semiconductor device having multiple stacked passive devices, the thickness of the semiconductor device may be adjustable to match the thickness of the core for a particular packaging task. The first layer passive device of the semiconductor device may further include an ESD protection circuit. Also, based on the combined effect of the stacked passive devices, the electrical properties of the resulting passive component may be improved or enhanced. For example, a capacitor resulting from a semiconductor device formed based on multiple stacked passive devices as described above may have a capacitance based on the combined capacitances of all the capacitive structures of the stacked passive devices, and the resulting capacitor may have an increased capacitance value compared to a semiconductor device formed based on a single passive device and occupying the same footprint.

[0089]

[0100] Figure 9 shows a side view of a package 900 according to an aspect of the present disclosure, including a surface mount substrate 902, an integrated device 903, and an integrated passive device 905 (for example, having a packaging substrate and an embedded semiconductor device). The package 900 may be coupled to a printed circuit board (PCB) 906 via a plurality of solder interconnects 910. The PCB 906 may include at least one board dielectric layer 960 and a plurality of board interconnects 962.

[0090]

[0101] The surface mount substrate 902 includes at least one dielectric layer 920 (e.g., a substrate dielectric layer), a plurality of interconnection parts 922 (e.g., substrate interconnection parts), a solder resist layer 940, and a solder resist layer 942. The integrated device 903 may be coupled to the surface mount substrate 902 via a plurality of solder interconnection parts 930. The integrated device 903 may be coupled to the surface mount substrate 902 via a plurality of pillar interconnection parts 932 and a plurality of solder interconnection parts 930. The integrated passive device 905 may be coupled to the surface mount substrate 902 via a plurality of solder interconnection parts 950. The integrated passive device 905 may be coupled to the surface mount substrate 902 via a plurality of pillar interconnection parts 952 and a plurality of solder interconnection parts 950.

[0091]

[0102] The package (e.g., 900) may be implemented within a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 900) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 900) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 900) may be configured to send and receive signals with different frequencies and / or different communication protocols.

[0092]

[0103] Figure 10 shows an exemplary method 1000 for providing or manufacturing a package including an integrated device having an embedded semiconductor device, according to an aspect of the present disclosure. In some implementations, the method 1000 of Figure 10 may be used to provide or manufacture the package 900 of Figure 9 as described in the present disclosure. However, the method 1000 may be used to provide or manufacture any of the packages described in the present disclosure.

[0093]

[0104] It should be noted that the method in Figure 10 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package containing an integrated device with an integrated passive device. In some implementations, the order of the processes may be changed or modified.

[0094]

[0105] This method involves preparing a substrate (e.g., 902) (in 1005). The substrate 902 may be provided by a supplier or manufactured by the supplier. The substrate 902 includes at least one dielectric layer 920 and a plurality of interconnection sections 922. The substrate 902 may include an embedded trace substrate (ETS). In some mounting configurations, at least one dielectric layer 920 may include a prepreg layer.

[0095]

[0106] The method involves bonding at least one integrated device (e.g., 903) to a first surface of a substrate (e.g., 902) (in 1010). For example, the integrated device 903 may be bonded to the substrate 902 via a plurality of pillar interconnects 932 and a plurality of solder interconnects 930. The plurality of pillar interconnects 932 may be optional. The plurality of solder interconnects 930 are bonded to a plurality of interconnects 922. A solder reflow process may be used to bond the integrated device 903 to the plurality of interconnects via the plurality of solder interconnects 930.

[0096]

[0107] The method also involves bonding at least one integrated passive device (e.g., 905) to a first surface of a substrate (e.g., 902) (in 1010). For example, the integrated passive device 905 may be bonded to the substrate 902 via a plurality of pillar interconnects 952 and a plurality of solder interconnects 950. The plurality of pillar interconnects 952 may be optional. The plurality of solder interconnects 950 are bonded to a plurality of interconnects 922. A solder reflow process may be used to bond the integrated passive device 905 to the plurality of interconnects via the plurality of solder interconnects 950.

[0097]

[0108] The method involves bonding a plurality of solder interconnects (e.g., 910) (in 1015) to a second surface of a substrate (e.g., 902). A solder reflow process may be used to bond the plurality of solder interconnects 910 to the substrate.

[0098]

[0109] Figure 11 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, dies, interposer packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a fixed-location terminal device 1106, a wearable device 1108, or an automated vehicle 1110 may include a device 1100 as described herein. Device 1100 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1102, 1104, 1106, and 1108, and the vehicle 1110 shown in Figure 11 are merely examples. Device 1100 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) compatible devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0099]

[0110] In the detailed explanation above, it will be seen that in the examples, different features are grouped together. This form of disclosure should not be understood as an intention that the exemplary clauses have more features than are explicitly stated within each clause. Rather, the various aspects of this disclosure may contain fewer features than all the features of the individual exemplary clauses disclosed. Accordingly, the following clauses should be considered incorporated into the explanation, and each clause may be valid on its own as a separate example. Each dependent clause may refer within itself to a specific combination with one of the other clauses, but the aspects (singular or plural) of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of aspects (singular or plural) of dependent clauses with the subject matter of any other dependent or independent clause, or any combination of features with other dependent and independent clauses. The various aspects disclosed herein explicitly include certain combinations (e.g., contradictory aspects such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if a clause is not directly subordinate to an independent clause, it is intended that the nature of the clause may be included in any other independent clause.

[0100]

[0111] Examples of implementation forms are described in the following numbered clauses.

[0101]

[0112] Clause 1. A semiconductor device comprising a first layer passive device including a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion; and one or more second layer passive devices disposed on the first layer passive device, wherein each of the one or more second layer passive devices comprises a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion; A semiconductor device comprising: one or more second-layer passive devices, each including a metallization portion and a set of through-substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to the corresponding metallization portion; and a passive component, each including a metallization portion of a first-layer passive device, one or more sets of TSVs of one or more second-layer passive devices, and a passive device portion of a first-layer passive device electrically coupled to one or more passive device portions of one or more second-layer passive devices through one or more metallization portions of one or more second-layer passive devices.

[0102]

[0113] Clause 2. The semiconductor device according to Clause 1, further comprising an electrostatic discharge (ESD) protection circuit disposed within the substrate portion of the first layer passive device and electrically coupled to the passive device portion of the first layer passive device.

[0103]

[0114] Clause 3. The semiconductor device according to Clause 1 or 2, wherein the thickness of the substrate portion of the first layer passive device is greater than the thickness of the substrate portions of one or more second layer passive devices.

[0104]

[0115] Clause 4. A semiconductor device as described in any of Clauses 1 to 3, wherein the thickness of the semiconductor device is in the range of 1.2 mm to 1.8 mm.

[0105]

[0116] A semiconductor device according to any one of Clauses 5.5, further comprising at least two electrical terminal structures disposed on the upper surface of the uppermost second layer passive device among one or more second layer passive devices, wherein at least two of the electrical terminal structures are configured as electrical terminals of passive components.

[0106]

[0117] Clause 6. A semiconductor device according to any one of Clauses 1 to 5, wherein the passive device portion of the first layer passive device is disposed on the substrate portion of the first layer passive device, the first layer passive device further comprises a first conductive structure disposed on the upper surface of the first layer passive device, one or more second layer passive devices include a first second layer passive device, the first second layer passive device includes a second conductive structure, and the first conductive structure is bonded to the second conductive structure.

[0107]

[0118] Clause 7. The semiconductor device according to Clause 6, wherein the first conductive structure is connected to the second conductive structure based on a fusion bond or hybrid bond.

[0108]

[0119] The semiconductor device according to Clause 6, further comprising: Clause 8. A first soldering structure connecting a first conductive structure to a second conductive structure.

[0109]

[0120] Clause 9. A semiconductor device according to any one of Clauses 6 to 8, wherein the passive device portion of the first second layer passive device is disposed on the substrate portion of the first second layer passive device, and the second conductive structure is disposed on the underside of the first second layer passive device and connected to a set of TSVs of the first second layer passive device.

[0110]

[0121] Clause 10. A semiconductor device according to any one of Clauses 6 to 8, wherein the substrate portion of the first second layer passive device is disposed on the passive device portion of the first second layer passive device, and the second conductive structure is disposed on the underside of the first second layer passive device and adjacent to the metallization portion of the first second layer passive device.

[0111]

[0122] Clause 11. A semiconductor device according to any one of Clauses 1 to 10, further comprising a sealing structure based on a molding material on a first layer passive device and surrounding one or more second layer passive devices.

[0112]

[0123] Clause 12. A semiconductor device according to any one of Clauses 1 to 11, wherein the passive device portion of the first layer passive device and one or more passive device portions of one or more second layer passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof.

[0113]

[0124] Clause 13. A method for manufacturing a semiconductor device, comprising providing a first layer passive device, wherein the first layer passive device includes a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, the passive device portion being located between the substrate portion and the metallization portion; and stacking one or more second layer passive devices on the first layer passive device to form a semiconductor device, wherein each of the one or more second layer passive devices includes a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, the passive device portion being located between the substrate portion and the metallization portion. A method comprising: distributing between a substrate portion, a passive device portion, and a metallization portion, and a set of through-substrate vias (TSVs) passing through the corresponding substrate portion and electrically coupled to the corresponding metallization portion; and forming a passive component comprising a metallization portion of a first-layer passive device, one or more sets of TSVs of one or more second-layer passive devices, and a passive device portion of a first-layer passive device electrically coupled to one or more passive device portions of one or more second-layer passive devices through one or more metallization portions of one or more second-layer passive devices.

[0114]

[0125] The method according to Clause 14, further comprising forming an electrostatic discharge (ESD) protection circuit in the substrate portion of the first layer passive device that is electrically coupled to the passive device portion of the first layer passive device.

[0115]

[0126] The method according to Clause 15. The method according to Clause 13 or 14, further comprising forming at least two electrical terminal structures on the uppermost second layer passive device of one or more second layer passive devices, wherein at least two electrical terminal structures are configured as electrical terminals of the passive component.

[0116]

[0127] Clause 16. The method according to any one of Clauses 13 to 15, wherein stacking one or more second-layer passive devices on a first-layer passive device includes mounting a first second-layer passive device among one or more second-layer passive devices onto the upper surface of the first-layer passive device, the first-layer passive device further comprising a first conductive structure disposed on the upper surface of the first-layer passive device, the first second-layer passive device comprising a second conductive structure, the first conductive structure being bonded to the second conductive structure.

[0117]

[0128] The method according to Clause 17, wherein mounting a first second-layer passive device of one or more second-layer passive devices onto the top surface of a first-layer passive device includes performing fusion bonding or hybrid bonding to connect a first conductive structure to a second conductive structure.

[0118]

[0129] The method according to Clause 16, wherein mounting a first second-layer passive device among one or more second-layer passive devices onto the top surface of a first-layer passive device forms a first soldering structure connecting a first conductive structure to a second conductive structure.

[0119]

[0130] Clause 19. The method according to any one of Clauses 16 to 18, further comprising making a portion of the substrate of a first second layer passive device concave so that the substrate portion of the first second layer passive device is disposed on the passive device portion of the first second layer passive device, and forming a third conductive structure disposed on the upper surface of the first second layer passive device and connected to a set of TSVs of the first second layer passive device.

[0120]

[0131] Clause 20. The method according to any one of Clauses 13 to 19, further comprising arranging a molding material on a first layer passive device to form a sealing structure, surrounding one or more second layer passive devices.

[0121]

[0132] The method according to any one of the terms in Clause 21, further comprising forming a passive device portion of a first layer passive device and one or more passive device portions of one or more second layer passive devices, comprising a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof.

[0122]

[0133] Clause 22. An electronic device comprising an integrated circuit device including a semiconductor device, wherein the semiconductor device is a first-layer passive device comprising a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, the passive device portion being disposed between the substrate portion and the metallization portion, and one or more second-layer passive devices disposed on the first-layer passive device, where each of the one or more second-layer passive devices comprises a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, the passive device portion being disposed between the substrate portion and the metallization portion. An electronic device comprising: one or more second-layer passive devices, each including a substrate portion, a passive device portion, and a metallization portion, and a set of through-substrate vias (TSVs) passing through the corresponding substrate portion and electrically coupled to the corresponding metallization portion; and a passive component, each including a metallization portion of a first-layer passive device, one or more sets of TSVs of one or more second-layer passive devices, and a passive device portion of a first-layer passive device electrically coupled to one or more passive device portions of one or more second-layer passive devices through one or more metallization portions of one or more second-layer passive devices.

[0123]

[0134] Clause 23. The electronic device according to Clause 22, further comprising an electrostatic discharge (ESD) protection circuit disposed within the substrate portion of the first layer passive device and electrically coupled to the passive device portion of the first layer passive device.

[0124]

[0135] Clause 24. An electronic device according to Clause 22 or 23, wherein the thickness of the substrate portion of the first layer passive device is greater than the thickness of the substrate portions of one or more second layer passive devices.

[0125]

[0136] Clause 25. An electronic device as described in any of Clauses 22 to 24, wherein the thickness of the semiconductor device is in the range of 1.2 mm to 1.8 mm.

[0126]

[0137] Clause 26. An electronic device according to any one of Clauses 22 to 25, further comprising at least two electrical terminal structures disposed on the upper surface of the uppermost second layer passive device among one or more second layer passive devices, wherein at least two of the electrical terminal structures are configured as electrical terminals of passive components.

[0127]

[0138] Clause 27. An electronic device according to any one of Clauses 22 to 26, wherein the passive device portion of the first layer passive device is disposed on the substrate portion of the first layer passive device, the first layer passive device further comprises a first conductive structure disposed on the upper surface of the first layer passive device, one or more second layer passive devices include a first second layer passive device, the first second layer passive device includes a second conductive structure, and the first conductive structure is bonded to the second conductive structure.

[0128]

[0139] Clause 28. The electronic device according to Clause 27, wherein the first conductive structure is connected to the second conductive structure based on fusion bonding or hybrid bonding.

[0129]

[0140] Clause 29. The electronic device according to Clause 27, wherein the semiconductor device further comprises a first soldering structure connecting a first conductive structure to a second conductive structure.

[0130]

[0141] Clause 30. An electronic device according to any one of Clauses 27 to 29, wherein the passive device portion of the first second layer passive device is disposed on the substrate portion of the first second layer passive device, and the second conductive structure is disposed on the underside of the first second layer passive device and connected to a set of TSVs of the first second layer passive device.

[0131]

[0142] Clause 31. An electronic device according to any one of Clauses 27 to 29, wherein the substrate portion of the first second layer passive device is disposed on the passive device portion of the first second layer passive device, and the second conductive structure is disposed on the underside of the first second layer passive device and adjacent to the metallization portion of the first second layer passive device.

[0132]

[0143] Clause 32. An electronic device according to any of Clauses 22 to 31, wherein the semiconductor device further comprises a sealing structure based on a molding material on a first layer passive device and surrounding one or more second layer passive devices.

[0133]

[0144] Clause 33. An electronic device according to any of Clauses 22 to 32, wherein the passive device portion of the first layer passive device and one or more passive device portions of one or more second layer passive devices comprises a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof.

[0134]

[0145] Clause 34. An electronic device is any of the electronic devices described in any of Clauses 22 to 33, including music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, or devices in an automated vehicle.

[0135]

[0146] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0136]

[0147] Furthermore, those skilled in the art will understand that various exemplary logic blocks, modules, circuits, and algorithmic steps described in relation to the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly demonstrate this hardware-software compatibility, various exemplary components, blocks, modules, circuits, and steps have been outlined above in relation to their functions. Whether such functions are implemented as hardware or executed as software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways for specific applications, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0137]

[0148] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or run using general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0138]

[0149] The methods, sequences, and / or algorithms described in relation to the embodiments disclosed herein may be embodied in hardware directly, in software modules executed by a processor, or in a combination of the two. The software modules may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside within an ASIC. The ASIC may reside within a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside within the user terminal as separate components.

[0139]

[0150] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. Where implemented in software, the functions may be stored on or transmitted via computer-readable media as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, including any media that facilitate the transfer of computer programs from one location to another. Storage media may be any available media accessible by a computer. Such computer-readable media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other media accessible by a computer that can be used to carry or store desired program code in the form of instructions or data structures. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used herein, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where a disc typically reproduces data magnetically, and a disc optically reproduces data using a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0140]

[0151] While the above disclosures illustrate exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made to this Specified without departing from the scope of the Disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, no component, function, action, or instruction described herein or in the claims should be construed as important or essential unless explicitly stated so. In addition, terms such as “set,” “group,” etc., as used herein are intended to include one or more of the elements described. Also, as used herein, terms such as “has,” “have,” and “having” are open-ended terms that do not limit the elements they modify (for example, an element that “has” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise specified. Furthermore, the term "or" as used herein, when used in a series, is intended to be inclusive and may be used interchangeably with "and / or" unless otherwise specified (for example, when used in combination with "either" or "only one of") or when the choices are not mutually exclusive (for example, "one or more" should not be interpreted as "one and more"). Moreover, components, functions, actions, and instructions may be described or claimed in the singular, but the plural is intended unless explicitly stated to limit them to the singular. Also, when used herein, the articles "a," "an," "the," and "said" are intended to include one or more items and may be used interchangeably with "at least one," "one or more," etc.In addition, the terms “at least one” and “one or more” as used herein include “one” component, function, action, or instruction as described or claimed, and further include “two or more” components, functions, actions, or instructions as described or claimed.

Claims

1. It is a semiconductor device, A first-layer passive device comprising a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, One or more second-layer passive devices disposed on the first-layer passive device, wherein each of the one or more second-layer passive devices is A substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, and the substrate portion, passive device portion, and metallization portion, A set of through-substrate vias (TSVs) that pass through the corresponding substrate portion and are electrically coupled to the corresponding metallization portion, One or more second-tier passive devices, A passive component comprising the metallization portion of the first layer passive device, one or more sets of TSVs of the one or more second layer passive devices, and the passive device portion of the first layer passive device electrically coupled to one or more passive device portions of the one or more second layer passive devices through one or more metallization portions of the one or more second layer passive devices, A semiconductor device equipped with the following features.

2. The first layer passive device, An electrostatic discharge (ESD) protection circuit is disposed within the substrate portion of the first layer passive device and electrically coupled to the passive device portion of the first layer passive device. The semiconductor device according to claim 1, further comprising the above.

3. The semiconductor device according to claim 1, wherein the thickness of the substrate portion of the first layer passive device is greater than the thickness of the substrate portion of the one or more second layer passive devices.

4. The semiconductor device according to claim 1, wherein the thickness of the semiconductor device is in the range of 1.2 mm to 1.8 mm.

5. At least two electrical terminal structures disposed on the upper surface of the uppermost second-layer passive device among the one or more second-layer passive devices, wherein the at least two electrical terminal structures are configured as electrical terminals of the passive component, The semiconductor device according to claim 1, further comprising the above.

6. The passive device portion of the first layer passive device is disposed on the substrate portion of the first layer passive device, The first layer passive device further comprises a first conductive structure disposed on the upper surface of the first layer passive device, The one or more second layer passive devices include a first second layer passive device. The first second layer passive device includes a second conductive structure, The first conductive structure is bonded to the second conductive structure. The semiconductor device according to claim 1.

7. The first conductive structure is connected to the second conductive structure based on fusion bonding or hybrid bonding. The semiconductor device according to claim 6.

8. A first soldering structure for connecting the first conductive structure to the second conductive structure, The semiconductor device according to claim 6, further comprising the above.

9. The passive device portion of the first second layer passive device is disposed on the substrate portion of the first second layer passive device, The second conductive structure is disposed on the lower surface of the first second layer passive device and is connected to the set of TSVs of the first second layer passive device. The semiconductor device according to claim 6.

10. The substrate portion of the first second layer passive device is disposed on the passive device portion of the first second layer passive device, The second conductive structure is disposed on the lower surface of the first second layer passive device, and is adjacent to the metallization portion of the first second layer passive device, The semiconductor device according to claim 6.

11. A sealing structure based on the molding material on the first layer passive device and surrounding one or more second layer passive devices. The semiconductor device according to claim 1, further comprising the above.

12. The passive device portion of the first layer passive device and the one or more passive device portions of the one or more second layer passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof. The semiconductor device according to claim 1.

13. A method for manufacturing semiconductor devices, The invention provides a first layer passive device, wherein the first layer passive device includes a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, and the passive device portion is located between the substrate portion and the metallization portion. To form the semiconductor device, one or more second layer passive devices are stacked on the first layer passive device, wherein each of the one or more second layer passive devices is A substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, and the substrate portion, passive device portion, and metallization portion, A set of through-substrate vias (TSVs) that pass through the corresponding substrate portion and are electrically coupled to the corresponding metallization portion, This includes, A passive component is formed, which includes the metallization portion of the first layer passive device, one or more sets of TSVs of the one or more second layer passive devices, and the passive device portion of the first layer passive device that is electrically coupled to one or more passive device portions of the one or more second layer passive devices through the metallization portion of the one or more second layer passive devices, Methods that include...

14. A static discharge (ESD) protection circuit is formed in the substrate portion of the first layer passive device, electrically coupled to the passive device portion of the first layer passive device. The method according to claim 13, further comprising:

15. The method involves forming at least two electrical terminal structures on the upper surface of the uppermost second-layer passive device among the one or more second-layer passive devices, wherein the at least two electrical terminal structures are configured as electrical terminals of the passive component. The method according to claim 13, further comprising:

16. The above-mentioned stacking of one or more second-layer passive devices on the first-layer passive device is This includes attaching the first second layer passive device among the one or more second layer passive devices to the upper surface of the first layer passive device, The first layer passive device further comprises a first conductive structure disposed on the upper surface of the first layer passive device, The first second layer passive device includes a second conductive structure, The first conductive structure is bonded to the second conductive structure. The method according to claim 13.

17. The first of the one or more second-layer passive devices is attached to the upper surface of the first-layer passive device. The method includes performing fusion bonding or hybrid bonding to connect the first conductive structure to the second conductive structure. The method according to claim 16.

18. The first of the one or more second-layer passive devices is attached to the upper surface of the first-layer passive device. This includes forming a first soldering structure that connects the first conductive structure to the second conductive structure. The method according to claim 16.

19. The method involves making a portion of the substrate of the first second layer passive device concave, such that the substrate portion of the first second layer passive device is disposed on the passive device portion of the first second layer passive device. A third conductive structure is formed, which is disposed on the upper surface of the first second layer passive device and connected to the set of TSVs of the first second layer passive device. The method according to claim 16, further comprising:

20. To form a sealing structure, a molding material is placed on the first layer passive device and surrounds the one or more second layer passive devices. The method according to claim 13, further comprising:

21. To form the passive device portion of the first layer passive device and the one or more passive device portions of the one or more second layer passive devices, comprising a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof. The method according to claim 13, further comprising:

22. It is an electronic device, The integrated circuit device includes a semiconductor device, and the semiconductor device is A first-layer passive device comprising a substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, One or more second-layer passive devices disposed on the first-layer passive device, wherein each of the one or more second-layer passive devices is A substrate portion, a passive device portion, and a metallization portion arranged in a stacked configuration, wherein the passive device portion is disposed between the substrate portion and the metallization portion, and the substrate portion, passive device portion, and metallization portion, A set of through-substrate vias (TSVs) that pass through the corresponding substrate portion and are electrically coupled to the corresponding metallization portion, One or more second-tier passive devices, A passive component comprising the metallization portion of the first layer passive device, one or more sets of TSVs of the one or more second layer passive devices, and the passive device portion of the first layer passive device electrically coupled to one or more passive device portions of the one or more second layer passive devices through one or more metallization portions of the one or more second layer passive devices, An electronic device equipped with the following features.

23. The first layer passive device, An electrostatic discharge (ESD) protection circuit is disposed within the substrate portion of the first layer passive device and electrically coupled to the passive device portion of the first layer passive device. The electronic device according to claim 22, further comprising the above.

24. The electronic device according to claim 22, wherein the thickness of the substrate portion of the first layer passive device is greater than the thickness of the substrate portion of the one or more second layer passive devices.

25. The electronic device according to claim 22, wherein the thickness of the semiconductor device is in the range of 1.2 mm to 1.8 mm.

26. An electrical terminal structure comprising at least two electrical terminal structures disposed on the upper surface of the uppermost second-layer passive device among the one or more second-layer passive devices, wherein the at least two electrical terminal structures are configured as electrical terminals of the passive component, The electronic device according to claim 22, further comprising the above.

27. The passive device portion of the first layer passive device is disposed on the substrate portion of the first layer passive device, The first layer passive device further comprises a first conductive structure disposed on the upper surface of the first layer passive device, The one or more second layer passive devices include a first second layer passive device. The first second layer passive device includes a second conductive structure, The first conductive structure is bonded to the second conductive structure. The electronic device according to claim 22.

28. The first conductive structure is connected to the second conductive structure based on fusion bonding or hybrid bonding. The electronic device according to claim 27.

29. The aforementioned semiconductor device A first soldering structure for connecting the first conductive structure to the second conductive structure, The electronic device according to claim 27, further comprising the above.

30. The passive device portion of the first second layer passive device is disposed on the substrate portion of the first second layer passive device, The second conductive structure is disposed on the lower surface of the first second layer passive device and is connected to the set of TSVs of the first second layer passive device. The electronic device according to claim 27.

31. The substrate portion of the first second layer passive device is disposed on the passive device portion of the first second layer passive device, The second conductive structure is disposed on the lower surface of the first second layer passive device, and is adjacent to the metallization portion of the first second layer passive device, The electronic device according to claim 27.

32. The aforementioned semiconductor device A sealing structure based on the molding material on the first layer passive device and surrounding one or more second layer passive devices. The electronic device according to claim 22, further comprising the above.

33. The passive device portion of the first layer passive device and the one or more passive device portions of the one or more second layer passive devices comprise a deep trench capacitor, an integrated stack capacitor, a metal-insulator-metal capacitor, a metal-oxide-metal capacitor, or a combination thereof. The electronic device according to claim 22.

34. The electronic device according to claim 22, wherein the electronic device includes a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in an automated vehicle.

Images