Arrayed optoelectronic tweezers chip and method of manufacturing the same

Abstract

The application discloses an array type photoelectric tweezers chip and a manufacturing method thereof, and belongs to the technical field of micro-nano manipulation and semiconductor devices. The chip comprises a substrate layer, a transistor array structure, a liquid phase manipulation cavity and an upper plate structure. The transistor array structure comprises a plurality of NPN type or PNP type photoelectric transistors arranged in a horizontal array, and a deep trench isolation structure extending longitudinally into the substrate layer is arranged between adjacent units. The light receiving surface of each photoelectric transistor unit faces the liquid phase manipulation cavity, and is not covered by an upper light shielding metal layer. The virtual electrode working mode is adopted, a localized dielectrophoresis electric field is generated through light irradiation, and the accurate capture and manipulation of micro-nano particles in the liquid phase cavity are realized. The application solves the problems of low integration of a traditional optical tweezers chip, obstruction of light transmission caused by a metal light shielding layer and the like, has the advantages of compact structure, sensitive response, programmable array and the like, and can be widely applied to the fields of biological cell manipulation, nano material assembly and micro-fluidic analysis.

Description

Technical Field

[0001] This application relates to the field of semiconductor optoelectronic device technology, specifically to an array-type optoelectronic tweezers chip and its manufacturing method. Background Technology

[0002] Optoelectronic tweezers (OET) are a technology that uses the principle of photoinduced dielectric electrophoresis to achieve non-contact precision manipulation of micro and nano particles, cells and biomolecules. They have been widely used in biomedical fields such as single-cell sorting, cell fusion and nanoparticle manipulation.

[0003] However, existing photoelectric tweezers under-electrode technology has the following common problems: Schemes based on photoconductive thin films: These employ photoconductive thin films such as hydrogenated amorphous silicon (a-Si:H), which lack a carrier amplification mechanism, resulting in an equivalent photocurrent gain of less than 1 and low photoelectric conversion efficiency. In commonly used biomedical working media, the maximum photoconductivity under illumination is far lower than the dielectric conductivity, and the virtual electrode effect is severely degraded due to bypass effects, leading to a significant decrease or even failure of the actual controllability of the device in physiologically conductive solutions. Furthermore, continuous uniform thin films lack physical isolation between pixels, allowing photogenerated carriers to diffuse freely laterally, with the minimum pixel size typically not less than 50 μm, which cannot meet the fine manipulation requirements of nanoparticles and subcellular structures.

[0004] The solution based on phototransistor arrays: The front side of the chip retains the metal electrode lead structure, which limits the utilization of the light-receiving area; The array usually only contains single-polarity (all NPN or all PNP) transistors, and does not involve monolithic integration of transistors of different polarities on the same chip; Under the condition of ultra-small pixel size (≤10μm), the physical and electrical isolation between pixels is not perfect, and the deep trench isolation process solution is lacking.

[0005] Therefore, there is an urgent need to develop an optoelectronic tweezers chip that can balance high photocurrent gain, physiological conductivity, environmental stability, and submicron-level manipulation precision. Summary of the Invention

[0006] To address the problems existing in the prior art regarding the low photoelectric conversion efficiency of photoelectric tweezers chips, the decrease or even failure of maneuverability in physiologically conductive solutions, the limitation of minimum pixel size, the limitation of light-receiving area utilization by metal electrode leads in phototransistor array schemes, and the imperfect physical and electrical isolation between pixels under ultra-small pixel size conditions, this invention provides an array-type photoelectric tweezers chip, including a substrate layer, a transistor array structure, a liquid phase maneuvering cavity, and an upper electrode structure. The substrate layer serves as a supporting base for the bottom electrode and a common conductive path. The transistor array structure is disposed above the substrate and includes multiple phototransistor units arranged in a horizontal array. The phototransistor units are NPN or PNP type structures. A deep trench isolation structure is disposed between adjacent phototransistor units, and the deep trench isolation structure extends longitudinally into the interior of the substrate to achieve electrical decoupling between adjacent units. The light-receiving surface of the phototransistor unit faces the liquid phase manipulation cavity and is not covered by a light-shielding metal layer. The liquid phase manipulation cavity is formed between the transistor array structure and the upper electrode structure, and is used to hold the micro-nano particle suspension to be manipulated. The upper electrode structure is located above the liquid phase manipulation cavity, providing a uniform bias electric field.

[0007] In a preferred embodiment, the substrate is an N+ type silicon substrate, and a Ti / Au composite metal layer is disposed on its back side as a common collector lead-out terminal.

[0008] In a preferred embodiment, the phototransistor unit is provided with an emitter, a base, and a collector from top to bottom; the emitter and collector of the PNP type unit are P+ doped regions, and the base is an N doped region; the emitter and collector of the NPN type unit are N+ doped regions, and the base is a P doped region.

[0009] In a preferred embodiment, the doping concentration of the emitter is 1 × 10⁻⁶. 19 ~5×10 19 cm -3 The implantation depth is 0.1–0.5 μm; the doping concentration of the base is 1 × 10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 1–3 μm; the doping concentration of the collector is 1 × 10⁻⁶. 14 ~5×10 19 cm -3 .

[0010] In a preferred embodiment, the deep trench isolation structure is filled with at least one insulating dielectric material selected from SiO2, Si3N4 or polyimide (PI); the depth of the deep trench is greater than the depth of the deepest doped region of the phototransistor unit, thereby achieving full dielectric physical isolation.

[0011] In a preferred embodiment, the multiple phototransistor units can be arranged in any of the following ways: cross array, striped array, or asymmetrical arrangement.

[0012] In a preferred embodiment, the width of the deep trench isolation structure is 1 to 2 μm, and the depth-to-width ratio is 10:1 to 20:1; the lateral dimension of the phototransistor unit is not less than 3 μm.

[0013] In a preferred embodiment, the upper electrode structure includes a transparent substrate and a transparent conductive layer (ITO) on its inner surface, which is enclosed by an insulating pad and a transistor array structure to form a liquid phase manipulation cavity with a height of 10 to 200 μm.

[0014] On the other hand, the present invention provides a method for manufacturing an array-type optoelectronic tweezers chip, comprising the following steps: S1. Substrate preparation: Provide an N+ type silicon substrate layer and grow a silicon epitaxial layer on its surface; S2. Preparation of deep trench isolation region: An isolation trench is formed by etching process, which runs through the entire epitaxial layer and extends to the substrate layer, and then filled with insulating medium; S3. Transistor Array Fabrication: Ion implantation is used to form corresponding base and emitter regions within the isolated epitaxial region. When NPN and PNP mixed arrangements are involved, different types of impurity ions are implanted in separate steps. The implantation energy of the ion implantation process is 10–200 keV, and the dose is 1 × 10⁻⁶. 13 ~1×10 16 cm -2 ; S4. Post-processing: Deposit the back electrode and surface passivation protective layer, and complete the bonding assembly with the upper electrode plate; the post-processing also includes annealing treatment, the annealing treatment temperature is 800~1200℃, and the time is 10 seconds~2 hours.

[0015] Compared with the prior art, the technical solution disclosed in this invention has the following beneficial effects: 1. Pixel-level electrical isolation to eliminate crosstalk: The deep trench isolation structure extends vertically into the substrate layer, with a depth greater than the deepest doped region of the phototransistor unit, achieving full dielectric physical isolation between adjacent pixels and completely eliminating electrical crosstalk between pixels. Compared to planar OET devices without deep trench isolation, pixel isolation is improved by more than two orders of magnitude, enabling single-particle manipulation with micron-level precision.

[0016] 2. High photoresponse sensitivity with no light-shielding metal layer: Each phototransistor unit faces the liquid-phase manipulation cavity with no light-shielding metal layer covering it, employing a virtual electrode operation mode. This structural design allows incident light to directly illuminate the base region of the phototransistor, maximizing the generation efficiency of photogenerated carriers. Compared to traditional photoelectric tweezers devices with metal interconnect layers, the photoresponse sensitivity is significantly improved, enabling dielectrophoretic manipulation at lower light power and reducing the risk of photodamage to biological samples such as cells.

[0017] 3. Bipolar Dielectrophoresis Manipulation, Flexible Functionality: By integrating NPN and PNP phototransistor units on the same chip, positive dielectrophoresis (pDEP) and negative dielectrophoresis (nDEP) force fields can be generated respectively. Utilizing various array arrangements such as cross arrays, stripe arrays, or asymmetric proportions, pDEP / nDEP functional partitions can be formed on the same chip, enabling the simultaneous capture and sorting of different types of micro and nanoparticles, providing hardware support for complex manipulation tasks such as cell phenotype screening and nanomaterial classification.

[0018] 4. Compact structure and easy on-chip integration: The chip is manufactured using standard silicon-based semiconductor technology, which is compatible with CMOS technology. It is easy to integrate with microfluidic systems and signal processing circuits to realize a complete on-chip opto-tweezers (OET-on-chip) system, which greatly reduces the system size and cost and has good industrialization prospects. Attached Figure Description

[0019] Exemplary embodiments of the present invention can be more fully understood by referring to the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain the present invention and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0020] Figure 1 A cross-sectional schematic diagram of an NPN / PNP longitudinal phototransistor array structure provided by the present invention; Figure 2 A cross-sectional schematic diagram of a partial structure of an NPN / PNP longitudinal phototransistor array provided by the present invention; Figure 3 This is a top view of the transistor array structure in Embodiment 1 of the present invention (cross array arrangement). Figure 4 This is a top view schematic diagram of the stripe array arrangement in Embodiment 2 of the present invention; Figure 5 This is a top view of the asymmetrical proportional arrangement in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the process flow for the array-type optoelectronic tweezers chip manufacturing method provided in Embodiment 4 of the present invention. Attached Figure

[0021] 1. Substrate layer; 21. PNP phototransistor unit; 211. PNP emitter; 212. PNP base; 213. PNP collector; 22. NPN phototransistor unit; 221. NPN emitter; 222. NPN base; 223. NPN collector; 3. Liquid phase manipulation chamber; 4. Upper electrode structure; 5. Back metal layer; 6. Deep trench isolation structure. Detailed Implementation

[0022] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present application.

[0023] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this application are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them. It should also be understood that in the embodiments of this application, "multiple" can refer to two or more, and "at least one" can refer to one, two, or more. It should also be understood that any component, data, or structure mentioned in the embodiments of this application can generally be understood as one or more unless explicitly limited or given a contrary suggestion in the context. Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this application generally indicates that the related objects before and after are in an "or" relationship. It should also be understood that the descriptions of the various embodiments in this application emphasize the differences between them; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be elaborated upon one by one.

[0024] In the description of this invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "virtual electrode" refers to a region on the chip surface where, when a phototransistor unit is illuminated, the equivalent resistance of the device is significantly reduced due to the generation of photogenerated carriers, resulting in enhanced conductivity. This region functions as if a physical metal electrode were placed at that location, but in reality, there is no metal structure there; hence the term "virtual electrode." The position and shape of the virtual electrode can be programmed in real time using illumination patterns, giving the chip a highly flexible controllability.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "electrical decoupling" refers to the electrical independence between adjacent phototransistor units through a deep trench isolation structure, so that the working state (light / dark state) of one unit does not affect the electrical characteristics of adjacent units, thereby ensuring that each pixel can be independently programmed and controlled.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "positive dielectric electrophoresis (pDEP)" refers to the dielectric effect in which particles are attracted to and move towards regions of high electric field strength, which typically occurs when the polarizability of the particles is greater than that of the surrounding medium.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "negative dielectrophoresis (nDEP)" refers to the dielectrophoretic effect in which particles are repelled and moved toward regions of low electric field strength, which typically occurs when the polarizability of the particles is less than that of the surrounding medium.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the term "asymmetric ratio arrangement" refers to an arrangement in an array chip in which two or more units with different physical properties (such as generating dielectric forces in different directions) are arranged in a non-uniform manner in terms of spatial distribution weight and functional area division.

[0031] Furthermore, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. Techniques, methods, and devices known to those skilled in the art will not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0032] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0033] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Example 1: Cross-array arrangement type of array-type optoelectronic tweezers chip like Figure 1 As shown, this embodiment provides an array-type optoelectronic tweezers chip, which includes, from bottom to top: a substrate layer 1, a transistor array structure (composed of multiple PNP type optoelectronic transistor units 21 and NPN type optoelectronic transistor units 22), a liquid phase manipulation cavity 3, and an upper electrode structure 4; a back metal layer 5 is provided on the back side of the substrate layer 1.

[0035] Substrate 1 is an N+ type silicon substrate with a thickness of 500–700 μm and a resistivity of no more than 0.005 Ω·cm. Substrate 1 has the following dual functions: firstly, it serves as the mechanical support substrate for the entire chip, providing sufficient structural rigidity; secondly, it serves as a common conductive path, with a Ti / Au composite metal layer 5 (Ti layer thickness approximately 20 nm, Au layer thickness approximately 200 nm) disposed on its back side, serving as a common collector lead for applying DC bias voltage to the chip.

[0036] The N+ type heavily doped substrate has extremely low resistivity and can be regarded as a good conductor, ensuring that the collectors of each phototransistor unit form a low-impedance common node, thereby establishing a basis for a uniform electric field distribution between the chip and the liquid phase manipulation cavity.

[0037] like Figure 2 As shown, the transistor array structure is formed in the silicon epitaxial layer above the substrate 1, including multiple PNP type phototransistor units 21 and NPN type phototransistor units 22 arranged in a horizontal array.

[0038] The PNP type phototransistor unit 21 includes, from top to bottom: PNP emitter 211: P+ doped region, doping concentration of 1×10⁻⁶ 19 ~5×10 19 cm -3 The injection depth is approximately 0.3 μm; PNP base 212: N-type doped region, doping concentration of 1×10⁻⁶ 16 ~1×10 18 cm -3 The thickness is about 1 to 3 μm, which is the main region for the generation of photogenerated carriers; PNP collector 213: P+ doped region, doping concentration of 1×10⁻⁶ 14 ~5×10 19 cm -3 .

[0039] The NPN type phototransistor unit 22 includes, from top to bottom: NPN emitter 221: N+ doped region, doping concentration of 1×10⁻⁶ 19 ~5×10 19 cm -3 The injection depth is approximately 0.3 μm; NPN base 222: P-type doped region, doping concentration of 1×10⁻⁶ 16 ~1×10 18 cm -3 The thickness is approximately 1–3 μm; NPN collector 223: N+ doped region, doping concentration of 1×10⁻⁶ 14 ~5×10 19 cm -3 .

[0040] The light-receiving surface (i.e., the upper surface of the emitter) of each phototransistor unit faces the liquid-phase manipulation cavity 3, and there is no light-shielding metal layer covering it. When light of a specific wavelength shines on the base region of the phototransistor, photogenerated electron-hole pairs are generated. Under the action of the built-in electric field, they separate to form a photocurrent, which reduces the internal resistance of the device. This is equivalent to forming a localized "virtual electrode" on the chip surface, thereby generating a non-uniform alternating electric field in the liquid-phase manipulation cavity 3, driving the dielectrophoresis (DEP) force to manipulate the micro-nano particles in the cavity.

[0041] like Figure 3 As shown, in this embodiment, the PNP type phototransistor unit 21 and the NPN type phototransistor unit 22 are arranged in a checkerboard pattern (cross array arrangement), and the polarity of any pixel is opposite to that of all its adjacent pixels. This arrangement can simultaneously form regularly alternating pDEP regions and nDEP regions on the chip surface, which is suitable for the synchronous capture and separation of mixed particle groups.

[0042] Each phototransistor unit has a lateral dimension (pixel size) of 10 μm and a pixel pitch of 1 μm. The corresponding deep trench isolation structure 6 has a width of 1 μm and an aspect ratio of 15:1 (depth approximately 15 μm). The deep trench is filled with SiO2 insulating dielectric to achieve full dielectric physical isolation between adjacent units. The trench depth (15 μm) is greater than the depth of the deepest doped region (approximately 5 μm), ensuring complete electrical decoupling.

[0043] The liquid-phase manipulation cavity 3 is formed by the upper surface of the transistor array structure (covered by a surface passivation protective layer) and the inner surface of the upper electrode structure 4, with a height (cavity spacing) of 50 μm. It is supported and sealed by a SU-8 photoresist insulating gasket with a height of 50 μm. The cavity is filled with a suspension containing the micro- or nano-particles to be manipulated (such as cell suspension, nanoparticle solution, etc.).

[0044] The upper electrode structure 4 includes, from top to bottom: Transparent substrate: 0.5mm thick borosilicate glass with a light transmittance greater than 90% (visible light range); Transparent conductive layer: An ITO (indium tin oxide) thin film sputtered onto the inner surface of a transparent substrate, with a thickness of approximately 100 nm and a sheet resistance of no more than 20 Ω.

[0045] By applying an AC bias voltage of 10kHz to 1MHz (peak-to-peak value 5 to 20V) between the transparent conductive layer (upper electrode structure) and the back metal layer 5 (common collector), a uniform background alternating electric field is established in the liquid phase control cavity 3, which serves as the driving power source for dielectrophoretic control.

[0046] Working principle: When the chip is working, an AC bias voltage is first applied between the upper electrode structure (ITO layer) and the back metal layer. In the absence of light, each phototransistor unit is in the off state, with high internal resistance. The electric field distribution in the liquid phase cavity is uniform, and no obvious DEP force field is generated.

[0047] When a spatial light modulator (SLM) or a digital micromirror device (DMD) projects visible light (wavelength 600–900 nm) of a specific pattern onto the chip surface, photogenerated carriers are generated at the base of the phototransistor unit under illumination. The equivalent device resistance decreases rapidly (the internal resistance can be reduced to less than 1 / 100 of that in the dark state under illumination), forming a "bright virtual electrode" at the corresponding pixel position. This significantly increases the local electric field strength and gradient, generating positive dielectric electrophoresis (pDEP) or negative dielectric electrophoresis (nDEP) forces on micro- and nano-particles in the liquid cavity (depending on the transistor polarity), thus enabling particle capture, movement, or sorting manipulation.

[0048] By dynamically changing the pattern of the projected light, real-time programmable manipulation of single or multiple particles can be achieved without the need for mechanical moving parts.

[0049] Example 2: Striped Array Type Array Optoelectronic Tweezers Chip The main difference between this embodiment and Embodiment 1 lies in the arrangement of the transistor array structure. For example... Figure 4 As shown, this embodiment uses a stripe array arrangement: Phototransistor units of the same polarity are connected along the X direction (first direction) of the chip to form a striped area; NPN type striped areas and PNP type striped areas are arranged alternately along the Y direction (second direction) of the chip, with a stripe width of 20μm (containing 2 columns of pixel units) and a spacing (isolation groove) of 1.5μm; The deep trench isolation structure 6 has a width of 1.5μm and a depth-to-width ratio of 12:1 (depth of approximately 18μm), and is filled with Si3N4 insulating dielectric. The height of the liquid phase manipulation chamber is 100 μm; The pixel's horizontal dimension is 20μm × 20μm.

[0050] The advantage of stripe array arrangement is that it forms a wider pDEP / nDEP functional band along the X direction, which is suitable for application scenarios that require guiding particle flow in a fixed direction (such as particle sorting channels). It can be used in conjunction with the flow channel structure in microfluidic chips to achieve continuous sorting of particles in flow.

[0051] Other technical features (substrate layer, phototransistor unit structural parameters, upper electrode structure, etc.) are the same as in Example 1, and will not be repeated here.

[0052] Example 3: Asymmetric Proportional Array-Type Optoelectronic Tweezers Chip The main difference between this embodiment and Embodiment 1 lies in the arrangement ratio of the transistor array structure. For example... Figure 5 As shown, this embodiment uses an asymmetrical proportional arrangement: In the chip array region, the ratio of NPN type phototransistor units 22 to PNP type phototransistor units 21 can be flexibly set according to the capture requirements of target particles, without being limited by a specific ratio; NPN type units (generating pDEP force fields) are concentrated in the central region of the chip, forming the main capture area, which is suitable for the efficient capture of target particles (such as cells of a specific particle size). PNP-type cells (which generate an nDEP force field) are distributed around the chip to form a repulsive boundary, preventing non-target particles from entering the capture area.

[0053] The pixel has a horizontal dimension of 3μm, a deep trench isolation width of 1μm, an aspect ratio of 20:1 (depth of approximately 20μm), and is filled with polyimide (PI) insulating medium; The liquid phase manipulation chamber has a height of 30 μm, making it suitable for precise manipulation of single-cell layers.

[0054] In another embodiment, PNP phototransistor units 21 are concentrated in the central region of the chip array, forming a central repulsion region or impurity capture region; while NPN phototransistor units 22 are distributed in the peripheral region.

[0055] The central PNP region generates an nDEP force field, which can push away non-target particles (such as small fragments or specific impurities) or capture them at a specific electric field frequency. The surrounding NPN region generates a pDEP force field, which attracts and maintains the target particles at the edge of the chip or in a specific flow channel region, thus achieving "outward sorting" of the target particles.

[0056] The advantage of asymmetric ratio arrangement is that it can form functional partitions with different electric field intensities on the same chip, which is suitable for selective capture and enrichment of specific target particles in mixed samples, and improves the selectivity of manipulation.

[0057] Other technical features are the same as in Embodiment 1, and will not be repeated here.

[0058] Example 4: Manufacturing method of array-type optoelectronic tweezers chip like Figure 6 As shown, this embodiment provides a method for manufacturing an array-type optoelectronic tweezers chip. Taking the chip of Embodiment 1 (cross-array arrangement type) as an example, the method includes the following steps: S1. Substrate Preparation An N+ type silicon substrate layer 1 (resistivity ≤ 0.005 Ω·cm, thickness approximately 600 μm) is provided. An N-type silicon epitaxial layer (thickness approximately 5–15 μm, doping concentration approximately 1 × 10⁻⁶) is epitaxially grown on the substrate surface using chemical vapor deposition (CVD). 16 cm -3 ).

[0059] The thickness of the epitaxial layer determines the longitudinal dimension space of the subsequent transistor structure. The epitaxial growth time and temperature need to be precisely controlled according to the target device parameters (growth temperature is about 1100℃, growth rate is about 1μm / min).

[0060] S2. Preparation of deep trench isolation zone (1) Photolithography defines the location of the isolation trench: Deep ultraviolet (DUV) photolithography is used to form a deep trench mask pattern on the surface of the epitaxial layer with a minimum line width of 1μm, corresponding to the design location of the deep trench isolation structure 6; (2) Deep silicon etching: Bosch process (alternating SF6 etching and C4F8 passivation cycle) is used for deep reactive ion etching (DRIE) with an etching rate of about 5 μm / min. The etching depth penetrates the entire epitaxial layer and extends into the N+ type silicon substrate layer by about 3 to 5 μm, with a total depth of about 5 to 20 μm and an aspect ratio of 10:1 to 20:1. (3) Insulating medium filling: The deep trench wall is thermally oxidized (to form a SiO2 pad of about 50nm), and then SiO2 is deposited to fill the deep trench using high-density plasma CVD (HDP-CVD) process, followed by chemical mechanical polishing (CMP) planarization treatment.

[0061] S3. Transistor Array Fabrication Within each isolated outer island region, PNP and NPN type phototransistor units are formed sequentially: (1) Preparation of PNP type units: Collector formation: Utilizing the intrinsic N-type background of the epitaxial layer, no additional implantation is required; Base formation: The N-type background epitaxial layer serves as the PNP base 212, with a resistivity of approximately 0.01 Ω·cm; Emitter formation: The P+ emitter region is defined by photolithography, and BF2+ ion implantation is performed at an implantation energy of 80 keV (within the range of 10–200 keV) and a dose of 5 × 10⁻⁶ ions. 15 cm -2 (located in 1×10) 13 ~1×10 16 cm -2 Within the range), after annealing, a P+ emitter 211 is formed (depth approximately 0.3 μm, concentration approximately 2 × 10⁻⁶). 19 cm -3 ); (2) Fabrication of NPN type units: Base formation: Photolithography defines the P-type base region, using B... + Ion implantation, implantation energy 100 keV (within the range of 10–200 keV), dose 1 × 10⁻⁶ 13 cm -2 (located in 1×10) 13 ~1×10 16 cm -2 Within the range), a P-type base 222 is formed (depth approximately 1.5 μm, concentration approximately 5 × 10⁻⁶). 17 cm -3 ); Emitter formation: The N+ emitter region is defined by photolithography, and P+ ion implantation (phosphorus) is performed at an implantation energy of 60 keV (within the range of 10–200 keV) and a dose of 5 × 10⁻⁶. 15 cm -2 (located in 1×10) 13 ~1×10 16 cm -2 Within the range), after annealing, an N+ emitter 221 is formed (depth approximately 0.2 μm, concentration approximately 2 × 10⁻⁶). 19 cm -3 ); Collector: The N+ type silicon substrate layer 1 is directly used as the common collector, and there is no need to form it separately; (3) Annealing activation: Anneal at 1000℃ (within the range of 800~1200℃) for 30min (within the range of 10 seconds to 2 hours) in a N2 protective atmosphere to activate the implanted impurity ions and repair lattice damage.

[0062] S4. Subsequent Processes (1) Back electrode deposition: The back side of the N+ type silicon substrate 1 is thinned (to about 200 μm) and chemical mechanical polishing (CMP) is performed. Then, Ti layer (20 nm) and Au layer (200 nm) are deposited sequentially by electron beam evaporation to form back metal layer 5 (Ti / Au composite layer). After being patterned by dicing, it is used as the common collector lead-out terminal. (2) Surface passivation protection: A 100nm SiO2 passivation protection layer is deposited on the front side of the transistor array structure using plasma enhanced CVD (PECVD) process to prevent the electrolyte solution in the liquid phase cavity from corroding the device surface; (3) Fabrication of the upper electrode structure: A 100nm ITO transparent conductive layer is deposited on the inner surface of a borosilicate glass substrate (0.5mm thick) using magnetron sputtering. The sheet resistance is about 15Ω and the transmittance is >90% (visible light). (4) Cavity assembly and bonding: SU-8 photoresist insulating pad (50μm high) is formed on the front side of the transistor array chip by photolithography. The upper electrode structure 4 is aligned and bonded to the front side of the chip to form a sealed liquid phase control cavity 3 with a height of 50μm. Liquid inlet / outlet of the liquid phase control cavity is introduced to complete the chip assembly.

[0063] Performance parameters compared with existing technologies: Performance indicators a-Si:H photodiode PNP phototransistor (this invention) NPN type phototransistor (this invention) Built-in gain None (<1) 1× 50～200× 50～200× Minimum pixel size ~50μm ~30μm ≥3μm ≥3μm Dark current / pixel High (nA~μA) <1nA <1nA <2nA High conductivity solution compatible No (>1 mS / cm) weak Yes (≤15mS / cm) Yes (≤15mS / cm) Front metal interconnect need need None (virtual electrode) None (virtual electrode) Pixel crosstalk High (no isolation) medium <1% (deep trench isolation) <1% (deep trench isolation) CMOS process compatible Difference good good good In summary, this invention achieves the following core advantages by integrating an NPN / PNP phototransistor lateral array with a deep trench isolation structure, a liquid-phase manipulation cavity, and a transparent upper electrode structure onto a single chip: Strong pixel independence: The deep trench isolation structure completely eliminates electrical crosstalk between adjacent pixels, ensuring single-pixel level control precision; High photoresponse efficiency: The virtual electrode design without a light-shielding metal layer maximizes the utilization of incident light, and the optical power required for manipulation is low (<10mW / cm²). 2 ), reducing phototoxicity to biological samples; Bipolar manipulation: The NPN / PNP complementary array provides pDEP and nDEP bipolar force fields on the same chip, offering flexible functionality; Programmable arrays: Multiple array configurations, such as cross arrays, striped arrays, and asymmetric proportional arrangements, meet different application requirements; CMOS process compatibility: Manufactured using all-silicon semiconductor processes, it is compatible with mature CMOS production lines and has the potential for large-scale production.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application.

Claims

1. An array-type optoelectronic tweezers chip, characterized in that: include: Substrate layer, transistor array structure, liquid phase manipulation chamber and upper electrode structure; The substrate layer serves as a supporting base for the bottom electrode and a common conductive path. The transistor array structure is disposed above the substrate layer and includes multiple phototransistor units arranged in a horizontal array; the phototransistor units are NPN or PNP type structures; a deep trench isolation structure is provided between adjacent phototransistor units, and the deep trench isolation structure extends longitudinally into the interior of the substrate layer to achieve electrical decoupling between adjacent units; the light-receiving surface of the phototransistor unit faces the liquid phase manipulation cavity and is not covered by a light-shielding metal layer.

2. The array-type photoelectric tweezers chip according to claim 1, characterized in that: The substrate is an N+ type silicon substrate, and a metal layer is disposed on its back side as a common collector lead-out terminal. The metal layer is a Ti / Au composite layer.

3. The array-type photoelectric tweezers chip according to claim 1, characterized in that: The phototransistor unit is provided with an emitter, a base, and a collector in sequence from top to bottom. The emitter and collector of the PNP type phototransistor unit are P+ doped regions, and its base is an N-doped region. The emitter and collector of the NPN type phototransistor unit are N+ doped regions, and its base is a P-doped region.

4. The array-type photoelectric tweezers chip according to claim 3, characterized in that: The emitter has a doping concentration of 1×10⁻⁶. 19 ~5×10 19 cm -3 The implantation depth is 0.1–0.5 μm; the doping concentration of the base is 1 × 10⁻⁶. 16 ~1×10 16 cm -3 The thickness is 1–3 μm; the doping concentration of the collector is 1 × 10⁻⁶. 14 ~5×10 19 cm -3 .

5. The array-type photoelectric tweezers chip according to claim 1, characterized in that: The deep trench isolation structure is filled with at least one insulating dielectric material selected from silicon dioxide (SiO2), silicon nitride (Si3N4), or polyimide (PI); the depth of the deep trench isolation structure is greater than the depth of the deepest doped region of the phototransistor unit, so as to achieve full dielectric physical isolation between adjacent units.

6. The array-type photoelectric tweezers chip according to claim 1, characterized in that: The plurality of the aforementioned phototransistor units are arranged in any of the following manner: Cross array arrangement: The NPN type structure and PNP type structure are arranged alternately in a checkerboard pattern, and the polarity of any pixel is opposite to that of its neighboring pixels; Striped array arrangement: Phototransistor units of the same polarity are connected along the first direction to form a striped area, and NPN type phototransistor units and PNP type phototransistor units are arranged alternately along the second direction; Asymmetric arrangement: The transistor array structure is composed of varying numbers of NPN and PNP phototransistor units to form functional zones with different electric field intensities on the chip surface.

7. The array-type photoelectric tweezers chip according to claim 1, characterized in that: The width of the deep trench isolation structure is 1 to 2 μm, and the depth:width ratio is 10:1 to 20:

1. The lateral dimension of the phototransistor unit is not less than 3 μm.

8. The array-type photoelectric tweezers chip according to claim 1, characterized in that: The upper electrode structure includes a transparent substrate and a transparent conductive layer disposed on its inner surface; the upper electrode structure and the transistor array structure are supported by an insulating pad to enclose and form a liquid phase manipulation cavity with a height of 10μm to 200μm.

9. A method for manufacturing an array-type optoelectronic tweezers chip, characterized in that: Includes the following steps: S1: Substrate preparation: Provide an N+ type silicon substrate layer and grow a silicon epitaxial layer on its surface; S2: Deep trench isolation region fabrication: An isolation trench is formed by etching process, which runs through the entire epitaxial layer and extends to the substrate layer, and then filled with an insulating medium; S3: Transistor array fabrication: Ion implantation process is used to form corresponding base and emitter regions in the isolated epitaxial region; when NPN and PNP mixed arrangement is involved, different types of impurity ions are implanted in separate processes. S4: Back-end process: Deposit the back electrode, surface passivation protective layer, and complete the bonding assembly with the upper electrode structure.

10. The manufacturing method according to claim 9, characterized in that: The ion implantation process in step S3 involves an implantation energy of 10–200 keV and a dose of 1 × 10⁻⁶. 13 ~1×10 16 cm -2 The subsequent process in step S4 also includes annealing, wherein the annealing temperature is 800-1200℃ and the time is 10 seconds to 2 hours.

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