An event-driven, all-digital low-dropout linear regulator

Abstract

This invention discloses an event-driven, all-digital low-dropout linear regulator, comprising a sampling module, a control module, and a power transistor array. The sampling module acquires the load voltage at the current time step and outputs a voltage status signal and a large voltage drop signal. The voltage status signal and the large voltage drop signal are input to the control module. A scenario determination module determines the operating scenario of the digital control logic unit based on the voltage status signal and the large voltage drop signal. A fast-slow dual-clock driving module determines whether the fast clock or the slow clock is the master clock. The control module determines the adjustment mechanism adopted by the digital control logic unit to control the power transistor array under the master clock according to the operating scenario, and selects whether to trigger the combinational logic feedforward path. If the combinational logic feedforward path is triggered, the power transistor array is directly turned on. By controlling the power transistor array to turn on or off, the load voltage at the next time step is adjusted. This invention achieves a balance between high energy efficiency and engineering robustness.

Description

Technical Field

[0001] This invention relates to the field of voltage control, and more specifically to an event-driven, all-digital low-dropout linear regulator. Background Technology

[0002] With the development of the information society, the demands of modern electronic systems on computing power and energy efficiency are increasing at an unprecedented pace. From high-performance data center processors to energy-constrained wearable devices, the core of almost all electronic devices relies on a stable and efficient power supply. In order to minimize product size and improve product performance, System-on-Chip (SoC) has gradually become the main trend in chip design. In order to achieve optimal performance within a limited chip area and power budget, SoC integrates increasingly complex heterogeneous computing units, and the highly dynamic resources experience drastic load fluctuations under different working scenarios.

[0003] To address this issue, sophisticated power management technologies have emerged. Dynamic Voltage and Frequency Scaling (DVFS) technology divides the SoC into multiple independent power supply voltage domains and equips each functional unit with an independent voltage regulator (VR). This dynamically adjusts the supply voltage according to the actual load requirements, becoming a key means to improve overall system energy efficiency and reduce power consumption. Among various voltage regulators, low dropout linear regulators (LDOs) are widely used in the local power supply networks within SoCs due to their advantages such as no external inductor, simple circuit structure, fast response speed, and low output ripple.

[0004] Based on their control loop architecture, LDOs are mainly divided into two categories: analog LDOs and digital LDOs. However, as semiconductor process nodes evolve towards smaller sizes and power supply voltages continuously decrease, the intrinsic gain of transistors declines, posing significant challenges to traditional analog LDO design. Analog LDOs struggle to maintain high loop gain and wide bandwidth at low voltages and are difficult to scale down proportionally with process technology. Furthermore, due to the poor design portability of analog circuits, each process migration requires a cumbersome, full-custom redesign of the analog LDO.

[0005] To overcome the bottlenecks of analog LDOs under advanced manufacturing processes, digital LDOs have gradually become a research hotspot. Digital LDOs utilize digital logic gates to implement control loops, offering advantages such as strong low-voltage operation capability, good noise immunity, and ease of integration. In particular, fully digital synthesizable LDO systems can be designed directly using standard digital cell libraries and hardware description languages, significantly shortening the design cycle and improving design portability.

[0006] Despite the numerous advantages of digital LDOs, most existing designs employ a synchronous control architecture based on periodic sampling. In this architecture, the regulator needs to sample and assess the output voltage every clock cycle, adjusting the power transistor's on / off state accordingly. To quickly recover the output voltage during sudden load current changes, the control loop typically needs to operate at a high clock frequency, which often significantly increases the digital LDO's power consumption. Conversely, reducing the clock frequency to decrease power consumption significantly reduces the control loop's response speed, making it difficult for the digital LDO to adjust the output current promptly during load transitions, resulting in significant overshoot or undershoot in the output voltage. Therefore, synchronous clock-based digital LDOs present a fundamental trade-off between response speed and power consumption, limiting their application potential in high-efficiency SoCs.

[0007] Furthermore, digital LDOs commonly suffer from limit cycle oscillation (LCO) during steady-state operation. Due to the quantization characteristics of digital control and the fixed-period control update mechanism, synchronous digital LDOs still periodically adjust the conduction state of the power transistors even when the output voltage is close to the target value, resulting in continuous ripple in the output voltage under steady-state conditions. This ripple not only degrades power supply quality but also affects noise-sensitive analog or mixed-signal modules.

[0008] To address the aforementioned issues, existing research has attempted improvements through methods such as hybrid control, predictive control, or adaptive clocking. However, these solutions often require additional analog auxiliary circuitry and complex calibration mechanisms, thus diminishing their practical application value in large-scale SoCs. Therefore, overcoming the power consumption and response speed bottlenecks imposed by synchronous clock control to achieve a voltage regulation mechanism with fast response and low ripple has become a pressing technical challenge in the current digital LDO field. Summary of the Invention

[0009] The purpose of this application is to propose an event-driven, all-digital low-dropout linear regulator to address the aforementioned technical problems.

[0010] This invention provides an event-driven, all-digital low-dropout linear regulator, comprising a sampling module, a control module, and a power transistor array. The sampling module acquires the load voltage at the current time step and detects the voltage state and voltage drop, outputting a voltage state signal and a large voltage drop signal. The control module includes a scenario determination module, a fast / slow dual-clock driving module, a combinational logic feedforward path, and a digital control logic unit. The voltage state signal and the large voltage drop signal are input to the control module. The scenario determination module determines the operating scenario of the digital control logic unit based on the received voltage state signal and the large voltage drop signal. The fast / slow dual-clock driving module determines whether the fast clock or the slow clock is the master clock based on the received voltage state signal. The control module determines the adjustment mechanism adopted by the digital control logic unit to control the power transistor array under the master clock based on the operating scenario. It selects whether to trigger the combinational logic feedforward path based on the voltage state signal or the large voltage drop signal, the operating scenario, and the circuit load. If the combinational logic feedforward path is triggered, the power transistor array is directly controlled to turn on. By controlling the power transistor array to turn on or off, the load voltage at the next time step is adjusted.

[0011] Preferably, the power transistor array includes a small-size power transistor array and a large-size power transistor array. The small-size power transistor array contains several small-size power transistors, and the large-size power transistor array contains several large-size power transistors. The adjustment mechanism adopted by the digital control logic unit to control the power transistor array under the master clock includes a single-step fine-grained adjustment mechanism and a multi-step coarse-grained adjustment mechanism. The single-step fine-grained adjustment mechanism is used to adjust the on or off of a small-size power transistor in a single master clock cycle, and the multi-step coarse-grained adjustment mechanism is used to adjust the on or off of more than one large-size power transistor in a single master clock cycle.

[0012] Preferably, the sampling module includes a first voltage comparator, a second voltage comparator, a third voltage comparator, a fourth voltage comparator, and a voltage drop detector. The first, second, third, and fourth voltage comparators are used to compare the load voltage at the current time step with the first, second, third, and fourth reference voltages, respectively, and output a first state signal, a second state signal, a third state signal, and a fourth state signal based on the comparison results, thus forming a voltage state signal. The voltage drop detector is used to detect the voltage drop of the load voltage at the current time step and generate a large voltage drop signal.

[0013] Preferably, the operating scenarios include overshoot scenario, stable scenario, normal voltage drop scenario, and severe voltage drop scenario. The voltage status signal and the large voltage drop signal are input to the scenario determination module in the control module. When the first status signal is a high-level signal, the operating scenario is determined to be an overshoot scenario; when the first status signal, the third status signal, and the fourth status signal are all low-level signals, the operating scenario is determined to be a stable scenario; when the third status signal is a high-level signal and the fourth status signal is a low-level signal, the operating scenario is determined to be a normal voltage drop scenario; when the fourth status signal or the large voltage drop signal is a high-level signal, the operating scenario is determined to be a severe voltage drop scenario.

[0014] Preferably, the control module is used to execute the following control logic:

[0015] When the working scenario is an overshoot scenario, the control digital control logic unit adopts a multi-step coarse-grained adjustment mechanism to shut down the large-size power transistors, and dynamically adjusts the required number of large-size power transistors to be shut down according to the number of large-size power transistors that have been turned on.

[0016] When the working environment is stable, the control digital control logic unit uses a single-step fine-grained adjustment mechanism to turn the small-size power transistor on or off based on the second state signal.

[0017] When the operating scenario is a normal voltage drop scenario, the circuit load is determined as heavy or light based on the number of large-size power transistors that are already turned on. When the circuit load is heavy, the combinational logic feedforward path is triggered to directly turn on M1 large-size power transistors, and the digital control logic is controlled to turn on the large-size power transistors in parallel using a limited binary search method. When the circuit load is light, the digital control logic is directly controlled to turn on the large-size power transistors in parallel using a limited binary search method.

[0018] When the operating scenario is a severe voltage drop scenario, the combinational logic feedforward path is triggered to directly turn on M2 large-size power transistors, and the control digital control logic uses the traditional binary search method to turn on the large-size power transistors in parallel.

[0019] Preferably, when the operating scenario is a stable scenario, if the second state signal is a high-level signal, the digital control logic unit turns on the small-sized power transistor according to the single-step fine-grained adjustment mechanism; if the second state signal is a low-level signal, the digital control logic unit turns off the small-sized power transistor according to the single-step fine-grained adjustment mechanism.

[0020] When the working scenario is a normal voltage drop scenario, if the number of large-size power transistors that have been turned on is greater than the number threshold, the circuit load is determined to be heavy; if the number of large-size power transistors that have been turned on is less than or equal to the number threshold, the circuit load is determined to be light.

[0021] The combinational logic feedforward path is allowed to be triggered only once in N cycles.

[0022] As a preferred option, compared to the traditional bisection method, the step size of the amplitude-limited bisection method is limited by the maximum step size.

[0023] Preferably, when the fast and slow dual-clock drive module determines that the fourth state signal is a high-level signal, it determines that the fast clock is the master clock; when it determines that the fourth state signal is a low-level signal, it determines that the slow clock is the master clock.

[0024] Preferably, the first, second, third, and fourth voltage comparators are all voltage comparators. Each voltage comparator includes a cross-coupled NAND gate module, an NOT gate module, and a cross-coupled NOR gate module. The input ports of the NAND gate module are the negative port, the positive port, and the master clock, respectively. The cross-coupled NAND gate module compares the voltages input to the negative and positive ports. The output signal of the NAND gate module is inverted by the NOT gate module and then input to the NOR gate module. The NOR gate module forms an SR latch, which is used to restore the inverted logic and latch the output signal of the voltage comparator.

[0025] Preferably, the voltage drop detector includes a capacitor, a NAND gate module, a NOT gate module, and a buffer connected in sequence; one end of the capacitor is input to the load voltage of the current time step, and the other end is connected to the NAND gate module whose two inputs are in a short-circuit state.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] (1) The event-driven all-digital low-dropout linear regulator proposed in this invention proposes a hybrid control architecture in which an asynchronous combinational logic feedforward path and a digital logic controller work together in the design of the digital LDO architecture. The combinational logic feedforward path uses the output signal of the fourth voltage comparator used to detect whether a serious voltage drop occurs or the large voltage drop signal output by the voltage drop detector as the driving signal. It will form a low-latency fast channel through the combinational logic feedforward path, which significantly shortens the response time. The synchronous channel is managed by the digital logic controller to uniformly manage the conduction state of the power transistor array and complete the control word update, mode switching and steady-state fine adjustment.

[0028] (2) The event-driven all-digital low-dropout linear regulator proposed in this invention proposes a hierarchical control mechanism for multiple working scenarios in the control strategy of digital LDO, integrating fast and slow clock, load sensing and dual-loop collaborative strategy to adapt to the adjustment requirements under different load and voltage conditions, and further improve the stability of the system.

[0029] (3) The event-driven all-digital low-dropout linear regulator proposed in this invention can reduce system power consumption while ensuring fast transient response and effectively suppress output voltage oscillation, thus taking into account both high energy efficiency and engineering robustness. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the circuit architecture of an event-driven all-digital low-dropout linear regulator according to an embodiment of this application.

[0032] Figure 2 This is a schematic diagram of the voltage comparator structure of an event-driven all-digital low-dropout linear regulator according to an embodiment of this application.

[0033] Figure 3 This is a schematic diagram of the voltage drop detector of an event-driven all-digital low-dropout linear regulator, as an embodiment of this application.

[0034] Figure 4 This is a schematic diagram illustrating the response delay of a digital LDO in an emergency.

[0035] Figure 5 This is a schematic diagram illustrating the operation of an event-driven, all-digital low-dropout linear regulator in a stable scenario, as an embodiment of this application.

[0036] Figure 6 This is a schematic diagram illustrating the operation of an event-driven, all-digital low-dropout linear regulator in an overshoot scenario, as an embodiment of this application.

[0037] Figure 7 This is a schematic diagram illustrating the operation of an event-driven, all-digital low-dropout linear regulator according to an embodiment of this application in a normal voltage drop scenario.

[0038] Figure 8 This is a schematic diagram illustrating the operation of an event-driven, all-digital low-dropout linear regulator in a severe voltage drop scenario, as an embodiment of this application.

[0039] Figure 9 This is a schematic diagram of the processing path of an event-driven all-digital low-dropout linear regulator under severe voltage drop, as an embodiment of this application.

[0040] Figure 10This is a schematic diagram illustrating the complementary control signals of the combinational logic feedforward path of the dropout detector of an event-driven all-digital low-dropout linear regulator, as shown in an embodiment of this application.

[0041] Reference numerals: 1. Sampling module; 2. Control module; 3. Power transistor array; 21. Fast and slow dual clock drive module; 22. Combinational logic feedforward path; 23. Digital control logic unit. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0043] Figure 1 This application illustrates an event-driven, all-digital low-dropout linear regulator, including a sampling module 1, a control module 2, and a power transistor array 3. The sampling module 1 acquires the load voltage at the current time step and detects the voltage state and voltage drop, outputting a voltage state signal and a large voltage drop signal. The control module 2 includes a scenario determination module, a fast / slow dual-clock drive module 21, a combinational logic feedforward path 22, and a digital control logic unit 23. The voltage state signal and the large voltage drop signal are input to the control module 2, and the scenario determination module determines the digital control logic unit based on the received voltage state signal and large voltage drop signal. The working scenario of logic unit 23; the fast and slow dual clock drive module 21 is used to determine whether the fast clock or the slow clock is the master clock based on the received voltage status signal. The control module 2 determines the adjustment mechanism adopted by the digital control logic unit 23 to control the power transistor array 3 under the master clock according to the working scenario. Based on the voltage status signal or large voltage drop signal, the working scenario and the circuit load, it selects whether to trigger the combinational logic feedforward path 22. If the combinational logic feedforward path 22 is triggered, it directly controls the power transistor array 3 to turn on. By controlling the power transistor array 3 to turn on or off, the load voltage of the next time step is adjusted.

[0044] Specifically, embodiments of this application propose an event-driven, all-digital low-dropout linear regulator, the overall architecture of which is as follows: Figure 1 As shown, the system consists of three main parts: a sampling module 1, a control module 2, and a power transistor array 3. The inputs to the sampling module 1 are the load voltage OUT and four reference voltages V. REFH V REFR V REFL and V REFLL The outputs of the four voltage comparators in sampling module 1 are 4-bit voltage status signals (CMP).OUT It also serves as an input signal for control module 2, used to sense the current state of the load circuit. Furthermore, sampling module 1 includes a voltage drop detector for asynchronously detecting large voltage drops, which outputs a large voltage drop signal VD. Control module 2 includes a scene determination module (not shown), a fast / slow dual-clock drive module 21, a combinational logic feedforward path 22, and a digital control logic unit 23; the large voltage drop signal VD and the voltage status signal CMP... OUT Together they serve as the input signals for the combinational logic feedforward path 22 in the control module 2, to ensure that the combinational logic feedforward path 22 can be correctly triggered.

[0045] In a specific embodiment, the power transistor array 3 includes a small-size power transistor array and a large-size power transistor array. The small-size power transistor array contains several small-size power transistors, and the large-size power transistor array contains several large-size power transistors. The adjustment mechanism adopted by the digital control logic unit 23 to control the power transistor array 3 under the master clock includes a single-step fine-grained adjustment mechanism and a multi-step coarse-grained adjustment mechanism. The single-step fine-grained adjustment mechanism is used to adjust the on or off of a small-size power transistor in a single master clock cycle, and the multi-step coarse-grained adjustment mechanism is used to adjust the on or off of more than one large-size power transistor in a single master clock cycle.

[0046] Specifically, the power transistor array 3 can be divided into a small-size power transistor array and a large-size power transistor array. The small-size power transistor array consists of several small-size power transistors, while the large-size power transistor array consists of several large-size power transistors and their corresponding multiplexers. The multiplexers select the control signal output from the combinational logic feedforward path 22 or the control signal output from the digital control logic 23. The output of the combinational logic feedforward path 22 is a 128-bit control signal, which, together with the 128-bit control signal output from the digital control logic 23, serves as the control signal for the 128 large-size power transistors. The chip select logic of the multiplexer selects whether to use the combinational logic feedforward path 22 or the digital control logic 23 for control. However, the output of the combinational logic feedforward path 22 is not controlled by the master clock, while the output and update of the digital control logic 23 are controlled by the master clock. The output of digital control logic unit 23 serves as the control signal for power transistor array 3. A 128-bit output signal is used as one of the inputs to the multiplexer of the large-size power transistor array, and a 32-bit output signal is used as the input signal for the small-size power transistor array. There is a one-to-one correspondence between the power transistors and the control signals. For the inputs of power transistor array 3, in addition to the control signals, the chip's supply voltage is also connected as an input to the source of power transistor array 3. The output of power transistor array 3 is the load voltage OUT for the next time step. It is connected to the drain of the power transistors. The supply voltage will supplement or reduce the current by turning power transistor array 3 on or off, thereby adjusting to obtain the load voltage OUT for the next time step.

[0047] The architecture of the embodiments in this application is designed to output a stable voltage close to the reference voltage V. REFR With the load voltage OUT as the target, the sampling module 1 continuously senses the voltage state at the current time step and feeds back the detection results to the control module 2 to implement the corresponding compensation strategy. The final strategy is applied based on the power transistor array 3. For scenarios requiring high load operation, the control module 2 will drive the power transistor array 3 to turn on a certain number of power transistors to supplement the current; conversely, if the system requires low load operation, it will also drive the power transistor array 3 to turn off some power transistors to reduce the output current.

[0048] In a specific embodiment, the sampling module 1 includes a first voltage comparator, a second voltage comparator, a third voltage comparator, a fourth voltage comparator, and a voltage drop detector. The first voltage comparator, the second voltage comparator, the third voltage comparator, and the fourth voltage comparator are used to compare the load voltage at the current time step with the first reference voltage, the second reference voltage, the third reference voltage, and the fourth reference voltage, respectively, and output a first state signal, a second state signal, a third state signal, and a fourth state signal based on the comparison results, thereby forming a voltage state signal. The voltage drop detector is used to detect the voltage drop of the load voltage at the current time step and generate a large voltage drop signal.

[0049] Specifically, sampling module 1 internally includes four voltage comparators for detecting voltage states and one voltage drop detector for detecting voltage drops. The voltage comparators and voltage drop detector share the load voltage OUT of the current time step as input, but the outputs of the two circuits are independent. For the voltage comparator, its two inputs are the positive and negative terminals, used only to distinguish the two inputs and as a standard for voltage magnitude comparison. The voltage comparator samples with the master clock; if the voltage at the positive terminal is higher than the voltage at the negative terminal, the voltage comparator outputs a high level; otherwise, it outputs a low level. Reference voltage V REFH The input is to the negative terminal of voltage comparator 1, with reference voltage V. REFR V REFL and V REFLL The input is given to the positive ports of the remaining three voltage comparators. The load voltage OUT at the current time step is used as the detected voltage and is connected to the positive port of the first voltage comparator and the negative ports of the remaining three voltage comparators. Four different reference voltages represent different voltage thresholds. The load voltage OUT at the current time step is higher than the reference voltage V. REFH At this time, the system will be in a high-voltage region, and the corresponding voltage comparator will output a high-level signal; the load voltage OUT at the current time step is between V... REFH and V REFL Between these points, the system is in the stable region; the load voltage OUT at the current time step is between V. REFL and V REFLL During this period, the system is in a low-voltage region; the load voltage OUT at the current time step is lower than V. REFLL At this time, the system is in the extremely low voltage region. Thus, the system forms four voltage regions: high voltage, stable voltage, low voltage, and extremely low voltage. The voltage drop detector is only used to detect the magnitude of the load voltage OUT drop at the current time step. By sensing the change in the slope during the voltage drop, it provides rapid feedback on the voltage decrease to the system. The introduction of the voltage drop detector can effectively alleviate the dependence of traditional synchronous comparators on clock frequency, achieving timely detection of voltage status without using a high-speed clock.

[0050] In a specific embodiment, the first voltage comparator, the second voltage comparator, the third voltage comparator, and the fourth voltage comparator are all voltage comparators. Each voltage comparator includes a cross-coupled NAND gate module, an NOT gate module, and a cross-coupled NOR gate module. The input ports of the NAND gate module are the negative port, the positive port, and the master clock, respectively. The cross-coupled NAND gate module is used to compare the voltages input to the negative port and the positive port. The output signal of the NAND gate module is inverted by the NOT gate module and then input to the NOR gate module. The NOR gate module forms an SR latch, which is used to restore the inverted logic and latch the output signal of the voltage comparator.

[0051] The voltage comparator in sampling module 1 is conventionally designed as an analog circuit. To improve system portability, embodiments of this application use a voltage comparator composed of digital standard units. The structure of the voltage comparator used in this application is as follows: Figure 2 As shown, the input ports of this structure are INn and INp, representing the negative and positive ports of the voltage comparator, respectively. The three-input NAND gate module on the left side of sampling module 1, cross-coupled with the main clock CLK, samples the voltages of inputs INn and INp. The NOT gate module in the middle of sampling module 1 stabilizes the comparison result at the power supply voltage or ground. The NOR gate module on the right side of sampling module 1 forms an SR latch, used to latch the output of the voltage comparator and restore the just-inverted logic.

[0052] In a specific embodiment, the voltage drop detector includes a capacitor, a NAND gate module, a NOT gate module, and a buffer connected in sequence; one end of the capacitor is input to the load voltage of the current time step, and the other end is connected to the NAND gate module whose two inputs are in a short-circuit state.

[0053] Specifically, considering that the effect of load current on the voltage change slope in a digital LDO system is directly determined by the capacitor charging and discharging formula:

[0054]

[0055] Where dV / dt is the slope of the voltage change, I net C is the net current of the circuit. loadThe load capacitance is the current supplied by the LDO minus the current consumed by the load. Therefore, the greater the change in load current, the greater the net current of the circuit. Since the load capacitance often changes very little, the voltage change slope will be greater under large load current steps. This means that in severe voltage drop scenarios, the load voltage OUT at the current time step will decrease faster. If sampling is still dependent on a synchronous voltage comparator, the voltage drop will increase due to clock intervals. Even if the subsequent control module 2 uses a faster adjustment strategy, the voltage drop handling capability of the digital LDO system will still be limited by the length of one clock cycle in sampling module 1.

[0056] To overcome the limitations of voltage sampling frequency, an embodiment of this application introduces a voltage drop detector, the structure of which is as follows: Figure 3 As shown, the structure consists of a 1pF capacitor, a NAND gate module, a NOT gate module, and a buffer. One side of the capacitor is connected to the load voltage OUT of the current time step, and the other side serves as an input to two NAND gate modules with their inputs shorted. The output of the NAND gate module is connected to the input of the NOT gate module, and the output of the NOT gate module is connected to the input of the buffer. The output of the buffer is a large voltage drop signal VD, used to characterize whether a large voltage drop has occurred in the load voltage of the current time step. If VD is always low, it means that the voltage drop detector has not detected a large voltage drop; conversely, if VD is high, it means that a large voltage drop has been detected. VD, as the input signal of the combinational logic feedforward path 22, controls the activation of the asynchronous path. To maximize the portability of the design, the gate modules used in the embodiments of this application are all standard cells. The capacitor of the voltage drop detector and the equivalent impedance of the input terminal of the subsequent gate circuit together constitute a high-pass response network. The load voltage OUT at the current time step is connected as an input to the capacitor. The output VD of the voltage drop detector indicates whether a significant voltage drop has been detected. VD is low by default. If a pull-up pulse appears on VD, it indicates that a significant voltage drop at the load voltage OUT at the current time step has been detected. Due to the capacitor, when the load voltage OUT at the current time step is in a steady state, its change is very small. At this time, the voltage at node Vs depends on the voltage division relationship of the equivalent impedance of the pull-up / pull-down network inside the NAND gate module. For digital circuits, the current formula for a MOSFET operating in the linear region is:

[0057] ;

[0058] in, Leakage current, For carrier mobility, Gate oxide capacitance per unit area The aspect ratio of the transistor. Gate-source voltage, Threshold voltage, This is the drain-source voltage. Since electron mobility is generally higher than hole mobility, NMOS has a higher driving capability than PMOS for the same size. For a NAND gate, the NMOS transistors in its pull-down network are connected in series, and due to voltage division, the driving capability of the NMOS is weakened. In contrast, the PMOS transistors in the pull-up network of a NAND gate are connected in parallel. Therefore, under standard cell size ratios, the equivalent impedances of the pull-up and pull-down networks are similar, resulting in the Vs node being fixed at approximately half the supply voltage in steady state. In TSMC's 28nm process, with a standard supply voltage of 0.9V, Vs is fixed at 0.48V. At this point, Vs, as the input of the NOT gate module, will strongly conduct the pull-down network and weakly conduct the pull-up network, thus the output of the NOT gate module will be at a lower voltage level. This voltage is further reinforced by the buffer to ensure logic "0", and VD will remain low while the load voltage OUT at the current time step is stable.

[0059] When a significant voltage drop occurs at the load voltage OUT in the current time step, the high-pass filter will detect this change and pull Vs down accordingly, gradually strengthening the pull-up network of the NOT gate module. When the voltage drop reaches a certain level, the pull-up network of the NOT gate module will change the output level of the NOT gate and pull it up to a high level. Vs also serves as the input of the NAND gate module, so the pull-up network of the NAND gate module will also be strengthened, reducing the impedance of the pull-up network. The enhanced current from the PMOS will continue to charge the Vs node until it returns to its original stable state. Figure 3 As shown. Therefore, the high level output of the NOT gate module will be a small pulse, and the buffer will widen the pulse as a control signal for subsequent digital circuits. Thus, this circuit realizes the sensing of the load voltage OUT drop at the current time step and can recover autonomously. Under TSMC's 28nm process, when the structure is powered by a standard voltage, a change of 45mV is enough to pull VD high within a 0.2ns voltage drop time. Therefore, when facing a large load current step, the high slope of the voltage change will reach the detection threshold more quickly, further shortening the voltage drop detection time. Compared to a voltage comparator, the introduction of a voltage drop detector allows the voltage drop state sampling of a digital LDO system to no longer depend on a high clock frequency.

[0060] In a specific embodiment, the operating scenarios include overshoot scenario, stable scenario, normal voltage drop scenario, and severe voltage drop scenario. The voltage status signal and the large voltage drop signal are input to the scenario determination module in the control module 2. When the first status signal is a high-level signal, the operating scenario is determined to be an overshoot scenario; when the first status signal, the third status signal, and the fourth status signal are all low-level signals, the operating scenario is determined to be a stable scenario; when the third status signal is a high-level signal and the fourth status signal is a low-level signal, the operating scenario is determined to be a normal voltage drop scenario; when the fourth status signal or the large voltage drop signal is a high-level signal, the operating scenario is determined to be a severe voltage drop scenario.

[0061] In a specific embodiment, when the fast and slow dual-clock driving module 21 determines that the fourth state signal is a high-level signal, it determines that the fast clock is the master clock; when it determines that the fourth state signal is a low-level signal, it determines that the slow clock is the master clock.

[0062] Specifically, using a fast clock significantly increases system power consumption, while using a slow clock significantly reduces system transient response speed. Therefore, the embodiments of this application design two clocks: a fast clock CLK. fast and slow clock CLK slow Among them, CLK slow By CLK fast The clocks are obtained through frequency division, ensuring they are in phase and eliminating the need for additional cross-clock domain operations, thus reducing design complexity. CLK fast CLK serves as the sampling clock for the voltage comparator. fast and CLK slow CLK is an optional master clock, used only in severe voltage drop scenarios where the load voltage OUT at the current time step is in an extremely low voltage region. fast Only CLK is used as the master clock for control module 2; otherwise, CLK is used. slow The master clock.

[0063] Considering that the transient response speed of traditional digital LDO systems is limited by the clock frequency, embodiments of this application introduce an asynchronous combinational logic feedforward path 22 to alleviate this problem. The combinational logic feedforward path 22 receives the output from the dropout detector and directly controls the power transistor array 3 based on the actual state of the load voltage OUT at the current time step. The load voltage OUT at the current time step is connected as an input to the dropout detector, and its large dropout signal VD is connected as an input to the combinational logic feedforward path 22. The combinational logic feedforward path 22 has two inputs, VD and CMP. OUT This module is based on CMP OUTThe result determines the state of the load voltage OUT at the current time step. VD is used for faster asynchronous detection of whether a large voltage drop has occurred. VD only goes high when a large voltage drop occurs, causing it to go high, or when detected by CMP. OUT The combinational logic feedforward path 22 is triggered only when the load voltage OUT, representing the current time step, is below the low-voltage region. This is due to CMP. OUT It is generated by the master clock, therefore CMP OUT The control mechanism only controls the combinational logic feedforward path 22, which is driven by the master clock. The actual asynchronous operation in the system occurs when the voltage drop detector detects a significant voltage drop, causing the large voltage drop signal VD to go high. This drives the combinational logic feedforward path 22 to turn on multiple large-size power transistors simultaneously, injecting a large current to adjust the load voltage OUT for the next time step. Therefore, in extreme scenarios where a severe voltage drop is detected, asynchronous operation can quickly take corresponding compensation measures without being constrained by the master clock frequency.

[0064] In a specific embodiment, compared with the traditional bisection method, the step size of the amplitude-limited bisection method is limited to the maximum step size.

[0065] To further improve system stability, the embodiments of this application are based on a dual-loop adjustment strategy consisting of a multi-step coarse-grained adjustment mechanism and a single-step fine-grained adjustment mechanism. Different adjustment measures are adopted according to the different regions of the load voltage at the current time step fed back by the sampling module 1. Considering that traditional digital LDO systems are based on linear control using shift registers, this means that only one bit of the control word can change per cycle, which significantly reduces the system's response speed. Therefore, the embodiments of this application introduce a binary search strategy to improve the system's response speed by increasing the step size of the control word change. However, considering the over-adjustment problem of this method, the maximum amplitude of the binary search is limited in the embodiments of this application, and it is designed in conjunction with the combinational logic feedforward path 22.

[0066] Considering that the overall response time of a digital LDO system in handling emergencies consists of three parts: sampling delay, processing delay, and compensation delay, such as... Figure 4As shown. For traditional synchronous digital LDO systems, the voltage sampling delay is limited not only by the inherent delay of its own circuitry but also by the clock frequency. A higher clock frequency results in more samples per unit time, leading to more accurate and timely voltage state assessment. However, since sampling module 1 often employs a voltage comparator structure, which requires a certain recovery time to reset to the initial comparison state during normal operation, the clock frequency cannot exceed the recovery time; otherwise, the reliability of the voltage comparator output will significantly decrease. Furthermore, the processing time of digital control logic unit 23 is also limited by inherent delay and clock frequency. Compared to other components of a digital LDO system, digital control logic unit 23 is often larger in scale, so an excessively high clock frequency will also affect the system's dynamic power consumption. The compensation delay mainly originates from the delay between the control word and the startup of the power transistor array 3; therefore, it is an inherent delay within the module, and compared to the other two factors, its optimizable points and the proportion of its delay are relatively small.

[0067] Therefore, the factors affecting the response speed of a digital LDO system are mainly divided into two parts: whether the sampling is timely and whether the system processing speed is fast enough. To improve the transient response of the system, the embodiments of this application not only optimize the processing speed of the digital control logic unit 23, but also combine the control of the voltage drop detector, the combinational logic feedforward path 22, and the power transistor array 3. In scenarios where the clock frequency is limited, the voltage drop detector can detect the voltage drop regardless of the clock frequency and generate a large voltage drop signal VD. This signal is input as an asynchronous control signal to the combinational logic feedforward path 22, thereby directly driving the conduction of a large number of power transistors through the combinational logic feedforward path 22, mitigating further expansion of the voltage drop amplitude.

[0068] For the design of the power transistor array 3, considering that the larger the size of the PMOS, the larger its output current, in order to cooperate with the dual-loop adjustment strategy of multi-step coarse-grained regulation mechanism and single-step fine-grained regulation mechanism, the power transistor array 3 in this application uses two different sizes of PMOS. In one example, the number of PMOS in the large-size power transistor array is 128, which is used for large-step fast regulation in the multi-step coarse-grained regulation mechanism loop; while the number of PMOS in the small-size power transistor array is 32, which is used for small-step control in the single-step fine-grained regulation mechanism loop to alleviate the LCO phenomenon.

[0069] In the embodiments of this application, the working scenario is divided into four scenarios: overshoot scenario, stable scenario, normal voltage drop scenario, and severe voltage drop scenario. To ensure system stability, the digital control logic unit 23 is required as the control core of the digital LDO system. Its output serves as the control word for the power transistor array 3, corresponding one-to-one with each power transistor in the array. The embodiments of this application propose a multi-scenario hierarchical control mechanism, integrating fast and slow clocks, load sensing, and dual-loop collaborative strategies to adapt to the adjustment requirements under different load and voltage conditions.

[0070] (1) In the overshoot scenario, the control module 2 is forced to adopt a slow clock and load-sensing backoff mechanism. The control module 2 dynamically adjusts the backoff step size according to the number of currently conducting power transistors, and actively reduces the adjustment acceleration in combination with historical state detection, effectively preventing secondary voltage drop and oscillation.

[0071] (2) For stable scenarios, control module 2 prioritizes the use of fine-grained control loops composed of small-sized power transistors, and performs linear fine-tuning in conjunction with a slow clock. This strategy significantly reduces the switching frequency of the power transistors and effectively suppresses the LCO phenomenon.

[0072] (3) For ordinary voltage drop scenarios, the control module 2 adopts a conservative adjustment strategy. Under light load, the large step adjustment of the combinational logic feedforward path 22 is actively shielded, and only the digital control logic 23 is allowed to slowly compensate linearly; under heavy load, the combinational logic feedforward path 22 is triggered, and at the same time, the digital control logic 23 achieves smooth current catch-up through the amplitude-limited binary increment strategy to avoid sudden jumps.

[0073] (4) For severe voltage drop scenarios, control module 2 adopts an aggressive adjustment strategy. Driven by the voltage drop detection module and the voltage comparator, the combinational logic feedforward path 22 is used to achieve a fast response without clock wait, quickly injecting a preset large current. During this process, the digital control logic unit 23 enters a fast adjustment state based on a fast clock, and combines the traditional binary exponential step growth to quickly increase the output voltage.

[0074] In a specific embodiment, control module 2 is used to execute the following control logic:

[0075] When the working scenario is an overshoot scenario, the control digital control logic unit 23 adopts a multi-step coarse-grained adjustment mechanism to shut down the large-size power transistors, and dynamically adjusts the required number of large-size power transistors to be shut down according to the number of large-size power transistors that have been turned on.

[0076] When the working scenario is a stable scenario, the control digital control logic unit 23 uses a single-step fine-grained adjustment mechanism to turn the small-size power transistor on or off according to the second state signal.

[0077] When the operating scenario is a normal voltage drop scenario, the circuit load is determined as heavy or light based on the number of large-size power transistors that are already turned on. When the circuit load is heavy, the combinational logic feedforward path 22 is triggered to directly turn on M1 large-size power transistors, and the digital control logic 23 is controlled to turn on the large-size power transistors in parallel using a limited binary search method. When the circuit load is light, the digital control logic 23 is directly controlled to turn on the large-size power transistors in parallel using a limited binary search method.

[0078] When the operating scenario is a severe voltage drop scenario, the combinational logic feedforward path 22 is triggered to directly turn on M2 large-size power transistors, and the digital control logic unit 23 is controlled to turn on the large-size power transistors in parallel using the traditional binary search method.

[0079] In a specific embodiment, when the working scenario is a stable scenario, if the second state signal is a high-level signal, the digital control logic unit 23 turns on the small-sized power transistor according to the single-step fine-grained adjustment mechanism; if the second state signal is a low-level signal, the digital control logic unit 23 turns off the small-sized power transistor according to the single-step fine-grained adjustment mechanism.

[0080] When the working scenario is a normal voltage drop scenario, if the number of large-size power transistors that have been turned on is greater than the number threshold, the circuit load is determined to be heavy; if the number of large-size power transistors that have been turned on is less than or equal to the number threshold, the circuit load is determined to be light.

[0081] The combinational logic feedforward path 22 is allowed to be triggered only once in N cycles.

[0082] Specifically, in the embodiments of this application, a stable scenario is defined as the scenario where the load voltage OUT at the current time step is stable near the reference voltage, and the system's operating path is as follows: Figure 5 As shown. In this application, the stable range of the load voltage OUT at the current time step is defined as the reference voltage V. REFH and V REFL This region is called the stable region. Therefore, upon entering this region, the first, third, and fourth voltage comparators will output logic "0", corresponding to a low-level signal. This indicates that the load voltage OUT at the current time step is in the stable region among the four voltage regions: high voltage, stable, low voltage, and extremely low voltage. At this time, the outputs of the first, third, and fourth voltage comparators will remain low due to the relationship between the load voltage OUT at the current time step and the corresponding three reference voltages. The status feedback of the load voltage OUT at the current time step mainly comes from the second voltage comparator in sampling module 1. Subsequently, the digital control logic unit 23 will receive the output signal CMP from the voltage comparators. OUTAs a control signal, this control signal has a width of 4 bits. From the least significant bit to the most significant bit, it represents the output signals of the first, second, third, and fourth voltage comparators, respectively. These signals are provided to the digital control logic unit 23 for processing, characterizing the load voltage state at the current time step. When the load voltage OUT at the current time step is lower than the reference voltage V... REFR When the output signal of the second voltage comparator is high, the output logic "1" will be output, which corresponds to a high-level signal. This indicates that the digital control logic 23 needs to turn on a certain number of power transistors to supplement the current in order to increase the load voltage OUT of the next time step. Otherwise, the output logic "0" will be output, which corresponds to a low-level signal. The digital control logic 23 will turn off a certain number of power transistors.

[0083] In a stable scenario, the outputs of the first, third, and fourth voltage comparators will stabilize at a low level. These three data points, all logic "0", will be used as inputs by the digital control logic unit 23. In this case, the digital control logic unit 23 will switch from a multi-step coarse-grained adjustment mode to a single-step fine-grained adjustment mode. In the multi-step coarse-grained adjustment mode, the digital control logic unit 23 regulates a large array of 128 power transistors. The 128-bit control signal output by the digital control logic unit 23 is used to drive the large power transistors to turn on or off. Because the large power transistors have a large current, their regulation capability is strong, hence the coarse-grained nature. "Multi-step" indicates that the digital control logic unit 23 adjusts more than one power transistor per cycle under a single master clock. For the single-step fine-grained adjustment mechanism, the number of power transistors adjusted per cycle under a single master clock is 1. Furthermore, the digital control logic unit 23 regulates a 32-cell array of small-sized power transistors. In this mode, the 32-bit control signal output by the digital control logic unit 23 drives the small-sized power transistors. This switching process effectively disables the control of the large-sized power transistors and enables linear control of the small-sized power transistors, thus preventing excessive adjustment amplitudes that could lead to oscillations. In this mode, the coarse-grained adjustment loop controlling the large-sized power transistor array is locked, maintaining a constant number of active transistors to provide a stable reference current. The adjustment task is entirely transferred to the single-step fine-grained adjustment loop controlling the small-sized power transistor array. The single-step fine-grained adjustment loop consistently uses a slow clock CLK after frequency division. slow The control logic performs linear shift operations on the control words of the power transistor array 3 one by one to achieve the minimum resolution current step. In the embodiments of this application, based on slow clock low-frequency operation, combined with single-step fine-grained adjustment loop and small-size power transistor array, the dynamic power consumption of the system under stable conditions can be significantly reduced. The fine compensation also effectively alleviates the LCO phenomenon caused by comparator synchronization quantization, and improves the smoothness and stability of the output voltage.

[0084] Specifically, when the system experiences a step change from high current load demand to low current load demand, the load voltage OUT at the current time step will exhibit an upward overshoot phenomenon. Therefore, this is defined as an overshoot scenario in the embodiments of this application. In the embodiments of this application, when the load voltage OUT at the current time step exceeds the reference voltage V... REFH The corresponding first voltage comparator will output a logic "1", corresponding to a high-level signal, indicating that the load voltage OUT at the current time step is at a high level, resulting in voltage overshoot. A certain number of power transistors need to be turned off to adjust the load voltage OUT at the next time step; this is the control word rollback operation. For the scenario where the load voltage OUT at the current time step experiences overshoot, the system's operating path is as follows: Figure 6 As shown. In this scenario, the load voltage OUT at the current time step is in the high-voltage region of sampling module 1, and the system mainly consists of V REFH The first voltage comparator, which serves as the reference voltage, is responsible for sensing in this state. Once the first voltage comparator detects that the voltage has deviated from V in a cycle... REFH This threshold, CMP OUT V corresponds to REFH When the output of the first voltage comparator, which serves as the reference voltage, changes from logic "1" to logic "0", the system will exit the overshoot scenario control.

[0085] Since the overshoot scenario has deviated from a stable state, maintaining the original single-step fine-grained control loop as the control logic would lengthen the system's settling time, meaning the unstable overshoot state would persist for a longer period. Unstable voltages often cause potential damage to the system; therefore, digital LDO systems need to maximize their ability to handle sudden events. In this scenario, the digital LDO system of this application will utilize a multi-step coarse-grained control loop as the core control logic, no longer limiting the control step size to a single-step linear adjustment. Correspondingly, the power transistor array 3 corresponding to the control logic is changed from a small-size power transistor array to a large-size power transistor array to achieve greater control strength.

[0086] Considering that the impact of the same rollback operation varies under different load demands, and that there is a delay between the system completing the adjustment and the corresponding voltage change, over-regulation is highly likely. Therefore, in scenarios involving voltage overshoot, the system will select a slow clock CLK. slowAs the master clock, the system employs a tiered backoff step design to ensure sufficient regulation capability while avoiding over-regulation. The current load state is determined by calculating the number of currently active power transistors (TUFs). In one example, when the number of active large-size power transistors exceeds 96, the circuit load is considered heavy, and the corresponding backoff step is set to 8, meaning that eight large-size power transistors can be turned off simultaneously in a single control operation. When the number of active large-size power transistors is between 64 and 96, the circuit load is considered medium, and the backoff step is set to 4. When the number of active large-size power transistors is between 32 and 64, the circuit load is considered low, and the backoff step is set to 2. When the number of active large-size power transistors is less than 32, the backoff step is set to 1. This tiered backoff step design allows the system to maintain rapid regulation capability under high current and maintain regulation accuracy and stability under low current.

[0087] Specifically, when the load experiences a step change from low current demand to high current demand, the load voltage OUT at the current time step will exhibit a downward undershoot, i.e., a voltage drop. When an overshoot occurs in a digital LDO system, the output voltage usually does not exceed the input voltage, but the voltage drop is more pronounced. The supply voltage is inextricably linked to the timing of digital circuits; the lower the voltage, the greater the delay of each unit. Therefore, voltage drops can easily lead to timing or functional problems in the system. In the embodiments of this application, the voltage drop handling of the digital LDO system is divided into two parts: a normal voltage drop scenario and a severe voltage drop scenario. Reference voltage V REFL and V REFLL The area between is defined as the low-pressure area, when V is detected. REFL and V REFLL The corresponding voltage comparator outputs are logic "1" and logic "0" respectively, indicating that the load voltage OUT at the current time step is in a low-voltage state, which represents a normal voltage drop scenario in the system. In this scenario, the system's operating path is as follows: Figure 7 As shown.

[0088] Since the normal voltage drop scenario indicates that the load voltage OUT at the current time step is in the low-voltage region of sampling module 1, the system mainly consists of V REFL and V REFLL The third and fourth voltage comparators, which serve as reference voltages, are responsible for sensing in this state. When the third and fourth voltage comparators sense that the load voltage OUT at the current time step is higher than V, they will perform this sensing operation. REFL or below V REFLL CMP OUT China-Israel V REFL and V REFLLThe outputs of the third and fourth voltage comparators, which serve as reference voltages, will change from logic "1" to logic "0" and from logic "0" to logic "1" respectively. At this point, the system will break away from the control of the normal voltage drop scenario and enter the severe voltage drop scenario.

[0089] To improve the regulation capability of digital LDO systems in ordinary voltage drop scenarios, embodiments of this application change the graded back-off strategy of digital control logic 23 in overshoot scenarios to a binary search strategy. The traditional binary search strategy, compared to the linear regulation of synchronous circuits, can grow exponentially with the cycle. If the total number of controls is N, the time complexity of the binary search strategy is reduced from N for linear regulation to log₂N. However, for digital LDO systems, due to the large step size adjustment in the traditional binary search strategy, this strategy can only achieve rapid regulation when the system requires significant compensation, while over-regulation is prone to occur in other scenarios. Therefore, this strategy sacrifices stability to some extent. To balance speed and stability, embodiments of this application limit the maximum step size of the binary search in ordinary voltage drop scenarios, i.e., using a limited binary search method. Since ordinary voltage drop scenarios often do not require large compensation, embodiments of this application still use a slow clock CLK. slow As the master clock for the control logic, the maximum step size for maximum adjustment is limited to 8, corresponding to a maximum of 8 large-size power transistors that can be controlled in a single control operation. During this process, the step size of the binary search method changes with the slow clock as follows: 1, 2, 4, 8, and then remains at an adjustment step size of 8.

[0090] To further improve the speed of handling voltage drops, embodiments of this application introduce a combinational logic feedforward path 22 under heavy load conditions. When the system is currently under heavy load, once the voltage comparator detects a normal voltage drop, the combinational logic feedforward path 22 will simultaneously activate eight additional large-size power transistors to mitigate the voltage drop. Since the combinational logic feedforward path 22 is purely combinational logic, it is not limited by the clock frequency, thus improving the system's transient response capability. When the combinational logic feedforward path 22 is active, the control signals for the eight activated large-size power transistors are driven by combinational logic. Once the load voltage OUT of the current time step leaves the low-voltage region, these eight large-size power transistors will turn off. This leads to a situation where, after the combinational logic feedforward path 22 is activated, the load voltage OUT of the current time step is pulled up to leave the low-voltage region, then the combinational logic feedforward path 22 is turned off, the power transistor array 3 is turned off, and the load voltage OUT of the current time step falls back to the low-voltage region, resulting in repeated oscillations. To avoid oscillations, a cooling mechanism is defined in the embodiments of this application. If an asynchronous operation has occurred within 10 cycles, the combinational logic feedforward path 22 will not be reactivated within those 10 cycles. Furthermore, the embodiments of this application constrain the combinational logic feedforward path 22 to be activated only under heavy load conditions; under light load conditions, it will be automatically ignored, preventing oscillations caused by excessive adjustment gradients. To ensure system stability, while the combinational logic feedforward path 22 drives the power transistor array 3, the synchronous digital control logic unit 23 gradually takes over the driving operation of the feedforward combinational logic path using a limited binary method over the cycle. This takeover mechanism ensures that even when the feedforward combinational logic path exits, the internal control word has accumulated to the corresponding level, thereby eliminating the risk of voltage drop due to the removal of the feedforward combinational logic path. If the output voltage is still in the low-voltage region after the takeover is completed, the digital control logic unit 23 will reset the exponential growth logic based on the current conduction state and continue to execute the limited binary method adjustment until the voltage recovers.

[0091] Specifically, when the system load current demand experiences a step change from low to high, causing the load voltage OUT at the current time step to enter the extremely low voltage region of voltage sampling module 1, this corresponds to a severe voltage drop scenario in the digital LDO system. In this state, the system's operating path is as follows: Figure 8 As shown.

[0092] In the embodiments of this application, the reference voltage V REFLL The region below is defined as an extremely low pressure region, when V is detected. REFLLWhen the corresponding voltage comparator outputs are logic "1", it indicates that the load voltage OUT at the current time step is in an extremely low voltage state. This is the second scenario for digital LDO systems to handle voltage drops. In this case, the voltage drop is significant, requiring more aggressive adjustment measures to mitigate its continued increase. Therefore, in this scenario, the system is mainly composed of voltages starting from V... REFLL The fourth voltage comparator, which serves as the reference voltage, is responsible for sensing in this state.

[0093] Because the load current demand step corresponding to a severe voltage drop is too large, it can easily lead to instability or even errors in the load circuit. Therefore, more effective measures are needed to cope with large step changes. The embodiments of this application implement more aggressive strategy optimizations at two levels: sampling of the load voltage OUT at the current time step and processing of the voltage drop. Regarding voltage drop processing, the digital control logic 23 still uses a multi-step long coarse-grained adjustment loop in conjunction with a large-size power transistor array for adjustment. However, unlike ordinary voltage drop scenarios, the main clock of the control logic will switch to the fast clock CLK at this time. fast The fast clock will drive the digital control logic unit 23 at a frequency four times that of the slow clock. Furthermore, compared to normal voltage drop scenarios, severe voltage drop scenarios require greater adjustment. Therefore, in selecting the control strategy, the design retains the traditional binary exponential increase strategy, but in this scenario, there is no limit to the maximum adjustment step size. Control module 2 will use the traditional binary strategy based on the fast clock to perform exponential adjustment to turn on the large-size power transistor.

[0094] To address scenarios with severe voltage drops and further improve the system's transient response, embodiments of this application integrate the control of the voltage drop detector, the combinational logic feedforward path 22, and the power transistor array 3. The output VD of the voltage drop detector also serves as the control signal for the feedforward combinational logic path; once VD goes high, the feedforward combinational logic path is triggered, such as... Figure 9 As shown. From the voltage drop detector to the combinational logic feedforward path 22, and then to the control of the power transistor array 3, this path is completely asynchronous. Therefore, this asynchronous combinational path can improve the voltage drop handling capability of the digital LDO system from both the sampling module 1 and the control module 2. The asynchronous combinational path allows the embodiments of this application to drive subsequent control logic based on events. Once the voltage drop detector detects the generation of a large voltage drop, VD will go high, and the control signal ELL of the combinational logic feedforward path 22 will also go high. The combinational logic feedforward path 22 will drive a large number of power transistors to be turned on simultaneously, and the digital LDO system will inject more current to the load to meet the load's current demand.

[0095] Similar to the handling of ordinary voltage drop scenarios, in order to ensure the stability and reliability of the design, the control signals of the power transistor array 3 still need to be taken over by the digital control logic 23. After the system detects that VD is pulled high to activate the combinational logic feedforward path 22, the digital control logic 23 will gradually take over the large-size power transistors based on a fast clock and a traditional binary search strategy to achieve implicit control switching.

[0096] Compared to normal voltage drop scenarios, severe voltage drop requires more aggressive handling. Therefore, the number of PMOS power transistors controlled by the combinational logic feedforward path 22 in a single operation will increase from 8 to 64. When the combinational logic feedforward path 22 is triggered, it will directly drive the activation of an additional 64 large-size power transistors on top of the current power transistor array 3. If the number of unactivated large-size power transistors is less than 64, all 128 large-size power transistors will be activated.

[0097] Since the pulse time of VD generated by the voltage drop detector is independent of the voltage state and determined by its own structure, the voltage OUT may not rise to the reference voltage V. REFLL The above describes the situation where VD is pulled low. In this case, the combinational logic feedforward path 22 will be turned off, causing the voltage to continue to decrease. To solve this problem, embodiments of this application set the control signal of the combinational logic feedforward path 22 to be jointly controlled by a voltage comparator and a voltage drop detector, with the two being complementary OR logic, such as... Figure 10 As shown, the output VELL of the fourth voltage comparator and the output VD of the voltage drop detector are connected to an OR gate module. If either of them is high, the output of the OR gate module will also be high. The output of the OR gate module is connected to the combinational logic feedforward path 22 and serves as a control input to activate this path. Once the OR gate module output is pulled high, the combinational logic feedforward path 22 is activated. The output of the combinational logic feedforward path 22 will replace the digital control logic 23 to take control of the portion of the large-size power transistors that need to be turned on at once, used to quickly turn on a certain number of power transistors and adjust the excessively low voltage OUT. VD is responsible for detecting voltage changes before the voltage comparator is activated, acting as an early warning and activating the combinational logic feedforward path 22 before the voltage comparator takes effect. The output VELL of the voltage comparator is responsible for maintaining the open state of the combinational logic feedforward path 22, acting as a voltage holder. After the VD signal disappears, the output of the voltage comparator remains valid, and the power transistors already turned on by the combinational logic feedforward path 22 can remain on. The coordinated control of these two components combines their respective advantages in voltage control, preventing further voltage drops.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An event-driven, all-digital low-dropout linear regulator, characterized in that, The system includes a sampling module, a control module, and a power transistor array. The sampling module acquires the load voltage at the current time step and detects the voltage state and voltage drop, outputting a voltage state signal and a large voltage drop signal. The control module includes a scenario determination module, a fast / slow dual-clock driving module, a combinational logic feedforward path, and a digital control logic unit. The voltage state signal and the large voltage drop signal are input to the control module. The scenario determination module determines the operating scenario of the digital control logic unit based on the received voltage state signal and the large voltage drop signal. The fast / slow dual-clock driving module determines whether the fast clock or the slow clock is the master clock based on the received voltage state signal. The control module determines the adjustment mechanism adopted by the digital control logic unit to control the power transistor array under the master clock based on the operating scenario. It selects whether to trigger the combinational logic feedforward path based on the voltage state signal or the large voltage drop signal, the operating scenario, and the circuit load. If the combinational logic feedforward path is triggered, it directly controls the power transistor array to turn on. By controlling the power transistor array to turn on or off, the load voltage at the next time step is adjusted.

2. The event-driven, all-digital low-dropout linear regulator according to claim 1, characterized in that, The power transistor array includes a small-size power transistor array and a large-size power transistor array. The small-size power transistor array contains several small-size power transistors, and the large-size power transistor array contains several large-size power transistors. The adjustment mechanism adopted by the digital control logic unit to control the power transistor array under the master clock includes a single-step fine-grained adjustment mechanism and a multi-step coarse-grained adjustment mechanism. The single-step fine-grained adjustment mechanism is used to adjust the on or off of a small-size power transistor in a single master clock cycle, and the multi-step coarse-grained adjustment mechanism is used to adjust the on or off of more than one large-size power transistor in a single master clock cycle.

3. The event-driven all-digital low-dropout linear regulator according to claim 2, characterized in that, The sampling module includes a first voltage comparator, a second voltage comparator, a third voltage comparator, a fourth voltage comparator, and a voltage drop detector. The first, second, third, and fourth voltage comparators are used to compare the load voltage at the current time step with the first, second, third, and fourth reference voltages, respectively, and output a first state signal, a second state signal, a third state signal, and a fourth state signal based on the comparison results, which constitute the voltage state signal. The voltage drop detector is used to detect the voltage drop of the load voltage at the current time step and generate a large voltage drop signal.

4. The event-driven all-digital low-dropout linear regulator according to claim 3, characterized in that, The operating scenarios include overshoot scenario, stable scenario, normal voltage drop scenario, and severe voltage drop scenario. The voltage status signal and the large voltage drop signal are input to the scenario determination module in the control module. When the first status signal is a high-level signal, the operating scenario is determined to be an overshoot scenario; when the first status signal, the third status signal, and the fourth status signal are all low-level signals, the operating scenario is determined to be a stable scenario; when the third status signal is a high-level signal and the fourth status signal is a low-level signal, the operating scenario is determined to be a normal voltage drop scenario; when the fourth status signal or the large voltage drop signal is a high-level signal, the operating scenario is determined to be a severe voltage drop scenario.

5. The event-driven all-digital low-dropout linear regulator according to claim 4, characterized in that, The control module is used to execute the following control logic: When the working scenario is an overshoot scenario, the digital control logic unit uses a multi-step coarse-grained adjustment mechanism to shut down the large-size power transistors, and dynamically adjusts the required number of large-size power transistors to be shut down according to the number of large-size power transistors that have been turned on. When the working scenario is a stable scenario, the digital control logic unit controls the small-size power transistor to turn on or off according to the second state signal using a single-step fine-grained adjustment mechanism. When the operating scenario is a normal voltage drop scenario, the circuit load is determined to be either heavy or light based on the number of large-size power transistors that are already turned on. When the circuit load is heavy, the combinational logic feedforward path is triggered to directly turn on M1 large-size power transistors, and the digital control logic is controlled to turn on the large-size power transistors in parallel using a limited binary search method. When the circuit load is light, the digital control logic is directly controlled to turn on the large-size power transistors in parallel using a limited binary search method. When the operating scenario is a severe voltage drop scenario, the combinational logic feedforward path is triggered to directly turn on M2 large-size power transistors, and the digital control logic is controlled to turn on the large-size power transistors in parallel using the traditional binary search method.

6. The event-driven all-digital low-dropout linear regulator according to claim 5, characterized in that, When the operating scenario is a stable scenario, if the second state signal is a high-level signal, the digital control logic unit turns on the small-size power transistor according to the single-step fine-grained adjustment mechanism; if the second state signal is a low-level signal, the digital control logic unit turns off the small-size power transistor according to the single-step fine-grained adjustment mechanism. When the operating scenario is a normal voltage drop scenario, if the number of large-size power transistors that have been turned on is greater than the number threshold, the circuit load is determined to be heavy load; if the number of large-size power transistors that have been turned on is less than or equal to the number threshold, the circuit load is determined to be light load. The combinational logic feedforward path is allowed to be triggered only once within N cycles.

7. The event-driven all-digital low-dropout linear regulator according to claim 5, characterized in that, Compared to the traditional bisection method, the step size of the amplitude-limited bisection method is limited by the maximum step size.

8. The event-driven all-digital low-dropout linear regulator according to claim 4, characterized in that, When the fast and slow dual-clock driving module determines that the fourth state signal is a high-level signal, it determines that the fast clock is the master clock; when it determines that the fourth state signal is a low-level signal, it determines that the slow clock is the master clock.

9. The event-driven all-digital low-dropout linear regulator according to claim 2, characterized in that, The first, second, third, and fourth voltage comparators are all voltage comparators. Each voltage comparator includes a cross-coupled NAND gate module, a NOT gate module, and a cross-coupled NOR gate module. The input ports of the NAND gate module are the negative port, the positive port, and the master clock, respectively. The voltages input to the negative and positive ports are compared using the cross-coupled NAND gate module. The output signal of the NAND gate module is inverted by the NOT gate module and then input to the NOR gate module. The NOR gate module forms an SR latch, which is used to restore the inverted logic and latch the output signal of the voltage comparator.

10. The event-driven all-digital low-dropout linear regulator according to claim 2, characterized in that, The voltage drop detector includes a capacitor, a NAND gate module, a NOT gate module, and a buffer connected in sequence; one end of the capacitor is input to the load voltage of the current time step, and the other end is connected to two NAND gate modules whose inputs are in a short-circuit state.

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