Semiconductor structure with self-adjusting multi-layer spacer matrix for high-density transistor arrays and methods for their formation

Abstract

A method for forming a semiconductor structure, comprising: forming a two-dimensional array of discrete dielectric template structures (42T) over a substrate (8), wherein the discrete dielectric template structures (42T) are spaced apart from one another by trenches (41); forming a first dielectric spacer matrix layer (44) by depositing a first dielectric spacer material in lower sections of the trenches (41); forming a second dielectric spacer matrix layer (46) by depositing a second dielectric spacer material in upper sections of the trenches (41); forming a pair of a source cavity (51) and a drain cavity (59) within a volume of each of the discrete dielectric template structures (42T); forming a source electrode (52) and a drain electrode (56) in each source cavity (51) and drain cavity (59), respectively.each drain cavity (59); and forming gate electrodes (15) before and after the formation of the two-dimensional array of discrete dielectric template structures (42T), thereby forming a two-dimensional array of field-effect transistors (701).

Description

RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US application serial no. 63 / 287,741, filed on December 9, 2021, entitled “Semiconductor Device and Manufacturing Method Thereof”, the entire contents of which are hereby incorporated by reference into the present text. BACKGROUND

[0002] A wide variety of transistor structures have been developed to meet different design criteria. Thin-film transistors (TFTs) made from oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because TFTs can be processed at low temperatures and therefore do not damage previously manufactured components. For example, the manufacturing conditions and techniques do not damage previously manufactured front-end-of-line (FEOL) and middle-end-of-line (MEOL) components. List of characters

[0003] Aspects of this disclosure are best understood by referring to the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion.

[0004] Among figures identified by a combination of a figure number and an alphabetical suffix, figures with the same figure number correspond to the same processing step. Among figures with a figure number in the range of 2 to 12, figures labeled with a combination of a figure number and the alphabetical suffix "A" are top views. Among figures with a figure number in the range of 2 to 12, figures labeled with a combination of a figure number and an alphabetical suffix selected from "B", "C", "D", or "E" are vertical cross-sectional views along a vertical plane B-B', C-C', D-D', or E-E' of a structure illustrated in a figure labeled with the same figure number and the alphabetical index "A".In figures with a number of figures in the range of 2 to 12, the vertical cross-sectional planes B - B', C - C', D - D' and E - E' are shown in different top views or different vertical cross-sectional views. Fig. Figure 1 is a vertical cross-sectional view of a first exemplary structure after the formation of complementary metal-oxide-semiconductor transistors (CMOS transistors), first metal interconnect structures formed in dielectric material layers of a lower level, and a dielectric insulating layer according to an embodiment of the present disclosure. Fig. 2A - Fig. Figures 2C are different views of a section of a memory array region of the first exemplary structure after the formation of an in-process insulating layer at a gate level and word lines according to a first embodiment of the present disclosure. Fig. 2A is a top view, and Fig. 2B and Fig. 2C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 2A. Fig. 3A - Fig. Figure 3C shows different views of the section of the memory array region of the first exemplary structure after the formation of gate-connection via structures and gate electrodes according to the first embodiment of the present disclosure. Fig. 3A is a top view, and Fig. 3B and Fig. 3C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 3A. Fig. 4A - Fig. Figures 4C show different views of the section of the memory array region of the first exemplary structure after the formation of a gate dielectric layer, a continuous active layer, a dielectric stencil material layer and a hard mask layer according to the first embodiment of the present disclosure. Fig. 4A is a top view, and Fig. 4B and Fig. 4C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 4A. Fig. 5A - Fig. Figure 5C shows different views of the section of the memory array region of the first exemplary structure after the formation of a structured hard mask layer, discrete dielectric stencil structures and active layers according to the first embodiment of the present disclosure. Fig. 5A is a top view, and Fig. 5B and Fig. 5C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 5A. Fig. 6A - Fig. Figure 6C shows different views of the section of the storage array region of the first exemplary structure after the formation of a dielectric etch stop lining and a first dielectric spacer matrix layer in trenches between the discrete dielectric stencil structures according to the first embodiment of the present disclosure. Fig. 6A is a top view, and Fig. 6B and Fig. 6C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 6A. Fig. 7A - Fig. Figure 7C shows different views of the section of the storage array region of the first exemplary structure after the vertical recession of the first dielectric spacer matrix layer, which is selective for the discrete dielectric stencil structures, according to the first embodiment of the present disclosure. Fig. 7A is a top view, and Fig. 7B and Fig. 7C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 7A. Fig. 8A - Fig. Figure 8C shows different views of the section of the storage array region of the first exemplary structure after the formation of a second dielectric spacer matrix layer in recessed volumes of the trenches according to the first embodiment of the present disclosure. Fig. 8A is a top view, and Fig. 8B and Fig. 8C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 8A. Fig. 9A - Fig. Figure 9D shows different views of the section of the memory array region of the first exemplary structure after the formation of an etch mask material layer, at least one structure transfer support layer and a structured photoresist layer according to the first embodiment of the present disclosure. Fig. 9A is a top view, and Fig. 9B, Fig. 9C and Fig. 9D are vertical cross-sectional views along the vertical plane B - B', C - C' or D - D' of Fig. 9A. Fig. 10A - Fig. Figure 10D shows different views of the section of the storage array region of the first exemplary structure after the formation of source cavities and drain cavities by transferring a structure in the photoresist layer through the discrete dielectric template structures - selectively for the second dielectric spacer matrix layer - according to the first embodiment of the present disclosure. Fig. 10A is a top view, and Fig. 10B, Fig. 10 and Fig. 10D are vertical cross-sectional views along the vertical plane B - B', C - C' or D - D' of Fig. 10A. Fig. 11A - Fig. Figure 11D shows different views of the section of the storage array region of the first exemplary structure after the deposition of at least one metallic material in the source cavities and the drain cavities according to the first embodiment of the present disclosure. Fig. 11A is a top view, and Fig. 11B, Fig. 11C and Fig. 11D are vertical cross-sectional views along the vertical plane B - B', C - C' or D - D' of Fig. 11A. Fig. 12A - Fig. Figure 12E shows different views of the section of the storage array region of the first exemplary structure after the formation of source electrodes and drain electrodes according to the first embodiment of the present disclosure. Fig. 12A is a top view, and Fig. 12B, Fig. 12C, Fig. 12D and Fig. 12E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 12A. Fig. 13A - Fig. Figure 13E shows different views of the section of the storage array region of the first exemplary structure after the formation of at least one first dielectric material layer at the interconnect level and first metal interconnect structures at the interconnect level according to the first embodiment of the present disclosure. Fig. 13A is a top view, and Fig. 13B, Fig. 13C, Fig. 13D and Fig. 13E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 13A. Fig. 14A - Fig. Figure 14E shows different views of the section of the storage array region of the first exemplary structure after the formation of at least one second dielectric material layer at the interconnect level and second metal interconnect structures at the interconnect level according to the first embodiment of the present disclosure. Fig. 14A is a top view, and Fig. 14B, Fig. 14C, Fig. 14D and Fig. 14E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 14A. Fig. 15A - Fig. Figure 15E shows different views of the section of the storage array region of the first exemplary structure after the formation of a two-dimensional array of capacitor structures according to the first embodiment of the present disclosure. Fig. 15A is a horizontal cross-sectional view along the line shown in the Fig. 15B - Fig. 15E shown horizontal plane A - A', and Fig. 15B, Fig. 15C, Fig. 15D and Fig. 15E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 15A. Fig. 16A - Fig. Figure 16E shows different views of the section of the memory array region of a first alternative arrangement of the first exemplary structure after the formation of a two-dimensional array of resistive storage elements according to the first embodiment of the present disclosure. Fig. 16A is a horizontal cross-sectional view along the line shown in the Fig. 16B - Fig. 16E shown horizontal plane A - A', and Fig. 16B, Fig. 16C, Fig. 16D and Fig. 16E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 16A. Fig. Figure 17 is a vertical cross-sectional view of the first exemplary structure after the formation of additional dielectric material layers at the connection level and additional metal interconnect structures of an upper level according to the first embodiment of the present disclosure. Fig. 18A - Fig. Figure 18C shows different views of the section of the storage array region of a second alternative arrangement of the first exemplary structure after the formation of source electrodes and drain electrodes according to the first embodiment of the present disclosure. Fig. 18A is a top view, and Fig. 18B and Fig. 18C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 19A. Fig. 19A - Fig. 19C are different views of the section of the storage array region of a third alternative arrangement of the first exemplary structure after the formation of source electrodes and drain electrodes according to the first embodiment of the present disclosure. Fig. 19A is a top view, and Fig. 19B and Fig. 19C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 19A. Fig. 20A - Fig. 20C are different views of the section of the storage array region of a second alternative arrangement of the first exemplary structure after the formation of source electrodes and drain electrodes according to the first embodiment of the present disclosure. Fig. 20A is a top view, and Fig. 20B and Fig. 20C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 20A. Fig. 21A - Fig. 21C are different views of the section of a memory array region of a second exemplary structure after the formation of a two-dimensional array of memory structures and interconnect-level metal interconnect structures embedded in interconnect-level dielectric material layers, according to a second embodiment of the present disclosure. Fig. 21A is a top view, and Fig. 21B and Fig. 21C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 21A. Fig. 22A - Fig. Figure 22C shows different views of the section of the memory array region of the first exemplary structure after the formation of a gate dielectric layer, a continuous active layer, a dielectric stencil material layer and a hard mask layer according to the first embodiment of the present disclosure. Fig. 22A is a top view, and Fig. 22B and Fig. 22C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 22A. Fig. 23A - Fig. Figure 23C shows different views of the section of the memory array region of the second exemplary structure after the formation of a structured hard mask layer and discrete dielectric stencil structures according to the second embodiment of the present disclosure. Fig. 23A is a top view, and Fig. 23B and Fig. 23C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 23A. Fig. 24A - Fig. Figure 24C shows different views of the section of the storage array region of the second exemplary structure after the formation of a dielectric etch stop lining and a first dielectric spacer matrix layer in trenches between the discrete dielectric stencil structures according to the second embodiment of the present disclosure. Fig. 24A is a top view, and Fig. 24B and Fig. 24C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 24A. Fig. 25A - Fig. Figure 25C shows different views of the section of the storage array region of the second exemplary structure after the vertical recession of the first dielectric spacer matrix layer, which is selective for the discrete dielectric stencil structures, according to the second embodiment of the present disclosure. Fig. 25A is a top view, and Fig. 25B and Fig. 25C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 25A. Fig. 26A - Fig. Figure 26C shows different views of the section of the storage array region of the second exemplary structure after the formation of a second dielectric spacer matrix layer in recessed volumes of the trenches according to the second embodiment of the present disclosure. Fig. 26A is a top view, and Fig. 26B and Fig. 26C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 26A. Fig. 27A - Fig. Figure 27D shows different views of the section of the storage array region of the second exemplary structure after the formation of an etch mask material layer, at least one structure transfer support layer and a structured photoresist layer according to the second embodiment of the present disclosure. Fig. 27A is a top view, and Fig. 27B, Fig. 27C and Fig. 27D are vertical cross-sectional views along the vertical plane B - B', C - C' or D - D' of Fig. 27A. Fig. 28A - Fig. Figure 28D shows different views of the section of the storage array region of the second exemplary structure after the formation of source cavities and drain cavities by transferring a structure in the photoresist layer through the discrete dielectric template structures - selectively for the second dielectric spacer matrix layer - according to the second embodiment of the present disclosure. Fig. 28A is a top view, and Fig. 28B, Fig. 28C and Fig. 28D are vertical cross-sectional views along the vertical plane B - B', C - C' or D - D' of Fig. 28A. Fig. 29A - Fig. Figure 29D shows different views of the storage array region section of the second exemplary structure after the deposition of at least one metallic material in the source cavities and the drain cavities according to the second embodiment of the present disclosure. Fig. 29A is a top view, and Fig. 29B, Fig. 29C and Fig. 29D are vertical cross-sectional views along the vertical plane B - B', C - C' or D - D' of Fig. 29A. Fig. 30A - Fig. Figure 30E shows different views of the section of the storage array region of the second exemplary structure after the formation of source electrodes and drain electrodes according to the second embodiment of the present disclosure. Fig. 30A is a top view, and Fig. 30B, Fig. 30°C Fig. 30D and Fig. 30E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 30A. Fig. 31A - Fig. Figure 31E shows different views of the section of the memory array region of the second exemplary structure after the formation of a two-dimensional array of active layers according to the second embodiment of the present disclosure. Fig. 31A is a top view, and Fig. 31B, Fig. 31C, Fig. 31D and Fig. 31E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 31A. Fig. 32A - Fig. Figure 32E shows different views of the section of the storage array region of the second exemplary structure after the formation of a gate dielectric layer and gate electrodes according to the second embodiment of the present disclosure. Fig. 32A is a top view, and Fig. 32B, Fig. 32C, Fig. 32D and Fig. 32E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 32A. Fig. 33A - Fig. Figure 33E shows different views of the section of the memory array region of the second exemplary structure after the formation of an insulating layer on a gate level according to the second embodiment of the present disclosure. Fig. 33A is a horizontal cross-sectional view along the horizontal plane A - A' of the Fig. 33B, Fig. 33C, Fig. 33D and Fig. 33E, and the Fig. 33B, Fig. 33C, Fig. 33D and Fig. 33E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 33A. Fig. 34A - Fig. Figure 34C shows different views of a section of a memory array region of a third exemplary structure after the formation of an in-process insulating layer at a gate level and word lines according to a third embodiment of the present disclosure. Fig. 34A is a top view, and Fig. 34B and Fig. 34C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 34A. Fig. 35A - Fig. Figure 35C shows different views of the storage array region section of the third exemplary structure after the formation of a two-dimensional array of stacks consisting of a gate electrode, a dielectric barrier layer and a charge storage element according to the third embodiment of the present disclosure. Fig. 3A is a top view, and Fig. 3B and Fig. 3C are vertical cross-sectional views along the vertical plane B - B' or C - C' of Fig. 3A. Fig. 36A - Fig. Figure 36E shows different views of the section of the memory array region of the third exemplary structure after the formation of a two-dimensional array of flash memory devices, at least one first dielectric layer at the interconnect level and first metal interconnect structures at the interconnect level according to the third embodiment of the present disclosure. Fig. 36A is a top view, and Fig. 36B, Fig. 36C, Fig. 36D and Fig. 36E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 36A. Fig. 37A - Fig. Figure 37E shows different views of the section of a storage array region of a fourth exemplary structure after the formation of a dielectric tunnel layer and a two-dimensional array of stacks of a charge storage element, a dielectric barrier layer and a gate electrode according to the fourth embodiment of the present disclosure. Fig. 37A is a top view, and Fig. 37B, Fig. 37C, Fig. 37D and Fig. 37E are vertical cross-sectional views along the vertical plane B - B, C - C', D - D' or E - E' of Fig. 37A. Fig. 38A - Fig. Figure 38E shows different views of the section of a memory array region of a fourth exemplary structure after the formation of a two-dimensional array of flash memory devices according to the fourth embodiment of the present disclosure. Fig. 38A is a top view, and Fig. 38B, Fig. 38C, Fig. 38D and Fig. 38E are vertical cross-sectional views along the vertical plane B - B', C - C', D - D' or E - E' of Fig. 38A. Fig. Figure 39 is a vertical cross-sectional view of a fifth alternative arrangement of the first exemplary structure according to the first embodiment of the present disclosure. Fig. Figure 40 is a vertical cross-sectional view of an alternative arrangement of the second exemplary structure according to the second embodiment of the present disclosure. Fig. Figure 41 is a vertical cross-sectional view of an alternative arrangement of the third exemplary structure according to the third embodiment of the present disclosure. Fig. Figure 42 is a vertical cross-sectional view of an alternative arrangement of the fourth exemplary structure according to the fourth embodiment of the present disclosure. Fig. Figure 43 is a vertical cross-sectional view of an alternative arrangement for any of the exemplary structures according to an embodiment of the present disclosure. Fig. Figure 44 is a first flowchart illustrating the general processing steps for manufacturing the semiconductor devices according to an embodiment of the present disclosure. Fig. Figure 45 is a second flowchart illustrating the general processing steps for manufacturing the semiconductor devices according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0006] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.Elements with the same reference numbers refer to the same element, and it is assumed that they have the same material composition and thickness range unless explicitly stated otherwise.

[0007] In general, the structures and methods of this disclosure can be used to form an embedded random access memory (RAM) in back-end-of-line (BEOL) structures in sophisticated nodes. Such an embedded RAM can offer advantages in terms of device density compared to a static random access memory (SRAM). This disclosure uses transistors (for example, thin-film transistors) that have an active layer of semiconducting metal oxide. Therefore, the embedded RAM of this disclosure can have a BEOL structure and, unlike single-crystal silicon-based field-effect transistors or fin field-effect transistors that use single-crystal semiconductor fins, does not occupy any device area at a front-end-of-line (FEOL) level.The RAM access transistors can be formed as thin-film transistors using a self-aligned dielectric matrix. This matrix comprises a first dielectric spacer matrix layer, which, by using a dielectric material with a low k-value, can ensure reduced capacitive coupling between adjacent pairs of access transistors, and a second dielectric spacer matrix layer superimposed on the first, which acts as a self-aligned etching mask for forming source and drain cavities. In this respect, the source and drain regions are self-aligned to the dielectric matrix, and electrical connections between adjacent access transistors can be avoided. The various embodiments of this disclosure are now described with reference to the accompanying drawings.

[0008] With reference to Fig. Figure 1 illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure comprises a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may have a semiconductor material layer 9, at least in its upper section. The semiconductor material layer 9 may be a surface section of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 contains a single-crystal semiconductor material, such as single-crystal silicon. In another embodiment, the substrate 8 may be a single-crystal silicon substrate containing a single-crystal silicon material.

[0009] Flat-ditch insulation structures 720, containing a dielectric material such as silicon oxide, can be formed in an upper section of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-wells and n-wells, can be formed within any region laterally enclosed by a section of the flat-ditch insulation structures 720. Field-effect transistors 701 can be formed above the top of the semiconductor material layer 9. For example, each field-effect transistor 701 can have a source electrode 732, a drain electrode 738, a semiconductor channel 735 having a surface section of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 can have a single-crystal semiconductor material.Each gate structure 750 can include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 can be formed on each source electrode 732, and a drain-side metal-semiconductor alloy region 748 can be formed on each drain electrode 738.

[0010] The first exemplary structure can include a memory array region 100, in which an array of memory cells can subsequently be formed. The first exemplary structure can further include a peripheral region 200, in which metal wiring for the array of memory devices is arranged. In general, the field-effect transistors 701 in the CMOS circuit 700 can be electrically connected to an electrode of a respective memory cell by a respective set of metal interconnect structures.

[0011] Devices (for example, field-effect transistors 701) in the peripheral region 200 can provide functions that operate the array of memory cells to be subsequently formed. More specifically, devices in the peripheral region can be configured to control the programming, erasing, and sensing (reading) operations of the array of memory cells. For example, the devices in the peripheral region can include a sensing circuit and / or a programming circuit. The devices formed on the top surface of the semiconductor material layer 9 can include complementary metal-oxide-semiconductor transistors (CMOS transistors) and optionally additional semiconductor devices (such as resistors, diodes, capacitor structures, etc.) and are collectively referred to as the CMOS circuit 700.

[0012] One or more of the field-effect transistors 701 in the CMOS circuit 700 can have a semiconductor channel 735 that includes a section of the semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 contains a single-crystal semiconductor material, such as single-crystal silicon, then the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit 700 can have a single-crystal semiconductor channel, such as a channel made of single-crystal silicon. In one embodiment, several field-effect transistors 701 in the CMOS circuit 700 can each have a node that is subsequently electrically connected to a node of a memory cell to be formed subsequently.For example, several field-effect transistors 701 in the CMOS circuit 700 can each have a source electrode 732 or a drain electrode 738, which is then electrically connected to a node of a respective memory cell to be formed subsequently.

[0013] In one embodiment, the CMOS circuit 700 can include a programming control circuit configured to control gate voltages of a set of field-effect transistors 701 used to program a respective memory cell, as well as gate voltages of subsequently formed transistors.In this embodiment, the programming control circuit can be configured to provide a first programming pulse that programs a respective dielectric material layer in a selected memory cell into a first polarization state in which the electrical polarization in the dielectric material layer points to a first electrode of the selected memory cell, and a second programming pulse that programs the dielectric material layer in the selected memory cell into a second polarization state in which the electrical polarization in the dielectric material layer points to a second electrode of the selected memory cell.

[0014] In one embodiment, the substrate 8 can comprise a substrate of single-crystal silicon, and the field-effect transistors 701 can each have a section of the single-crystal silicon substrate as a semiconducting channel. For the purposes of this text, a “semiconducting” element refers to an element with an electrical conductivity in the range of 1.0 × 10⁻⁶. -6 S / cm up to 1.0 × 10 5 S / cm. For the purposes of this text, a "semiconductor material" refers to a material with an electrical conductivity in the range of 1.0 × 10 -6 S / cm up to 1.0 × 10 5 S / cm in the absence of electrical dopants in the material and is able to create a doped material with an electrical conductivity in the range of 1.0 S / cm to 1.0 × 10 5 S / cm can be produced with suitable doping using an electrical dopant.

[0015] According to one aspect of the present disclosure, the field-effect transistors 701 can subsequently be electrically connected to drain electrodes and gate electrodes—and optionally to source electrodes—of access transistors having semiconducting metal oxide plates that are to be formed over the field-effect transistors 701. In one embodiment, a subset of the field-effect transistors 701 can subsequently be electrically connected to at least one of the drain electrodes and gate electrodes.For example, the 701 field-effect transistors can include first word line drivers configured to apply a first gate voltage to first word lines via a first subset of subsequent lower-level metal interconnect structures, and second word line drivers configured to apply a second gate voltage to second word lines via a second subset of the lower-level metal interconnect structures. Furthermore, the 701 field-effect transistors can include bit line drivers configured to apply a bit line bias to subsequent bit lines, and read amplifiers configured to detect electrical current flowing through the bit lines during a read operation.

[0016] Various metal interconnect structures formed within dielectric material layers can subsequently be formed over the substrate 8 and the semiconductor devices (for example, field-effect transistors 701) located thereon. In an illustrative example, the dielectric material layers can, for example, include: a first dielectric material layer 601, which may be a layer surrounding the contact structure connected to the source and drains (sometimes referred to as a dielectric material layer 601 at a contact level), a first dielectric material layer 610 at an interconnect level, and a second dielectric material layer 620 at an interconnect level.The metal interconnect structures can include: device contact via structures 612 formed in the first dielectric material layer 601 and contacting a respective component of the CMOS circuit 700, first metal conductor structures 618 formed in the first dielectric material layer 610 at an interconnect level, first metal via structures 622 formed in a lower section of the second dielectric material layer 620 at an interconnect level, and second metal conductor structures 628 formed in an upper section of the second dielectric material layer 620 at an interconnect level.

[0017] Each of the dielectric material layers (601, 610, 620) can contain a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628) can contain at least one conductive material, which may be a combination of a metallic lining layer (such as a metallic nitride or a metallic carbide) and a metallic filler material. Each metallic lining layer can contain TiN, TaN, WN, TiC, TaC, and WC, and each metallic filler material component can contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metallic lining and metallic filler materials may also be used within the considered scope of the disclosure.In one embodiment, the first metal via structures 622 and the second metal conductor structures 628 can be formed as integrated conductor and via structures by a dual damascus process. The dielectric material layers (601, 610, 620) are referred to in this text as lower-level dielectric material layers. The metal interconnect structures (612, 618, 622, 628) formed within the lower-level dielectric material layers are also referred to in this text as lower-level metal interconnect structures.

[0018] Although the present disclosure is described with reference to an embodiment in which an array of memory cells can be formed above the second dielectric material layer 620 on a conductor and via plane, embodiments in which the array of memory cells can be formed on a different metal interconnect plane are also expressly considered in the present text.

[0019] An array of transistors and an array of memory cells can subsequently be deposited over the dielectric material layers (601, 610, 620) in which the metal interconnect structures (612, 618, 622, 628) have been formed. The set of all dielectric material layers formed prior to the formation of an array of transistors or an array of memory cells is collectively referred to as the dielectric material layers (601, 610, 620) of a lower layer. The set of all metal interconnect structures formed within the dielectric material layers (601, 610, 620) of a lower layer is referred to in this text as the first metallic interconnect structures (612, 618, 622, 628).In general, first metal interconnect structures (612, 618, 622, 628) formed within at least one dielectric material layer (601, 610, 620) of a lower level can be formed above the semiconductor material layer 9 located in the substrate 8.

[0020] According to one aspect of the present disclosure, transistors (for example, thin-film transistors (TFTs)) can subsequently be formed in a metal interconnect layer located above those metal interconnect layers that comprise the dielectric material layers (601, 610, 620) of a lower layer and the first metal interconnect structures (612, 618, 622, 628). In one embodiment, a planar dielectric material layer having a uniform thickness can be formed above the dielectric material layers (601, 610, 620) of a lower layer. The planar dielectric material layer is referred to in this text as an in-process insulating layer 635' on a gate layer.The in-process insulating layer 635' at a gate level contains a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material, and can be deposited by chemical vapor deposition. The thickness of the in-process insulating layer 635' at a gate level can range from 20 nm to 300 nm, although thinner and thicker layers are also possible. Additional insulating layers can be added to the in-process insulating layer 635 at a gate level in subsequent processing steps, thereby increasing its thickness.

[0021] In general, dielectric layers at an interconnect level (such as the dielectric material layer (601, 610, 620) of a lower level), which feature the metal interconnect structures (such as the first metal interconnect structures (612, 618, 622, 628)), can be formed via semiconductor devices. The process-internal insulating layer 635' at a gate level can be formed over the dielectric layers at an interconnect level.

[0022] In one embodiment, the substrate 8 can have a layer of single-crystal semiconductor material (such as a semiconductor material layer 9), and field-effect transistors (such as complementary metal-oxide-semiconductor transistors (CMOS transistors)) can have a corresponding section of the single-crystal semiconductor layer since a corresponding channel region can be formed on the substrate 8. A memory array having a two-dimensional array of unit cell structures can then be placed over the Fig. 1. The first exemplary structure was illustrated.

[0023] With reference to the Fig. 2A - Fig. 2C A photoresist layer (not shown) can be deposited over the process-internal insulating layer 635' at a gate plane and lithographically structured to form a conduction-and-space structure. Each conduction structure in the structured photoresist layer can be spaced laterally along a first horizontal direction hd1 and can extend laterally along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1. In one embodiment, the conduction-and-space structure in the structured photoresist layer can be a periodic structure with a periodicity along the first horizontal direction hd1. A region for forming a unit cell structure is marked with a dashed rectangle labeled "UC" and is referred to in this text as a unit cell region UC.According to one embodiment of the present disclosure, at least four gaps in the conduit-and-gap structure extend laterally through each unit cell region UC. In other words, each unit cell region UC has segments of at least four gap structures.

[0024] An anisotropic etching process can be performed to transfer the structure of the interstices in the photoresist to an upper section of the process-internal insulating layer 635' at a gate plane. In the interstices from which the material of the process-internal insulating layer 635' at a gate plane is removed by the anisotropic etching process, conduit trenches can be formed, which are referred to in this text as word conduit trenches. The word conduit trenches can extend laterally along the second horizontal direction hd2 and can be laterally spaced from each other along the first horizontal direction hd1. In one embodiment, the word conduit trenches can comprise straight conduit trenches with straight sidewalls extending laterally along the second horizontal direction hd2.The word-guiding trenches can have a periodicity along the first horizontal direction hd1 that is the same as the width of the unit cell region UC along the first horizontal direction hd1. In one embodiment, the word-guiding trenches can have the same width along the first horizontal direction hd1, regardless of their position. The depth of the word-guiding trenches can be in a range of 10 nm to 300 nm, such as 30 nm to 100 nm, although smaller or larger thicknesses can also be used. The structured photoresist layer can then be removed, for example, by ashenation.

[0025] At least one metallic material can be deposited in the word conductor trenches. For example, a metallic word conductor lining layer containing a metallic barrier material and a metallic word conductor filler layer containing a metallic filler material can be deposited sequentially in the word conductor trenches and over the process-internal insulating layer 635' at a gate level. The metallic word conductor lining layer can contain a metallic barrier material such as TiN, TaN, WN, TiC, TaC, WC, or a stack thereof, and can be deposited by physical or chemical vapor deposition. Other metallic lining materials are also within the considered scope of the disclosure. The thickness of the metallic word conductor lining layer can be in the range of 1 nm to 30 nm, although smaller and larger thicknesses can also be used.The metallic word-conducting filler layer can contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other metallic filler materials are also within the considered scope of the disclosure. The thickness of the metallic word-conducting filler layer can be chosen such that each of the word-conducting trenches is filled with the combination of the metallic word-conducting lining layer and the metallic word-conducting filler layer.

[0026] A planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed to remove portions of the metallic word line lining layer and the metallic word line filler layer that lie above the horizontal plane encompassing the top of the process-internal insulating layer 635' at a gate level. Each remaining contiguous portion of the metallic word line lining layer and the metallic word line filler layer that fills a respective word line trench forms a word line 3. Each word line 3 may contain a metallic word line lining 4 and a metallic word line filler portion 5. Each metallic word line lining 4 is a portion of the metallic word line lining layer that remains after the planarization process.Each metallic word line filler section 5 is a section of the metallic word line filler layer that remains after the planarization process.

[0027] With reference to the Fig. 3A - Fig. 3C allows an insulating material layer (referred to in this text as an insulating layer at the gate via plane) to be deposited over the in-process insulating layer 635' at a gate plane and to be integrated into the in-process insulating layer 635' at a gate plane. The thickness of the in-process insulating layer 635' at a gate plane can be increased by the thickness of the added insulating material layer, which can be in a range of, for example, 30 nm to 300 nm, such as 60 nm to 150 nm, although smaller and larger thicknesses can also be used.

[0028] Through-hole plating cavities can be formed through the in-process insulating layer 635' at a gate level such that the tops of the word lines 3 at the bottom of each through-hole plating cavity are physically exposed. At least one metallic material can be deposited in the through-hole plating cavities. For example, a metallic through-hole lining layer containing a metallic barrier material and a metallic through-hole filler layer containing a metallic filler material can be deposited sequentially in the through-hole plating cavities and over the in-process insulating layer 635' at a gate level. The metallic through-hole lining layer can contain a metallic barrier material, such as TiN, TaN, WN, TiC, TaC, WC, or a stack thereof, and can be deposited by physical or chemical evaporation.The thickness of the metallic via lining layer can range from 1 nm to 30 nm, although thinner and thicker layers are also possible. The metallic via filler layer can contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. The thickness of the metallic via filler layer can be selected so that each via cavity is filled with the combination of the metallic via lining layer and the metallic via filler layer.

[0029] A planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed to remove portions of the metallic via lining layer and the metallic via filler layer that lie above the horizontal plane encompassing the top of the process-internal insulating layer 635' at a gate plane. Each remaining contiguous portion of the metallic via lining layer and the metallic via filler layer that fills a respective via cavity forms a gate-connection via structure 12. Each gate-connection via structure 12 can have a metallic via lining 13 and a metallic via filler section 14.Each metallic via lining 13 is a section of the metallic via lining layer that remains after the planarization process. Each metallic via filler section 14 is a section of the metallic via filler layer that remains after the planarization process.

[0030] An additional insulating layer (referred to in this text as a gate-plane insulating layer) can be deposited over the in-process insulating layer 635' at a gate plane and can be integrated into the in-process insulating layer 635' at a gate plane. The thickness of the in-process insulating layer 635' at a gate plane can increase by the thickness of the added insulating layer, which can be in a range of, for example, 30 nm to 300 nm, such as 60 nm to 150 nm, although smaller and larger thicknesses can also be used. The in-process insulating layer 635' at a gate plane becomes a gate-plane insulating layer 635 whose thickness does not increase in subsequent processing steps.

[0031] Gate cavities (not shown) can be formed through the insulating layer 635 at a gate plane such that the top surfaces of the gate interconnection vias 12 can be physically exposed at the bottom of the gate cavities. One top surface of a gate interconnection via 12 can be physically exposed at the bottom of each gate cavity.

[0032] In one embodiment, each of the gate cavities can have a rectangular horizontal cross-sectional shape. At least one metallic material can be deposited in the gate cavities. For example, a metallic gate lining layer containing a metallic barrier material and a metallic gate filler layer containing a metallic filler material can be deposited sequentially in the gate cavities and over the insulating layer 635 on a gate plane. The metallic gate lining layer can contain a metallic barrier material, such as TiN, TaN, WN, TiC, TaC, WC, or a stack thereof, and can be deposited by physical or chemical vapor deposition. The thickness of the metallic gate lining layer can be in the range of 1 nm to 30 nm, although thinner and thicker thicknesses can also be used.The metallic gate filler layer can contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. The thickness of the metallic gate filler layer can be selected so that each of the gate cavities is filled with the combination of the metallic gate lining layer and the metallic gate filler layer.

[0033] A planarization process, such as a chemical-mechanical polishing (CMP) process, can be performed to remove sections of the metallic gate lining layer and the metallic gate filler layer that lie above the horizontal plane encompassing the top of the insulating layer 635 on a gate plane. Each remaining contiguous section of the metallic gate lining layer and the metallic gate filler layer filling a respective gate cavity forms a gate electrode 15. Each gate electrode 15 may have a metallic gate lining 16 and a metallic gate filler section 17. Each metallic gate lining 16 is a section of the metallic gate lining layer remaining after the planarization process. Each metallic gate filler section 17 is a section of the metallic gate filler layer remaining after the planarization process.An array of gate electrodes 15 can be formed as a one-dimensional periodic array of gate electrodes 15 with a uniform center-to-center spacing along the first horizontal direction hd1. Alternatively, the array of gate electrodes 15 can be formed as a two-dimensional array of gate electrodes 15 exhibiting a planar overlap with a respective pair of source electrodes and drain electrodes, which are to be formed subsequently.

[0034] With reference to the Fig. 4A - Fig. In step 4C, a gate dielectric layer 10, a continuous active layer 20L, a dielectric template material layer 42L, and a hard mask layer 47L can be sequentially deposited over the insulating layer 635 on a gate plane and the gate electrodes 15. The gate dielectric layer 10 can be formed over the insulating layer 635 on a gate plane and the gate electrodes 15 by depositing at least one gate dielectric material. The gate dielectric material can, for example, be silicon oxide, silicon oxynitride, a dielectric metal oxide (such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.) with a dielectric constant greater than that of silicon nitride (which is 7.9) and is generally referred to as a high k-value dielectric material, or a stack thereof.Other suitable dielectric materials are also within the considered scope of the disclosure. The gate dielectric material can be deposited by atomic layer deposition or chemical evaporation. The thickness of the gate dielectric layer 10 can be in the range of 1 nm to 50 nm, such as 3 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0035] The continuous active layer 20L, which contains a semiconducting material, can be deposited over the gate dielectric layer 10. The continuous active layer 20L can be an unstructured (i.e., overlying) semiconductor material layer. In one embodiment, the continuous active layer 20L can comprise a composite semiconductor material. In one embodiment, the semiconducting material comprises a material which, when appropriately doped with electrical dopants (which can be p-type or n-type dopants), exhibits an electrical conductivity in the range of 1.0 S / m to 1.0 × 10⁻⁶. 5S / m. Examples of semiconducting materials that can be used for the continuous active layer 20L include indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived from these. In general, the continuous active layer 20L can comprise oxides of at least one metal, such as at least two metals and / or at least three metals, selected from In, Zn, Ga, Sn, Pb, Zr, Sr, Ru, Mn, Mg, Nb, Ta, Hf, Al, La, Sc, Ti, V, Cr, Mo, W, Fe, Co, Ni, Pd, Ir, Ag, and any combination thereof. Some of the metallic elements may be present in a dopant concentration, for example, in an atomic percentage of less than 1.0%.Other suitable semiconducting materials also fall within the considered scope of the disclosure. In one embodiment, the semiconducting material of the continuous active layer can contain 20L of indium gallium zinc oxide.

[0036] The continuous active layer 20L can contain a polycrystalline semiconducting material or an amorphous semiconducting material, which can subsequently be annealed to a polycrystalline semiconducting material with a larger average grain size. The continuous active layer 20L can be deposited by physical evaporation, although other suitable deposition processes can also be used. The thickness of the continuous active layer 20L can be in the range of 1 nm to 50 nm, such as 2 nm to 30 nm and / or 4 nm to 15 nm, although smaller and larger thicknesses can also be used.

[0037] The dielectric template material layer 42L contains a dielectric material that can provide electrical insulation between the source and drain electrodes to be subsequently formed. The dielectric template material layer 42L contains a material that can act as a planarization stop layer in subsequent planarization processes. In one embodiment, the dielectric template material layer 42L can comprise and / or consist substantially of undoped silicate glass or doped silicate glass. The thickness of the dielectric template material layer 42L can be in the range of 2 nm to 1,000 nm, such as 5 nm to 200 nm, although smaller and larger thicknesses can also be used.

[0038] The hard mask layer 47L can contain a hard mask material that can be used as an etching mask during a subsequent anisotropic etching process to etch unmasked sections of the dielectric stencil material layer 42L. In one embodiment, the hard mask layer 47L can comprise and / or consist substantially of silicon nitride, silicon carbide nitride, amorphous carbon, or a dielectric metal oxide. The thickness of the hard mask layer 47L can be in the range of 2 nm to 50 nm, although smaller and larger thicknesses can also be used.

[0039] With reference to the Fig. 5A - Fig. 5C can have a photoresist layer (not shown) deposited over the hard mask layer 47L and can be lithographically structured to form a two-dimensional array of structured photoresist material sections. In one embodiment, the two-dimensional array of structured photoresist material sections can be a periodic two-dimensional array of structured photoresist material sections, possessing a first periodicity along the first horizontal direction hd1 and a second periodicity along the second horizontal direction hd2. In one embodiment, the first periodicity can be in a range of 10 nm to 500 nm, and the second periodicity can be in a range of 5 nm to 500 nm, although smaller and larger dimensions can also be used for the first and second periodicities.In one embodiment, each structured photoresist material section can have a rectangular horizontal cross-sectional shape. In another embodiment, the gap between adjacent pairs of structured photoresist material sections can be in a range of 1 nm to 40 nm, such as 2 nm to 20 nm and / or 3 nm to 10 nm, although smaller and larger dimensions can also be used for each gap. In another embodiment, a single rectangular structured photoresist material section can be formed in each unit cell region UC.

[0040] An anisotropic etching process can be performed to transfer the structure in the structured photoresist material sections through the hard mask layer 47L, the dielectric template material layer 42L, and the continuous active layer 20L. The structure in the structured photoresist material sections can be replicated in the structured sections of the hard mask layer 47L, in the structured sections of the dielectric template material layer 42L, and in the structured sections of the continuous active layer 20L. The structured sections of the hard mask layer 47L are collectively referred to as a structured hard mask layer 47. The structured sections of the dielectric template material layer 42L form a two-dimensional array of discrete dielectric template structures 42T.The structured sections of the continuous active layer 20L form a two-dimensional array of active layers 20.

[0041] In one embodiment, the sidewalls of the structured hard mask layer 47 can be vertical or substantially vertical. In another embodiment, the sidewalls of the discrete dielectric stencil structures 42T can be vertical or substantially vertical. In yet another embodiment, the sidewalls of the active layers 20 can be vertical or substantially vertical. The structured hard mask layer 47 can be used as an etch mask structure at least during a final stage of the anisotropic etching process and can improve the vertical profile of the sidewalls of the discrete dielectric stencil structures 42T and the sidewalls of the active layers 20. In other words, the sidewalls of the discrete dielectric stencil structures 42T and the sidewalls of the active layers 20 can be made more vertical by using the structured hard mask layer 47.The structured photoresist material sections can be consumed during the anisotropic etching process, or can be removed after the anisotropic etching process, for example by ashenation.

[0042] A periodic two-dimensional array of layer stacks consisting of an active layer 20, a discrete dielectric stencil structure 42T, and a section of the structured hard mask layer 47 (i.e., a hard mask section) can be formed over the gate dielectric layer 10. The sidewalls of an active layer 20, a discrete dielectric stencil structure 42T, and a hard mask section within each layer stack can be vertically aligned, meaning they can be stacked on top of or below each other and lie within a respective vertical plane.In general, the dielectric template material layer 42L and the continuous active layer 20L can be structured into a stack of the two-dimensional array of discrete dielectric template structures 42T and a two-dimensional array of active layers 20, which have the same horizontal cross-sectional shape and the same two-dimensional periodicity. In embodiments in which each active layer 20 has a rectangular horizontal cross-sectional shape, having a pair of longitudinal edges extending along the first horizontal direction hd1 and a pair of lateral edges extending along the second horizontal direction hd2, the length of the longitudinal edges is referred to in this text as a length AL_L of an active layer, and the length of the lateral edges is referred to in this text as a width AL_W of an active layer.The length AL_L of an active layer can be in a range of 8 nm to 480 nm, and the width AL_W of an active layer can be in a range of 3 nm to 480 nm, although smaller and larger dimensions can also be used for the length AL_L and width AL_W of an active layer.

[0043] The discrete dielectric template structures 42T within the two-dimensional array of discrete dielectric template structures 42T can be spaced apart from each other by trenches 41. The trenches 41 comprise first trenches extending laterally along the first horizontal direction hd1 and second trenches extending laterally along the second horizontal direction hd2. The width of each trench 41 can be in the range of 1 nm to 20 nm, although smaller and larger widths can also be used. Bottom surfaces of the two-dimensional array of active layers 20 can be formed within a first horizontal plane HP1, which has a top surface of the gate dielectric layer 10. Top surfaces of the two-dimensional array of discrete dielectric template structures 42T can be formed within a second horizontal plane HP2.

[0044] With reference to the Fig. 6A to Fig. In embodiment 6C, a dielectric etch stop lining 43 can optionally be formed on all side walls of the active layers 20 and the discrete dielectric template structures 42T, as well as on physically exposed sections of the gate dielectric layer 10. In embodiments where the structured hard mask layer 47 is present, the dielectric etch stop lining 43 can be formed on surfaces of the structured hard mask layer 47. Alternatively, the structured hard mask layer 47 can be selectively removed for materials of the active layers 20 and the discrete dielectric template structures 42T prior to the formation of the dielectric etch stop lining 43. In this embodiment, the dielectric etch stop lining 43 can be formed on the top surfaces of the discrete dielectric template structures 42T.The dielectric etch stop lining 43 comprises a non-porous dielectric material that can act as an etch stop layer during a subsequent anisotropic etching process that removes unmasked sections of the discrete dielectric stencil structures 42T. For example, the dielectric etch stop lining 43 can comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a dielectric metal oxide with a dielectric constant greater than 7.9, i.e., a high k-value dielectric material. The thickness of the dielectric etch stop lining 43 can be in the range of 0.3 nm to 3 nm, such as 0.6 nm to 1.5 nm, although smaller or larger thicknesses can also be used.The dielectric etch stop lining 43 can be deposited using a conformal deposition process, such as an atomic layer deposition process or a chemical evaporation process.

[0045] A first dielectric spacer matrix layer 44 can be deposited in the remaining volume of the trenches 41 between the discrete dielectric stencil structures 42T. The first dielectric spacer matrix layer 44 comprises a first dielectric spacer material that differs from the materials of the discrete dielectric stencil structures 42T and the dielectric etch stop lining 43. In one embodiment, the first dielectric spacer matrix layer 44 comprises a material that can subsequently be selectively omitted from the material of the discrete dielectric stencil structures 42T.For example, in embodiments where the discrete dielectric template structures 42T comprise undoped silicate glass or doped silicate glass, the first dielectric spacer matrix layer 44 may comprise a porous or non-porous dielectric material with a low k-value having a dielectric constant of less than 3.9. In one embodiment, the first dielectric spacer matrix layer 44 may comprise non-porous organosilicate glass and / or may consist substantially of non-porous organosilicate glass or of such. In another example, the first dielectric spacer matrix layer 44 may comprise (and / or consist substantially of) a dielectric diffusion barrier material capable of effectively blocking the diffusion of oxygen or hydrogen atoms.For example, the first dielectric spacer matrix layer 44 can comprise and / or consist essentially of a dielectric metal oxide material, such as a high k-value dielectric metal oxide material, silicon nitride, or silicon carbide nitride. Alternatively, the first dielectric spacer matrix layer 44 can also comprise a silicate glass material. In this embodiment, the material of the first dielectric spacer matrix layer 44 is selected such that the first dielectric spacer matrix layer 44 can subsequently be selectively recessed for the material of the discrete dielectric template structures 42T.In an illustrative example, the discrete dielectric template structures 42T can comprise undoped silicate glass, and the first dielectric spacer matrix layer 44 can comprise a doped silicate glass that offers a higher etch rate than undoped silicate glass (such as borosilicate glass). The first dielectric spacer matrix layer 44 can be deposited by a conformal deposition process, such as a chemical vapor deposition process or an atomic layer deposition process.

[0046] A planarization process can be performed to remove sections of the first dielectric spacer matrix layer 44 and the optional dielectric etch stop lining 43 from above the second horizontal plane HP2, that is, the horizontal plane that has the top surfaces of the discrete dielectric stencil structures 42T. In embodiments in which the structured hard mask layer 47 is present, a chemical-mechanical polishing process or a recess etching process can be performed using the structured hard mask layer 47 as a polish stop or as an etch stop. The recess etching process can be extended, or an additional recess etching process can be performed, to vertically recess remaining sections of the first dielectric spacer matrix layer 44 and the optional dielectric etch stop lining 43 from above the second horizontal plane HP2.The structured hard mask layer 47 can then be selectively removed – for example, by a wet etching process – for the discrete dielectric stencil structures 42T. In embodiments where the structured hard mask layer 47 is removed before the deposition of the optional dielectric etch stop lining 43 and the first dielectric spacer matrix layer 44, the discrete dielectric stencil structures 42T can be used as a polishing stop structure or as an etching stop structure.

[0047] With reference to the Fig. 7A - Fig. 7C allows the first dielectric spacer matrix layer 44 to be selectively recessed vertically for the discrete dielectric stencil structures 42T by performing a selective etching process. The chemistry of the selective etching process can be chosen such that the selective etching process removes the material of the first dielectric spacer matrix layer 44 without removing the material of the discrete dielectric stencil structures 42T, or with only minimal removal of the material of the discrete dielectric stencil structures 42T. The selective etching process can comprise an anisotropic etching process or an isotropic etching process. Alternatively, in embodiments in which the processing steps of Fig. 6A - Fig. 6C uses a recess etching process, the duration of the recess etching process in the processing steps of the Fig. 6A - Fig. 6C is extended such that the top surface of the first dielectric spacer matrix layer 44 is vertically recessed beneath the second horizontal layer HP2. In some embodiments, the removal of the structured hard mask layer 47 can be carried out after the top surface of the first dielectric spacer matrix layer 44 has been recessed beneath the second horizontal layer HP2.

[0048] A recess region 45 can be formed between the recessed horizontal surface of the first dielectric spacer matrix layer 44 and the second horizontal plane HP2 within the volumes of upper sections of the trenches 41, as described in the processing steps of the Fig. 5A - Fig. 5C were formed. The depth of the recess region 45 can be in a range of 10% to 90%, such as 20% to 80%, and / or 30% to 70% of the height (i.e., the thickness) of the discrete dielectric stencil structures 42T. For example, the depth of the recess region 45 can be in a range of 1 nm to 900 nm, such as 10 nm to 200 nm, and / or 5 nm to 50 nm, although shallower and greater depths can also be used. In one embodiment, sections of the dielectric etch stop lining 43 that extend beyond the recessed top surface of the first dielectric spacer matrix layer 44 can be removed by performing an isotropic etching process. In general, lower sections of the trenches 41 can be filled with the optional dielectric etch stop lining 43 and the first dielectric spacer matrix layer 44.The recess region 45 may be present in the upper sections of the trenches 41.

[0049] With reference to the Fig. 8A - Fig. In embodiment 8C, a second dielectric spacer matrix layer 46, comprising a second dielectric spacer material, can be deposited in the recess region 45, which includes recessed volumes of the trenches 41. The second dielectric spacer material differs from the materials of the discrete dielectric stencil structures 42T and the first dielectric spacer matrix layer 44. The second dielectric spacer material can be the same as, or different from, the material of the dielectric etch stop lining 43. In one embodiment, the second dielectric spacer matrix layer 46 comprises a material that can function as an etch mask material during a subsequent anisotropic etching process that etches the material of the discrete dielectric stencil structures 42T.In embodiments where the discrete dielectric template structures 42T comprise undoped silicate glass or doped silicate glass, the second dielectric spacer matrix layer 46 can, for example, comprise silicon nitride, silicon carbide nitride, silicon oxynitride, or a dielectric metal oxide with a dielectric constant greater than 7.9, i.e., a high k-value dielectric metal oxide material. Alternatively, the second dielectric spacer matrix layer 46 can comprise a low k-value nitrogen-doped dielectric material, such as nitrogen-doped organosilicate glass.Alternatively, the first dielectric spacer matrix layer 44 can comprise a doped silicate glass material, such as borosilicate glass or fluorosilicate glass, and the second dielectric spacer matrix layer 46 can comprise undoped silicate glass, which can act as an etch mask material for the doped silicate glass material during a subsequent anisotropic etching process. The second dielectric spacer matrix layer 46 can be deposited by a conformal deposition process, such as a chemical vapor deposition process or an atomic layer deposition process.

[0050] A planarization process can be performed to remove sections of the second dielectric spacer matrix layer 46 from above the second horizontal plane HP2, that is, the horizontal plane that has the top surfaces of the discrete dielectric template structures 42T. A chemical-mechanical polishing process or a recess etching process can be performed to remove the sections of the second dielectric spacer matrix layer 46 from above the second horizontal plane HP2. In embodiments where overpolishing or overetching is used during the planarization process, the second horizontal plane HP2 can be shifted vertically downwards by the overpolishing distance or the overetching distance, which may be in a range from 0 nm to 50 nm, such as 0 nm to 5 nm, and / or 0 nm to 1 nm.The planarized top surface of the second dielectric spacer matrix layer 46 can be located within the same horizontal plane as the horizontal plane that has the top surfaces of the discrete dielectric stencil structures 42T, that is, the second horizontal plane HP2.

[0051] The combination of the optional dielectric etch stop lining 43, the first dielectric spacer matrix layer 44, and the second dielectric spacer matrix layer 46 is referred to in this text as a dielectric composite matrix (43, 44, 46) that laterally surrounds the two-dimensional array of discrete dielectric stencil structures 42T. In other words, each discrete dielectric stencil structure 42T within the two-dimensional array of discrete dielectric stencil structures 42T is laterally surrounded by the dielectric composite matrix (43, 44, 46). In embodiments in which the dielectric composite matrix (43, 44, 46) comprises the dielectric etch stop lining 43, the dielectric etch stop lining 43 can contact the entire bottom and side walls of the first dielectric spacer matrix layer 44 as well as the lower sections of each of the discrete dielectric stencil structures 42T.The dielectric etch stop lining 43 can contact segments of the underside of the second dielectric spacer matrix layer 46.

[0052] In one embodiment, the underside of the dielectric composite matrix (43, 44, 46) and the undersides of the active layers 20 within the two-dimensional array of active layers 20 can be located within the same horizontal plane, that is, the first horizontal plane HP1. In another embodiment, the underside of each active layer 20 within the two-dimensional array of active layers 20 can be located within a horizontal plane that includes the underside of the dielectric composite matrix (43, 44, 46), that is, within the first horizontal plane HP1.

[0053] With reference to the Fig. 9A - Fig. 9D an etch mask material layer 71L, at least one optional structure transfer support layer (73L, 75L) and a photoresist layer 77 can be formed successively over the two-dimensional array of discrete dielectric template structures 42T and the dielectric composite matrix (43,44,46).

[0054] The etch mask material layer 71L can contain a material that can function as an etch mask material during an anisotropic etching step that etches the material of the first dielectric spacer matrix layer 44. In embodiments where the first dielectric spacer matrix layer 44 comprises a silicate glass material, the etch mask material layer 71L can, for example, comprise silicon nitride, silicon carbide nitride, silicon oxynitride, or a dielectric metal oxide material with a dielectric constant greater than 7.9. In embodiments where the first dielectric spacer matrix layer 44 comprises non-porous organosilicate glass, the etch mask material layer 71L can comprise silicon oxide. The etch mask material layer 71L can be formed by a conformal or non-conformal deposition process.The thickness of the etch stop material layer 71L can be in a range of 2 nm to 100 nm, such as 5 nm to 50 nm, and / or 10 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0055] The at least one optional structure transfer support layer (73L, 75L) can comprise at least one material that can advantageously be used to improve the precision of the image transfer from the photoresist layer 77 to unmasked sections of the discrete dielectric stencil structures 42T. In an illustrative example, the at least one optional structure transfer support layer (73L, 75L) can comprise a first structure transfer support layer 73L and a second structure transfer support layer 75L. The first structure transfer support layer 73L can comprise a bottom anti-reflection coating (BARC) known to those skilled in the art. The second structure transfer support layer 75L can comprise a spin-on oxide (SOG) material with a thickness in the range of 10 nm to 35 nm.In general terms, any lithographic material stack that can improve image formation in the photoresist layer 77 and / or improve the precision of structure transfer to underlying material layers can be used for the at least one optional structure transfer support layer (73L, 75L).

[0056] The photoresist layer 77 can be formed over the etch stop material layer 71L and the at least one optional structure transfer support layer (73L, 75L). According to one aspect of the present disclosure, a two-dimensional array of openings in the photoresist layer 77 can be formed by lithographic exposure and development.The structure of the openings in the photoresist layer 77 can be chosen such that each opening in the two-dimensional array of openings in the photoresist layer 77 has a respective region that extends continuously over an adjacent pair of dielectric stencil structures 42T, which are selected from the discrete dielectric stencil structures 42T that are laterally spaced along the first horizontal direction hd1, which is the horizontal direction along which a first subset of the trenches 41 (i.e., the first trenches) are laterally spaced from each other, as well as over a section of the second dielectric spacer matrix layer 46.In other words, each opening in the photoresist layer 77 extends continuously over a section of a first discrete dielectric template structure 42T, a section of a second discrete dielectric template structure 42T spaced laterally from the section of the first discrete dielectric template structure 42T along the first horizontal direction hd1, and the section of the dielectric composite matrix (43, 44, 46) located between the section of the first discrete dielectric template structure 42T and the section of the second discrete dielectric template structure 42T.

[0057] In one embodiment, the photoresist layer 77 can be structured with a conduction-and-space structure in which the openings in the photoresist layer 77 have straight edges extending laterally along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1. In one embodiment, each opening in the photoresist layer 77 can have a first straight edge extending across a first column of the discrete dielectric stencil structures 42T arranged along the second horizontal direction hd2, and can have a second straight edge extending across a second column of the discrete dielectric stencil structures 42T. The second column can be offset laterally from the first column by less than one center-to-center spacing of the two-dimensional array of discrete dielectric stencil structures 42T along the first horizontal direction hd1.A section of the dielectric composite matrix (43, 44, 46) that fills a second trench, that is, a trench 41 that extends laterally along the second horizontal direction hd2, lies under each opening in the photoresist layer 77.

[0058] With reference to the Fig. 10A - Fig. 10D can transfer the structure in the photoresist layer 77 through at least one optional structure transfer support layer (73L, 75L) and the etch mask material layer 71L and into sections of the discrete dielectric template structures 42T, which are selective for the material of the second dielectric spacer matrix layer 46, by performing an anisotropic etching process. In one embodiment, the anisotropic etching process can comprise a first anisotropic etching step that transfers the structure in the photoresist layer 77 through at least one optional structure transfer support layer (73L, 75L) and the etch mask material layer 71L. The etch mask material layer 71L can be structured into etch mask material sections 71 that replicate the structure of the openings in the photoresist layer 77.In one embodiment, the etch mask material sections 71 can be formed as a one-dimensional periodic array of etch mask material sections 71 comprising a conduction and gap structure with a periodicity along the first horizontal direction hd1 that is the same as the periodicity of the gate electrodes 15 and the periodicity of the active layers 20 along the first horizontal direction hd1. In one embodiment, each etch mask material section 71 can have a pair of straight longitudinal edges extending laterally along the second horizontal direction hd2, across which a column of discrete dielectric stencil structures 42T and an underlying column of active layers 20, arranged along the second horizontal direction hd2, can spread.In one embodiment, each etch mask material section 71 can have a uniform width throughout and can be located in a central section of each discrete dielectric stencil structure 42T within a respective column of discrete dielectric stencil structures 42T.

[0059] The anisotropic etching process can include a second anisotropic etching step that selectively etches the material of the discrete dielectric stencil structures 42T to the material of the second dielectric spacer matrix layer 46. For the purposes of this text, an etching process that etches a first material is referred to as selective etching of a second material if the etch rate of the second material during the etching process is less than 1 / 3 of the etch rate of the first material during the etching process. Thus, the etch rate of the material of the second dielectric spacer matrix layer 46 during the second anisotropic etching step is less than 1 / 3, and preferably less than 1 / 10 and / or less than 1 / 30, of the etch rate of the material of the discrete dielectric stencil structures 42T during the second anisotropic etching step.The second anisotropic etching step anisotropically etches sections of the discrete dielectric stencil structures 42T that are not masked by the structured etch mask material layer, i.e., the etch mask material sections 71. In other words, the photoresist layer 77 and the second dielectric spacer matrix layer 46 can mask any underlying materials prior to the anisotropic etching process. In one embodiment, the chemistry of the second anisotropic etching step can be selective for the material of the dielectric etch stop lining 43. In other words, in embodiments where the dielectric etch stop lining 43 is present, the dielectric etch stop lining 43 can be used as an etch stop structure to protect the first dielectric spacer matrix layer 44 from collateral etching during the second anisotropic etching step.

[0060] In general, sections of the discrete dielectric stencil structures 42T located within the openings in the photoresist layer 77 can be selectively etched during the second anisotropic etching step for the material of the second dielectric spacer matrix layer 46. Source cavities 51 and drain cavities 59 can be formed in the volumes created when sections of discrete dielectric stencil structures 42T are removed by the etching process. The structure of the openings in the photoresist layer 77 can be selectively transferred through the discrete dielectric stencil structures 42T for the second dielectric spacer matrix layer 46.Thus, the structure of the source cavities 51 and the drain cavities 59 can be a composite structure that links the structure of the openings in the photoresist layer 77 and the structure of the discrete dielectric template structures 42T. In other words, the structure of the source cavities 51 and the drain cavities 59 has regions that are located within one of the openings in the photoresist layer 77 and within one of the discrete dielectric template structures 42T, respectively. A top surface of an active layer 20 can be physically exposed at the bottom of both each source cavity 51 and each drain cavity 59.

[0061] A pair consisting of a source cavity 51 and a drain cavity 59 can be formed within a volume of each of the discrete dielectric stencil structures 42T. The volume of the source cavity 51 and the volume of the drain cavity 59 can be equal or substantially equal, or they can differ from each other by 50% to 200%, 75% to 133%, or 90% to 110% for each source cavity 51 / drain cavity 59 pair formed by removing sections of the same discrete dielectric stencil structure 42T. Each remaining section of the discrete dielectric stencil structures 42T after the second anisotropic etching step contains a dielectric interelectrode spacer 42 that separates the source cavity 51 and the drain cavity 59.Each dielectric intermediate electrode spacer 42 is located between one of the source cavities 51 and one of the drain cavities 59 and is physically exposed to them. In a subsequent processing step, a source electrode 52 can be formed in each source cavity 51, and in a subsequent processing step, a drain electrode 56 can be formed in each drain cavity 59. After the formation of the source electrodes 52 and the drain electrodes 56, each dielectric intermediate electrode spacer 42 can be positioned between a source electrode 52 and the drain electrode 56.

[0062] According to one aspect of the present disclosure, an etch mask material section 71 lies over a column of dielectric inter-electrode spacers 42 arranged along the second horizontal direction hd2. The etch mask material section 71 protects physically exposed sidewall surfaces of the column of dielectric inter-electrode spacers 42 from corner erosion throughout the entire second anisotropic etching step. Thus, the entirety of all physically exposed sidewalls of the dielectric inter-electrode spacers 42 can be located within vertical planes that coincide vertically with the longitudinal sidewalls of the etch mask material sections 71, which extend laterally along the second horizontal direction hd2.

[0063] In contrast, the upper corner sections of the second dielectric spacer matrix layer 46, located adjacent to the source cavities 51 or the drain cavities 59, can be subjected to collateral etching during the second anisotropic etching step, albeit at a lower etch rate. Thus, corner rounding can occur at the upper corner sections of the second dielectric spacer matrix layer 46, located adjacent to the source cavities 51 or the drain cavities 59, during the second anisotropic etching step. In various embodiments, each source cavity 51 and each drain cavity 59 can comprise at least one contoured sidewall adjacent to a top surface of the second dielectric spacer matrix layer 46, such as three contoured sidewalls adjacent to a top surface of the second dielectric spacer matrix layer 46.Each contoured sidewall can comprise a tapered convex surface segment of the second dielectric spacer matrix layer 46, which adjoins a vertically extending surface segment of the second dielectric spacer matrix layer 46. The vertically extending surface segment of the second dielectric spacer matrix layer 46 can adjoin a vertical sidewall of the dielectric etch stop lining 43 or, in embodiments in which no dielectric etch stop lining is present, can adjoin a vertical sidewall of the first dielectric spacer matrix layer 44.

[0064] With reference to the Fig. 11A - Fig. 11D can deposit at least one metallic material in the source cavities 51 and the drain cavities 59 and over the etch mask material sections 71 (i.e., the structured sections of the etch mask material layer 71L), a two-dimensional array of dielectric interelectrode spacers 42, and the dielectric composite matrix (43, 44, 46). The at least one metallic material can comprise a metallic lining material and a metallic filler material. For example, a metallic lining layer 53L containing a metallic lining material can be deposited, and subsequently, a metallic filler layer 54L containing a metallic filler material can be deposited. The metallic lining layer 53L can contain a conductive metal nitride or a conductive metal carbide such as TiN, TaN, WN, TiC, TaC, and / or WC.Other suitable materials may also be used within the considered scope of the disclosure. The metallic lining layer 53L may be deposited by a non-conforming deposition process, such as a physical vapor deposition process, or by a conforming deposition process, such as a chemical vapor deposition process. The thickness of the horizontally extending sections of the metallic lining layer 53L that contact a top surface of each of the active layers 20 may be in the range of 1 nm to 30 nm, such as 2 nm to 10 nm, although smaller and larger thicknesses may also be used. The metallic filler layer 54L may contain W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof.Other suitable materials within the considered scope of the disclosure may also be used. The metallic filler layer 54L can be formed by physical vapor deposition, chemical vapor deposition, electroplating, and / or electroless deposition. The thickness of the metallic filler layer 54L can be selected such that the source cavities 51 and the drain cavities 59 are filled with the combination of the metallic lining layer 53L and the metallic filler layer 54L.

[0065] With reference to the Fig. 12A - Fig. 12E Excess sections of the at least one metallic material above the second horizontal plane HP2, that is, the horizontal plane comprising the top of the dielectric composite matrix (43, 44, 46) and the two-dimensional array of dielectric inter-electrode spacers 42, can be removed by a planarization process. The planarization process can include a chemical-mechanical polishing (CMP) process and / or a recess etching process. The etch mask material sections 71 can be removed collaterally during the planarization process. Other suitable planarization processes can also be used. Each remaining section of the at least one metallic material filling a source cavity 51 forms a source electrode 52. Each remaining section of the at least one metallic material filling a drain cavity 59 forms a drain electrode 56.A source electrode 52 and a drain electrode 56 can be formed in each source cavity 51 and in each drain cavity 59, respectively.

[0066] In one embodiment, each source electrode 52 can have a metallic source lining 53, which is a remaining portion of the metallic lining layer 53L deposited in the source cavity 51, and can have a metallic source filler section 54, which is a remaining portion of the metallic filler layer 54L deposited in the source cavity 51. Each drain electrode 56 can have a metallic drain lining 57, which is a remaining portion of the metallic lining layer 53L deposited in the drain cavity 59, and can have a metallic drain filler section 58, which is a remaining portion of the metallic filler layer 54L deposited in the drain cavity 59. In general, a source electrode 52 and a drain electrode 56 can be formed on respective portions of a top surface of each active layer 20.In each unit cell area UC, a transistor (for example, a thin-film transistor) can be formed.

[0067] In one embodiment, the side walls of the dielectric intermediate electrode spacers 42, which are perpendicular to the first horizontal direction hd1, extend straight from a top surface of each dielectric intermediate electrode spacer 42 to a bottom surface of each dielectric intermediate electrode spacer 42. Thus, the entirety of each interface between the dielectric intermediate electrode spacers 42 and the source electrodes 52 is straight and vertical (that is, it lies within a two-dimensional Euclidean plane), and the entirety of each interface between the dielectric intermediate electrode spacers 42 and the drain electrodes 56 is straight and vertical.

[0068] In one embodiment, at least one interface between each of the source electrodes 52 and the dielectric composite matrix (43, 44, 46) can be contoured, meaning that it need not lie entirely in a Euclidean plane, and it can be tapered, meaning that each point has a tangent plane that runs at an angle with respect to a vertical direction. In one embodiment, each of the at least one interface between each of the source electrodes 52 and the dielectric composite matrix (43, 44, 46) can comprise a contoured and tapered interface segment extending downward from an edge of a horizontal top surface of the second dielectric spacer matrix layer 46, and a vertical interface segment adjoining a lower edge of the contoured and tapered interface segment and extending downward to a bottom surface of the dielectric composite matrix (43, 44, 46).In embodiments where the dielectric etch stop lining 43 is present, the vertical interface segment can have an interface between the dielectric etch stop lining 43 and one of the source electrodes 52 and drain electrodes 56, respectively. In embodiments where the dielectric etch stop lining 43 is not present, the vertical interface segment can have an interface between the first dielectric spacer matrix layer 44 and one of the source electrodes 52 and drain electrodes 56, respectively.

[0069] The contour of the interfaces between the dielectric composite matrix (43, 44, 46) and each of the source electrodes 52 and drain electrodes 56 can cause each of the source electrodes 52 and drain electrodes 56 to have expanded vertical cross-sectional profiles, in which the lateral dimensions of each of the source electrodes 52 and drain electrodes 56 gradually increase near the upper sections, which are located near the second horizontal plane HP2.More precisely, the lateral dimensions of each of the source electrodes 52 and the drain electrodes 56, measured along the first horizontal direction hd1 and / or along the second horizontal direction hd2 as a function of a vertical distance from the substrate, below the interface between the first dielectric spacer matrix layer 44 and the second dielectric spacer matrix layer 46, can be uniform and can gradually increase with the vertical distance from the substrate at the level of the second dielectric spacer matrix layer 46, i.e., they can exhibit expanded properties.

[0070] The length of the bottom of a source electrode 52 along the first horizontal direction hd1, measured at an interface with an underlying active layer 20, is referred to in this text as the source bottom length (SBL). The length of the top of a source electrode 52 (contained in the second horizontal plane HP2) along the first horizontal direction hd1 is referred to in this text as the source top length (STL). According to one aspect of this disclosure, the source top length STL may be greater than the source bottom length SBL. The length of each source electrode 52 along the first horizontal direction hd1 at the plane of the first dielectric spacer matrix layer 44 may be uniform and may be the same as the source bottom length SBL.The length of each source electrode 52 along the horizontal direction hd1 on the plane of the second dielectric spacer matrix layer 46 gradually increases with a vertical distance from the substrate between the lower source length SBL and the upper source length STL. The difference between the upper source length STL and the lower source length SBL can be in a range of 0.5 nm to 10 nm, such as 1 nm to 8 nm and / or 2 nm to 6 nm, although smaller and larger dimensions can also be used.

[0071] The length of the underside of a drain electrode 56 along the first horizontal direction hd1, measured at an interface with an underlying active layer 20, is referred to in this text as the drain bottom length (DBL). The length of the top side of a drain electrode 56 (contained in the second horizontal plane HP2) along the first horizontal direction hd1 is referred to in this text as the drain top length (DTL). According to one aspect of this disclosure, the drain top length DTL may be greater than the drain bottom length DBL. The length of each drain electrode 56 along the first horizontal direction hd1 at the plane of the first dielectric spacer matrix layer 44 may be uniform and may be the same as the drain bottom length DBL.The length of each drain electrode 56 along the horizontal direction hd1 on the plane of the second dielectric spacer matrix layer 46 gradually increases with vertical distance from the substrate between the lower drain length DBL and the upper drain length DTL. The difference between the upper drain length DTL and the lower drain length DBL can be in a range of 0.5 nm to 10 nm, such as 1 nm to 8 nm and / or 2 nm to 6 nm, although smaller and larger dimensions can also be used.

[0072] The length of each dielectric interelectrode spacer 42 along the first horizontal direction hd1 defines the channel length of a respective thin-film transistor and is referred to in this text as a gate length GL. The sum of the lower source length SBL, the gate length GL, and the lower drain length DBL can be equal to the length AL_L of an active layer.

[0073] The width of the bottom of a source electrode 52 along the second horizontal direction hd2, measured at an interface with an underlying active layer 20, is referred to in this text as the source bottom width (SBW). The width of the top of a source electrode 52 (contained in the second horizontal plane HP2) along the second horizontal direction hd2 is referred to in this text as the source top width (STW). According to one aspect of this disclosure, the source top width STW may be greater than the source bottom width SBW. The width of each source electrode 52 along the second horizontal direction hd2 at the level of the second dielectric spacer matrix layer 44 may be uniform and may be the same as the source bottom width.The width of each source electrode 52 along the horizontal direction hd2 at the level of the second dielectric spacer matrix layer 46 gradually increases with vertical distance from the substrate between the lower source width SBW and the upper source width STW. The difference between the upper source width STW and the lower source width SBW can be in a range of 1 nm to 20 nm, such as 2 nm to 16 nm and / or 4 nm to 12 nm, although smaller and larger dimensions can also be used. The lower source width SBW can be the same as the width AL_W of an active layer, that is, the lateral dimension of an underlying active layer 20 along the second horizontal direction hd2.

[0074] The width of the underside of a drain electrode 56 along the second horizontal direction hd2, measured at an interface with an underlying active layer 20, is referred to in this text as the lower drain width. The width of the top side of a drain electrode 56 (contained in the second horizontal plane HP2) along the second horizontal direction hd2 is referred to in this text as the upper drain width (drain top width, DTW). According to one aspect of this disclosure, the upper drain width may be greater than the lower drain width DBW. The width of each drain electrode 56 along the second horizontal direction hd2 at the level of the second dielectric spacer matrix layer 44 may be uniform and may be the same as the lower drain width.The width of each drain electrode 56 along the horizontal direction hd2 at the level of the second dielectric spacer matrix layer 46 gradually increases with a vertical distance from the substrate between the lower drain width and the upper drain width. The difference between the upper drain width and the lower drain width can be in a range of 1 nm to 20 nm, such as 2 nm to 16 nm and / or 4 nm to 12 nm, although smaller and larger dimensions can also be used. The lower drain width can be the same as the width AL_W of an active layer, that is, the lateral dimension of an underlying active layer 20 along the second horizontal direction hd2.

[0075] Each connected combination of a dielectric intermediate electrode spacer 42, a source electrode 52, and a drain electrode 56 is referred to in this text as a source-spacer-drain combination (52, 42, 56). Each source-spacer-drain combination (52, 42, 56) is laterally surrounded by the dielectric composite matrix (43, 44, 46). A two-dimensional array of source-spacer-drain combinations (52, 42, 56) is located above a two-dimensional array of active layers 20, such that a lower circumferential boundary of each source-spacer-drain combination (52, 42, 56) coincides with an upper circumferential boundary of a respective underlying active layer 20.In other words, the length AL_L of an active layer (which is the dimension of each active layer 20 along the first horizontal direction hd1) can be the same as the sum of the lower source length SBL, the gate length GL and the lower drain length DBL.

[0076] In one embodiment, the entirety of an interface between the dielectric intermediate electrode spacer 42 and the source electrode 52 within each source-spacer-drain combination (52, 42, 56), as well as the entirety of an interface between the dielectric intermediate electrode spacer 42 and the drain electrode 56 within each source-spacer-drain combination (52, 42, 56), can be located within vertical planes. In contrast, an interface between the source electrode 52 within each source-spacer-drain combination (52, 42, 56) and the dielectric composite matrix (43, 44, 46) can comprise a contoured interface segment that borders a top surface of the second dielectric spacer matrix layer 46.A tapered convex surface segment of the second dielectric spacer matrix layer 46 can contact a tapered concave surface segment of the source electrode 52 at the contoured interface segment. Likewise, an interface between the drain electrode 56 within each drain-spacer-drain combination (52, 42, 56) and the dielectric composite matrix (43, 44, 46) can include a contoured interface segment bordering a top surface of the second dielectric spacer matrix layer 46. A tapered convex surface segment of the second dielectric spacer matrix layer 46 can contact a tapered concave surface segment of the drain electrode 56 at the contoured interface segment.

[0077] In general, a two-dimensional array of source-spacer-drain combinations (52, 42, 56) can be arranged over a substrate and can be laterally spaced apart from each other by a dielectric composite matrix (43,44,46). Each source-spacer-drain combination (52, 42, 56) selected from the two-dimensional array of source-spacer-drain combinations (52, 42, 56) comprises a dielectric intermediate electrode spacer 42 in contact with a source electrode 52 and a drain electrode 56. The dielectric composite matrix (43, 44, 46) comprises a first dielectric spacer matrix layer 44, which includes a first dielectric spacer material, and a second dielectric spacer matrix layer 46, which includes a second dielectric spacer material and lies above the first dielectric spacer matrix layer 44.Each source-spacer-drain combination (52, 42, 56) within the two-dimensional array of source-spacer-drain combinations (52, 42, 56) contacts a horizontal surface of a respective active layer 20 within the two-dimensional array of active layers 20.

[0078] Each connected combination of a source electrode 52, a drain electrode 56, and a dielectric intermediate electrode spacer 42 contacts a horizontal surface of a respective stack consisting of an active layer 20 selected from the two-dimensional array of active layers 20, a gate dielectric layer 10, and a gate electrode 15. In one embodiment, a top surface of the dielectric composite matrix (43, 44, 46), top surfaces of the dielectric intermediate electrode spacers 42, and top surfaces of the source electrodes 52 and the drain electrodes 56 are located within the same horizontal plane, that is, in the second horizontal plane HP2.

[0079] In one embodiment, the dielectric composite matrix (43, 44, 46) comprises a dielectric etch stop lining 43 that contacts a bottom surface and side walls of the first dielectric spacer matrix layer 44 and contacts lower sections of each of the source electrodes 52 and drain electrodes 56, as well as lower sections of each dielectric intermediate electrode spacer 42. In another embodiment, the dielectric etch stop lining 43 can contact all side walls of an active layer 20 and can have a bottom surface located within the same horizontal plane (i.e., the first horizontal plane HP1) that contains all the bottom surfaces of an active layer 20.

[0080] While the first exemplary structure is described using an embodiment in which gate electrodes 15 are formed prior to the formation of the two-dimensional array of discrete dielectric template structures 42T, various embodiments of the present disclosure allow the formation of gate electrodes 15 prior to or after the formation of the two-dimensional array of discrete dielectric template structures 42T, thereby forming a two-dimensional array of field-effect transistors (including a two-dimensional array of thin-film transistors).

[0081] In general, a two-dimensional array of active layers 20 can be formed before or after the formation of the source electrodes 52 and the drain electrodes 56, such that each of the active layers 20 has a planar overlap within one of the respective source electrodes 52 and with one of the respective drain electrodes 56. For the purposes of this text, "planar overlap" means an overlap in areas in a top view along a vertical direction. Generally, the two-dimensional array of active layers 20 lies above or below the two-dimensional array of source-spacer-drain combinations (52, 42, 56). The gate electrodes 15 are spaced from the two-dimensional array of active layers 20 by a dielectric gate layer 10.

[0082] With reference to the Fig. 13A - Fig. 13E at least one first dielectric material layer at the connection level (70) and first metallic interconnect structures at the connection level (72, 74, 76, 78) can be formed over the dielectric composite matrix (43, 44, 46) and the source-spacer-drain combinations (52, 42, 56). The at least one first dielectric material layer 70 at a connection level can comprise a first dielectric material layer at a via level through which source-contact via structures 72 and drain-contact via structures 76 extend vertically, as well as a first dielectric material layer at a conductor level in which source interconnect pads 74 and bit lines 78 are formed.In one embodiment, the first dielectric material layer on a via plane can be formed first, and the source-contact via structures 72 and the drain-contact via structures 76 can be formed through the first dielectric material layer on a via plane. The first dielectric material layer on a conductor plane can then be formed over the first dielectric material layer on a via plane, and the first source interconnect pads 74 and the bit lines 78 can then be formed through the first dielectric material layer on a conductor plane on one of the respective source-contact via structures 72 and the drain-contact via structures 76.

[0083] Alternatively, the first dielectric material layer on a via plane and the first dielectric material layer on a conductor plane can be formed as a single dielectric material layer, and a dual damascene process can be performed to form integrated conductor and via structures. The integrated conductor and via structures include source-side integrated conductor and via structures, each featuring a combination of a source-contact via structure 72 and a first-source interconnect pad 74, and drain-side integrated conductor and via structures, each featuring a combination of drain-contact via structures 76 and a bit line 78 integrally formed within the drain-contact via structures 76.In one embodiment, each bit line 78 extends laterally along the first horizontal direction hd1 and can be electrically connected to a set of drain electrodes 56 arranged along the first horizontal direction hd1.

[0084] In general, source-contact via structures 72 can be formed on the source electrodes 52, and drain-contact via structures 76 can be formed on the drain electrodes 56. Bit lines 78 can be formed on the drain-contact via structure 76 such that each of the bit lines 78 extends laterally along a horizontal direction perpendicular to the longitudinal direction of the word lines 3. The bit lines 78 can extend laterally along a horizontal direction (such as the first horizontal direction hd1) that differs from the second horizontal direction hd2. In one embodiment, each of the active layers 20 can have a rectangular horizontal cross-sectional shape with first sides parallel to the first horizontal direction hd1 and second sides parallel to the second horizontal direction hd2.

[0085] With reference to the Fig. 14A - Fig. 14E At least one second dielectric material layer on a connection plane 80 and second metal interconnect structures (82, 84) can be formed above the at least one first dielectric material layer 70 on a connection plane. The at least one second dielectric material layer 80 on a connection plane can comprise a second dielectric material layer on a via plane through which source-connection via structures 82 extend vertically, as well as a second dielectric material layer on a conductor plane in which second source-connection pads 84 are formed. In one embodiment, the second dielectric material layer can be formed on a via plane, and the source-contact via structures 82 can be formed through the second dielectric material layer on a via plane.The second dielectric material layer on a conduction plane can then be formed over the second dielectric material layer on a via plane, and the second source connection pads 84 can then be formed through the second dielectric material layer on a conduction plane on one of the respective source connection via structures 82.

[0086] Alternatively, the second dielectric material layer on a via plane and the second dielectric material layer on a conduction plane can be formed as a single dielectric material layer, and a dual damascene process can be performed to form integrated conduction and via structures. The integrated conduction and via structures feature source-side integrated conduction and via structures, each comprising a combination of a source-connection via structure 82 and a second-source connection pad 84.

[0087] In general, dielectric material layers (70, 80) can be formed on a connection plane above the field-effect transistors. Source-connection metal interconnect structures (72, 74, 82, 84) can be formed within the dielectric material layers (70, 80) on a connection plane, which can be used to electrically connect each of the source electrodes 52 to a conductive node of a respective storage element to be formed subsequently.

[0088] With reference to the Fig. 15A - Fig. 15E A two-dimensional array of memory structures can be formed above the two-dimensional array of field-effect transistors. The metal interconnect structures (72, 74, 82, 84) located between the two-dimensional array of field-effect transistors and the two-dimensional array of memory structures can be configured such that each memory structure within the two-dimensional array of memory structures is electrically connected to a source electrode 52 of a respective field-effect transistor within the two-dimensional array of field-effect transistors.

[0089] In an illustrative example, capacitor structures 98 and a dielectric material layer 90 can be formed on a storage plane above the dielectric material layers (70, 80) on a connection plane. For example, first electrodes 92 (also referred to as first capacitor plates) can be formed on the top surfaces of the second source connection pads 84 by depositing and structuring a first conductive material, which may be a metallic material or a heavily doped semiconductor material. A dielectric node layer 94 can be formed on each first electrode 92 by depositing a dielectric node material such as silicon nitride and / or a dielectric metal oxide (for example, aluminum oxide, lanthanum oxide, and / or hafnium oxide).A second electrode 96 (also referred to as a second capacitor plate or a ground-side plate) can be formed on physically exposed surfaces of the node dielectric by depositing and structuring a second conductive material, which may be a metallic material or a heavily doped semiconductor material. Each section of the dielectric node layer 94 located between a first electrode 92 and the second electrode 96 constitutes a node dielectric. Any connected combination of a first electrode 92, a node dielectric (which is a section of the dielectric node layer 94), and the second electrode 96 can constitute a capacitor structure 98. The dielectric material layer 90 at a storage level can be formed over the capacitor structures 98.Each of the capacitor structures 98 can be formed within the dielectric material layer 90 on a storage plane and surrounded laterally by it.

[0090] In one embodiment, each of the first electrodes 92 can be electrically connected to (that is, electrically bonded to) one of the respective source electrodes 52. Each of the second electrodes 96 can be electrically grounded, for example, by forming an array of conductive via structures (not shown) that contact the second electrodes 96 and are connected to an overlying metal plate (not shown). In general, the capacitor structures 98 can be formed above a horizontal plane that has a top surface of the bit lines 78. Each of the capacitor structures 98 includes a node that is electrically connected to one of the respective source electrodes 52. In this way, a two-dimensional array of memory cells 99 can be provided. Each memory cell 99 includes a respective access transistor (which is one of the thin-film transistors) and a respective capacitor structure 98.Each memory cell 99 can be formed within a respective unit cell area UC.

[0091] With reference to the Fig. 16A - Fig. 16E illustrates a first alternative arrangement of the first exemplary structure, which is shown in the Fig. 14A - Fig. The first exemplary structure illustrated in Figure 14E can be derived by using a two-dimensional array of resistor memory structures 198 instead of the one shown in the Fig. 15A - Fig. Figure 15E illustrates two-dimensional arrays of capacitor structures. In this embodiment, each resistive storage structure 198 can comprise a vertical stack of a respective first electrode 192, a resistive storage element 194 containing a material providing at least two different levels of specific electrical resistance, and a second electrode 196. Each resistive storage element 194 can comprise any of the resistive storage elements known in the prior art, which include a phase-change storage material section, a magnetic tunnel junction cell, an oxygen-vacancy modulated dielectric metal oxide section (such as hafnium oxide), a metal-insulator transition (MIT) section (which may contain, for example, VO₂ or Nb₂), etc.The second electrodes 196 can be electrically connected to a suitable voltage source or to an electrical ground, as required. In the illustrated example, a metal plate 199 can be formed over the two-dimensional array of the second electrodes 196. Alternative electrical connection regimes can also be used, as required. In this way, a two-dimensional array of memory cells 99 can be provided. Each memory cell 99 comprises a respective access transistor (which is one of the thin-film transistors) and a respective resistance storage structure 198. Each memory cell 99 can be formed within a respective unit cell area UC.

[0092] In general terms, a two-dimensional array of memory structures can be formed above or below the two-dimensional array of field-effect transistors of the present disclosure. Metal interconnect structures (72, 74, 76, 78, 82, 84) can be formed above or below the two-dimensional array of field-effect transistors such that each memory structure within the two-dimensional array of memory structures is electrically connected to a source electrode 52 of a respective field-effect transistor within the two-dimensional array of field-effect transistors.In some embodiments, the two-dimensional array of storage structures comprises a two-dimensional array of capacitor structures, each having a first capacitor plate (such as a first electrode 92), a node dielectric (which is a section of a dielectric node layer 94 in contact with the first capacitor plate), and a second capacitor plate (such as a second electrode 96); or a two-dimensional array of resistor storage structures, each having a first electrode 192, a resistor storage element 194 containing a material providing at least two different levels of specific electrical resistance, and a second electrode 196.

[0093] With reference to Fig. Figure 17 illustrates the first exemplary structure after the formation of a two-dimensional array of memory cells 99 above the insulating layer 635 at a gate level. Various additional metal interconnect structures (632, 668) can be formed in the insulating layer 635 at a gate level, the dielectric layer 40, the dielectric material layers (70, 80) at a connection level, and the dielectric material layer 90 at a memory level. The additional metal interconnect structures (632, 668) can, for example, include second metal via structures 632 that can be formed through the insulating layer 635 at a gate level and the dielectric layer 40 on a top surface of one of the respective second metal via structures 628.Furthermore, the additional metal interconnect structures (632, 668) can, for example, include metal conductor structures formed in upper sections of the dielectric material layer 90 on a storage level, which are referred to in this text as the sixth metal conductor structures 668.

[0094] Subsequently, an additional dielectric material layer can be formed on an interconnect level, along with additional metal interconnect structures. For example, a seventh dielectric material layer 670 can be formed on an interconnect level above the dielectric material layer 90 on a storage level, in which seventh metal conductor structures 678 and sixth metal via structures 672 are embedded. Although the present disclosure describes an embodiment using seven levels of metal conductor structures, embodiments using a smaller or larger number of interconnect levels are also expressly considered in this text.

[0095] In general, the shapes of the top surfaces of the source electrodes 52 and the drain electrodes 56 can be changed depending on the degree and geometry of the chamfer at the upper edges of the second dielectric spacer matrix layer 46 during the second anisotropic etching step in the processing steps of the Fig. 10A - Fig. 10D vary. Fig. 18A - Fig. 18C, Fig. 19A - Fig. 19C and Fig. 20A - Fig. Figure 20C illustrates variations in the shapes of the top surfaces of the source electrodes 52 and the drain electrodes 56 during processing steps 12A - 12E, which are due to variations in the processing conditions during the second anisotropic etching step in the processing steps of the Fig. 10A - Fig. 10D can occur.

[0096] Fig. 18A - Fig. Figure 18C illustrates a second alternative arrangement of the first exemplary structure after the formation of source electrodes 52 and drain electrodes 56. In the second alternative arrangement, the top surfaces of the source electrodes 52 and the drain electrodes 56 can each have the shape of a rounded rectangle.

[0097] Fig. 19A - Fig. Figure 19C illustrates a third alternative arrangement of the first exemplary structure after the formation of source electrodes 52 and drain electrodes 56. In this embodiment, the chamfer on the upper circumferential edges of the second dielectric spacer matrix layer 46 can be applied during the second anisotropic etching step in the processing steps of the Fig. 10A - Fig. 10D may be more pronounced than in the second alternative configuration of the first exemplary structure. In the third alternative configuration, the section of the upper circumferential edge of each of the source electrodes 52 and the drain electrodes 56 in contact with the dielectric composite matrix (43, 44, 46) may have a respective contour profile such that the entirety or a predominant section of the upper circumferential edge of each of the source electrodes 52 and the drain electrodes 56 in contact with the dielectric composite matrix (43, 44, 46) is curved.

[0098] Fig. 20A - Fig. Figure 20C illustrates a fourth alternative arrangement of the first exemplary structure after the formation of source electrodes 52 and drain electrodes 56. In this embodiment, each discrete dielectric template structure 42T can be formed with a non-rectangular horizontal cross-sectional shape, such that the areas in which the source electrodes 52 and the drain electrodes 56 are to be formed have a greater width along the second horizontal direction hd2 than the areas in which the dielectric inter-electrode spacers 42 are subsequently to be formed. In the fourth alternative arrangement, end sections of each of the source electrodes 52 and the drain electrodes 56, which project laterally along the second horizontal direction hd2, can have a rounded horizontal cross-sectional profile.

[0099] We consider the overall Fig. 18A - Fig. 18C, Fig. 19A - Fig. 19C and Fig. 20A - Fig. 20C, where the horizontal cross-sectional shapes of the discrete dielectric stencil structures 42T and the horizontal cross-sectional shapes of the source electrodes 52 and the drain electrodes 56 can be selected to optimize the device performance of the field-effect transistors. In general, the etch mask material sections 71 can be formed with straight edges extending laterally along the second horizontal direction hd2. In this embodiment, the entirety of the vertical side walls of the dielectric intermediate electrode spacers 42, which contact the source electrodes 52 or the drain electrodes 56, can be located within a respective Euclidean vertical plane, that is, within a respective vertical plane without curvature.

[0100] A top surface of the dielectric composite matrix (43, 44, 46), top surfaces of the dielectric intermediate electrode spacers 42, and top surfaces of the source electrodes 52 and the drain electrodes 56 can be formed within the same horizontal plane, such as the second horizontal plane HP2. In one embodiment, the entirety of each interface between the dielectric intermediate electrode spacers 42 and the source electrodes 52 can be straight and vertical and can be located in a respective vertical Euclidean plane. In another embodiment, the entirety of each interface between the dielectric intermediate electrode spacers 42 and the drain electrodes 56 can be straight and vertical and can be located in a respective vertical Euclidean plane.In one embodiment, at least one, and / or each, interface between each of the source electrodes 52 and the dielectric composite matrix (43, 44, 46) comprises a contoured and tapered interface segment extending downwards from an edge of a horizontal top surface of the second dielectric spacer matrix layer 46, and a vertical interface segment bordering a lower edge of the contoured and tapered interface segment and extending downwards to a bottom surface of the dielectric composite matrix (43, 44, 46).In one embodiment, at least one, and / or each, interface between each of the drain electrodes 56 and the dielectric composite matrix (43, 44, 46) comprises a contoured and tapered interface segment extending downwards from an edge of a horizontal top surface of the second dielectric spacer matrix layer 46, and a vertical interface segment bordering a lower edge of the contoured and tapered interface segment and extending downwards to a bottom surface of the dielectric composite matrix (43, 44, 46).

[0101] With reference to the Fig. 21A - Fig. 21C may provide a second exemplary structure according to a second embodiment of the present disclosure from the one in Fig. The first exemplary structure illustrated in Figure 1 can be derived by omitting the formation of the process-internal insulating layer 635' at a gate level and by forming a two-dimensional array of memory structures (98, 198). The two-dimensional array of memory structures (98, 198) can comprise a two-dimensional array of capacitor structures 98 or a two-dimensional array of resistor memory structures 198. The components of the two-dimensional array of memory structures (98, 198) can be arranged vertically such that a first electrode (92, 192) of the memory structures (98, 198) is formed at the top. In this embodiment, a subset of metal interconnect structures (such as source-connection via structures 82), which are to be formed subsequently, can contact a top surface of each of the first electrodes (92, 192) of the memory structures (98, 198).In general, the two-dimensional array of storage structures (98, 198) can be formed within a dielectric material layer 90 on a storage plane.

[0102] Dielectric material layers (70, 80) on a connection plane can be formed above the dielectric material 90 on a storage plane, and metal interconnect structures (72, 74, 76, 78, 82, 84) can be formed within the dielectric material layers (70, 80) on a connection plane. For example, at least one second dielectric material layer 80 on a connection plane and second metal interconnect structures 82 on a top plane can be formed above the dielectric material layer 90 on a storage plane. The at least one second dielectric material layer 80 on a connection plane can include a second dielectric material layer on a via plane through which source-contact via structures 82 extend vertically. Each of the source-contact via structures 82 can contact a respective first electrode of the storage structures (98, 198).

[0103] Subsequently, at least one first dielectric material layer 70 on a connection plane and an optional dielectric etch stop layer 171 can be formed. First metal interconnect structures (72, 74, 76, 78) on a connection plane can be formed in the at least one first dielectric material layer 70 on a connection plane and the optional electrical etch stop layer 171. The at least one first dielectric material layer 70 on a connection plane can comprise a first dielectric material layer on a conductor plane in which source interconnect pads 74 and bit lines 78 are formed, and a first dielectric material layer on a via plane through which source contact via structures 72 and drain contact via structures 76 extend vertically.

[0104] In general, source-contact via structures 72 can be formed on the source electrodes 52, and drain-contact via structures 76 can be formed on the drain electrodes 56. Bit lines 78 can be formed on the drain-contact via structure 76 such that each of the bit lines 78 extends laterally along a horizontal direction perpendicular to the longitudinal direction of the word lines 3. The bit lines 78 can extend laterally along a horizontal direction (such as the first horizontal direction hd1) that differs from the second horizontal direction hd2. In one embodiment, each of the active layers 20 can have a rectangular horizontal cross-sectional shape with first sides parallel to the first horizontal direction hd1 and second sides parallel to the second horizontal direction hd2.

[0105] Source-connect metal interconnect structures (72, 74, 82) can be formed within the dielectric material layers (70, 80) at the interconnect level and can be used to electrically connect each first electrode of the memory structures (98, 198) to a respective source electrode to be formed subsequently. In this embodiment, each source-contact via structure 72 can be formed through the dielectric etch stop layer 171 at a location where a source electrode is to be formed subsequently. Likewise, drain-connect metal interconnect structures (76, 78) can be formed within the dielectric material layers (70, 80) at the interconnect level and can be used to electrically connect the bit lines 78 to a respective subset of the drain electrodes to be formed subsequently.In this embodiment, each drain-contact via structure 78 can be formed through the dielectric etch stop layer 171 at a location where a drain electrode is subsequently to be formed. The source-contact via structures 72 can be formed as a two-dimensional periodic array of source-contact via structures 78, and the drain-contact via structures 76 can be formed as a two-dimensional periodic array of drain-contact via structures 76.

[0106] With reference to the Fig. 22A - Fig. 22C, a dielectric stencil material layer 42L and a hard mask layer 47L can be formed over the two-dimensional periodic array of source-contact vias 78 and the two-dimensional periodic array of drain-contact vias 76. The processing steps of the Fig. 4A - Fig. 4C can be used to form the dielectric stencil material layer 42L and the hard mask layer 47L. Each of the dielectric stencil material layer 42L and the hard mask layer 47L can have the same material composition and thickness range as in the first embodiment of the present disclosure.

[0107] With reference to the Fig. 23A - Fig. 23C can perform the processing steps of the Fig. 5A - Fig. 5C is performed to pattern the hard mask layer 47L and the dielectric stencil material layer 42L into a patterned hard mask layer 47 and a two-dimensional periodic array of discrete dielectric stencil structures 42T. The bottom surfaces of the discrete dielectric stencil structures 42T can be located within a first horizontal plane HP1, and the top surfaces of the discrete dielectric stencil structures 42T can be located within a second horizontal plane HP2. Because a continuous active layer is not present in the second exemplary structure during this processing step, the anisotropic etching process can utilize the dielectric etch stop layer 171 as an etch stop structure during the patterning of the dielectric stencil material layer 42L into the discrete dielectric stencil structures 42T.

[0108] With reference to the Fig. 24A - Fig. 24C can perform the processing steps of the Fig. 6A - Fig. 6C is used to deposit and planarize a dielectric etch stop lining 43 and a first dielectric spacer matrix layer 44. The structured hard mask layer 47 can optionally be removed. The top surface of the first dielectric spacer matrix layer 44 can be coplanar—or substantially coplanar—with the top surfaces of the two-dimensional periodic array of discrete dielectric stencil structures 42T.

[0109] With reference to the Fig. 25A - Fig. 25C can be used for the processing steps of the Fig. 7A - Fig. The process 7C is carried out to vertically recess the top surface of the first dielectric spacer matrix layer 44. A recess region 45 can be formed above the recessed top surface of the first dielectric spacer matrix layer 44.

[0110] With reference to the Fig. 26A - Fig. 26C can be used for the processing steps of the Fig. 8A - Fig. 8C is carried out to form a second dielectric spacer matrix layer 46, which may have a top surface within the second horizontal plane HP2. A dielectric composite matrix (43, 44, 46) is formed, which may have the same height (i.e., vertical thickness) as the two-dimensional array of discrete dielectric template structures 42T.

[0111] With reference to the Fig. 27A - Fig. 27D, an etch mask material layer 71L, at least one optional structure transfer support layer (73L, 75L), and a photoresist layer 77 can be sequentially formed over the two-dimensional array of discrete dielectric stencil structures 42T and the dielectric composite matrix (43, 44, 46). The processing steps of the Fig. 9A - Fig. 9D can be used. The photoresist layer 77 can be structured with openings in the same way as described above. Fig. 9A - Fig. 9D described.

[0112] With reference to the Fig. 28A - Fig. 28D can perform the processing steps of the Fig. 10A - Fig. 10D is performed to transfer the structure in the photoresist layer 77 through at least one optional structure transfer support layer (73L, 75L) and the etch mask material layer 71L and into a section of the discrete dielectric stencil structures 42T – selectively for the material of the second dielectric spacer matrix layer 46. An anisotropic etching process can be performed in the same way as described above with reference to the Fig. 10A - Fig. 10D described. The horizontal cross-sectional profiles and the vertical cross-sectional profiles of each of the source cavities 51, the drain cavities 59 and the second dielectric spacer matrix layer 46 can be the same as above with reference to the Fig. 10A - Fig. 10D described.

[0113] With reference to the Fig. 29A - Fig. 29D can be used for the processing steps of the Fig. 11A - Fig. 11D is performed to deposit at least one metallic material in the source cavities 51 and the drain cavities 59 and over the etch mask material sections 71 (that is, the structured sections of the etch mask material layer 71L), a two-dimensional array of dielectric interelectrode spacers 42, and the dielectric composite matrix (43, 44, 46). For example, the at least one metallic material can comprise a metallic lining layer 53L and a metallic filler material layer 54L.

[0114] With reference to the Fig. 30A - Fig. 30E can perform the processing steps of the Fig. 12A - Fig. 12E are carried out to planarize the at least one metallic material and form source electrodes 52 and drain electrodes 56. The horizontal and vertical cross-sectional profiles of each of the source electrodes 52, the drain electrodes 56, and the second dielectric spacer matrix layer 46 can be the same as described above with reference to the Fig. 12A - Fig. 12E is described. A two-dimensional array of source-spacer-drain combinations (52, 42, 56) is formed.

[0115] A top surface of the dielectric composite matrix (43, 44, 46), top surfaces of the dielectric intermediate electrode spacers 42, and top surfaces of the source electrodes 52 and the drain electrodes 56 can be formed within the same horizontal plane, such as the second horizontal plane HP2. In one embodiment, the entirety of each interface between the dielectric intermediate electrode spacers 42 and the source electrodes 52 can be straight and vertical and can be located in a respective vertical Euclidean plane. In another embodiment, the entirety of each interface between the dielectric intermediate electrode spacers 42 and the drain electrodes 56 can be straight and vertical and can be located in a respective vertical Euclidean plane.In one embodiment, at least one, and / or each, interface between each of the source electrodes 52 and the dielectric composite matrix (43, 44, 46) comprises a contoured and tapered interface segment extending downwards from an edge of a horizontal top surface of the second dielectric spacer matrix layer 46, and a vertical interface segment bordering a lower edge of the contoured and tapered interface segment and extending downwards to a bottom surface of the dielectric composite matrix (43, 44, 46).In one embodiment, at least one, and / or each, interface between each of the drain electrodes 56 and the dielectric composite matrix (43, 44, 46) comprises a contoured and tapered interface segment extending downwards from an edge of a horizontal top surface of the second dielectric spacer matrix layer 46, and a vertical interface segment bordering a lower edge of the contoured and tapered interface segment and extending downwards to a bottom surface of the dielectric composite matrix (43, 44, 46).

[0116] In one embodiment, the dielectric composite matrix (43, 44, 46) comprises a dielectric etch stop lining 43, which contacts a bottom surface and side walls of the first dielectric spacer matrix layer 44 and contacts lower sections of each of the source electrodes 52 and drain electrodes 56, as well as lower sections of each dielectric intermediate electrode spacer 42. In another embodiment, the dielectric etch stop lining 43 can have a bottom surface that lies within the same horizontal plane (i.e., the first horizontal plane HP1) that contains the bottom surfaces of the dielectric intermediate electrode spacers 42.

[0117] In the second exemplary structure, a two-dimensional array of storage structures (98, 198) is formed before the formation of the source electrodes 52 and the drain electrodes 56. Each storage structure (98, 198) within the two-dimensional array of storage structures (98, 198) is electrically connected to a respective source electrode 52 within the two-dimensional array of source-spacer-drain combinations (52, 42, 56).

[0118] With reference to the Fig. 31A - Fig. 31E A continuous active layer can be deposited over the dielectric composite matrix (43, 44, 46) and the two-dimensional array of source-spacer-drain combinations (52, 42, 56). The continuous active layer can then be structured into a two-dimensional periodic array of active layers 20, which can have the same material composition and thickness range as the active layers 20 in the first exemplary structure. In one embodiment, the two-dimensional array of active layers 20 can be formed over the source electrodes 52 and the drain electrodes 56, such that each active layer 20 within the two-dimensional array of active layers 20 is formed directly on the top surfaces of a respective pair of a source electrode 52 and a drain electrode 56.In one embodiment, a bottom surface of each active layer 20 within the two-dimensional array of active layers 20 can be located within a horizontal plane that has a top surface of the dielectric composite matrix (43, 44, 46). In another embodiment, each source-spacer-drain combination (52, 42, 56) within the two-dimensional array of source-spacer-drain combinations (52, 42, 56) contacts a horizontal surface of a respective active layer 20 within the two-dimensional array of active layers 20.

[0119] In one embodiment, each of the active layers 20 can have the same horizontal cross-sectional shape, which may be rectangular, covering the entire top surface of a respective underlying source-spacer-drain combination (52, 42, 56). In another embodiment, the sidewalls of each active layer 20 can be laterally offset outwards from a circumference of the top surface of an underlying source-spacer-drain combination (52, 42, 56) without contacting each other. The gap between adjacent pairs of active layers 20 can be in a range of 1 nm to 40 nm, such as 2 nm to 20 nm, although smaller and larger dimensions for the gap can also be used.

[0120] With reference to the Fig. 32A - Fig. In 32E, a gate dielectric layer 10 and gate electrodes 15 can be formed over the two-dimensional array of active layers 20. The gate dielectric layer 10 can have the same material composition and thickness range as the gate dielectric layer 10 of the first embodiment of the present disclosure. The gate electrodes 15 can extend laterally along the second horizontal direction hd2 over a respective column of active layers 20. The lateral extension of the gate electrodes 15 along the first horizontal direction hd1 and the planar overlap of each gate electrode 15 with a respective underlying active layer 20 in a top view can be the same or approximately the same as in the first exemplary structure.

[0121] In the second embodiment, the gate electrodes 15 can be formed after the formation of the two-dimensional array of discrete dielectric template structures 42T, the source electrodes 52, and the drain electrodes 56. Undersides of the active layers 20 within the two-dimensional array of active layers 20 and segments of a bottom side of the gate dielectric layer 10 that contact the second dielectric spacer matrix layer 46 can be located within the same horizontal plane (such as the second horizontal plane HP2) as the top sides of the source electrodes 52 and the drain electrodes 56 and the second dielectric spacer matrix layer 46.

[0122] With reference to the Fig. 33A - Fig. 33E an insulating layer 635 can be deposited on the gate plane over the gate electrodes 15 and planarized to form a two-dimensional array of memory cells 99.

[0123] We consider the overall Fig. 1 - Fig. 33E, where a two-dimensional array of memory structures (98, 198) can be formed above or below a two-dimensional array of field-effect transistors (which may include a two-dimensional array of thin-film transistors). Metal interconnect structures (72, 74, 76, 78, 82, 84) can be formed above or below the two-dimensional array of field-effect transistors, such that each memory structure (98, 198) within the two-dimensional array of memory structures (98, 198) is electrically connected to a source electrode 52 of a respective field-effect transistor within the two-dimensional array of field-effect transistors.

[0124] Within the two-dimensional array of field-effect transistors, a two-dimensional array of active layers 20 lies above or below a two-dimensional array of source-spacer-drain combinations (52, 42, 56). In one embodiment, each connected combination of a source electrode 52, a drain electrode 56, and a dielectric intermediate electrode spacer 42 contacts a horizontal surface of a respective stack consisting of an active layer 20 selected from the two-dimensional array of active layers 20, a gate dielectric layer 10, and a gate electrode 15.

[0125] The gate electrodes 15 can be formed before or after the formation of the two-dimensional array of discrete dielectric template structures 42T, the source electrodes 52, and the drain electrodes 56. The two-dimensional array of active layers 20 can be formed before or after the formation of the source electrodes 52 and the drain electrodes 56, such that each of the active layers 20 has a planar overlap within one of the respective source electrodes 52 and with one of the respective drain electrodes 56. A bottom surface of each active layer 20 within the two-dimensional array of active layers 20 can be located within a horizontal plane that has a top surface or a bottom surface of the dielectric composite matrix (43, 44, 46). The horizontal plane can be a first horizontal plane HP1, as described above, or a second horizontal plane HP2, as described above.

[0126] With reference to the Fig. 34A - Fig. 34C, a third exemplary structure according to a third embodiment of the present disclosure may be the same or substantially the same as that described in the Fig. 2A - Fig. Figure 2C illustrated a first embodiment of the present disclosure. The width of each word line 3 can be uniform along the second horizontal direction hd2 and can be optimized as required. In one embodiment, the width of each word line 3 can be larger than the lateral dimension along the first horizontal direction hd1 of a stack consisting of a gate electrode, a dielectric barrier layer, and a subsequently formed charge storage element.

[0127] With reference to the Fig. 35A - Fig. In 35C, a two-dimensional array of stacks consisting of a gate electrode 15, a dielectric barrier 152, and a charge storage element 154 can be formed over the word lines 3. For example, a gate electrode material layer, a continuous dielectric barrier, and a continuous charge storage material layer can be deposited over the word lines 3. A photoresist layer (not shown) can be deposited over the continuous charge storage material layer and can be lithographically structured into a two-dimensional array of discrete photoresist material sections located, in a top view, within regions of the word lines 3. An anisotropic etching process can be performed to transfer the structure in the photoresist layer through the continuous charge storage material layer, the continuous dielectric barrier, and the gate electrode material layer.The continuous charge storage material layer can be subdivided into a two-dimensional array of charge storage elements 154. The continuous dielectric barrier layer can be subdivided into a two-dimensional array of dielectric barrier layers 152. The gate electrode material layer can be subdivided into a two-dimensional array of gate electrodes 15. Within each stack consisting of a gate electrode 15, a dielectric barrier layer 152, and a charge storage element 154, the side walls of the gate electrode 15, the dielectric barrier layer 152, and the charge storage element 154 can be vertically aligned, that is, they can be located within the same vertical plane.

[0128] Each gate electrode 15 comprises at least one conductive material, such as at least one metallic material. The thickness of each gate electrode 15 can be in the range of 10 nm to 150 nm, such as 30 nm to 100 nm, although smaller and larger thicknesses can also be used. Each dielectric barrier 152 comprises at least one dielectric material that can effectively block the tunneling of electrons. For example, each dielectric barrier 152 can comprise silicon oxide and / or a dielectric metal oxide (such as aluminum oxide). The thickness of each dielectric barrier 152 can be in the range of 5 nm to 30 nm, such as 8 nm to 15 nm, although smaller and larger thicknesses can also be used. Each charge storage element 154 comprises a material in which electrical charges can be stored.For example, each charge storage element 154 can comprise a dielectric charge-trapping material (such as silicon nitride) or a potential-free gate material (which can comprise a semiconductor or metallic material). The thickness of each charge storage element 154 can be in the range of 5 nm to 100 nm, for example, 10 nm to 30 nm, although smaller and larger thicknesses can also be used. An additional insulating material layer (referred to in this text as a gate-electrode-level insulating layer) can be deposited over the in-process insulated layer 635' at a gate level and can be integrated into the in-process insulated layer 635' at a gate level to provide a gate-level insulating layer 635.

[0129] With reference to the Fig. 36A - Fig. 36E can perform the processing steps of the Fig. 4A - Fig. Figures 4C to 156 are carried out with the modification that a dielectric tunneling layer 156 is used instead of the gate dielectric layer 10. The dielectric tunneling layer 156 is a type of gate dielectric layer that allows charge carriers to tunnel through it. The dielectric tunneling layer 156 thus contains a dielectric material through which charge carriers (such as electrons or holes) can tunnel. Any dielectric tunneling material known to those skilled in the art can be used for the dielectric tunneling layer 156. In an illustrative example, the dielectric tunneling layer 156 can comprise silicon oxide or a stack of layers consisting of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer (known in the prior art as an ONO stack).The thickness of the dielectric tunnel layer 156 can be in a range of 1 nm to 6 nm, such as 2 nm to 4 nm, although smaller and larger thicknesses can also be used.

[0130] The horizontal and vertical cross-sectional profiles of each of the source electrodes 52, drain electrodes 56, and the second dielectric spacer matrix layer 46 can be the same as in the first and second exemplary structures. Generally, a stack comprising a dielectric tunnel layer 156, a charge storage element 154, and a dielectric barrier layer 152 is formed between each of the gate electrodes 15 and a respective adjacent pair of source electrodes 52 and drain electrodes 56, selected from the source electrodes 52 and drain electrodes 56. A two-dimensional array of layer stacks (15, 152, 154) is provided below the dielectric tunnel layer 156.Each of the layer stacks (15, 152, 154) comprises a charge storage element 154, a dielectric barrier layer 152 and a gate electrode 15 and is spaced from a respective active layer 20 within the two-dimensional array of active layers 20 by the dielectric tunnel layer 156.

[0131] A bottom surface of the dielectric composite matrix (43, 44, 46) and bottom surfaces of the active layers 20 within the two-dimensional array of active layers 20 are located within the same horizontal plane, such as the first horizontal plane HP1. A bottom surface of each active layer 20 within the two-dimensional array of active layers 20 is located within a horizontal plane that has a bottom surface of the dielectric composite matrix (43, 44, 46), such as the first horizontal plane HP1. Each source-spacer-drain combination (52, 42, 56) within the two-dimensional array of source-spacer-drain combinations (52, 42, 56) contacts a horizontal surface (such as the top surface) of a respective active layer 20 within the two-dimensional array of active layers 20.

[0132] Subsequently, dielectric material layers can be formed on a connection plane (not shown) over the source electrodes 52 and the drain electrodes 56, and metal interconnect structures (not shown) can be formed in the dielectric material layers on a connection plane to establish an electrical connection with the source electrodes 52 and the drain electrodes 56. In one embodiment, each source electrode 52 can be electrically biased by a respective node in the CMOS circuit 700, and each drain electrode 56 can be electrically biased by a respective node in the CMOS circuit 700. In an illustrative example, the source electrodes 52 can be electrically grounded, and a drain electrode 56 can be connected to bit line drivers within the CMOS circuit 700.

[0133] With reference to the Fig. 37A - Fig. 37E can provide a fourth exemplary structure according to the fourth embodiment of the present disclosure from the one described in the Fig. 32A - Fig. 32E illustrated second exemplary structure can be derived by the formation of the two-dimensional array of memory structures (98, 198) in the processing steps of the Fig. 21A - Fig. 21C is omitted by modifying the electrical connections for source-connected via structures 82, 184 such that each source electrode 52 is electrically connected to a respective node in the CMOS circuit 700 by forming a dielectric tunnel layer 156 instead of a gate dielectric layer 10, and by forming a two-dimensional array of layer stacks (15, 152, 154) instead of the gate electrodes 15 used in the second exemplary structure. Thus, each source electrode 52 can be electrically biased by a respective node in the CMOS circuit 700, and each drain electrode 56 can be electrically biased by a respective node in the CMOS circuit 700. In an illustrative example, the source electrodes 52 can be electrically grounded, and a drain electrode 56 can be connected to bit line drivers within the CMOS circuit 700.

[0134] The dielectric tunneling layer 156 is a type of gate dielectric layer that allows charge carriers to tunnel through it. The dielectric tunneling layer 156 in the fourth exemplary structure can have the same material composition and thickness range as the dielectric tunneling layer 156 in the third exemplary structure. The two-dimensional array of layer stacks (15, 152, 154) in the fourth exemplary structure can be the same, or substantially the same, as the two-dimensional array of layer stacks (15, 152, 154) in the third exemplary structure, except that the vertical order of layers within each layer stack (15, 152, 154) is reversed.In one embodiment, the two-dimensional array of layer stacks (15, 152, 154) in the fourth exemplary structure can be formed by successive deposition and subsequent structuring of a continuous charge storage material layer, a continuous dielectric barrier layer and a gate electrode material layer.

[0135] The horizontal and vertical cross-sectional profiles of each of the source electrodes 52, drain electrodes 56, and the second dielectric spacer matrix layer 46 can be the same as in the first and second exemplary structures. Generally, a stack comprising a dielectric tunnel layer 156, a charge storage element 154, and a dielectric barrier layer 152 is formed between each of the gate electrodes 15 and a respective adjacent pair of source electrodes 52 and drain electrodes 56, selected from the source electrodes 52 and drain electrodes 56. A two-dimensional array of layer stacks (154, 152, 15) is provided above the dielectric tunnel layer 156.Each of the layer stacks (154, 152, 15) comprises a charge storage element 154, a dielectric barrier layer 152 and a gate electrode 15 and is spaced from a respective active layer 20 within the two-dimensional array of active layers 20 by the dielectric tunnel layer 156.

[0136] In one embodiment, the undersides of the active layers 20 within the two-dimensional array of active layers 20 and segments of an underside of a dielectric tunneling layer 156 (which is a gate dielectric layer that allows charges to tunnel through it), which contact the second dielectric spacer matrix layer 46, are located within the same horizontal plane (such as the second horizontal plane HP2) as the top sides of the source electrodes 52 and the drain electrodes 56. In another embodiment, an underside of each active layer 20 within the two-dimensional array of active layers 20 is located within a horizontal plane that has a top side of the dielectric composite matrix (43, 44, 46).

[0137] With reference to the Fig. 38A - Fig. 38E A dielectric material layer 635 can be formed on a gate plane above the two-dimensional array of layer stacks (154, 152, 15). Conductor trenches extending laterally along the second horizontal direction hd2 can be formed in an upper section of the dielectric material layer 635 on a gate plane, such that the tops of a column of gate electrodes 15 are physically exposed at the bottom of each conductor trench. At least one conductive material can be deposited in the conductor trenches, and excess sections of the at least one conductive material can be removed from above the horizontal plane that forms the top of the dielectric material layer 635 on a gate plane. Remaining sections of the at least one conductive material form word lines 3.Each word line 3 contacts a respective column of the gate electrodes 15 and extends laterally along the second horizontal direction hd2.

[0138] Several alternative configurations of the exemplary structures described above can be provided. According to one aspect of the present disclosure, the first dielectric spacer matrix layer 44 can be formed by depositing and vertically recessing more than two dielectric materials. The dielectric etch stop lining 43 can optionally be used in any of the various alternative configurations. Although examples of the alternative configurations described below do not use a dielectric etch stop lining 43, embodiments in which a dielectric etch stop lining 43 is used in conjunction with the modifications in the alternative configurations described below are expressly considered in the present text.

[0139] With reference to Fig. 39 A fifth alternative arrangement of the first exemplary structure can be derived from the first exemplary structure or from any of the previously described alternative arrangements of the first exemplary structure by using a combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B. The first dielectric spacer sublayer 44A can comprise any dielectric material that can be vertically recessed—selectively for the material of the discrete dielectric template structures 42T. The first dielectric spacer sublayer 44A can be formed by depositing a first dielectric spacer sublayer material in the trenches 41 and vertically recessing the top surface of the first dielectric spacer sublayer 44A below the second horizontal plane HP2.The second dielectric spacer sublayer 44B can comprise any dielectric material that can be vertically recessed—selectively for the material of the discrete dielectric template structures 42T—and differs from the material of the first dielectric spacer sublayer 44A. The second dielectric spacer sublayer 44B can be formed by depositing a second dielectric spacer sublayer material in the trenches 41 above the top surface of the first dielectric spacer sublayer 44A and vertically recessing the top surface of the second dielectric spacer sublayer 44A below the second horizontal plane HP2. The combination of the first dielectric spacer sublayer 44A and the second dielectric spacer sublayer 44B forms the first dielectric spacer matrix layer 44.A second dielectric spacer matrix layer 46 can be formed above the first dielectric spacer matrix layer 44, such that a top surface of the second dielectric spacer matrix layer 46 is located within the second horizontal plane HP2. In general, the materials of the first dielectric spacer sublayer 44A and the second dielectric spacer sublayer 44B can be selected from any material that can be used for the first dielectric spacer matrix layer 44 of the embodiments described above.

[0140] With reference to Fig. 40 An alternative arrangement of the second exemplary structure can be derived from the second exemplary structure by replacing the first dielectric spacer matrix layer 44 in the second exemplary structure, as described above, with a combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B. The processing steps, which refer to the fifth alternative arrangement of the in Fig. The first exemplary structure described in Figure 39 can be used to provide the combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B in the alternative arrangement of the second exemplary structure.

[0141] With reference to Fig. 41 An alternative arrangement of the third exemplary structure can be derived from the third exemplary structure by replacing the first dielectric spacer matrix layer 44 in the third exemplary structure, as described above, with a combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B. The processing steps, which refer to the fifth alternative arrangement of the in Fig. The first exemplary structure described in Figure 39 can be used to provide the combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B in the alternative arrangement of the third exemplary structure.

[0142] With reference to Fig. 42 An alternative arrangement of the fourth exemplary structure can be derived from the fourth exemplary structure by replacing the first dielectric spacer matrix layer 44 in the fourth exemplary structure, as described above, with a combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B. The processing steps, which refer to the fifth alternative arrangement of the in Fig. The first exemplary structure described in Figure 39 can be used to provide the combination of a first dielectric spacer sublayer 44A and a second dielectric spacer sublayer 44B in the alternative arrangement of the fourth exemplary structure.

[0143] With reference to Fig. Figure 43 illustrates an alternative arrangement for any of the exemplary structures according to an embodiment of the present disclosure. Fig. The alternative setup illustrated in section 43 can be derived from any of the exemplary structures described above by vertically stacking several two-dimensional arrays of memory cells 99. While a setup in which four two-dimensional arrays of memory cells 99 are vertically stacked in Fig. As illustrated in Figure 44, the present text also explicitly considers additional facilities in which two, three, five or more two-dimensional arrays of memory cells are stacked vertically.

[0144] With reference to Fig. 44 A first flowchart illustrates a first set of general processing steps for manufacturing the semiconductor devices according to an embodiment of the present disclosure.

[0145] Referring to step 4410 and the Fig. 1 - Fig. 3C and Fig. 34A - Fig. 35C, gate electrodes 15 are formed over a substrate.

[0146] Referring to step 4420 and the Fig. 4A - Fig. 5C and Fig. 36A - Fig. 36E forms a two-dimensional array of discrete dielectric template structures 42T. The discrete dielectric template structures 42T are spaced apart from each other by trenches 41.

[0147] Referring to step 4430 and the Fig. 6A - Fig. 7C, Fig. 36A - Fig. 36E, Fig. 39 and Fig. 41 A first dielectric spacer matrix layer 44 is formed by depositing a first dielectric spacer material in lower sections of the trenches 41.

[0148] Referring to step 4440 and the Fig. 8A - Fig. 8C and Fig. 36A - Fig. 36E a second dielectric spacer matrix layer 46 is formed by depositing a second dielectric spacer material in upper sections of the trenches 41.

[0149] Referring to step 4450 and the Fig. 9A - Fig. 10D and Fig. 36A - Fig. 36E a pair of a source cavity 51 and a drain cavity 59 is formed within a volume of each of the discrete dielectric template structures 42T.

[0150] Referring to step 4460 and the Fig. 11A - Fig. 17, Fig. 18A - Fig. 18C, Fig. 19A - Fig. 19C, Fig. 20A - Fig. 20C and Fig. 36A - Fig. 36E a source electrode 52 and a drain electrode 56 are formed in each source cavity 51 and each drain cavity 59, respectively.

[0151] With reference to Fig. 45 A second flowchart illustrates a second set of general processing steps for manufacturing the semiconductor devices according to an embodiment of the present disclosure.

[0152] Referring to step 4510 and the Fig. 21A - Fig. 23C and Fig. 37A - Fig. 37E forms a two-dimensional array of discrete dielectric template structures 42T. The discrete dielectric template structures 42T are spaced apart from each other by trenches 41.

[0153] Referring to step 4520 and the Fig. 24A - Fig. 25°C, Fig. 37A - Fig. 37E, Fig. 40 and Fig. 42 A first dielectric spacer matrix layer 44 is formed by depositing a first dielectric spacer material in lower sections of the trenches 41.

[0154] Referring to step 4530 and the Fig. 26A - Fig. 26C and Fig. 37A - Fig. 37E a second dielectric spacer matrix layer 46 is formed by depositing a second dielectric spacer material in upper sections of the trenches 41.

[0155] Referring to step 4540 and the Fig. 27A - Fig. 28D and Fig. 37A - Fig. 37E a pair of a source cavity 51 and a drain cavity 59 is formed within a volume of each of the discrete dielectric template structures 42T.

[0156] Referring to step 4550 and the Fig. 29A - Fig. 30E and Fig. 37A - Fig. 37E a source electrode 52 and a drain electrode 56 are formed in each source cavity 51 and each drain cavity 59, respectively.

[0157] Referring to step 4560 and the Fig. 31A - Fig. 33E, Fig. 37A - Fig. 37E and Fig. 38A - Fig. 38E Gate electrodes 15 are formed via the source electrodes 52 and the drain electrodes 56.

[0158] With reference to all the drawings and according to various embodiments of the present disclosure, a semiconductor structure is provided comprising: a two-dimensional array of source-spacer-drain combinations (52, 42, 56) arranged over a substrate and laterally spaced apart from one another by a dielectric composite matrix (43, 44, 46), wherein each source-spacer-drain combination (52, 42, 56) selected from the two-dimensional array of source-spacer-drain combinations (52, 42, 56) comprises a dielectric intermediate electrode spacer 42 in contact with a source electrode 52 and a drain electrode 56, and wherein the dielectric composite matrix (43, 44, 46) comprises a first dielectric spacer matrix layer 44, which includes a first dielectric spacer material, and a second dielectric spacer matrix layer 46.comprising a second dielectric spacer material and located above the first dielectric spacer matrix layer; a two-dimensional array of active layers 20 located above or below the two-dimensional array of source-spacer-drain combinations (52, 42, 56); gate electrodes 15 spaced from the two-dimensional array of active layers 20 by a gate dielectric layer 10; and a two-dimensional array of memory structures (98, 198), wherein each memory structure (98, 198) within the two-dimensional array of memory structures (98, 198) is electrically connected to a respective source electrode 52 within the two-dimensional array of source-spacer-drain combinations (52, 42, 56).

[0159] With reference to all the drawings and according to various embodiments of the present disclosure, a semiconductor structure is provided comprising: a two-dimensional array of source-spacer-drain combinations (52, 42, 56) arranged over a substrate and laterally spaced apart from one another by a dielectric composite matrix (43, 44, 46), wherein each source-spacer-drain combination (52, 42, 56) selected from the two-dimensional array of source-spacer-drain combinations (52, 42, 56) comprises a dielectric intermediate electrode spacer 42 in contact with a source electrode 52 and a drain electrode 56, and wherein the dielectric composite matrix (43, 44, 46) comprises a first dielectric spacer matrix layer 44, which includes a first dielectric spacer material, and a second dielectric spacer matrix layer 46.comprising a second dielectric spacer material and located above the first dielectric spacer matrix layer; a two-dimensional array of active layers 20 located above or below the two-dimensional array of source-spacer-drain combinations (52, 42, 56); and a two-dimensional array of layer stacks (15, 152, 154), each layer stack comprising a charge storage element 154, a dielectric barrier layer 152, and a gate electrode 15, and spaced from a respective active layer 20 within the two-dimensional array of active layers 20 by a dielectric tunnel layer 156.

[0160] The various embodiments of the present disclosure can be used to provide a two-dimensional array of transistors (for example, thin-film transistors) that are laterally spaced apart from one another by a dielectric composite matrix (43, 44, 46), thereby limiting the lateral extensions of the source electrodes 52 and the drain electrodes 56 during the fabrication process. In this respect, the source electrodes 52 and the drain electrodes 56 of the transistors are self-aligned. The self-alignment of the two-dimensional array of transistors allows for fabrication with improved product yield and lower power variability.

[0161] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

Claims

[1] Method for forming a semiconductor structure, comprising: Forming a two-dimensional array of discrete dielectric template structures over a substrate, wherein the discrete dielectric template structures are spaced apart from each other by trenches; Forming a first dielectric spacer matrix layer by depositing a first dielectric spacer material in lower sections of the trenches; Forming a second dielectric spacer matrix layer by depositing a second dielectric spacer material in the upper sections of the trenches; Forming a pair of a source cavity and a drain cavity within a volume of each of the discrete dielectric template structures; Forming a source electrode and a drain electrode in each source cavity and each drain cavity, respectively; and Forming gate electrodes before or after the formation of the two-dimensional array of discrete dielectric template structures, thereby forming a two-dimensional array of field-effect transistors. [2] The method of claim 1, further comprising: Deposition and structuring of a photoresist layer over the two-dimensional array of discrete dielectric stencil structures and the second dielectric spacer matrix layer to form a two-dimensional array of apertures; and anisotropic etching - selective for a material of the second dielectric spacer matrix layer - of sections of the discrete dielectric stencil structures located within areas of the openings in the photoresist layer. [3] Method according to claim 2, wherein each opening in the two-dimensional array of openings has a respective region that extends continuously over an adjacent pair selected from the discrete dielectric stencil structures spaced laterally along a first horizontal direction along which a first subset of the trenches extends laterally, and over a section of the second dielectric spacer matrix layer. [4] Method according to claim 3, wherein: the photoresist layer is structured with a conduit-and-space structure in which the openings have straight edges extending laterally along a second horizontal direction perpendicular to the first horizontal direction; and Each opening in the photoresist layer has a first straight edge extending over a first slit of the discrete dielectric stencil structures arranged along the second horizontal direction, and a second straight edge extending over a second slit of the discrete dielectric stencil structures, the second slit being offset laterally from the first slit by less than a center-to-center distance of a two-dimensional array of the discrete dielectric stencil structures along the first horizontal direction. [5] The method of claim 2, further comprising: Forming an etch mask material layer over the second dielectric spacer matrix layer; Structuring the etch mask material layer by performing a first anisotropic etching step that transfers a structure in the photoresist layer through the etch mask material layer; and anisotropic etching of sections of the discrete dielectric stencil structures that are not masked by the structured etch mask material layer, by performing a second anisotropic etching step that selectively etches a material of the two-dimensional array of discrete dielectric stencil structures to a material of the second dielectric spacer matrix layer. [6] Method according to claim 5, wherein: Each remaining section of the discrete dielectric stencil structures after the second anisotropic etching step comprises a dielectric inter-electrode spacer located between each of the source cavities and each of the drain cavities, and physically exposed to them; the method comprises forming a two-dimensional array of active layers before or after the formation of the source electrodes and the drain electrodes, such that each of the two-dimensional array of active layers has a planar overlap within one of the source electrodes and with one of the drain electrodes; and Each connected combination of a source electrode, a drain electrode and a dielectric intermediate electrode spacer contacts a horizontal surface of a respective stack consisting of an active layer selected from the two-dimensional array of active layers, a gate dielectric layer and a gate electrode selected from the gate electrodes. [7] Method according to claim 1, wherein: the gate electrodes are formed prior to the formation of the two-dimensional array of discrete dielectric template structures; and The procedure includes: Forming a gate dielectric layer, a continuous active layer, and a dielectric template material layer over the gate electrodes; and Structuring the dielectric template material layer and the continuous active layer into a stack of the two-dimensional array of discrete dielectric template structures and a two-dimensional array of active layers. [8] Method according to claim 1, wherein: the gate electrodes are formed after the formation of the two-dimensional array of discrete dielectric template structures; and The procedure includes: Forming a two-dimensional array of active layers over the source electrodes and the drain electrodes, wherein each active layer within the two-dimensional array of active layers is formed directly on the top surfaces of a respective pair of source electrodes and drain electrodes; and Forming a gate dielectric layer over the two-dimensional array of active layers, wherein the gate electrodes are formed over the gate dielectric layer. [9] The method of claim 1, further comprising: Forming a two-dimensional array of memory structures above or below the two-dimensional array of field-effect transistors; and Forming metal interconnect structures above or below the two-dimensional array of field-effect transistors, such that each memory structure within the two-dimensional array of memory structures is electrically connected to a source electrode of a respective field-effect transistor within the two-dimensional array of field-effect transistors. [10] The method of claim 1, further comprising forming a stack comprising a dielectric tunnel layer, a charge storage element and a dielectric barrier layer between each of the gate electrodes and a respective adjacent pair of a source electrode and a drain electrode selected from the source electrodes and the drain electrodes. [11] Semiconductor structure comprising: a two-dimensional array of source-spacer-drain combinations arranged over a substrate and laterally spaced from each other by a dielectric composite matrix, wherein each source-spacer-drain combination selected from the two-dimensional array of source-spacer-drain combinations comprises a dielectric intermediate electrode spacer in contact with a source electrode and a drain electrode, and wherein the dielectric composite matrix comprises a first dielectric spacer matrix layer comprising a first dielectric spacer material, and a second dielectric spacer matrix layer comprising a second dielectric spacer material and lying above the first dielectric spacer matrix layer; a two-dimensional array of active layers that lies above or below the two-dimensional array of source-spacer-drain combinations; Gate electrodes that are spaced apart from the two-dimensional array of active layers by a gate dielectric layer; and a two-dimensional array of memory structures, wherein each memory structure within the two-dimensional array of memory structures is electrically connected to a respective source electrode within the two-dimensional array of source-spacer-drain combinations. [12] Semiconductor structure according to claim 11, wherein a top side of the dielectric composite matrix, top sides of the dielectric intermediate electrode spacers and top sides of the source electrodes and the drain electrodes are located within the same horizontal plane. [13] Semiconductor structure according to claim 11, wherein: a totality of each interface between the dielectric intermediate electrode spacers and the source electrodes is straight; and at least one interface between each of the source electrodes and the dielectric composite matrix comprises a contoured and tapered interface segment extending downwards from an edge of a horizontal top surface of the second dielectric spacer matrix layer, and a vertical interface segment bordering a bottom edge of the contoured and tapered interface segment and extending downwards to a bottom surface of the dielectric composite matrix. [14] Semiconductor structure according to claim 11, wherein the dielectric composite matrix comprises a dielectric etch stop lining which contacts a bottom and side walls of the first dielectric spacer matrix layer and contacts lower sections of each of the source electrodes and drain electrodes, as well as lower sections of each dielectric intermediate electrode spacer. [15] Semiconductor structure according to claim 11, wherein the two-dimensional array comprises memory structures: a two-dimensional array of capacitor structures comprising a respective first capacitor plate, a respective node dielectric, and a respective second capacitor plate; or a two-dimensional array of resistance storage structures comprising a first electrode, a resistance storage element containing a material providing at least two different levels of specific electrical resistance, and a second electrode. [16] Semiconductor structure comprising: a two-dimensional array of source-spacer-drain combinations arranged over a substrate and laterally spaced from each other by a dielectric composite matrix, wherein each source-spacer-drain combination selected from the two-dimensional array of source-spacer-drain combinations comprises a dielectric intermediate electrode spacer in contact with a source electrode and a drain electrode, and wherein the dielectric composite matrix comprises a first dielectric spacer matrix layer comprising a first dielectric spacer material, and a second dielectric spacer matrix layer comprising a second dielectric spacer material and lying above the first dielectric spacer matrix layer; a two-dimensional array of active layers that lies above or below the two-dimensional array of source-spacer-drain combinations; and a two-dimensional array of layer stacks, wherein each layer stack comprises a charge storage element, a dielectric barrier layer and a gate electrode, and is spaced apart from a respective active layer within the two-dimensional array of active layers by a dielectric tunnel layer. [17] Semiconductor structure according to claim 16, wherein a bottom side of the dielectric composite matrix and bottom sides of the active layers within the two-dimensional array of active layers are located within the same horizontal plane. [18] Semiconductor structure according to claim 16, wherein undersides of the active layers within the two-dimensional array of active layers and segments of an underside of the gate dielectric layer contacting the second dielectric spacer matrix layer are located within the same horizontal plane as topsides of the source electrodes and the drain electrodes. [19] Semiconductor structure according to claim 16, wherein: a totality of an interface between the dielectric intermediate electrode spacer and the source electrode within each source-spacer-drain combination and a totality of an interface between the dielectric intermediate electrode spacer and the drain electrode within each source-spacer-drain combination are located within vertical planes; an interface between the source electrode within each source-spacer-drain combination and the dielectric composite matrix comprises a contoured interface segment that borders a top surface of the second dielectric spacer matrix layer; and A tapered convex surface segment of the second dielectric spacer matrix layer contacts a tapered concave surface segment of the source electrode at the contoured interface segment. [20] Semiconductor structure according to claim 16, wherein a bottom side of each active layer within the two-dimensional array of active layers 20 is located within a horizontal plane that has a top side of the dielectric composite matrix or a bottom side of the dielectric composite matrix; and Each source-spacer-drain combination within the two-dimensional array of source-spacer-drain combinations contacts a horizontal surface of a respective active layer within the two-dimensional array of active layers.