Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. The method includes: providing a substrate; the substrate having a first surface and a second surface facing away from each other; forming a transistor array located in the substrate from the first surface; the transistor array including a plurality of transistors; the height of the transistors being less than the thickness of the substrate; thinning the substrate from the second surface until a first end of a conductive channel of the transistor is exposed; wherein the first end is the end of the conductive channel near the second surface; forming an insulating layer covering at least a portion of the first end of the conductive channel, such that a first width of the exposed first end of the conductive channel is less than a second width of the conductive channel; and forming a bit line structure covering a portion of the exposed first end of the conductive channel.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Vertical Channel Array Transistor (VCAT) architecture involves processing on the back side of the array wafer after thinning. The bit lines need to be aligned with the bottom edge of the active region. However, the array wafer is affected by physical factors such as heat, localized stress, overall warpage, supporting wafers, and bonding, leading to overall warpage and localized stress. This affects the alignment of the bit lines with the active region, resulting in alignment failure. Bit line-source alignment failure has become a pressing problem that needs to be solved. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0004] In a first aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor structure, comprising:

[0005] A substrate is provided; the substrate has a first surface and a second surface that are opposite to each other;

[0006] A transistor array is formed from a first surface of the substrate, located within the substrate; the transistor array includes a plurality of transistors; the height of the transistors is less than the thickness of the substrate;

[0007] The substrate is thinned from the second surface until the first end of the conductive channel of the transistor is exposed; wherein the first end is the end of the conductive channel near the second surface;

[0008] An insulating layer is formed covering at least a portion of the first end of the conductive channel, such that the first width of the exposed first end of the conductive channel is smaller than the second width of the conductive channel;

[0009] A bitline structure is formed covering the first end of the conductive channel of the exposed portion.

[0010] In some embodiments, a dielectric layer is filled between the plurality of transistors; the formation of an insulating layer covering at least a portion of the first end of the conductive channel includes:

[0011] After thinning the substrate, a portion of the conductive channel is etched from the first end of the conductive channel to form multiple recessed structures between the dielectric layers;

[0012] An insulating layer is formed on the sidewall of the recessed structure, such that the insulating layer covers at least a portion of the first end of the conductive channel to form a trench with the sidewall covered by the insulating layer.

[0013] In some embodiments, forming the insulating layer on the sidewall of the recessed structure includes:

[0014] The bottom surface and sidewalls of the recessed structure are covered with insulating material;

[0015] Remove the insulating material covering the bottom surface of the recessed structure to form the insulating layer covering the sidewalls of the recessed structure.

[0016] In some embodiments, a word line structure of the transistor is included between two adjacent conductive channels; the word line structure is located within the region of the recessed structure; the depth of the recessed structure on the word line structure is less than the depth of the recessed structure on the conductive channel;

[0017] The method of forming an insulating layer covering at least a portion of the first end of the conductive channel within the recessed structure further includes:

[0018] An insulating layer is formed within the recessed structure, covering a portion of the word line structure and at least a portion of the first end of the conductive channel.

[0019] In some embodiments, the bit line structure forming the first end of the conductive channel covering the exposed portion includes:

[0020] Conductive material is deposited in the trench to form the bit line structure; the width of the trench is equal to the first width.

[0021] In some embodiments, the method further includes:

[0022] Provides carrier wafers;

[0023] The first surface of the substrate is bonded to the carrier wafer.

[0024] In some embodiments, thinning the substrate from the second surface until the first end of the conductive channel of the transistor is exposed includes:

[0025] Flip the carrier wafer and substrate so that the second surface faces vertically upward;

[0026] The substrate is thinned from the second surface until the first end of the conductive channel of the transistor is exposed.

[0027] In some embodiments, the method further includes:

[0028] A storage capacitor connected to the transistor is formed on the first surface of the substrate.

[0029] In some embodiments, the method further includes:

[0030] A drain electrode is formed at the first end of the conductive channel;

[0031] A source electrode is formed at the second end of the conductive channel; the second end is the end of the conductive channel that is close to the first surface.

[0032] In a second aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0033] Substrate; the substrate has a first surface and a second surface that are opposite to each other;

[0034] A transistor array is located in the substrate; the transistor array includes a plurality of transistors;

[0035] An insulating layer covers at least a portion of the first end of a conductive channel, such that the first width of the first end of the conductive channel not covered by the insulating layer is smaller than the second width of the conductive channel; wherein the first end is the end of the conductive channel closer to the second surface;

[0036] The bit line structure is connected to the portion of the first end of the conductive channel that is not covered by the insulating layer.

[0037] In some embodiments, the semiconductor structure further includes:

[0038] A dielectric layer is located between the plurality of transistors;

[0039] Multiple recessed structures are located between the dielectric layers.

[0040] In some embodiments, the insulating layer is located on the sidewall of the recessed structure, and the insulating layer covers at least a portion of the first end of the conductive channel; the recessed structure with the insulating layer covering the sidewall is a trench.

[0041] In some embodiments, the bitline structure is located in the trench; the width of the trench is equal to the first width.

[0042] In some embodiments, the semiconductor structure further includes:

[0043] The word line structure of the transistor is located between two adjacent conductive channels; the word line structure is located within the region of the recessed structure; the depth of the recessed structure on the word line structure is less than the depth of the recessed structure on the conductive channel.

[0044] In some embodiments, the semiconductor structure further includes:

[0045] A storage capacitor is located on the first surface of the substrate and is connected to the transistor.

[0046] In some embodiments, the first end of the conductive channel includes the drain of the transistor;

[0047] The second end of the conductive channel includes the source of the transistor; the second end is the end of the conductive channel near the first surface.

[0048] This embodiment utilizes a sidewall deposition / etching process following back-side substrate etching to shrink the bit line trench size, thereby reducing the critical bit line dimensions, lowering parasitic capacitance between bit lines, and improving transistor readout performance. Furthermore, the bit line structure in this embodiment is directly formed on top of the bit line structure, preventing alignment failures due to overall substrate warping and localized stress. This reduces the probability of bit line-source alignment failure. Attached Figure Description

[0049] Figures 1A-1D This is a schematic diagram of a semiconductor structure in some embodiments;

[0050] Figure 2 A flowchart illustrating a semiconductor structure manufacturing method provided in this disclosure embodiment;

[0051] Figure 3A This is a schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure;

[0052] Figure 3B A top view of a transistor array provided in this disclosure embodiment;

[0053] Figure 3C A top view of another transistor array provided in an embodiment of this disclosure;

[0054] Figure 3D A cross-sectional view of a transistor array provided in an embodiment of this disclosure.

[0055] Figure 4A A top view of a transistor array provided in this disclosure embodiment;

[0056] Figure 4B A top view of another transistor array provided in an embodiment of this disclosure;

[0057] Figures 5A-5B This is a schematic diagram illustrating the formation of a recessed structure in a semiconductor structure manufacturing method according to an embodiment of the present disclosure;

[0058] Figures 6A-6B This is a schematic diagram illustrating the formation of trenches in a semiconductor structure manufacturing method according to an embodiment of this disclosure;

[0059] Figures 7A-7BThis is a schematic diagram of forming a bit line structure in a semiconductor structure manufacturing method provided by an embodiment of the present disclosure;

[0060] Figure 8 A cross-sectional view of a recessed structure in a semiconductor structure provided in an embodiment of this disclosure;

[0061] Figure 9 This is a schematic diagram of a semiconductor structure forming a storage capacitor according to an embodiment of the present disclosure;

[0062] Figure 10 This is a schematic diagram illustrating the formation of a source and drain in a semiconductor structure according to an embodiment of this disclosure;

[0063] Figures 11-15B This is a schematic diagram of the formation process of a semiconductor structure;

[0064] Figures 16A-20B This is a schematic diagram illustrating the formation process of a semiconductor structure according to an embodiment of the present disclosure.

[0065] Substrate 200; carrier wafer 201; transistor 300; conductive channel 301; insulating layer 302; bit line structure 303; dielectric layer 304; recessed structure 305; trench 306; word line structure 307; isolation layer 309; capacitor 310; drain 311; source 312; polysilicon layer 313; metal silicide layer 314; metal layer 315; conductive plug 316; air trench 317. Detailed Implementation

[0066] To facilitate understanding of this disclosure, exemplary embodiments thereof will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0067] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.

[0068] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0069] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0071] In some embodiments, the transistors of the memory include planar transistors and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor or a buried channel transistor, in terms of structure, the source and drain are located on the horizontal sides of the gate.

[0072] Figure 1A This is a schematic diagram of the planar transistor structure in some embodiments. Figure 1B This is a schematic diagram of a buried-channel transistor in some embodiments. For example... Figure 1A and 1B As shown, the source S and drain D of the transistor are located on the horizontal sides of the gate G, respectively. Thus, the source S and drain D occupy different positions on the horizontal plane, making the horizontal area of ​​both planar transistors and buried channel array transistors larger.

[0073] Furthermore, since transistors can be fabricated on silicon substrates, they can be used in various types of memory, such as Dynamic Random Access Memory (DRAM). Typically, DRAM consists of multiple memory arrays, each of which mainly includes a transistor and a capacitor controlled by the transistor; that is, DRAM consists of a memory array with one transistor T and one capacitor C (1T1C).

[0074] Figure 1C This is a schematic diagram of a DRAM memory array formed using planar transistors in some embodiments. Figure 1D This is a schematic diagram of a DRAM memory array formed using buried channel array transistors in some embodiments. For example... Figure 1C and 1D As shown, the source 312 (or drain 311) of the transistor in the DRAM memory array is connected to the bit line structure 303, and the drain 311 (or source 312) is connected to the capacitor 310.

[0075] Since the source and drain of planar transistors and buried channel array transistors are located on opposite sides of the gate, the bit lines and capacitors in the DRAM memory array are also located on the same side of the gate. Furthermore, subsequent processes require the connection between bit lines, transistors, and capacitors, as well as the connection between word lines (WL) and transistors. This results in complex circuit wiring and a high manufacturing difficulty in the memory array area of ​​DRAM memory.

[0076] Compared to the BCAT architecture, VCAT offers higher storage density. In VCAT, the source and drain of the transistors are located at the top and bottom of the vertical channel region. During semiconductor device fabrication, by combining wafer bonding and back substrate thinning techniques, bit lines or other structures can be placed on two opposite sides of the wafer. For example, in DRAM, the bit lines and capacitors of the DRAM memory array can be placed on two separate sides of the same wafer. This simplifies the circuit layout of word lines, bit lines, and capacitors, reducing the manufacturing complexity of semiconductor devices.

[0077] The VCAT architecture is fabricated on the back side after the array wafer is thinned. The bit lines need to be aligned with the lower end of the active region. However, the array wafer is affected by physical factors such as heat, local stress, overall warpage, supporting wafer, and bonding, resulting in overall warpage and local stress. This affects the alignment of the back bit lines with the active region, leading to alignment failure.

[0078] In some embodiments, the self-aligned bit line structure can solve the bit line alignment problem by etching back the back of the wafer to make the active region etched deeper and forming long strips of self-aligned bit lines in the etched area of ​​the active region. However, it has the problem of large bit line parasitic capacitance.

[0079] This disclosure provides a method for manufacturing a semiconductor structure, the method including as follows: Figure 2 The steps shown are as follows:

[0080] Step S101: Provide a substrate; the substrate has a first surface and a second surface that are opposite to each other;

[0081] Step S102: Form a transistor array located in the substrate from a first surface of the substrate; the transistor array includes a plurality of transistors; the height of the transistors is less than the thickness of the substrate;

[0082] Step S103: Thin the substrate from the second surface until the first end of the conductive channel of the transistor is exposed; wherein, the first end is the end of the conductive channel near the second surface;

[0083] Step S104: Form an insulating layer covering at least a portion of the first end of the conductive channel, such that the first width of the exposed first end of the conductive channel is smaller than the second width of the conductive channel;

[0084] Step S105: Form a bit line structure covering the first end of the conductive channel of the exposed portion.

[0085] First, perform step S101, providing, as follows Figure 3A The substrate 200 shown has a surface that is any surface perpendicular to its thickness direction. The thickness direction of the substrate 200, or the direction perpendicular to its surface, is defined as the Z-direction. The thickness of the substrate 200 along the Z-direction is defined as H. The top or bottom surface of the substrate 200 perpendicular to the Z-direction is a first surface S1 and a second surface S2, respectively, facing away from each other. Two intersecting X and Y directions are defined within the first surface S1 or the second surface S2 perpendicular to the Z-direction. In some embodiments, the X-direction is the direction in which the transistor forms the gate, and the Y-direction is the direction in which the transistor forms the bit line. The semiconductor substrate 200 may include a P-type semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; an N-type semiconductor substrate, such as an indium phosphide (InP) substrate; a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate; a silicon-on-insulator (SOI) substrate; and a germanium-on-insulator (GeOI) substrate. Furthermore, the substrate in this embodiment may also be a substrate with partially formed device structures or wiring, which is not limited here.

[0086] In step S102, the substrate 200 is processed from its first surface S1 using etching and deposition processes to form a transistor array located within the substrate 200. Figure 3B This is a top view of the transistor array located in the substrate from direction S1 to S2. The transistor array can have N rows along the X direction and M columns along the Y direction, where N and M are positive integers greater than or equal to 1. Figure 3B The transistor array in the image is arranged with rows aligned and columns aligned. Figure 3C This is another way of arranging transistor arrays. Figure 3C In the transistor array, the columns of transistors are arranged in an alternating vertical arrangement; for example, column 1L1 is above column 2L2. The arrangement of the transistor array is not limited to this and can have various configurations. The transistor array includes multiple transistors 300, each transistor performing a data storage function.

[0087] like Figure 3D As shown, Figure 3D for Figure 3B or Figure 3C The transistor in the cross-sectional view of substrate 200 at AA1 has a certain height h, and the height h of the transistor is less than the thickness H of the substrate. That is, the transistor is formed between the first surface S1 and the second surface S2, and the transistor is a certain distance (Hh) from the second surface S2 of the substrate.

[0088] In step S103, the substrate is flipped over, and then the substrate 200 is thinned from the second surface S2 until it is as shown. Figure 5A The first end of the conductive channel 301 of the transistor 300 shown is exposed. Figure 5A This is a top view of the thinned substrate along the second surface S2 direction. The thinning methods include, but are not limited to, etching processes and chemical mechanical polishing (CMP). Figure 5B for Figure 5A In the cross-sectional view at AA1, viewed from the second surface S2 towards the first surface S1, the first end D1 of the conductive channel 301 is recessed relative to the second surface S2 of the thinned substrate, and the opening above the conductive channel 301 has a second width a. The first end D1 is the end of the conductive channel 301 closest to the second surface S2.

[0089] Step S104 is performed, and then an insulating layer 302 is formed covering at least part of the first end of the conductive channel, such that the second width a of the exposed portion above the first end of the conductive channel 301 is reduced. Figure 6A This is a top view of the substrate along the direction of the second surface S2. Figure 6B for Figure 6A In the cross-sectional view at AA1, it can be understood that the opening of the conductive channel 301 after filling the insulating layer 302 has a first width b which is smaller than the second width a of the opening above the conductive channel 301 before filling the insulating layer 302. That is, the first width b of the exposed first end of the conductive channel 301 is smaller than the second width a of the conductive channel.

[0090] Step S105 is executed, and finally a bit line structure 303 covering the exposed portion of the first end of the conductive channel is formed at the opening of the conductive channel after the insulating layer is filled. Figure 7A This is a top view of the substrate on which the bit line structure 303 is formed along the direction of the second surface S2. Figure 7B for Figure 7A The cross-sectional view at AA1 shows that a bitline structure 303 is formed on the conductive channel 301. Methods for forming the bitline structure 303 include, but are not limited to, growth processes and deposition processes. The conductive materials used to form the bitline structure 303 include, but are not limited to, tungsten, cobalt, copper, aluminum, polycrystalline silicon (including doped polycrystalline silicon), doped silicon, metal silicides (e.g., titanium silicide), or any combination thereof. The bitline structure can use one or more of the above conductive materials; therefore, the bitline structure can be single-layered or multi-layered.

[0091] This embodiment utilizes a sidewall deposition / etching process following back-side substrate etching to shrink the bit line trench size, thereby reducing the critical bit line dimensions, lowering parasitic capacitance between bit lines, and improving transistor readout performance. Furthermore, the bit line structure in this embodiment is directly formed on top of the bit line structure, preventing alignment failures due to overall substrate warping and localized stress. This reduces the likelihood of bit line-source alignment failures.

[0092] In some embodiments, such as Figure 3B As shown, a dielectric layer 304 is filled between the plurality of transistors; in step S104 above, forming an insulating layer 302 covering at least a portion of the first end of the conductive channel includes:

[0093] Step S201: After thinning the substrate 200, continue to etch a portion of the conductive channel 301 from the first end of the conductive channel 301 to form a plurality of recessed structures 305 between the dielectric layers 304.

[0094] Step S202: The insulating layer 302 is formed on the sidewall of the recessed structure 305, such that the insulating layer 302 covers at least a portion of the first end D1 of the conductive channel, to form a trench 306 with the insulating layer 302 covering the sidewall.

[0095] In step S201, a dielectric layer 304 is further filled in the transistor array composed of multiple transistors. The dielectric layer 304 can be silicon dioxide or other insulating materials. The dielectric layer 304 is used for electrical isolation between the transistors. The substrate 200 is thinned from the second surface S2, and after thinning, as shown... Figure 4A and 4B As shown, when the substrate is thinned to the point where the first end of the transistor's conductive channel is just exposed, the thinning process stops, and etching of the first end of the transistor's conductive channel continues. The etching process includes, but is not limited to, dry etching and wet etching. Figure 5B As shown, a recessed structure 305 is formed between two adjacent dielectric layers 304 on the first end D1 of the conductive channel 301. Multiple recessed structures 305 are formed on multiple transistor arrays, and the multiple recessed structures 305 may be interconnected.

[0096] The recessed structure 305 has two opposing sidewalls, such as Figure 6B As shown, an insulating layer 302 is formed on the sidewall. The insulating layer 302 can be formed using a growth process, such as in-situ steam generation (ISSG) in a selective growth manner. ISSG is a thermal annealing deposition method that forms a high-quality oxide film by heating in a cavity and introducing oxygen atoms to bond with atoms in the semiconductor substrate. Deposition processes can also be used, including CVD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD). The formed insulating layer 302 covers the sidewall of the recessed structure 305 and at least a portion of the first end D1 of the conductive channel, forming a trench 306 with the insulating layer 302 covering the sidewall. It is understood that the opening of the trench 306 is smaller than the opening of the recessed structure 305. The insulating layer 302 can be silicon dioxide or other insulating materials, and the material of the insulating layer 302 can be the same as or different from that of the dielectric layer 304.

[0097] In some embodiments, step S202 above, forming the insulating layer 302 on the sidewall of the recessed structure 305, includes:

[0098] Step S301: Cover the bottom surface and sidewalls of the recessed structure 305 with insulating material;

[0099] Step S302: Remove the insulating material covering the bottom surface of the recessed structure 305 to form the insulating layer 302 covering the sidewalls of the recessed structure.

[0100] In some embodiments, the insulating layer 302 is formed on the sidewall of the recessed structure 305 in one step, for example, the insulating layer 302 covering the sidewall of the recessed structure 305 is formed only on the sidewall of the recessed structure 305 using methods including but not limited to growth processes and deposition processes.

[0101] In some embodiments, the formation of the insulating layer 302 on the sidewall of the recessed structure 305 is a multi-step process, such as a two-step process. Step 301: The insulating layer 302 is formed on the sidewall and bottom surface (i.e., the surface of the first end of the conductive channel) of the recessed structure 305 using a growth process or a deposition process. Step 302: The insulating layer 302 covering the bottom surface of the recessed structure 305 is removed by means including but not limited to wet etching or dry etching (e.g., plasma etching or reactive ion etching). The material forming the insulating layer 302 can have a high etching selectivity compared with the constituent material of the first end D1 of the conductive channel, so that the first end D1 of the conductive channel is used as the etching stop layer.

[0102] The etching method can use anisotropic etching process, which makes the lateral etching rate much lower than the longitudinal etching rate, thereby allowing the lateral insulating layer 302 to be retained.

[0103] In some embodiments, Figure 8 for Figure 5A The sectional view at BB1, as shown Figure 8 As shown, a word line structure 307 of the transistor is included between two adjacent conductive channels 301; the word line structure 307 is located in the region of the recessed structure 305; the depth of the recessed structure 305 on the word line structure 307 is less than the depth of the recessed structure 305 on the conductive channel 301.

[0104] In step S202 above, forming an insulating layer covering at least a portion of the first end of the conductive channel 301 within the recessed structure 305 further includes:

[0105] Step S401: An insulating layer is formed within the recessed structure 305, covering a portion of the word line structure 307 and at least a portion of the first end of the conductive channel 301.

[0106] In some embodiments, a word line structure 307 of the transistor is provided between two adjacent conductive channels 301. This can be either two conductive channels 301 sharing a single word line structure 307 to form a transistor, or one conductive channel 301 using a single word line structure 307 to form a transistor. When etching a portion of the conductive channel 301 from the first end D1 of the conductive channel, a portion of the substrate above the word line structure 307 is also etched. The recessed structure 305 also includes a region located above the word line structure 307.

[0107] In some embodiments, a word line structure 307 is formed between two conductive channels 301, the word line structure 307 having an isolation layer 309 for isolating the gate and drain (or source). Before thinning the substrate to expose the first end D1 of the conductive channel 301, a substrate is also present on the isolation layer 309, i.e., the depth of the word line structure 307 formed in the substrate is less than the depth of the conductive channel 301 in the substrate. When the conductive channel 301 and the word line structure 307 are etched downwards, after the substrate on the word line structure 307 is etched, the isolation layer 309 acts as an etching stop layer. However, there is no etching stop layer on the first end D1 of the conductive channel 301. The etching depth of the first end of the conductive channel 301 is greater than the etching depth of the word line structure 307. The first end of the conductive channel 301 and the etched area on the word line structure 307 together form a recessed structure 305 (recessed downwards relative to the substrates on both sides of the transistor array). Therefore, the depth of the recessed structure 305 on the word line structure 307 is less than the depth of the recessed structure 305 on the conductive channel 301.

[0108] In some embodiments, when an insulating layer is formed on the sidewall of the recessed structure 305, an insulating layer partially covering the word line structure 307 is also formed above the word line structure 307. The method of forming the insulating layer partially covering the word line structure 307 above the word line structure 307 can be the same as or different from the method of forming an insulating layer covering at least a portion of the first end of the conductive channel 301 on the sidewall of the recessed structure 305. The insulating layer partially covering the word line structure 307 and the insulating layer covering the first end of the conductive channel 301 can be formed simultaneously, or the insulating layer can be formed in stages, partially covering the word line structure 307 and the insulating layer covering the first end of the conductive channel 301.

[0109] In some embodiments, step S105 above includes the bit line structure 303 forming the first end of the conductive channel 301 covering the exposed portion, which includes:

[0110] Step S501: Deposit conductive material in the trench 306 to form the bit line structure 303; the width of the trench 306 is equal to the first width.

[0111] After the sidewalls of the recessed structure 305 are covered with the insulating layer 302, it becomes a trench 306. A conductive material can be deposited in the trench 306 using a growth or deposition process. One or more conductive materials can be used to form the bitline structure 303. For example, in some embodiments, a single conductive material can be used to fill the trench 306 until it is flush with the first end of the conductive channel 301. In other embodiments, three conductive materials can be used to fill the trench 306 in stages until it is flush with the first end of the conductive channel 301. The opening width of the trench 306 is the first width of the exposed first end of the conductive channel 301. The conductive material includes, but is not limited to, tungsten, cobalt, copper, aluminum, polycrystalline silicon, doped silicon, silicides, or any combination thereof. Therefore, the bitline structure 303 can include a single film layer (using one conductive material) or multiple film layers (using multiple conductive materials), and this disclosure does not limit this.

[0112] In some embodiments, the method further includes:

[0113] Step S601: Provide a carrier wafer;

[0114] Step S602: Bond the first surface S1 of the substrate to the carrier wafer.

[0115] In some embodiments, before thinning the second surface S2 of the substrate, the first surface S1 of the substrate needs to be fixed to a support structure to prevent damage to the already formed transistor array structure during the thinning of the second surface S2. The support structure can be a carrier wafer, which can use the same material as the substrate. For example, when the substrate is a silicon substrate, the wafer can be a silicon wafer. Then, the first surface S1 of the substrate is bonded to the surface of the carrier wafer.

[0116] In some embodiments, step S103 above, thinning the substrate from the second surface until the first end of the conductive channel of the transistor is exposed, includes:

[0117] Step S701: Flip the carrier wafer and the substrate so that the second surface is vertically facing upwards;

[0118] Step S702: Thin the substrate from the second surface until the first end of the conductive channel of the transistor is exposed.

[0119] In some embodiments, when the substrate on the second surface S2 is thinned, the carrier wafer has already been bonded to the first surface S1 of the substrate. Before thinning, the carrier wafer and the substrate need to be flipped so that the second surface S2 is vertically upward and the side containing the carrier wafer is downward. Then, the substrate is thinned from the second surface, and the thinning of the substrate can be stopped when the first end of the conductive channel 301 of the transistor is exposed.

[0120] In some embodiments, the method further includes:

[0121] Step S801: A storage capacitor for connecting the transistor is formed on the first surface S1 of the substrate 200.

[0122] like Figure 9 As shown, a storage capacitor 310 may also be formed on the first surface S1 of the substrate 200 and on the second end D2 corresponding to the first end of the conductive channel 301. The storage capacitor 310 is used to store data written to the memory cell. A dielectric layer may also be included between the storage capacitors 310 for electrical isolation between them.

[0123] In some embodiments, the method further includes:

[0124] Step S901: Form a drain at the first end of the conductive channel;

[0125] Step S902: A source electrode is formed at the second end of the conductive channel; the second end is the end of the conductive channel that is close to the first surface.

[0126] like Figure 10 As shown, in some embodiments, a drain 311 is formed at the first end D1 of the conductive channel 301 using processes including but not limited to ion implantation and thermal diffusion. Ion implantation and thermal diffusion can be performed after the first end of the conductive channel is exposed or before the bit line structure is formed.

[0127] A source 312 is formed at the second end D2 of the conductive channel 301; the second end is the end of the conductive channel 301 closest to the first surface S1. Alternatively, processes including but not limited to ion implantation and thermal diffusion can be used to form the source at the first end D1 of the conductive channel 301. Because the second end D2 of the conductive channel 301 is exposed before the formation of the storage capacitor 310, the source can be formed before the formation of the storage capacitor 310.

[0128] In some embodiments, the positions of the source 312 and the drain 311 can be interchanged. That is, the source 312 is formed at the first end D1 of the conductive channel 301; the drain 311 is formed at the second end D2 of the conductive channel 301; the second end D2 is the end of the conductive channel 301 closest to the first surface S1.

[0129] This disclosure also provides a semiconductor structure, such as... Figure 7B As shown, the semiconductor structure includes:

[0130] Substrate 200; the substrate has a first surface S1 and a second surface S2 that are opposite to each other;

[0131] A transistor array is located in the substrate 200; the transistor array includes a plurality of transistors;

[0132] An insulating layer 302 covers at least a portion of the first end D1 of the conductive channel 301, such that the first width b of the first end D1 of the conductive channel 301 not covered by the insulating layer 302 is smaller than the second width a of the conductive channel 301; wherein, the first end D1 is the end of the conductive channel 301 closest to the second surface S2.

[0133] Bit line structure 303 is connected to the portion of the first end D1 of the conductive channel 301 that is not covered by the insulating layer 302.

[0134] The semiconductor substrate 200 has a certain thickness, thus having a first surface S1 and a second surface S2 facing away from each other. An array of transistors can be mounted on the semiconductor substrate 200 for data storage and read / write functions. Each transistor includes at least one conductive channel 301.

[0135] The first end D1 of the conductive channel 301, which is close to the second surface S2, is partially covered by the insulating layer 302. The bit line structure 303 is located between the opposing insulating layers on the conductive channel 301 and covers the portion of the first end of the conductive channel that is not covered by the insulating layer.

[0136] This embodiment utilizes a sidewall deposition / etching process following back-side substrate etching to shrink the bit line trench size, thereby reducing the critical bit line dimensions, lowering parasitic capacitance between bit lines, and improving transistor readout performance. Furthermore, the bit line structure in this embodiment is directly formed on top of the bit line structure, preventing alignment failures due to overall substrate warping and localized stress. This reduces the likelihood of bit line-source alignment failures.

[0137] In some embodiments, such as Figure 5B As shown, the semiconductor structure further includes:

[0138] Dielectric layer 304 is located between the plurality of transistors;

[0139] A dielectric layer 304 is located between multiple transistors for electrical isolation between them. In other words, a dielectric layer 304 exists between transistors. Electrical isolation can be achieved between one transistor and another through this dielectric layer 304.

[0140] The dielectric layer 304 can be formed by depositing a silicon nitride layer on a semiconductor substrate and then patterning this silicon nitride layer to form a hard mask. Next, the semiconductor substrate is etched to form trenches between adjacent transistor elements. Finally, oxide is filled into the trenches to form the dielectric layer. In this embodiment, the depth of the dielectric layer can be greater than or equal to the depth of the transistor, thereby improving the electrical isolation effect.

[0141] Multiple recessed structures 305 are located between the dielectric layers 304.

[0142] In the formation of such Figure 7B Before the bit line structure 303 shown, multiple recessed structures 305 are located between the dielectric layers 304. Conductive channels 301 exist between the dielectric layers, and a recessed structure 305 is located above each conductive channel 301. The recessed structure 305 is used for subsequent placement of the bit line structure. In some embodiments, the bit line structure penetrates along the BB1 ​​direction, therefore the recessed structure 305 extends along... Figure 5A It runs through the BB1 ​​direction.

[0143] In some embodiments, such as Figure 6B As shown, the insulating layer 302 is located on the sidewall of the recessed structure, and the insulating layer 302 covers at least part of the first end D1 of the conductive channel 301; the recessed structure with the insulating layer 302 covering the sidewall is a trench 306.

[0144] The insulating layer 302 covers at least a portion of the first end D1 of the conductive channel 301, and also covers the sidewalls of the recessed structure. When the insulating layer 302 is not covering the area above the first end D1 of the conductive channel 301, it is a recessed structure; when the insulating layer 302 covers the area above the first end of the conductive channel 301 (i.e., the sidewalls are covered), it is a trench 306. It can be understood that the width b of the trench is less than the width a of the recessed structure. The insulating layer 302 can cover either of the two opposite sidewalls of the recessed structure, or any one of the two opposite sidewalls, both of which can reduce the size of the trench 306 formed after covering compared to the size of the recessed structure 305, thus reducing the size of the subsequently formed bitline structure.

[0145] In some embodiments, such as Figure 7B As shown, the bit line structure 303 is located in the trench; the width of the trench is equal to the first width.

[0146] Bit line structure 303 is located in and fills the trench, so the width of the trench is a first width a, and the width of bit line structure 303 is also a first width a. The material forming the bit line structure can be a conductive material including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, metal silicides (e.g., titanium silicide), or any combination thereof.

[0147] In some embodiments, Figure 8 for Figure 5A The sectional view at BB1, as shown Figure 8 As shown, the semiconductor structure further includes:

[0148] The word line structure 307 of the transistor is located between two adjacent conductive channels 301; the word line structure 307 is located within the region of the recessed structure 305; the depth c of the recessed structure 305 on the word line structure 307 is less than the depth d of the recessed structure 305 on the conductive channel 301.

[0149] In some embodiments, a word line structure 307 of the transistor is located between two conductive channels 301, and the word line structure 307 includes a gate of the transistor extending along the Y direction. In the transistor array, the gates in the same row can be connected, the transistors in the same row can share the same gate, or the gates in the same row can be disconnected, with each transistor connected to its own gate. The recessed structure 305 extends along the Y direction, and therefore the recessed structure 305 can also be formed above the word line structure 307.

[0150] In some embodiments, since the word line structure 307 has an isolation layer at one end near the second surface S2, when the substrate is etched downwards along the second surface S2 to the isolation layer, the isolation layer can act as an etching stop layer. Since there is no etching stop layer on the conductive channel, the etching depth d of the conductive channel will be greater than the etching depth c of the word line structure. That is, the depth of the recessed structure 305 on the word line structure 307 can be less than the depth of the recessed structure 305 on the conductive channel 301.

[0151] In some other embodiments, the word line structure 307 may not have a recessed structure 305, but only a bit line structure 303 may be formed on the conductive channel 301, and then the bit line structures 303 formed on each conductive channel 301 may be bridged on the word line structure 307.

[0152] In some embodiments, such as Figure 6AAs shown, the insulating layer 302 also covers part of the sidewall of the word line structure 307. This is because in some embodiments, the depth on the word line structure 307 is less than the depth of the recessed structure 305 on the conductive channel 301, that is, the top of the word line structure 307 is higher than the top of the conductive channel 301, so the deposited insulating layer can also partially cover the sidewall of the word line structure 307.

[0153] In some embodiments, the insulating layer 302 also covers a portion of the word line structure 307. This reduces the width of the opening of the recessed structure 305 above the word line structure 307. The width of the insulating layer 302 covering the word line structure 307 and the width of the insulating layer 302 covering the first end of the conductive channel 301 can be the same or different.

[0154] In some embodiments, such as Figure 9 As shown, the semiconductor structure further includes:

[0155] Storage capacitor 310 is located on the first surface S1 of the substrate and is connected to the transistor.

[0156] In some embodiments, when the semiconductor device is DRAM, the memory cell further includes a storage capacitor 310. For example... Figure 9 The diagram shown is a schematic representation of a DRAM memory cell provided in an embodiment of this disclosure. It can be seen that in the DRAM memory array, one end of the storage capacitor 310 is connected to the first end of the conductive channel 301 to form a 1T1C architecture memory cell. Within the memory cell, the storage capacitor 310 is connected to the second end D2 of the conductive channel 301 of the transistor, used to store data written to the memory cell.

[0157] In some embodiments, such as Figure 10 As shown, the first end of the conductive channel includes the drain of the transistor;

[0158] The second end D2 of the conductive channel 301 includes the source 312 of the transistor; the second end is the end of the conductive channel near the first surface S1.

[0159] The first end of the conductive channel 301 is the drain 311 of the transistor, which is close to the second surface S2; the second end of the conductive channel, that is, the end of the conductive channel 301 close to the first surface S1, is the source 312 of the transistor, and the channel is between the drain 311 and the source 312 of the transistor.

[0160] In some embodiments, the positions of the source 312 and the drain 311 can be interchanged. That is, the first end D1 of the conductive channel 301 is the source 312; the second end D2 of the conductive channel 301 is the drain 311; the second end D2 is the end of the conductive channel 301 closest to the first surface S1.

[0161] The source 312 and drain 311 do not need to be on the same surface of the substrate, which can further reduce the area occupied by each transistor and its associated memory cell on the substrate surface, greatly increasing the number of memory cells that can be arranged on the substrate and the utilization rate of the substrate. The drain of the transistor is connected to the bit line structure and is used to perform read or write operations on the memory cell where the transistor is located when the transistor is turned on.

[0162] This disclosure also provides the following examples:

[0163] In some embodiments, the bit lines of a transistor can be formed by the following steps:

[0164] like Figure 11 As shown, a substrate 200 is provided for forming bit lines. The substrate 200 has a first surface S1 and a second surface S2 that are opposite to each other. A transistor array is provided in the substrate, and the transistor array includes at least one transistor. In some embodiments, the transistor array can also be connected to a storage capacitor, where one transistor is connected to one storage capacitor. The side of the storage capacitor that is closer to it is the second surface S2. The storage capacitor and the bit line are located on opposite surfaces, that is, the bit line is formed on the first surface S1 of the substrate.

[0165] like Figure 12 As shown, a carrier wafer 201 is provided, and the carrier wafer 201 is bonded to the first surface S1 of the substrate 200 to which the bit line is to be formed. After bonding, the carrier wafer 201 and the substrate 200 are flipped so that the second surface S2 faces vertically upward.

[0166] The substrate is thinned along the second surface S2, such as... Figure 13A and Figure 13B As shown, Figure 13A This is a top view of the thinned substrate along the S2 surface. Figure 13B for Figure 13A A cross-sectional view along the X direction. Thinning processes include, but are not limited to, dry etching, wet etching, and CMP, until the first end of the conductive channel 301 of the transistor near the S2 surface in the substrate 200 is exposed.

[0167] like Figure 14A and Figure 14B As shown, Figure 14A This is a top view along the S2 surface after the deposition of the substrate material. Figure 14B for Figure 14AA cross-sectional view along the X direction. The method for depositing the bitline structure includes sequentially depositing a doped polysilicon layer 313, a metal silicide layer 314 (e.g., titanium silicide), and a metal layer 315 (e.g., tungsten) on the second surface S2 of the transistor array. Then, a structure is formed using self-aligned double patterning (SADP) as shown in the image. Figure 15A and 15B The semiconductor structure shown, Figure 15A This is a top view of the formed bitline structure viewed along the S2 surface. Figure 15B for Figure 15A A cross-sectional view along the AA1 direction. A bit line structure 303 located above the first end of the conductive channel 301, the bit line structure 303 being composed of a polysilicon layer 313, a metal silicide layer 314 (e.g., titanium silicide), and a metal layer 315 (e.g., tungsten metal).

[0168] The bit lines formed using the above method need to be aligned with the lower end of the active region. Due to the influence of physical factors such as heat, local stress, overall warping, and wafer bonding, there are problems with overall warping and local stress, which affect the alignment of the back bit lines and the active region, thus easily leading to bit line alignment failure.

[0169] In some embodiments, such as Figure 16A As shown, where, Figure 16A This is a cross-sectional view of the semiconductor structure along the direction of the bit line to be formed. A substrate 200 is provided for forming the bit line. The substrate has a first surface S1 and a second surface S2 facing away from each other. A transistor array is formed in the substrate 200. The transistor array consists of a plurality of transistors 300. A transistor 300 is connected to a storage capacitor 310 using a conductive plug 316. The conductive plug 316 can be made of metal silicide. The conductive plug 316 is used to form an ohmic contact between the storage capacitor 310 and the transistor 300. In some embodiments, the transistor 300 and the storage capacitor 310 can be directly connected without using the conductive plug 316. The storage capacitor 310 is close to the first surface S1. The storage capacitor 310 and the bit line to be formed are located on opposite surfaces, that is, the bit line will be formed on the second surface S2 of the substrate. Transistors 300 are arranged in pairs facing each other as a group of transistors. The word line structures 307 in a group of transistors are adjacent to each other, and the conductive channels 301 in a group of transistors are not adjacent to each other. The word line structure 307 has an isolation layer 309 at one end near the second surface of the substrate 200. An air trench 317 may also be provided between one group of transistors and another group of transistors.

[0170] like Figure 16B As shown, where, Figure 16BThis is a cross-sectional view of the semiconductor structure along the direction of the parallel word line structure. There is also a dielectric layer 304 between the conductive channels 301 and the second surface S2 of the substrate 200. There is also a certain thickness between the conductive channels 301 and the second surface S2 of the substrate 200.

[0171] A carrier wafer 201 is provided, and the carrier wafer 201 is bonded to the first surface S1 of the substrate to which the bit line is to be formed. After bonding, the carrier wafer and the substrate are flipped so that the second surface S2 faces vertically upward.

[0172] The substrate is thinned along its first surface using methods including, but not limited to, dry etching, wet etching, and CMP, until the first end of the conductive channel 301 of the transistor in the substrate is exposed. The first end of the conductive channel is exposed after thinning. Figure 17A and 17B As shown, where Figure 17A This is a cross-sectional view of the semiconductor structure in the direction of the bit lines to be formed. Figure 17B This is a cross-sectional view of the semiconductor structure along the direction parallel to the word line structure 307. The direction of the bit line to be formed can be perpendicular to the direction of forming the word line structure 307.

[0173] Then, the conductive channel 301 of the transistor is etched to form a structure like... Figure 18A and 18B The recessed structure 305 shown, wherein Figure 18A This is a cross-sectional view of the semiconductor structure in the direction of the bit lines to be formed. Figure 18B This is a cross-sectional view of the semiconductor structure along the direction parallel to the word line. The direction of the bit line to be formed can be perpendicular to the formation direction of the word line structure 307. For example... Figure 18A As shown, the depth of the recessed structure 305 on the word line structure 307 is less than the depth of the recessed structure 305 on the conductive channel 301. This is because after the substrate on the word line structure 307 is etched, the isolation layer 309 in the word line structure acts as an etching stop layer, while the first end of the conductive channel 301 does not have an isolation layer as an etching stop layer. Therefore, the etching depth at the first end of the conductive channel 301 is deeper than the etching depth in the area where the word line structure 307 is located. Figure 18B As shown, there is a recessed structure 305 between dielectric layers 304. This is because, during downward etching, the recessed structure 305 is formed on the transistor formation area, i.e., on the word line structure 307 and the conductive channel 301, so that the bit line structure can be formed in this recessed structure 305 later, instead of forming the bit line structure on the dielectric layer 304. Therefore, there is no need to etch the dielectric layer 304 downward.

[0174] like Figure 19A and 19B As shown, where Figure 19A This is a cross-sectional view of the semiconductor structure in the direction of the bit lines to be formed. Figure 19B This is a cross-sectional view of the semiconductor structure along the direction parallel to the word line structure 307. A covering insulating layer 302 is formed in at least one of the opposing sidewalls of the recessed structure 305, the insulating layer 302 covering a portion of the word line structure 307 and at least a portion of the first end of the conductive channel 301. The insulating layer 302 can be made of the same material as the dielectric layer 304. A trench 306 is formed after the sidewalls of the recessed structure 305 are covered with the insulating layer, the trench 306 having a narrower width than the recessed structure 305.

[0175] like Figure 20A and 20B As shown, where Figure 20A A cross-sectional view of the semiconductor structure along the bit line direction is formed. Figure 20B This is a cross-sectional view of the semiconductor structure along the direction parallel to the word line structure. One or more of the following are sequentially deposited in trench 306: a polysilicon layer, a metal silicide layer 314 (e.g., a titanium nitride layer), and a metal layer 315 (e.g., tungsten metal) to form the bit line structure 303. In the actual bit line material deposition process, the bit line material typically covers the upper surface of the insulating layer 302. Therefore, after the bit line material is deposited, the upper surface of the insulating layer 302 needs to undergo CMP treatment until the insulating layer 302 is exposed.

[0176] The bit line structure 303 is formed in a trench on the conductive channel, thus solving the alignment problem between the bit line and the active region. Furthermore, the sidewall deposition / etching process after back-side substrate etching shrinks the bit line trench size, thereby reducing the critical size of the bit line, lowering parasitic capacitance between bit lines, and improving DRAM read performance. In this embodiment, the bit line structure is formed directly on top of the bit line structure, preventing alignment failure due to overall substrate warping and localized stress. This solves the problem of bit line-source alignment failure.

[0177] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0178] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0179] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate has a first surface and a second surface that are opposite to each other; A transistor array is formed from a first surface of the substrate, located within the substrate; the transistor array includes a plurality of transistors; the height of the transistors is less than the thickness of the substrate; The substrate is thinned from the second surface until the first end of the conductive channel of the transistor is exposed; wherein the first end is the end of the conductive channel near the second surface; An insulating layer is formed covering at least a portion of the first end of the conductive channel, such that the first width of the exposed first end of the conductive channel is smaller than the second width of the conductive channel; A bitline structure is formed covering the first end of the conductive channel of the exposed portion.

2. The method according to claim 1, characterized in that, A dielectric layer is filled between the plurality of transistors; the forming of an insulating layer covering at least a portion of the first end of the conductive channel includes: After thinning the substrate, a portion of the conductive channel is etched from the first end of the conductive channel to form multiple recessed structures between the dielectric layers; An insulating layer is formed on the sidewall of the recessed structure, such that the insulating layer covers at least a portion of the first end of the conductive channel to form a trench with the sidewall covered by the insulating layer.

3. The method according to claim 2, characterized in that, The process of forming the insulating layer on the sidewall of the recessed structure includes: The bottom surface and sidewalls of the recessed structure are covered with insulating material; Remove the insulating material covering the bottom surface of the recessed structure to form the insulating layer covering the sidewalls of the recessed structure.

4. The method according to claim 2, characterized in that, The transistor includes a word line structure between two adjacent conductive channels; the word line structure is located within the region of the recessed structure; the depth of the recessed structure on the word line structure is less than the depth of the recessed structure on the conductive channel. The formation of the insulating layer covering at least a portion of the first end of the conductive channel further includes: An insulating layer is formed within the recessed structure, covering a portion of the word line structure and at least a portion of the first end of the conductive channel.

5. The method according to claim 4, characterized in that, The bit line structure forming the first end of the conductive channel covering the exposed portion includes: Conductive material is deposited in the trench to form the bit line structure; the width of the trench is equal to the first width.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Provides carrier wafers; The first surface of the substrate is bonded to the carrier wafer.

7. The method according to claim 6, characterized in that, Thinning the substrate from the second surface until the first end of the conductive channel of the transistor is exposed includes: Flip the carrier wafer and substrate so that the second surface faces vertically upward; The substrate is thinned from the second surface until the first end of the conductive channel of the transistor is exposed.

8. The method according to claim 1, characterized in that, The method further includes: A storage capacitor connected to the transistor is formed on the first surface of the substrate.

9. The method according to claim 1, characterized in that, The method further includes: A drain electrode is formed at the first end of the conductive channel; A source electrode is formed at the second end of the conductive channel; the second end is the end of the conductive channel that is close to the first surface.

10. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; the substrate has a first surface and a second surface that are opposite to each other; A transistor array is located in the substrate; the transistor array includes a plurality of transistors; An insulating layer covers at least a portion of the first end of a conductive channel, such that the first width of the first end of the conductive channel not covered by the insulating layer is smaller than the second width of the conductive channel; wherein the first end is the end of the conductive channel closer to the second surface; The bit line structure is connected to the portion of the first end of the conductive channel that is not covered by the insulating layer.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A dielectric layer is located between the plurality of transistors; Multiple recessed structures are located between the dielectric layers.

12. The semiconductor structure according to claim 11, characterized in that, The insulating layer is located on the sidewall of the recessed structure, and the insulating layer covers at least a portion of the first end of the conductive channel; the recessed structure with the insulating layer covering the sidewall is a trench.

13. The semiconductor structure according to claim 12, characterized in that, The bit line structure is located in the trench; the width of the trench is equal to the first width.

14. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: The word line structure of the transistor is located between two adjacent conductive channels; the word line structure is located within the region of the recessed structure; the depth of the recessed structure on the word line structure is less than the depth of the recessed structure on the conductive channel.

15. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A storage capacitor is located on the first surface of the substrate and is connected to the transistor.

16. The semiconductor structure according to claim 10, characterized in that, The first end of the conductive channel includes the drain of the transistor; The second end of the conductive channel includes the source of the transistor; the second end is the end of the conductive channel near the first surface.

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