Semiconductor Package

Abstract

A semiconductor package is provided. The semiconductor package includes a redistribution layer, a semiconductor chip and a molding layer, wherein the semiconductor chip is located on the redistribution layer, and the molding layer covers the sidewalls of the semiconductor chip and the top surface and sidewalls of the redistribution layer. The sidewalls of the redistribution layer are inclined relative to the bottom surface of the redistribution layer, and the sidewalls of the molding layer are separated from the sidewalls of the redistribution layer.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2019-0102600 filed on August 21, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Embodiments of the inventive concept relate to a semiconductor package, and more particularly, to a semiconductor package having improved reliability. Background Art

[0003] Integrated circuit chips can be implemented in the form of semiconductor packages so as to be appropriately applied to electronic products. With the increase in the integration density of semiconductor chips (or integrated circuit chips), it is difficult to form a desired number of interconnects. In order to overcome these limitations, wafer-level packaging and panel-level packaging have been developed. In order to achieve excellent electrical connections between internal components of semiconductor packages and / or between semiconductor packages, it may be necessary to improve the reliability of semiconductor packages. Summary of the invention

[0004] Embodiments of the inventive concept may provide a semiconductor package having improved reliability.

[0005] In one aspect, a semiconductor package may include a redistribution layer, a semiconductor chip, and a molding layer, wherein the semiconductor chip is located on the redistribution layer, and the molding layer covers the sidewalls of the semiconductor chip and the top surface and sidewalls of the redistribution layer. The sidewalls of the redistribution layer may be inclined relative to the bottom surface of the redistribution layer, and the sidewalls of the molding layer may be separated from the sidewalls of the redistribution layer.

[0006] In one aspect, a semiconductor package may include a redistribution layer, a semiconductor chip, and a molding layer, wherein the semiconductor chip is located on the redistribution layer, and the molding layer covers a top surface of the semiconductor chip and surrounds a plurality of sidewalls of the semiconductor chip. An edge portion of the molding layer may cover the plurality of sidewalls of the redistribution layer. Each of the plurality of sidewalls of the redistribution layer may form an inclined acute angle with a bottom surface of the redistribution layer.

[0007] In one aspect, a semiconductor package may include a redistribution layer, a semiconductor chip, a plurality of solder bumps, a molding layer, and a plurality of external terminals, wherein the semiconductor chip is located on the redistribution layer, the plurality of solder bumps are located between the semiconductor chip and the redistribution layer, the molding layer covers a plurality of sidewalls of the semiconductor chip and a top surface of the redistribution layer and surrounds a plurality of sidewalls of the redistribution layer, and a plurality of external terminals are located on a bottom surface of the redistribution layer. The plurality of sidewalls of the redistribution layer may include a first sidewall to a fourth sidewall. The first sidewall to the fourth sidewall may be separated from the plurality of sidewalls of the molding layer. The angle between the bottom surface of the redistribution layer and each of the first sidewall to the fourth sidewall may be an acute angle. The semiconductor chip may be electrically connected to the plurality of external terminals through the redistribution layer. The bottom surface of an edge portion of the molding layer may be coplanar with the bottom surface of the redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The inventive concept will become more apparent in view of the drawings and the accompanying detailed description.

[0009] Figure 1 is a plan view illustrating a semiconductor package according to some embodiments of the inventive concept.

[0010] Figure 2 is along Figure 1 A cross-sectional view taken along line II'.

[0011] Figure 3 is a plan view illustrating a method for manufacturing a semiconductor package according to some embodiments of the inventive concept.

[0012] Figures 4 to 15 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0013] Throughout the specification, the same reference numerals or the same reference signs may denote the same elements or components. Hereinafter, semiconductor packages according to some embodiments of the inventive concept will be described in detail.

[0014] Figure 1 is a plan view illustrating a semiconductor package according to some embodiments of the inventive concept. Figure 2 is along Figure 1 A cross-sectional view taken along line II'.

[0015] Reference Figure 1 and Figure 2 , the semiconductor package 1 may include a redistribution layer RDL, solder bumps 50 , a semiconductor chip 60 , a molding layer 70 , and external terminals 80 .

[0016] The redistribution layer RDL may be disposed between the bottom surface (or lower surface) 60b of the semiconductor chip 60 and the external terminal 80. The redistribution layer RDL may include a first interconnection layer 20, a second interconnection layer 30, and a chip connection portion 40. Although not shown in the drawings, the redistribution layer RDL may also include a plurality of interconnection layers.

[0017] The first interconnect layer 20 may be disposed on the top surface (or upper surface) of the external terminal 80. The first interconnect layer 20 may include a first conductive pattern 22 and a first insulating layer 23. The first conductive pattern 22 may be disposed on the top surface of the external terminal 80. The first conductive pattern 22 may include a conductive material. For example, the first conductive pattern 22 may include copper (Cu), a copper alloy, titanium (Ti) and / or aluminum (Al). The first conductive pattern 22 may be electrically connected to the external terminal 80. In this specification, it is understood that when a component is electrically connected to another component, it may be directly or indirectly connected to another component. The first insulating layer 23 may be disposed on the first conductive pattern 22. In more detail, the first insulating layer 23 may cover the top surface (or upper surface) and the sidewall (or side surface) of the first conductive pattern 22. The first insulating layer 23 may have a first through hole 24. The first through hole 24 may be disposed on the top surface of the first conductive pattern 22. The first through hole 24 may expose at least a portion of the top surface of the first conductive pattern 22. The first insulating layer 23 may include a curable material. The curable material may include an inorganic material (e.g., silicon oxide, silicon nitride and / or silicon oxynitride) and / or a polyamide-based polymer material. For example, the curable material may include at least one of photosensitive polyimide (PSPI), polybenzoxazole (PBO), phenol polymer, benzocyclobutene (BCB) polymer, and epoxy polymer.

[0018] The second interconnect layer 30 may be disposed on the first insulating layer 23. The second interconnect layer 30 may include a second seed layer 31, a second conductive pattern 32, and a second insulating layer 33. The second conductive pattern 32 may include a via portion 32a and a pad portion 32b. The second seed layer 31 may be disposed between the second conductive pattern 32 and the first insulating layer 23. In more detail, the second seed layer 31 may conformally cover the bottom surface (or lower surface) and the inner side wall (or inner side surface) of the first through hole 24 and a portion of the bottom surface (or lower surface) of the pad portion 32b of the second conductive pattern 32. The second seed layer 31 may include a conductive material. For example, the second seed layer 31 may include titanium (Ti), copper (Cu) and / or titanium nitride (TiN). The second conductive pattern 32 may be disposed on the second seed layer 31. The second conductive pattern 32 may have a T-shaped cross section or a substantially T-shaped cross section. The second conductive pattern 32 may be electrically connected to the first conductive pattern 22 through the second seed layer 31. In more detail, the via portion 32a of the second conductive pattern 32 may penetrate a portion of the first insulating layer 23 to be connected to the second seed layer 31. The second insulating layer 33 may be disposed on the second conductive pattern 32. In more detail, the second insulating layer 33 may cover the top surface (or upper surface) and the side wall (or side surface) of the second conductive pattern 32. The second insulating layer 33 may have a second through hole 34. The second through hole 34 may expose at least a portion of the top surface of the second conductive pattern 32. The second insulating layer 33 may include the same material as the first insulating layer 23. The second insulating layer 33 may include a curable material. The curable material may include an inorganic material (e.g., silicon oxide, silicon nitride and / or silicon oxynitride) and / or a polyamide-based polymer material. For example, the curable material may include at least one of a photosensitive polyimide (PSPI), a polybenzoxazole (PBO), a phenol polymer, a benzocyclobutene (BCB) polymer, and an epoxy polymer.

[0019] The chip connection portion 40 may be disposed on the second insulating layer 33. The chip connection portion 40 may include a third seed layer 41 and a third conductive pattern 42. The third conductive pattern 42 may include a via portion 42a and a pad portion 42b. The third seed layer 41 may be disposed between the third conductive pattern 42 and the second insulating layer 33. In more detail, the third seed layer 41 may conformally cover the bottom surface (or lower surface) and the inner side wall (or inner side surface) of the second through hole 34 and a portion of the bottom surface (or lower surface) of the pad portion 42b of the third conductive pattern 42. The third seed layer 41 may include the same material as the second seed layer 31. For example, the third seed layer 41 may include titanium (Ti), copper (Cu) and / or titanium nitride (TiN). The third conductive pattern 42 may be disposed on the third seed layer 41. The third conductive pattern 42 may have a T-shaped cross section or a substantially T-shaped cross section. The third conductive pattern 42 may be electrically connected to the second conductive pattern 32 through the third seed layer 41. In more detail, the via portion 42a of the third conductive pattern 42 may penetrate a portion of the second insulating layer 33 to be connected to the third seed layer 41. The third conductive pattern 42 may be electrically connected to the semiconductor device in the semiconductor chip 60. The chip connection portion 40 may be provided in plurality.

[0020] The solder bump 50 may be disposed on the third conductive pattern 42. The solder bump 50 may include a conductive material. For example, the solder bump 50 may include copper (Cu), nickel (Ni), aluminum (Al), and / or titanium (Ti).

[0021] The semiconductor chip 60 may be mounted on the redistribution layer RDL by solder bumps 50. The semiconductor chip 60 may be an application processor (AP) chip, a memory chip, a radio frequency (RF) chip, a logic chip, or a graphics chip. The semiconductor chip 60 may include a semiconductor device therein. The circuit elements in the semiconductor chip 60 may be disposed adjacent to the bottom surface (or lower surface) 60b of the semiconductor chip 60. The bottom surface 60b of the semiconductor chip 60 may be an active surface.

[0022] The molding layer 70 may be disposed on the semiconductor chip 60 and the redistribution layer RDL. In more detail, the molding layer 70 may seal the semiconductor chip 60. For example, the molding layer 70 may cover the top surface (or upper surface) 60a and the sidewall (or side surface) of the semiconductor chip 60. One sidewall of the molding layer 70 may be separated from one sidewall of the redistribution layer RDL. The distance between the one sidewall of the molding layer 70 and the one sidewall of the redistribution layer RDL may decrease as the vertical distance (vertical distance) from the bottom surface of the redistribution layer RDL decreases (for example, the distance between the sidewall of the molding layer 70 and the sidewall of the redistribution layer RDL may increase in the upward vertical direction). The molding layer 70 may also be disposed between the bottom surface 60b of the semiconductor chip 60 and the top surface (or upper surface) of the second insulating layer 33. The edge portion of the molding layer 70 may extend to the sidewall Ra of the redistribution layer RDL to cover the sidewall Ra of the redistribution layer RDL. The molding layer 70 may include a polymer material. For example, the mold layer 70 may include epoxy resin. The mold layer 70 may protect the semiconductor chip 60 from external heat, moisture, and / or impact.

[0023] For example, when viewed in a plan view, the mold layer 70 may have a plurality of sidewalls. The redistribution layer RDL may have a plurality of sidewalls Ra. Each sidewall of the mold layer 70 may face a corresponding one of the sidewalls Ra of the redistribution layer RDL. In some embodiments, the sidewall Ra of the redistribution layer RDL may include the sidewall 23a of the first insulating layer 23 and the sidewall 33a of the second insulating layer 33. Figure 1 , for example, when viewed in a plan view, the sidewall Ra of the redistribution layer RDL may include a first sidewall Ra1, a second sidewall Ra2, a third sidewall Ra3, and a fourth sidewall Ra4. For example, when viewed in a plan view, the second sidewall Ra2 may be opposite to the first sidewall Ra1, and the third sidewall Ra3 may be perpendicular to or substantially perpendicular to the first sidewall Ra1. The fourth sidewall Ra4 may be opposite to the third sidewall Ra3. The edge portion of the mold layer 70 may surround the first sidewall Ra1 to the fourth sidewall Ra4 of the redistribution layer RDL. Therefore, the first sidewall Ra1 to the fourth sidewall Ra4 may be separated from the sidewall 70a of the mold layer 70, so that the sidewall Ra of the redistribution layer RDL may not be exposed to the outside. If the sidewall Ra of the redistribution layer RDL is exposed to the outside, the corner where the sidewall Ra of the redistribution layer RDL intersects with the bottom surface of the redistribution layer RDL may be damaged by external impact. In the semiconductor package according to the embodiment of the inventive concept, the sidewall Ra of the redistribution layer RDL may be sealed by the mold layer 70 , and thus, the reliability of the semiconductor package under external impact may be improved.

[0024] The sidewall Ra of the redistribution layer RDL may be inclined (not perpendicular) relative to the bottom surface (or lower surface) of the redistribution layer RDL. Each of the angles between the bottom surface of the redistribution layer RDL and the sidewall Ra of the redistribution layer RDL may be an acute angle. For example, each of the angles between the bottom surface of the redistribution layer RDL and the sidewall Ra of the redistribution layer RDL may be equal to or greater than 45 degrees and less than 90 degrees. In more detail, the sidewall 23a of the first insulating layer 23 and the sidewall 33a of the second insulating layer 33 may be inclined relative to the bottom surface 23b of the first insulating layer 23. The angle between the bottom surface 23b of the first insulating layer 23 and each of the sidewalls 23a of the first insulating layer 23 may be a first angle θ1. The first angle θ1 may be an acute angle. For example, the first angle θ1 may be equal to or greater than 45 degrees and less than 90 degrees. The angle between the bottom surface 23b of the first insulating layer 23 (or the top surface (or upper surface) of the first insulating layer 23) and each of the sidewalls 33a of the second insulating layer 33 may be a second angle θ2. The second angle θ2 may be equal to the first angle θ1. Therefore, the sidewall 23a of the first insulating layer 23 may be coplanar with the sidewall 33a of the second insulating layer 33. The second angle θ2 may be an acute angle. For example, the second angle θ2 may be equal to or greater than 45 degrees and less than 90 degrees.

[0025] as Figure 1 and Figure 2 , the first to fourth side walls Ra1 to Ra4 of the redistribution layer RDL may be inclined relative to the bottom surface of the redistribution layer RDL. In more detail, the angles between the bottom surface of the redistribution layer RDL and the first to fourth side walls Ra1 to Ra4 may be acute angles. For example, each of the angles may be equal to or greater than 45 degrees and less than 90 degrees. The angles between the bottom surface of the redistribution layer RDL and the first to fourth side walls Ra1 to Ra4 may be equal to the first angle θ1 or the second angle θ2.

[0026] The bottom surface of the redistribution layer RDL may include the bottom surface (or lower surface) 23b of the first insulating layer 23. The bottom surface of the redistribution layer RDL may be disposed at the same level as the bottom surface 70b of the edge portion of the mold layer 70, and thus may be coplanar with the bottom surface 70b of the edge portion of the mold layer 70. The width W2 of the bottom surface of the redistribution layer RDL may be greater than the width W1 of the top surface of the redistribution layer RDL. In some embodiments, the distance between the first side wall Ra1 and the second side wall Ra2 of the redistribution layer RDL may decrease as the vertical distance from the bottom surface of the semiconductor chip 60 decreases. In some embodiments, the distance between the third side wall Ra3 and the fourth side wall Ra4 of the redistribution layer RDL may decrease as the vertical distance from the bottom surface of the semiconductor chip 60 decreases. The distance between the third side wall Ra3 and the fourth side wall Ra4 of the redistribution layer RDL may decrease in an upward vertical direction.

[0027] Figure 3 is a plan view illustrating a method for manufacturing a semiconductor package according to some embodiments of the inventive concept. Figures 4 to 15 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to some embodiments of the inventive concept.

[0028] Reference Figure 4 , a carrier substrate 10 may be prepared. The carrier substrate 10 may be a single crystal silicon substrate or a silicon on insulator (SOI) substrate. An adhesive layer 11 may be formed on the top surface (or upper surface) of the carrier substrate 10. The adhesive layer 11 may include a polymer material. The adhesive strength between the adhesive layer 11 and the carrier substrate 10 or between the adhesive layer 11 and the temporary insulating layer 12 may be changed by heat or light. Therefore, light or heat may be applied to the adhesive layer 11, and then the carrier substrate 10 may be removed. A temporary insulating layer 12 may be formed on the top surface (or upper surface) of the adhesive layer 11. The temporary insulating layer 12 may include an inorganic material and / or a polymer material. For example, the inorganic material may include silicon oxide, silicon nitride and / or silicon oxynitride, and the polymer material may include a polyamide-based polymer material. However, the embodiments of the inventive concept are not limited thereto. In the case where the temporary insulating layer 12 is disposed between the carrier substrate 10 and the redistribution layer to be described below, the temporary insulating layer 12 may protect the redistribution layer from heat, light or impact when the carrier substrate 10 is removed. An etch stop layer 13 may be formed on the top surface (or upper surface) of the temporary insulating layer 12. The etch stop layer 13 may define the level of the bottom surface (or lower surface) of the through portion 44 of the redistribution layer to be described below. The etch stop layer 13 may include a metal and / or a metal nitride. For example, the etch stop layer 13 may include, but is not limited to, titanium (Ti), copper (Cu), and / or titanium nitride (TiN).

[0029] The first conductive pattern 22 may be formed on the etch stop layer 13. For example, the first seed layer 21 may be formed on the top surface (or upper surface) of the etch stop layer 13. An etching mask having a through hole may be formed on the top surface (or upper surface) of the first seed layer 21. The through hole may define an area in which the first conductive pattern 22 will be formed. The first conductive pattern 22 may be formed by filling the through hole with a conductive material via an electroplating process. Thereafter, a portion of the first seed layer 21 and the etching mask may be removed. The first seed layer 21 between the etch stop layer 13 and the first conductive pattern 22 may not be removed. Therefore, the first seed layer 21 may remain between the etch stop layer 13 and the first conductive pattern 22. Alternatively, a conductive material may be deposited on the carrier substrate 10, and the deposited conductive material may then be patterned to form the first conductive pattern 22.

[0030] Reference Figure 5, a first insulating layer 23 may be formed on the first conductive pattern 22 and the etch stop layer 13. For example, the first insulating layer 23 may be formed by applying or depositing a sealing material on the first conductive pattern 22 and the etch stop layer 13. The first insulating layer 23 may be formed by using a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma CVD (HDPCVD) process, an atmospheric pressure CVD (APCVD) process, or a spin coating process. The first insulating layer 23 may cover the first conductive pattern 22 and the etch stop layer 13. In more detail, the first insulating layer 23 may cover the top surface (or upper surface) and sidewall (or side surface) of the first conductive pattern 22 and the top surface (or upper surface) of the etch stop layer 13, and may surround the sidewall (or side surface) of the first seed layer 21. A hardening process may be performed on the first insulating layer 23 as needed.

[0031] The first through hole 24 may be formed in the first insulating layer 23. For example, an etching process may be performed on the first insulating layer 23 to form the first through hole 24. The first through hole 24 may be formed on or above the first conductive pattern 22. The upper portion of the first insulating layer 23 may be overetched by an etching process. Therefore, the first through hole 24 may have a tapered shape whose width increases as the vertical distance from the first conductive pattern 22 increases (for example, the width of the first through hole 24 may increase in an upward vertical direction). The first through hole 24 may penetrate at least a portion of the first insulating layer 23 to expose at least a portion of the top surface (or upper surface) of the first conductive pattern 22. The first through hole 24 may define an area in which a via portion 32a of a second conductive pattern 32 to be described below is formed.

[0032] Reference Figure 6 , a second seed layer 31 may be formed on the first insulating layer 23. In more detail, the second seed layer 31 may be formed along the top surface (or upper surface) of the first insulating layer 23 and the bottom surface (or lower surface) and inner sidewall (or inner side surface) of the first through hole 24. Therefore, the second seed layer 31 may conformally cover the top surface of the first insulating layer 23 and the bottom surface and inner sidewall of the first through hole 24.

[0033] Reference Figure 7 , a mask layer M may be formed on the second seed layer 31. For example, the mask layer M may be formed by coating the top surface of the second seed layer 31 with a mask material. A through hole T may be formed in the mask layer M. The through hole T may be formed on or over the first through hole 24. The through hole T may expose the second seed layer 31 disposed on the bottom surface and the inner sidewall of the first through hole 24. The through hole T may define an area in which the second conductive pattern 32 is to be formed. When viewed in a plan view, the size of the shape of the through hole T may be equal to or greater than the size of the shape of the first through hole 24.

[0034] A second conductive pattern 32 may be formed on the exposed portion of the second seed layer 31. The second conductive pattern 32 may include a via portion 32a and a pad portion 32b. The via portion 32a may be formed by filling the first through hole 24 with a conductive material. For example, an electroplating process for filling the first through hole 24 with a conductive material may be performed by using the second seed layer 31 formed on the bottom surface and the inner sidewall of the first through hole 24 as a seed. Due to the shape of the first through hole 24, the via portion 32a of the second conductive pattern 32 may have a tapered shape, the width of which increases as the vertical distance from the first conductive pattern 22 increases (for example, the width of the via portion 32a of the second conductive pattern 32 may increase in the upward vertical direction). The pad portion 32b of the second conductive pattern 32 may be formed by filling at least a portion of the through hole T with a conductive material. For example, an electroplating process for filling at least a portion of the through hole T with a conductive material may be performed by using the via portion 32a of the second conductive pattern 32 exposed by the through hole T as a seed. In the above description, the process of forming the via portion 32a and the process of forming the pad portion 32b are described separately from each other. However, the process of forming the via portion 32a and the process of forming the pad portion 32b may be performed continuously, and the via portion 32a and the pad portion 32b may be formed as a single integral body.

[0035] Reference Figure 8 , a portion of the second seed layer 31 and the mask layer M may be removed. In more detail, the second seed layer 31 between the first insulating layer 23 and the second conductive pattern 32 may not be removed. Therefore, the second seed layer 31 may be disposed between the first insulating layer 23 and the second conductive pattern 32.

[0036] Reference Fig. 9 , the second insulating layer 33 may be formed on the first insulating layer 23 and the second conductive pattern 32. The second insulating layer 33 may be formed by the same method as the first insulating layer 23. For example, the second insulating layer 33 may be formed by applying or depositing a sealing material on the second conductive pattern 32 and the first insulating layer 23. The second insulating layer 33 may be formed by using a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma CVD (HDPCVD) process, an atmospheric pressure CVD (APCVD) process, or a spin coating process. A hardening process may be performed on the second insulating layer 33 as needed.

[0037] The second through hole 34 may be formed in the second insulating layer 33. The second through hole 34 may be formed by the same method as the first through hole 24. For example, an etching process may be performed on the second insulating layer 33 to form the second through hole 34. The second through hole 34 may be formed on or above the second conductive pattern 32. The upper portion of the second insulating layer 33 may be overetched by an etching process. Therefore, the second through hole 34 may have a tapered shape whose width increases as the vertical distance from the second conductive pattern 32 increases (for example, the width of the second through hole 34 may increase in an upward vertical direction). The second through hole 34 may penetrate the second insulating layer 33 to expose at least a portion of the top surface (or upper surface) of the second conductive pattern 32. The second through hole 34 may define an area in which a via portion 42a of a third conductive pattern 42 to be described below is formed.

[0038] Reference Fig.10 , a third conductive pattern 42 may be formed on the second insulating layer 33. The third conductive pattern 42 may be formed by the same method as the second conductive pattern 32. For example, a third seed layer 41 may be formed on the second insulating layer 33. In more detail, the third seed layer 41 may be formed along the top surface (or upper surface) of the second insulating layer 33 and the bottom surface (or lower surface) and inner sidewall (or inner side surface) of the second through hole 34. Therefore, the third seed layer 41 may conformally cover the top surface of the second insulating layer 33 and the bottom surface and inner sidewall of the second through hole 34.

[0039] A mask layer may be formed on the third seed layer 41. For example, the mask layer may be formed by coating the top surface of the third seed layer 41 with a mask material. A through hole may be formed in the mask layer. The through hole may expose the third seed layer 41 disposed on the bottom surface and the inner sidewall of the second through hole 34. When viewed in a plan view, the size of the shape of the through hole may be equal to or greater than the size of the shape of the second through hole 34.

[0040] A third conductive pattern 42 may be formed on the exposed portion of the third seed layer 41. The third conductive pattern 42 may include a via portion 42a and a pad portion 42b. The electroplating process of filling the second through hole 34 with a conductive material may be performed by using the third seed layer 41 formed on the bottom surface and the inner sidewall of the second through hole 34 as a seed, so that the via portion 42a may be formed. Due to the shape of the second through hole 34, the via portion 42a of the third conductive pattern 42 may have a tapered shape, the width of which increases as the vertical distance from the second conductive pattern 32 increases (for example, the width of the via portion 42a of the third conductive pattern 42 may increase in the upward vertical direction). The pad portion 42b of the third conductive pattern 42 may be formed by filling at least a portion of the through hole with a conductive material. In the above description, the process of forming the via portion 42a and the process of forming the pad portion 42b are described separately from each other. However, the process of forming the via portion 42 a and the process of forming the pad portion 42 b may be continuously performed, and the via portion 42 a and the pad portion 42 b may be formed as a single integral body.

[0041] Reference Figure 3 and Fig.11 , the first insulating layer 23 and the second insulating layer 33 may be etched to form a through portion 44. For example, a mask having holes may be prepared on the first insulating layer 23 and the second insulating layer 33. A laser may be used in the etching process. For example, the first insulating layer 23 and the second insulating layer 33 may be irradiated with a laser through a mask. The laser transmitted through the hole of the mask may etch the first insulating layer 23 and the second insulating layer 33 to form a through portion 44. The laser may be an ultraviolet laser using a gas in which an inert gas is mixed with a halogen gas. For example, the laser may be an argon fluoride (ArF) excimer laser, a krypton fluoride (KrF) excimer laser, a xenon chloride (XeCl) excimer laser, and / or a xenon fluoride (XeF) excimer laser. The wavelength of the laser may be in the range of 150 nm to 400 nm. Since the thermal expansion coefficient of the redistribution layer RDL is different from that of the carrier substrate 10, a warping phenomenon of the redistribution layer RDL may occur in the process of manufacturing the semiconductor package. When the redistribution layer RDL has the through portion 44 , the redistribution layer RDL may become softer or more flexible, and thus the warpage phenomenon of the redistribution layer RDL may be reduced or minimized. As a result, the reliability of the semiconductor package may be improved.

[0042] Reference Fig.12, a semiconductor chip 60 may be mounted on the third conductive pattern 42. In more detail, a solder bump 50 may be formed on a top surface (or upper surface) of the third conductive pattern 42. The semiconductor chip 60 may be mounted on the solder bump 50. For example, the semiconductor chip 60 may be connected to the solder bump 50 by a flip chip method.

[0043] Reference Fig.13 , a mold layer 70 may be formed on the carrier substrate 10, the first insulating layer 23, the second insulating layer 33, and the semiconductor chip 60. For example, an insulating material may be supplied onto the carrier substrate 10 to cover the semiconductor chip 60, and thus the mold layer 70 may be formed.

[0044] Reference Fig.14 , the carrier substrate 10, the adhesive layer 11, the temporary insulating layer 12, the etch stop layer 13, and the first seed layer 21 may be removed. Thus, the bottom surface of the first conductive pattern 22 may be exposed. An external terminal 80 may be formed on the bottom surface (or lower surface) of the first conductive pattern 22.

[0045] Reference Figure 3 and Fig.15 , Fig.14 The resulting structure can be divided into semiconductor packages 1. In more detail, the molding layer 70 between the semiconductor chips 60 can be cut along the scribe line SL. The cutting process can be performed by using a blade. The blade can be or include, but is not limited to, a diamond blade. If the redistribution layer RDL does not have a through portion 44, the blade used for cutting will cut both the molding layer 70 and the redistribution layer RDL. Since the redistribution layer RDL is more fragile than the molding layer 70, cracks will be generated at the contact surface when the blade contacts the redistribution layer RDL. When the redistribution layer RDL has a through portion 44, the blade used for cutting may not be in direct contact with the redistribution layer RDL, but the molding layer 70 may be cut. Therefore, cracks may not be generated at the redistribution layer RDL. Since one side wall 70a of the molding layer 70 contacts the blade during the cutting process, the surface roughness of the one side wall 70a of the molding layer 70 may be greater than the surface roughness of one side wall Ra of the redistribution layer RDL. The semiconductor package 1 can be manufactured by the above process.

[0046] According to an embodiment of the inventive concept, a sidewall of a redistribution layer of a semiconductor package may be covered by a mold layer, thereby reducing or preventing damage to the redistribution layer by a blade during a dicing process. As a result, the reliability of the semiconductor package may be improved.

[0047] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Therefore, the scope of the inventive concept will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be limited or restricted by the foregoing description.

Claims

1. A semiconductor package, the semiconductor package include: Redistribution layer; a semiconductor chip located on the redistribution layer; as well as a molding layer covering the sidewalls of the semiconductor chip and the top surface and sidewalls of the redistribution layer, wherein the sidewall of the redistribution layer is inclined relative to the bottom surface of the redistribution layer, wherein a sidewall of the molding layer is separated from a sidewall of the redistribution layer, and The surface roughness of the sidewall of the redistribution layer is smaller than the surface roughness of the sidewall of the molding layer.

2. The semiconductor package according to claim 1, in, The distance between the sidewall of the molding layer and the sidewall of the redistribution layer increases in an upward vertical direction.

3. The semiconductor package according to claim 1, in, An angle between a sidewall of the redistribution layer and a bottom surface of the redistribution layer is an acute angle.

4. The semiconductor package according to claim 3, in, An angle between a sidewall of the redistribution layer and a bottom surface of the redistribution layer is equal to or greater than 45 degrees and less than 90 degrees.

5. The semiconductor package according to claim 1, in, A bottom surface of the edge portion of the molding layer is coplanar with a bottom surface of the redistribution layer.

6. The semiconductor package according to claim 1, in, The redistribution layer includes a plurality of sidewalls, and The molding layer surrounds the plurality of side walls of the redistribution layer.

7. The semiconductor package according to claim 6, in, The molding layer includes a plurality of side walls, and The plurality of sidewalls of the redistribution layer are separated from the plurality of sidewalls of the molding layer.

8. The semiconductor package according to claim 7, in, Each of the plurality of sidewalls of the molding layer faces a corresponding one of the plurality of sidewalls of the redistribution layer, and Wherein, a distance between each of the plurality of sidewalls of the molding layer and a corresponding one of the plurality of sidewalls of the redistribution layer increases in an upward vertical direction.

9. The semiconductor package according to claim 1, in, The redistribution layer consists of: a first interconnect layer; a second interconnect layer disposed on the first interconnect layer; and a chip connection portion, located between the second interconnect layer and the semiconductor chip, wherein the bottom surface of the redistribution layer includes the bottom surface of the first interconnect layer, and The plurality of side walls of the first interconnect layer are coplanar with the plurality of side walls of the second interconnect layer.

10. The semiconductor package according to claim 9, in, The chip connection portion includes a plurality of chip connection portions, and The molding layer covers the bottom surface of the semiconductor chip and the side walls of the chip connecting portions.

11. A semiconductor package, the semiconductor package include: Redistribution layer; a semiconductor chip located on the redistribution layer; as well as a molding layer covering a top surface of the semiconductor chip and surrounding a plurality of side walls of the semiconductor chip, The edge portion of the molding layer covers a plurality of side walls of the redistribution layer. wherein each of the plurality of sidewalls of the redistribution layer forms an acute angle with a bottom surface of the redistribution layer, and The surface roughness of the plurality of side walls of the redistribution layer is smaller than the surface roughness of the plurality of side walls of the molding layer.

12. The semiconductor package according to claim 11, in, A bottom surface of the edge portion of the molding layer is coplanar with a bottom surface of the redistribution layer.

13. The semiconductor package according to claim 11, in, The acute inclination angle is equal to or greater than 45 degrees and less than 90 degrees.

14. The semiconductor package according to claim 11, in, The redistribution layer consists of: a first interconnect layer; a second interconnect layer disposed on the first interconnect layer; and a chip connection portion, located between the second interconnect layer and the semiconductor chip, wherein the bottom surface of the redistribution layer includes the bottom surface of the first interconnect layer, and The width of the bottom surface of the redistribution layer is greater than the width of the top surface of the redistribution layer.

15. The semiconductor package according to claim 14, in, The first interconnect layer includes a first insulating layer, wherein the second interconnect layer comprises a second insulating layer, and Wherein, each of the first insulating layer and the second insulating layer includes a photosensitive polymer.

16. The semiconductor package according to claim 11, in, The redistribution layer is surrounded by an edge portion of the molding layer.

17. The semiconductor package according to claim 11, in, The plurality of sidewalls of the redistribution layer include: a first side wall; a second side wall, opposite to the first side wall; a third side wall substantially perpendicular to the first side wall; and a fourth side wall, opposite to the third side wall, The first to fourth side walls are separated from the plurality of side walls of the molding layer.

18. The semiconductor package according to claim 11, in, A distance between a first sidewall of the redistribution layer and a second sidewall of the redistribution layer opposite to the first sidewall decreases in an upward vertical direction.

19. A semiconductor package, the semiconductor package include: Redistribution layer; a semiconductor chip located on the redistribution layer; a plurality of solder bumps disposed between the semiconductor chip and the redistribution layer; a molding layer covering the plurality of sidewalls of the semiconductor chip and the top surface of the redistribution layer and surrounding the plurality of sidewalls of the redistribution layer; as well as a plurality of external terminals disposed on a bottom surface of the redistribution layer, The plurality of sidewalls of the redistribution layer include first to fourth sidewalls, The first to fourth side walls are separated from the plurality of side walls of the molding layer. wherein an angle between the bottom surface of the redistribution layer and each of the first to fourth side walls is an acute angle, wherein the semiconductor chip is electrically connected to the plurality of external terminals through a redistribution layer, wherein a bottom surface of an edge portion of the molding layer is coplanar with a bottom surface of the redistribution layer, and The surface roughness of the plurality of sidewalls of the redistribution layer is smaller than the surface roughness of the plurality of sidewalls of the molding layer.

Images