Semiconductor structure and method for manufacturing the same

Abstract

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate, a plurality of interconnect layers, a first connector and a second connector. The semiconductor substrate includes a plurality of semiconductor devices in the semiconductor substrate. The interconnect layers are disposed on the semiconductor substrate and are electrically coupled to the semiconductor devices. The first connector is disposed on the plurality of interconnect layers and extends to contact with a first level of the plurality of interconnect layers. The second connector is disposed on the plurality of interconnect layers and is substantially flush with the first connector. The second connector extends further than the first connector to contact with a second level of the plurality of interconnect layers located between the first level of the plurality of interconnect layers and the semiconductor substrate, and the first connector is wider than the second connector.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure including connectors of different sizes and a manufacturing method thereof. Background Art

[0002] In recent years, the semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the continued reduction in the minimum feature size, which enables more components to be integrated into a given area. For example, the area occupied by the integrated components is close to the surface of the semiconductor wafer, however, there are physical limits to the density that can be achieved in forming a two-dimensional (2D) integrated circuit. For example, one of these limitations comes from the fact that as the number of semiconductor devices increases, the number and length of interconnects between semiconductor devices increase significantly. Since existing integrated circuit design rules require that the distance of the conductive wiring layout be reduced in the interconnect structure of the semiconductor device, the line spacing and spacing of the interconnect structure also become very small. This makes the parasitic capacitance between the conductive wiring in the interconnect structure higher. Therefore, the resistance-capacitance (RC) delay of the integrated circuit will increase. In addition, due to the small spacing between the conductive wiring, leakage current may become significant. Accordingly, efforts are continually being made to develop new mechanisms for forming semiconductor devices. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a semiconductor substrate, a plurality of interconnection layers, a first connector and a second connector. The semiconductor substrate comprises a plurality of semiconductor devices in the semiconductor substrate. The interconnection layer is disposed on the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed on the plurality of interconnection layers and extends to contact with a first level of the plurality of interconnection layers. The second connector is disposed on the plurality of interconnection layers and is substantially flush with the first connector. The second connector extends further than the first connector to contact with a second level of the plurality of interconnection layers located between the first level of the plurality of interconnection layers and the semiconductor substrate, and the first connector is wider than the second connector.

[0004] According to some embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a first semiconductor die and a second semiconductor die stacked on the first semiconductor die and bonded to the first semiconductor die. The first semiconductor die comprises a first bonding connector and a second bonding connector. The ratio of the height to the width of the second bonding connector is greater than the ratio of the height to the width of the first bonding connector. The second semiconductor die comprises a third bonding connector bonded to the first bonding connector of the first semiconductor die and a fourth bonding connector bonded to the second bonding connector of the first semiconductor die. The size of the third bonding connector and the size of the fourth bonding connector correspond to the size of the first bonding connector and the size of the second bonding connector, respectively.

[0005] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes at least the following steps: forming a first surface dielectric layer on a first interconnect structure on a first semiconductor substrate; forming a first through-hole opening and a second through-hole opening, wherein the second through-hole opening penetrates through the first surface dielectric layer and extends further than the first through-hole opening to expose at least a portion of the first interconnect structure in a tangible manner, and the second through-hole opening is narrower than the first through-hole opening; and forming a conductive material in the first through-hole opening and the second through-hole opening to form a first bonding connector and a second bonding connector, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1C is a schematic cross-sectional view showing various stages in a method of manufacturing a first layer of a semiconductor structure according to some embodiments of the present disclosure.

[0008] Figures 2A to 2D are schematic cross-sectional views showing various stages in a method for manufacturing a second layer of a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figures 3A to 3D are schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0010] Figure 4 is a schematic cross-sectional view illustrating a first layer of a semiconductor structure according to some embodiments of the present disclosure.

[0011] FIG. 5A to FIG. 5CSchematic partial cross-sectional views showing various stages in a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0012] Figure 6 is a schematic cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 7 is a schematic cross-sectional view illustrating an application of a semiconductor structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely one example and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed in itself.

[0015] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figure. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein can be used in conjunction with a test method that includes intermediate verification of a known good die to improve yield and reduce costs.

[0017] Figure 1A to Figure 1C is a schematic cross-sectional view showing various stages in a method for manufacturing a first layer of a semiconductor structure according to some embodiments of the present disclosure. Figure 1A , a first interconnect structure 120 is formed on a first semiconductor substrate 110. For example, the first semiconductor substrate 110 includes a bulk semiconductor that may be doped or undoped, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (e.g., quartz, glass, etc.), combinations thereof, etc. In some embodiments, the first semiconductor substrate 110 includes an elemental semiconductor (e.g., silicon or germanium in a crystalline structure, a polycrystalline structure, or an amorphous structure), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure or the substrate may include a multilayer compound semiconductor structure. In some embodiments, alloy SiGe is formed on a silicon substrate. In other embodiments, the SiGe substrate is strained. In some embodiments, the first semiconductor substrate 110 is a device wafer. For example, the first semiconductor substrate 110 includes a plurality of first semiconductor devices 112 formed in the first semiconductor substrate 110. The first semiconductor devices 112 may be or may include active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.) or other suitable electronic components.

[0018] The first semiconductor substrate 110 may include a circuit system (not shown) formed in a front-end-of-line (FEOL) process, and the first interconnect structure 120 may be formed in a back-end-of-line (BEOL) process. In some embodiments, the first interconnect structure 120 includes an inter-layer dielectric (ILD) layer formed on the first semiconductor substrate 110 and an inter-metallization dielectric (IMD) layer formed on the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of, for example, the following low-k dielectric materials: phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), SiOxCy, spin-on glass, spin-on polymer, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, etc. The ILD layer and the IMD layer may include any suitable number of dielectric material layers, and the number of dielectric material layers is not limited thereto.

[0019] In some embodiments, the first interconnect structure 120 interconnects the first semiconductor device 112. For example, the first interconnect structure 120 includes at least one first dielectric layer 124 disposed on the first semiconductor substrate 110 and a plurality of first interconnect layers 122 embedded in the first dielectric layer 124. For example, each of the first interconnect layers 122 includes a conductive line, a conductive pad, a via, etc. The material of the first interconnect layer 122 may include copper or a copper alloy, but other metals (e.g., aluminum, silver, gold, and combinations thereof) may also be used. In some embodiments, two or more layers of conductive lines of the first interconnect layer 122 are interconnected in a vertical direction by vias of the first interconnect layer 122 and buried in the first dielectric layer 124. The first interconnect layer 122 of the first interconnect structure 120 disposed on the first semiconductor substrate 110 may electrically couple the first semiconductor devices 112 formed in and / or on the first semiconductor substrate 110 to each other and electrically couple the first semiconductor devices 112 to external components.

[0020] For example, the first interconnect layer 122 of the first interconnect structure 120 includes a bottom interconnect layer M1, a top interconnect layer Mt (i.e., a first level of the plurality of interconnect layers), and an intermediate level interconnect layer located between the bottom interconnect layer M1 and the top interconnect layer Mt (e.g., a second level interconnect layer M2 directly located above the bottom interconnect layer M1, a third level interconnect layer M3 directly located above the second level interconnect layer M2, etc.). For ease of description, the term "top" is used herein to refer to the interconnect layer farthest from the first semiconductor substrate 110 relative to other interconnect layers, and the term "bottom" is used to refer to the interconnect layer closest to the first semiconductor substrate 110 relative to other interconnect layers. It should be noted that the four-level interconnect layer structure shown in the figure is only an example, and the first interconnect structure 120 may include more or fewer interconnect layers according to the requirements of the circuit design.

[0021] In some embodiments, at least one first passivation layer PS1 is disposed on the top interconnect layer Mt of the first interconnect structure 120. In some embodiments, the first passivation layer PS1 is a non-low dielectric constant dielectric layer. For example, the first passivation layer PS1 includes silicon oxide, silicon nitride, undoped silicate glass, polyimide, etc. As another option, the first passivation layer PS1 is omitted. In some embodiments, a first contact pad AP1 is formed on the first passivation layer PS1, and the first contact pad AP1 can be electrically contacted with the top interconnect layer Mt through a via. The material of the first contact pad AP1 may include aluminum, but other suitable conductive materials (such as copper) may also be used. It should be noted that in combination with Figure 1A The structure described is only an example. Figure 1A The structure shown in may include more elements and other configurations are possible.

[0022] Reference Figure 1B and Figure 1C , forming a first surface dielectric layer BD1 and a plurality of first bonding connectors (e.g., BC0, BC1, BC2, BC3, and BC4). For example, a surface dielectric material is formed on the first passivation layer PS1 and covers the first contact pad AP1. The surface dielectric material may be or may include an oxynitride layer (e.g., a silicon oxynitride (SiON) layer) or any suitable dielectric material (e.g., silicon oxide (SiO2), silicon nitride (SiN), etc.). Next, the surface dielectric material is patterned using a damascene technique or other suitable process to form a first surface dielectric layer BD1. In some embodiments, a dual damascene process is performed on the surface dielectric material to form a first surface dielectric layer BD1 having a plurality of trenches (e.g., TR0, TR1, TR2, TR3, and TR4) and through-hole openings (e.g., VO1, VO2, VO3, and VO4), such as Figure 1BIt should be understood that the combination Figure 1B The dual damascene technology described is only an example, and in other embodiments, a single damascene process or other suitable processes may be used.

[0023] In some embodiments, the trench is formed before the via opening. For example, an etching step is performed to remove some portions of the surface dielectric material to form trenches TR0, TR1, TR2, TR3 and TR4. At this stage, the conductive features below (e.g., the first contact pad AP1 and the first interconnect layer 122) are not exposed by the surface dielectric material. Then, via openings VO1, VO2, VO3 and VO4 are formed to expose the conductive features below at the intended location. The number of via openings may or may not correspond to the number of trenches. It should be understood that an etch stop layer (not shown) may be provided in the first interconnect structure 120 or may be provided between the surface dielectric material and the first interconnect structure 120. For example, during the process of forming the trenches, the via openings VO1, VO2, VO3 and VO4 extend downward from the bottom of the corresponding trenches TR1, TR2, TR3 and TR4 until the first contact pad AP1 and / or the interconnect layer 122 below are exposed in an accessible manner. The trench TR0 may not correspond to any of the via openings in the cross section. For example, the trench TR0 may be used to form a conductive line or act as a dummy pad.

[0024] Some of the through-hole openings (e.g., VO1) may extend downward to the first contact pad AP1 embedded in the surface dielectric material, so that at least a portion of the first contact pad AP1 is exposed in an accessible manner by the trench TR1 and the through-hole opening VO1 of the first surface dielectric layer BD1 for further electrical connection. In some embodiments, the trench TR1 and the corresponding through-hole opening VO1 exposing the first contact pad AP1 are omitted. Some of the through-hole openings (e.g., VO2) may pass through the first passivation layer PS1 to the top interconnect layer Mt, so that at least a portion of the top interconnect layer Mt is exposed in an accessible manner by the trench TR2 and the through-hole opening VO2. Some of the through-hole openings (e.g., VO3 and VO4) may pass through the first passivation layer PS1 and extend into the first dielectric layer 124 of the first interconnect structure 120, to the bottom interconnect layer M1 and / or any intermediate level interconnect layer (e.g., the second level interconnect layer M2 or the third level interconnect layer M3). In other embodiments, the via openings are formed before the trenches. Alternatively, the trenches and via openings are formed during the same process using, for example, a half tone mask.

[0025] Continue to refer to Figure 1B, the grooves and / or through-hole openings may taper from top to bottom. Alternatively, the surface dielectric layer BD1 includes substantially vertical sidewalls at locations where the grooves and / or through-hole openings are formed. In some embodiments, the top width (or diameter) of each groove is greater than the top width (or diameter) of the corresponding through-hole opening. The size of the grooves and the corresponding through-hole openings may be determined based on the function and process requirements of the first bonding connector to be subsequently formed. In some embodiments, the top width of any one of the plurality of grooves and the top width of the through-hole corresponding to the one groove are different from the top width of another of the grooves and the top width of the through-hole corresponding to the other groove.

[0026] For example, the top width WT1 of the trench TR2 is greater than the top width WT2 of the trench TR3. In some embodiments, the top width of the trench TR0 and / or the trench TR1 may be substantially the same as or similar to the top width WT1 of the trench TR2. In some embodiments, the top width WT1 of the trench TR2 is in the range of about 0.4 μm to about 5 μm. In some embodiments, the top width of the trench TR4 may be substantially the same as or similar to the top width WT2 of the trench TR3. In some embodiments, the top width WT2 of the trench TR3 is in the range of about 0.36 μm to about 4.5 μm. The top width WV1 of the through hole opening VO2 corresponding to the trench TR2 may be greater than the top width WV2 of the through hole opening VO3 corresponding to the trench TR3. In some embodiments, the top width of the through hole opening VO1 may be substantially the same as or similar to the top width WV1 of the through hole opening VO2. In some embodiments, the top width WV1 of the through hole opening VO2 is in the range of about 0.36 μm to about 2 μm. In some embodiments, the top width of the through hole opening VO4 may be substantially the same as or similar to the top width WV2 of the through hole opening VO3. In some embodiments, the top width WV2 of the through hole opening VO3 is in the range of about 0.1 μm to about 2 μm. It should be noted that the layout of the first interconnect structure 120 shown in the figure is only an example, and the top interconnect layer Mt or the lower interconnect layer may be distributed between the through hole opening VO2 and the through hole opening VO3 and / or between the through hole opening VO3 and the through hole opening VO4. Since the width of the through hole opening VO3 and / or VO4 is narrower than the width of the through hole opening VO2, the distribution layout area of ​​the first interconnect layer 122 can be extended wider and more feasible.

[0027] Still refer to Figure 1BIn some embodiments, the opening depth (or height) DV2 of the via opening VO3 is greater than the opening depth DV1 of the via opening VO2, so that the via opening VO3 extends further than the via opening VO2 to expose the second-level interconnect layer M2 below the top interconnect layer Mt. The via opening VO1 exposing the first contact pad AP1 may have the smallest opening depth among the via openings VO1, VO2, VO3, and VO4. It should be noted that Figure 1B The via openings VO2 and VO3 shown in the figure are only an example, and the via openings VO2 and VO3 with narrower widths may extend to any level (e.g., bottom interconnect layer M1, second-level interconnect layer M2, third-level interconnect layer M3) of the first interconnect layer 122 below the top interconnect layer Mt. In some embodiments, the via openings VO2 and / or VO3 with narrower widths may extend downward to expose the metal gate or tungsten contact in the first semiconductor device 112. The size of the via opening VO2 may be the same or similar to that of the via opening VO3, but is not limited thereto. For example, the via opening VO2 and the via opening VO3 may reach the same level or different levels of the first interconnect layer 122 below the top interconnect layer Mt. Alternatively, one of the via openings VO2 and VO3 is omitted. The number of via openings with narrower widths is not limited in the present disclosure. In some embodiments, the aspect ratio (opening depth DV2 / top width WV2) of the via opening VO3 is greater than the aspect ratio (opening depth DV1 / top width WV1) of the via opening VO2. In some embodiments, the aspect ratio (opening depth DV2 / top width WV2) of the via opening VO3 is about 0.3 to about 20. The aspect ratio (opening depth DV1 / top width WV1) of the via opening VO2 may be greater than the aspect ratio of the via opening VO1 exposing the first contact pad AP1.

[0028] Continue to refer to Figure 1CAfter forming the first surface dielectric layer BD1, a conductive material is formed in the trenches (TR0, TR1, TR2, TR3 and TR4) and the through-hole openings (VO1, VO2, VO3 and VO4) to form the first bonding connectors (BC0, BC1, BC2, BC3 and BC4). In an embodiment, the method of forming the first bonding connectors (BC0, BC1, BC2, BC3 and BC4) includes at least the following steps. For example, a diffusion barrier layer (not shown) is conformally formed on the first surface dielectric layer BD1 and the diffusion barrier layer covers the sidewalls and bottom of the trenches (TR0, TR1, TR2, TR3 and TR4) and the sidewalls and bottom of the through-hole openings (VO1, VO2, VO3 and VO4) to physically and electrically contact the first contact pads AP1 and the interconnect layer 122 exposed by the through-hole openings (VO1, VO2, VO3 and VO4). The diffusion barrier layer may include a barrier material (e.g., titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof) and may be formed using, for example, physical vapor deposition (PVD) or other suitable deposition processes. Next, a seed layer (not shown) may be conformally formed on the diffusion barrier layer using sputtering, plating, or other suitable deposition processes. For example, the seed layer may be a copper layer, a titanium / copper bilayer, or other suitable metal layer that facilitates the formation of thicker conductive materials during subsequent processing steps. Subsequently, conductive materials (e.g., copper, aluminum, silver, gold, metal alloys, etc.) are formed in the trenches (TR0, TR1, TR2, TR3, and TR4) and the via openings (VO1, VO2, VO3, and VO4) using plating, printing, or other suitable deposition processes to form first bonding connectors (BC0, BC1, BC2, BC3, and BC4). Thereafter, a planarization process (e.g., chemical mechanical polishing (CMP)) may be used to remove excess conductive materials to form a flat surface. It should be noted that the first bonding connectors (BC0, BC1, BC2, BC3, and BC4) may be formed using other suitable techniques. At this point, the first layer T1 of the semiconductor structure is substantially formed. In some embodiments, the first layer T1 of the semiconductor structure is regarded as a semiconductor die. In some embodiments, the above-mentioned manufacturing steps of the first layer T1 are performed at the wafer level, and the first layer T1 may or may not be singulated into a plurality of semiconductor dies (or chips) before the next step (e.g., bonding) is performed.

[0029] Still refer to Figure 1CThe first layer T1 includes a first surface S1 and a second surface S2 opposite to the first surface S1. The top surfaces of the first bonding connectors (BC0, BC1, BC2, BC3, and BC4) and the top surface of the first surface dielectric layer BD1 may be substantially flush at the first surface S1. The first bonding connector BC0 of the first layer T1 is substantially flush with the top surface of the first surface dielectric layer BD1. Figure 1C The cross section shown may not contact any of the conductive features below, for example, the first bonding connector BC0 acts as a metal line or a bonding pad. In some embodiments, the first bonding connector BC0 of the first layer T1 is an electrically floating virtual connector or virtual line. In some embodiments, the first bonding connector (such as BC1, BC2, BC3 and BC4) includes a groove portion (or a pad portion) and a through-hole portion extending downward from the corresponding groove portion. The groove portion of the first bonding connector (BC0, BC1, BC2, BC3 and BC4) may be substantially flush. In some embodiments, the first bonding connector (BC0, BC1, BC2, BC3 and BC4) is substantially coplanar with the first surface dielectric layer BD1. In some embodiments, the via portion of the first bonding connector BC1 tapers from the groove portion of the first bonding connector BC1 to the first contact pad AP1, the via portion of the first bonding connector BC2 tapers from the groove portion of the first bonding connector BC2 to the top interconnect layer Mt, and the via portions of the first bonding connectors BC3 and BC4 taper from the corresponding groove portions of the first bonding connectors BC3 and BC4 to the bottom interconnect layer M1 and / or the intermediate level of the first interconnect layer 122. In some embodiments, the via portion of the first bonding connector BC3 or BC4 is narrower and longer than the via portion of the first bonding connector BC1 or BC2. In some embodiments, the size of one of the first bonding connectors (e.g., BC1 or BC2) is at least about four times larger than the size of the other of the first bonding connectors (e.g., BC3 or BC4).

[0030] In some embodiments, power routing is performed in at least the top interconnect layer Mt of the first interconnect structure 120 or in some first interconnect layers 122 near the first surface dielectric layer BD1 in the first interconnect layer 122. For example, the first bonding connector BC2 directly connected to the top interconnect layer Mt can serve as a power connector for power distribution. In some embodiments, the first bonding connector BC1 connected to the top interconnect layer Mt through the first contact pad AP1 can also serve as a power connector. In some embodiments, signal routing is performed in the bottom interconnect layer M1 and / or any intermediate level below the top interconnect layer Mt, and the first bonding connectors BC3 and BC4 can serve as signal connectors for electrical signal distribution, and the first bonding connectors BC3 and BC4 are connected to the first interconnect layer 122 below the top interconnect layer Mt. Since the first bonding connectors (e.g., BC3 and BC4) connected to the signal routing are thinner than the first bonding connectors (e.g., BC1 and BC2) connected to the power routing, the power routing can be extended and distributed without compromising other characteristics of the integrated circuit. Since the first bonding connectors (e.g., BC3, BC4) are thinner, the line and spacing of the top interconnect layer Mt can be increased, thereby reducing the resistance-capacitance delay (RC delay) and improving the electrical performance. It should be understood that the actual size of the first bonding connector depends on the process technology node used, the number of first bonding connectors required (whether power or signals are transmitted through a specific bonding connector), and other factors based on product requirements.

[0031] Figures 2A to 2D is a schematic cross-sectional view showing various stages in a method for manufacturing a second layer of a semiconductor structure according to some embodiments of the present disclosure. Figure 2A and Figure 2B , a second interconnect structure 220 (marked at Figure 2C The second semiconductor substrate 210 may include a plurality of second semiconductor devices 212 formed in the second semiconductor substrate 210. The second semiconductor substrate 210 and the second semiconductor devices 212 may be the same as or similar to Figure 1A The first semiconductor substrate 110 and the first semiconductor device 112 described in the foregoing description are not described in detail herein for the sake of brevity. The first portion 220a of the second interconnect structure 220 may be similar to Figure 1A2. For example, the first portion 220a includes a portion of the second dielectric layer 224 and a portion of the second interconnect layer 222 embedded in the portion of the second dielectric layer 224. For example, the second interconnect layer 222 in the first portion 220a includes a bottom interconnect layer M1 electrically coupled to the second semiconductor device 212 and a second level interconnect layer M2 electrically connected to the bottom interconnect layer M1. It should be noted that although Figure 2A and Figure 2B FIG. 2 shows a two-level interconnect structure of the first portion 220 a, however, more or fewer interconnect layers may be formed in the first portion 220 a. The material of the first portion 220 a may be similar to Figure 1A The material of the first interconnecting structure 120 described above will not be described in detail for the sake of brevity.

[0032] Continue to refer to Figure 2A , an opening OP is formed on the first portion 220a using lithography and / or etching or other suitable techniques, and the opening OP extends downward into the second semiconductor substrate 210. The opening OP may include a circular, oval, square, rectangular, polygonal or other shape in a top view (not shown). In some embodiments, the opening OP tapers from the first portion 220a to the second semiconductor substrate 210. Alternatively, depending on the formation process, the opening OP may have substantially vertical sidewalls. The second semiconductor device 212 and the second interconnect layer 222 may be located away from the opening OP. At this stage, the opening OP does not penetrate the second semiconductor substrate 210. In other embodiments, the opening OP may penetrate the second semiconductor substrate 210.

[0033] Then, if Figure 2B As shown in , a conductive material may be formed in the opening OP by plating, printing or other suitable deposition processes to form a through semiconductor via (TSV) 230. For example, the conductive material may be formed by depositing one or more diffusion barrier layers or isolation layers, depositing a seed layer, and depositing a conductive material (e.g., tungsten, titanium, aluminum, copper, any combination thereof, and / or the like) into the opening OP by plating or other suitable processes. In some embodiments, a planarization process (e.g., a CMP process) is used to remove excess material formed on the first portion 220a so that the TSV 230 is substantially flush with the first portion 220a (e.g., the top surface of the dielectric layer 224 of the first portion 220a).

[0034] Reference Figure 2C, forming a second portion 220b of the second interconnect structure 220 on the first portion 220a and the TSV 230. The second portion 220b of the second interconnect structure 220 may be similar to Figure 1A 2. The upper portion of the first interconnect structure 120 described in the embodiment of the present invention is a portion of the second dielectric layer 224 and a portion of the second interconnect layer 222 embedded in the portion of the second dielectric layer 224. For example, the portion of the second interconnect layer 222 in the second portion 220b includes a third-level interconnect layer M3 embedded in the portion of the second dielectric layer 224 and electrically connected to the second-level interconnect layer M2 and the TSV 230, and a top interconnect layer Mt electrically connected to the third-level interconnect layer M3 and embedded in the portion of the second dielectric layer 224. It should be understood that the second portion 220b of the second interconnect structure 220 may include more than one interconnect layer located between the first portion 220a and the top interconnect layer Mt. The material of the second portion 220b may be similar to that of the first portion 220a, and will not be described again for the sake of simplicity.

[0035] In the illustrated embodiment, the TSV 230 is in physical and electrical contact with the middle level of the second interconnect layer 222. In other embodiments, the TSV 230 is in physical and electrical contact with the top interconnect layer Mt or the bottom interconnect layer M1 of the second interconnect structure 220. It should be noted that although only one TSV 230 is shown in the figure, more than one TSV 230 may be formed depending on the design requirements. In other embodiments, the TSV 230 may be formed using a via-first process. For example, the TSV 230 is formed before the second interconnect structure 220 is formed so that the TSV 230 extends only to the ILD layer of the second interconnect structure 220 covering the second semiconductor device 212, and does not extend into the IMD layer of the second interconnect structure 220. Alternatively, the TSV 230 may be formed using a via-last process (e.g., the TSV is formed after the second interconnect structure 220 is formed).

[0036] After forming the second portion 220b of the second interconnect structure 220, a second passivation layer PS2 is formed on the second portion 220b of the second interconnect structure 220, and a second contact pad AP2 is formed on the second passivation layer PS2. The second contact pad AP2 is electrically coupled to the second interconnect layer 222 below the second interconnect structure 220. The TSV 230 and the second contact pad AP2 may be electrically coupled via the second interconnect layer 222. The materials of the second passivation layer PS2 and the second contact pad AP2 may be similar to Figure 1A The materials of the first passivation layer PS1 and the first contact pad AP1 are described in detail, so they will not be described in detail for the sake of brevity.

[0037] Reference Figure 2D , a second surface dielectric layer BD2 and a plurality of second bonding connectors (e.g., BE0, BE1, BE2, BE3, and BE4) are formed on the second passivation layer PS2 and the second contact pad AP2. Thus, the second layer T2 of the semiconductor structure is formed. In some embodiments, the second layer T2 of the semiconductor structure is regarded as a semiconductor die. The formation process and materials of the second surface dielectric layer BD2 and the second bonding connectors (BE0, BE1, BE2, BE3, and BE4) can be similar to Figure 1B and Figure 1C The formation process and materials of the first surface dielectric layer BD1 and the first bonding connectors (BC0, BC1, BC2, BC3 and BC4) described in the present invention are not described in detail herein for the sake of brevity.

[0038] In some embodiments, some of the second bonding connectors (e.g., BE3, BE4) extending into the second interconnect structure 220 to physically and electrically contact the middle level of the interconnect layer (e.g., the second level interconnect layer M2) or the bottom interconnect layer M1 may be thinner than other second bonding connectors (e.g., BE1, BE2) that physically and electrically contact the top interconnect layer Mt and / or the second contact pad AP2. In some embodiments, the sizes of the second bonding connectors (BE0, BE1, BE2, BE3, and BE4) correspond to the sizes of the first bonding connectors (BC0, BC1, BC2, BC3, and BC4), respectively. The second layer T2 may include a third surface S3 and a fourth surface S4 that are opposite to each other. The second bonding connectors (BE0, BE1, BE2, BE3, and BE4) and the second surface dielectric layer BD2 may be substantially flush at the third surface S3. In some embodiments, due to the formation of the second bonding connectors (e.g., BC1, BC2, BC3, and BC4), the power or signal introduced into the TSV 230 can be provided by the second bonding connectors having different lengths. In some embodiments, compared with the conventional structure, in the second layer T2, the path to the conductive features located on different interconnect layers is significantly shortened, thereby improving the power connection efficiency. At this stage, the TSV 230 may or may not be exposed at the fourth surface S4 in an accessible manner. The above-mentioned manufacturing steps of the second layer T2 can be performed at the wafer level, and the second layer T2 may or may not be singulated into a plurality of semiconductor dies (or chips) before the next step (e.g., bonding) is performed.

[0039] Figures 3A to 3D Schematic cross-sectional views showing various stages in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Figure 3A, the first layer T1 and the second layer T2 are bonded together in a face-to-face configuration. For example, the first layer T1 and the second layer T2 are arranged in a manner that the first surface S1 of the first layer T1 and the third surface S3 of the second layer T2 face each other, and the first layer T1 and the second layer T2 are bonded. In some embodiments, the bonding interface IF between the first layer T1 and the second layer T2 includes dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), any combination thereof, and / or similar bonding techniques.

[0040] In some embodiments, the first layer T1 and the second layer T2 are separately manufactured, and a hybrid bonding process is performed on the first layer T1 and the second layer T2. For example, to facilitate hybrid bonding, surface preparation is performed on the bonding surface (e.g., the first surface S1 of the first layer T1 and the third surface S3 of the second layer T2) to remove particles on the surface. Surface preparation may include surface cleaning and activation or other suitable processes. In some embodiments, the top surface of the first bonding connector (BC0, BC1, BC2, BC3, and BC4) and the top surface of the second bonding connector (BE0, BE1, BE2, BE3, and BE4) may be cleaned by wet cleaning before performing the bonding process. By using, for example, a chemical used in wet cleaning, not only particles are removed, but also native oxide formed on the top surface of the first bonding connectors (BC0, BC1, BC2, BC3, and BC4) of the first layer T1 and the top surface of the second bonding connectors (BE0, BE1, BE2, BE3, and BE4) of the second layer T2 can be removed. After cleaning, activation of the top surface of the first surface dielectric layer BD1 and the top surface of the second surface dielectric layer BD2 can be performed to generate high bonding strength. In some embodiments, plasma activation can be performed to process the top surface of the first surface dielectric layer BD1 and the top surface of the second surface dielectric layer BD2.

[0041] In some embodiments, the first layer T1 is aligned with the second layer T2 and sub-micron alignment accuracy can be achieved. For example, each first bonding connector (BC0, BC1, BC2, BC3 and BC4) can be substantially aligned with the corresponding second bonding connector (BE0, BE1, BE2, BE3 and BE4). In some embodiments, some of the first bonding connectors (e.g., BC1, BC2) that serve as power connectors of the first layer T1 are substantially aligned with second bonding connectors (e.g., BE1, BE2) that also serve as power connectors of the second layer T2. For example, the power connections in the first layer T1 and the second layer T2 have short paths, thereby reducing the resistance of the power path. Some of the first bonding connectors (e.g., BC3, BC4) that serve as signal connectors of the first layer T1 can be substantially aligned with second bonding connectors (e.g., BE3, BE4) that also serve as signal connectors of the second layer T2. Once the first layer T1 and the second layer T2 are precisely aligned, the first layer T1 or the second layer T2 are placed on each other and the first layer T1 and the second layer T2 are brought into contact with each other. When the activated top surface of the first surface dielectric layer BD1 of the first layer T1 is brought into contact with the activated top surface of the second surface dielectric layer BD2 of the second layer T2, the first surface dielectric layer BD1 of the first layer T1 and the second surface dielectric layer BD2 of the second layer T2 are pre-bonded. In other words, the first layer T1 and the second layer T2 are pre-bonded by pre-bonding the first surface dielectric layer BD1 and the second surface dielectric layer BD2. After pre-bonding, the first bonding connectors (BC0, BC1, BC2, BC3, and BC4) may correspond to the second bonding connectors (BE0, BE1, BE2, BE3, and BE4), respectively, and may be in physical contact with the second bonding connectors (BE0, BE1, BE2, BE3, and BE4).

[0042] In some embodiments, after pre-bonding the first layer T1 and the second layer T2, hybrid bonding of the first layer T1 and the second layer T2 is performed. The hybrid bonding of the first layer T1 and the second layer T2 may include a process for dielectric bonding, a process for enhancing bonding between the first surface dielectric layer BD1 and the second surface dielectric layer BD2, and a thermal annealing process, which is beneficial to the bonding between the first bonding connectors (BC0, BC1, BC2, BC3, and BC4) of the first layer T1 and the second bonding connectors (BE0, BE1, BE2, BE3, and BE4) of the second layer T2. In some embodiments, the process temperature of the thermal annealing for connector bonding is higher than the process temperature of the process for dielectric bonding. Since the thermal annealing performed on the first bonding connectors (BC0, BC1, BC2, BC3 and BC4) of the first layer T1 and the second bonding connectors (BE0, BE1, BE2, BE3 and BE4) of the second layer T2 is performed at a relatively high temperature, metal diffusion and grain growth may occur at the bonding interface IF between the first bonding connectors (BC0, BC1, BC2, BC3 and BC4) of the first layer T1 and the second bonding connectors (BE0, BE1, BE2, BE3 and BE4) of the second layer T2. After performing the bonding of the first layer T1 and the second layer T2, the first bonding connectors (BC0, BC1, BC2, BC3 and BC4) and the second bonding connectors (BE0, BE1, BE2, BE3 and BE4) provide vertical electrical connections between the first layer T1 and the second layer T2, and the first internal connection structure 120 of the first layer T1 and the second internal connection structure 220 of the second layer T2 are physically and electrically contacted with each other through the first bonding connectors (BC0, BC1, BC2, BC3 and BC4) and the second bonding connectors (BE0, BE1, BE2, BE3 and BE4).

[0043] Reference Figure 3B After the first layer T1 and the second layer T2 are bonded, the fourth surface S4 (marked at Figure 3AA thinning process is performed on the second semiconductor substrate 210 so that the TSV 230 is exposed in a touchable manner. For example, the second semiconductor substrate 210 is thinned until the TSV 230 is exposed. In some embodiments, the TSV 230 may be slightly removed during the thinning process. The thinning process may include grinding, polishing and / or etching or other suitable techniques. In some embodiments, an isolation layer 240 is formed on the thinned fourth surface S4' of the second layer T2. For example, the isolation layer 240 includes an oxide formed by thermal oxidation of the second semiconductor substrate 210. In other embodiments, the isolation layer 240 is formed using a deposition process or other suitable techniques and may include silicon oxide, silicon nitride, etc. After formation, the TSV 230 may be covered by the isolation layer 240 at least in the lateral direction.

[0044] Reference Figure 3C , a redistribution structure 250 is formed on the isolation layer 240 and the TSV 230. The redistribution structure 250 may include at least one patterned dielectric layer 254 and at least one patterned conductive layer 252 (e.g., conductive wire, via, pad) disposed in the patterned dielectric layer 254. For example, the patterned conductive layer 252 and the patterned dielectric layer 254 may be formed using a suitable deposition technique, patterning technique, and metallization technique (e.g., dielectric deposition, photolithography, etching, seed layer deposition, plating, planarization, etc.) or other suitable processes. It should be noted that although Figure 3C A two-layer redistribution structure is shown in FIG. 2 , however, the redistribution structure 250 may include more or less patterned conductive layers and patterned dielectric layers. The number of patterned conductive layers and patterned dielectric layers is not limited thereto.

[0045] The bottom layer 252a in the patterned conductive layer may be embedded in the bottom layer 254a in the patterned dielectric layer and may be in physical and electrical contact with the TSV 230 below. The TSV 230 may include an inclined sidewall connected to the second interconnect structure 220 and the redistribution structure 250. For example, the TSV 230 tapers from the bottom layer 252a in the patterned conductive layer of the second interconnect structure 220 to the redistribution structure 250. The top layer 252b in the patterned conductive layer may be exposed in a touchable manner by the top layer 254b in the patterned dielectric layer. In some embodiments, the top layer 252b in the patterned conductive layer includes an external contact pad AP3 for further electrical connection. The external contact pad AP3 may be an under-bump metallurgy (UBM) pad for a subsequent ball-mounting process. The external contact pad AP3 may include a material similar to the first contact pad AP1 or the second contact pad AP2. It should be noted that although only one external contact pad AP3 is shown, the number of external contact pads AP3 is not limited in the present disclosure.

[0046] In some embodiments, the topmost layer 254b in the patterned dielectric layer may include one or more suitable passivation materials and / or protective materials to provide a certain degree of protection for the conductive features below. For example, the topmost layer 254b in the patterned dielectric layer includes a passivation layer (e.g., a silicon oxide layer, a silicon nitride layer, a combination thereof, etc.), a polymer layer (e.g., an epoxy resin layer, a polyimide layer, a benzocyclobutene (BCB) layer, a polybenzoxazole (PBO) layer, etc.), or a dielectric layer made of other suitable electrically insulating materials. The patterned conductive layer 252 of the rewiring structure 250 can rewire the circuit system below and can rewire the signals or power of the first layer T1 and the second layer T2.

[0047] Reference Figure 3D, external terminals 260 are formed on the redistribution structure 250. For example, a plurality of external terminals 260 (e.g., conductive balls) arranged in an array are formed on the external contact pads AP3 of the topmost layer 252b in the patterned conductive layer. In some embodiments, the external terminals 260 may be solder balls formed by ball placement and reflowing processes. In some other embodiments, the external terminals 260 may be or may include copper pillars, controlled collapse chip connection (C4) bumps, micro-bumps, copper layers, nickel layers, lead free (LF) layers, electroless nickel electroless palladium immersion gold (ENEPIG) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb layers, combinations thereof, and the like. It should be noted that the external terminals 260 may be formed using any suitable external terminals and any suitable processes.

[0048] In some embodiments, after forming the external terminals 260, a singulation process may be performed along a scribe line (not shown) to cut the resulting structure into a plurality of semiconductor structures 10. In some embodiments, the above steps may be performed at a wafer-to-wafer level, wherein the first layer T1 and the second layer T2 are provided in the form of wafers for bonding, and after bonding, the bonded structure is singulated into a plurality of semiconductor structures 10. In other embodiments, the above steps may be performed at a die-to-die level or a die-to-wafer level, wherein at least one of the first layer T1 and the second layer T2 is singulated into a plurality of semiconductor dies (or chips) before bonding.

[0049] like Figure 3D As shown in , the semiconductor structure 10 includes a first layer T1 and a second layer T2 that are vertically stacked and integrated together. In some embodiments, the semiconductor structure 10 including the integrated circuit can provide an entire system in an integrated circuit (IC) component. In some embodiments, the TSV 230 is used to provide a short grounding path for grounding the integrated circuit through the back side of the second layer T2, and the back side of the second layer T2 can be covered by a grounded metallic film (not shown). It should be noted that Figures 3A to 3DThe illustrated embodiment of pad-to-pad bonding (i.e., bonding the groove portion of the first bonding connector (BC0, BC1, BC2, BC3, and BC4) to the groove portion of the second bonding connector (BE0, BE1, BE2, BE3, and BE4)) is only an example, and the bonding connectors of the first layer T1 and / or the second layer T2 may be or may include vias (e.g., copper through-holes), conductive pads (e.g., copper pads), or a combination thereof. For example, the bonding between the first bonding connectors (BC0, BC1, BC2, BC3, and BC4) of the first layer T1 and the second bonding connectors (BE0, BE1, BE2, BE3, and BE4) of the second layer T2 may be via-to-via bonding, pad-to-pad bonding, or via-to-pad bonding, which will be described in more detail in other embodiments below.

[0050] Figure 4 is a schematic cross-sectional view showing a first layer of a semiconductor structure according to some embodiments of the present disclosure. Figure 4 , the first layer T1' is similar to Figure 1C The first layer T1 shown in the figure, the difference between the first layer T1' and the first layer T1 is the first bonding connector. For ease of understanding, the same elements in all figures use the same reference numerals and are not repeated herein. For example, a plurality of through-hole openings (not shown) are formed on the first surface dielectric layer BD3 of the first layer T1', and no grooves are formed on the first surface dielectric layer BD3. In some embodiments, at least a portion of the through-hole openings may extend downward into the first interconnect structure 120 using a single damascene process or other suitable techniques. Next, a conductive material is formed in the through-hole openings to form a plurality of first bonding connectors (e.g., BF0, BF1, BF2, BF3, and BF4). In some embodiments, the first bonding connectors (BF0, BF1, BF2, BF3, and BF4) have inclined sidewalls and may taper from the first surface S1' toward the second surface S2 in the thickness direction TD of the first layer T1'. Alternatively, each first bonding connection (eg, BF0, BF1, BF2, BF3, and BF4) includes substantially vertical sidewalls.

[0051] In some embodiments, some of the first bonding connectors (e.g., BF3, BF4) are in physical and electrical contact with the first interconnect layer 122 located below the top interconnect layer Mt. In some embodiments, some of the first bonding connectors (e.g., BF1, BF2) are in physical and electrical contact with the first contact pad AP1 and / or the top interconnect layer Mt, and other first bonding connectors (e.g., BF0) may serve as dummy connectors. In some embodiments, the first bonding connectors (e.g., BF3, BF4) connected to the first interconnect layer 122 located below the top interconnect layer Mt have the same or similar top widths. The top widths of the remaining first bonding connectors (e.g., BF0, BF1, BF2) may be the same or similar to each other, but may be different from the top widths of the first bonding connectors (e.g., BF3, BF4) connected to the first interconnect layer 122 located below the top interconnect layer Mt. Taking the first bonding connectors BF2 and BF3 as an example, the top width W1 of the first bonding connector BF2 is greater than the top width W2 of the first bonding connector BF3, and the first bonding connector BF3 extends farther from the first surface S1' of the first layer T1' than the first bonding connector BF2. In some embodiments, the top width W1 of the first bonding connector BF2 is in the range of about 0.3 μm to about 4.5 μm. In some embodiments, the top width W2 of the first bonding connector BF3 is in the range of about 0.1 μm to about 2.5 μm. The first bonding connector BF3 may be thinner than the first bonding connector BF2 and longer than the first bonding connector BF2. In some embodiments, the aspect ratio (height / top width) of the first bonding connector BF3 is about 0.3 to about 20.

[0052] In some embodiments, the first layer T1′ is bonded to the substrate in a face-to-face configuration using through-hole-to-pad bonding (i.e., bonding the first bonding connectors (BF0, BF1, BF2, BF3, and BF4) to the groove portions of the second bonding connectors (BE0, BE1, BE2, BE3, and BE4)). Figure 2D , to form a bonding structure, which can then be processed to form a semiconductor structure (not shown). In other embodiments, two first layers T1' can be bonded together in a face-to-face configuration using through-hole to through-hole bonding (i.e., bonding the first bonding connector of one of the first layers T1' to the first bonding connector of the other first layer T1') to form a bonding structure, and then TSVs, rewiring structures and external terminals can be formed on at least one of the first semiconductor substrates to provide electrical connections to external components. It should be noted that, depending on the design requirements, any number of first layers T1 or T1' and / or second layers T2 can be stacked in the vertical direction in any combination, and different layers can be electrically connected to each other at least through bonding connectors, TSVs and other conductive features.

[0053] FIG. 5A to FIG. 5C is a schematic partial cross-sectional view showing various stages in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. It should be noted that FIG. 5A to FIG. 5C Only a portion of the structure is shown. For example, two Figure 1C The first layer T1 (or two Figure 4 Then, the two first layers T1 (or the two first layers T1') are bonded together in a face-to-face configuration to form a bonded structure, FIG. 5A to FIG. 5C The first layer T1 (or Figure 4 In some embodiments, the first layer T1 and the second layer T2 may be bonded together to form Figure 3A The bonding structure shown in FIG. 5A to FIG. 5C The first layer T1 of the bonded structure may be shown after the bonded structure is flipped (eg, turned upside down). Alternatively, the first layer T1 of the bonded structure may be composed of Figure 4 It should be noted that the bonding structure may include more than two layers stacked and bonded to each other, and the number of stacked layers of the bonding structure is not limited in the present disclosure.

[0054] Reference Figure 5A and Figure 5B , an opening OP is formed on the first semiconductor substrate 110. For example, the opening OP passes through the first semiconductor substrate 110 and extends downward to the first interconnect structure 120, thereby exposing the first interconnect layer 122 in an accessible manner. The opening OP may taper from the first semiconductor substrate 110 to the first interconnect layer 122. Alternatively, the opening OP may include a substantially vertical sidewall. It should be noted that, depending on design requirements, the opening OP may extend to any level that exposes the first interconnect layer 122, Figure 5A The description is only an example. Subsequently, a conductive material is formed in the opening OP to form a TSV 330. For example, the TSV 330 is physically and electrically in contact with any level in the first interconnect layer 122. The material of the TSV 330 may be similar to Figure 2B For example, the conductive material may be formed by plating, printing or other suitable deposition processes, and then the excess material may be removed by, for example, a CMP process, so that the TSV 330 may be substantially flush with the second surface S2 of the first semiconductor substrate 110.

[0055] Reference Figure 5C, a redistribution structure 250 is formed on the second surface S2 of the first semiconductor substrate 110 and the TSV 330, and then an external terminal 260 is formed on the redistribution structure 250. The bottom layer 252a in the patterned conductive layer of the redistribution structure 250 may be in physical and electrical contact with the TSV 330. The redistribution structure 250 and the external terminal 260 may be electrically coupled to the first interconnect structure 120 through the TSV 330. In some embodiments, the TSV 330 may have an inclined sidewall and may taper from the bottom layer 252a in the patterned conductive layer to the first interconnect layer 122. The formation process and materials of the redistribution structure 250 and the external terminal 260 may be similar to those of Figure 3C and Figure 3D The formation process and materials of the redistribution structure 250 and the external terminal 260 are described in detail, so for the sake of simplicity, they will not be described again. After the redistribution structure 250 and the external terminal 260 are formed, a singulation process can be performed along the dicing line (not shown) to cut the resulting structure into a plurality of semiconductor structures 20.

[0056] Figure 6 is a schematic cross-sectional view showing a semiconductor structure according to some embodiments of the present disclosure. Figure 6, a semiconductor structure 30 including a first layer T1 and a third layer T3 stacked on the first layer T1 is provided. In some embodiments, the first layer T1 and the third layer T3 are bonded together in a face-to-back configuration. For example, the third layer T3 includes a second semiconductor substrate 210 of a second semiconductor device 212, a second interconnect structure 220 formed on and electrically coupled to the second semiconductor substrate 210, and a second contact pad AP2 in physical and electrical contact with the top interconnect layer Mt. In some embodiments, the third layer T3 includes a third surface dielectric layer BD4 and a plurality of third bonding connectors (e.g., BG1 and BG2), the third surface dielectric layer BD4 being formed on the second semiconductor substrate 210 opposite to the second interconnect structure 220, the plurality of third bonding connectors (e.g., BG1 and BG2) penetrating through the third surface dielectric layer BD4 and the second semiconductor substrate 210 to be in physical and electrical contact with the second interconnect layer 222 of the second interconnect structure 220. For example, the third bonding connector BG1 extends from the bonding interface IF' between the first layer T1 and the third layer T3, passes through the second semiconductor substrate 210, and extends into the second dielectric layer 224 to reach the top interconnect layer Mt of the second interconnect layer 222. In some embodiments, the third bonding connector BG2 extends from the bonding interface IF', passes through the second semiconductor substrate 210, and extends into the second dielectric layer 224 to the middle level (e.g., the second level interconnect layer M2) of the second interconnect layer 222 or the bottom interconnect layer M1 of the second interconnect layer 222. The third bonding connector BG1 may extend farther from the bonding interface IF' than the third bonding connector BG2. In some embodiments, the third bonding connector BG1 and the third bonding connector BG2 are correspondingly bonded to the first bonding connector BC1 and the first bonding connector BC4, which may serve as a power connector and a signal connector, respectively.

[0057] It should be understood that the third bonding connector (eg, BG1, BG2) may contact any level of the second interconnect layer 222 according to product requirements. Figure 6 The configuration of the third bonding connector shown in is only an example. The number of the third bonding connectors (e.g., BG1 and BG2) may or may not correspond to the number of the first bonding connectors (e.g., BC0, BC1, BC2, BC3, and BC4) of the first layer T1. The third bonding connectors (e.g., BG1 and BG2) may be formed after forming the third surface dielectric layer BD4. In other embodiments, some portions of the third bonding connectors (e.g., BG1 and BG2) that pass through the second semiconductor substrate 210 and extend into the second interconnect structure 220 may be formed before the portions of the third bonding connectors (e.g., BG1 and BG2) that are laterally embedded in the third surface dielectric layer BD4.

[0058] In some embodiments, the first layer T1 and the third layer T3 are arranged in a manner that the first surface S1 of the first layer T1 and the fifth surface S5 of the third layer T3 face each other and the first layer T1 and the third layer T3 are bonded. The third bonding connector (e.g., BG1 and BG2) and the third surface dielectric layer BD4 may be substantially flush at the fifth surface S5 of the third layer T3. In some embodiments, the bonding interface IF' between the first layer T1 and the third layer T3 includes dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), any combination thereof, and / or the like. The bonding interface IF' may be located between the first surface dielectric layer BD1 of the first layer T1 and the third surface dielectric layer BD4 of the third layer T3. The first surface dielectric layer BD1 of the first layer T1 and the third surface dielectric layer BD4 of the third layer T3 may be located between the first interconnect structure 120 of the first layer T1 and the second semiconductor substrate 210 of the third layer T3.

[0059] In some embodiments, the second contact pad AP2 electrically connected to the top interconnect layer Mt of the second interconnect layer 222 may serve as an external pad, and an external terminal 260 may be formed on the second contact pad AP2. For example, the third passivation layer PS3 formed on the second passivation layer PS2 may expose at least a portion of the second contact pad AP2 for the external terminal 260 formed subsequently in an accessible manner. The external terminal 260 may be electrically coupled to the second semiconductor device 212 through the second contact pad AP2 and the second interconnect layer 222. In some embodiments, the power signal or electrical signal of the first layer T1 may be transmitted to the external terminal 260 through the third bonding connector (e.g., BG1, BG2), the second interconnect layer 222, and the second contact pad AP2. It should be understood that the semiconductor structure 30 may include more than two layers and that bonding connectors and / or TSVs may be used to provide vertical electrical connections between two adjacent layers.

[0060] Figure 7 is a schematic cross-sectional view showing the application of a semiconductor structure according to some embodiments of the present disclosure. Figure 7 , a structure 40 is provided including a first component 42 and a second component 44 disposed on the first component 42. The first component 42 may be or may include a printed circuit board (PCB), a printed wiring board, an interposer, a packaging substrate, and / or other carriers capable of carrying an integrated circuit. In some embodiments, the second component 44 mounted on the first component 42 is similar to the above-mentioned combination of Figure 3D , Figure 5C and Figure 6The semiconductor structure 10, 20 or 30 described above. For example, the semiconductor structure 10, 20 or 30 can be electrically coupled to the first component 42 through a plurality of terminals 44a (e.g., external terminals 260). In some other embodiments, the second component 44 mounted on the first component 42 can be a semiconductor structure (e.g., a semiconductor structure 10, 20 or 30) that includes at least one semiconductor structure (e.g., a semiconductor structure 10, 20 or 30) packaged therein. Figure 3D , Figure 5C and Figure 6 For example, the second component 44 may include a plurality of semiconductor structures (eg, the combination of the above Figure 3D , Figure 5C and Figure 6 The invention relates to a semiconductor structure 10, 20 or 30 as described, a fan-out rewiring structure (not shown), and a plurality of terminals 44a, wherein the plurality of semiconductor structures are separated and laterally enclosed by an insulating encapsulation body (not shown), the fan-out rewiring structure can be formed on the insulating encapsulation body and these semiconductor structures to electrically couple to these semiconductor structures, and the plurality of terminals 44a are formed on the fan-out rewiring structure to electrically couple to the fan-out rewiring structure and the first component 42. Other packaging technologies can be used, and the packaging technologies are not limited in the present disclosure. The structure 40 can be part of an electronic system such as the following devices: a computer (such as a high-performance computer (HPC)), a computing device used in conjunction with an artificial intelligence (AI) system, a wireless communication device, a computer-related peripheral device, an entertainment device, etc. It should be noted that other applications may also exist.

[0061] According to some embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a semiconductor substrate, a plurality of interconnection layers, a first connector and a second connector. The semiconductor substrate comprises a plurality of semiconductor devices in the semiconductor substrate. The interconnection layer is disposed on the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed on the plurality of interconnection layers and extends to contact with a first level of the plurality of interconnection layers. The second connector is disposed on the plurality of interconnection layers and is substantially flush with the first connector. The second connector extends further than the first connector to contact with a second level of the plurality of interconnection layers located between the first level of the plurality of interconnection layers and the semiconductor substrate, and the first connector is wider than the second connector.

[0062] In some embodiments, the semiconductor structure further comprises a contact pad, the contact pad being disposed above the first level of the plurality of interconnect layers and being electrically coupled to the semiconductor device of the semiconductor substrate through the plurality of interconnect layers. In some embodiments, the semiconductor structure further comprises a third connector, the top surface of the third connector being substantially flush with the top surface of the first connector and the top surface of the second connector, the third connector extending to contact the contact pad. In some embodiments, the aspect ratio of the third connector is less than the aspect ratio of the second connector. In some embodiments, the aspect ratio of the second connector is in a range of about 0.3 to about 20. In some embodiments, the semiconductor structure further comprises a semiconductor through-hole, the semiconductor through-hole penetrating through the semiconductor substrate to contact any one of the plurality of interconnect layers, the semiconductor through-hole being electrically coupled to the semiconductor device of the semiconductor substrate through the plurality of interconnect layers. In some embodiments, the semiconductor through-hole tapers from the one of the plurality of interconnect layers to the semiconductor substrate.

[0063] According to some embodiments of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising a first semiconductor die and a second semiconductor die stacked on the first semiconductor die and bonded to the first semiconductor die. The first semiconductor die comprises a first bonding connector and a second bonding connector. The ratio of the height to the width of the second bonding connector is greater than the ratio of the height to the width of the first bonding connector. The second semiconductor die comprises a third bonding connector bonded to the first bonding connector of the first semiconductor die and a fourth bonding connector bonded to the second bonding connector of the first semiconductor die. The size of the third bonding connector and the size of the fourth bonding connector correspond to the size of the first bonding connector and the size of the second bonding connector, respectively.

[0064] In some embodiments, the first bonding connector of the first semiconductor die is substantially flush with the second bonding connector of the first semiconductor die at the bonding interface between the first semiconductor die and the second semiconductor die. In some embodiments, the first bonding connector and the second bonding connector extend in the thickness direction of the first semiconductor die, and the second bonding connector extends further from the bonding interface than the first bonding connector. In some embodiments, the first semiconductor die also includes a first semiconductor substrate and a plurality of first interconnect layers, the first semiconductor substrate including a plurality of first semiconductor devices in the first semiconductor substrate, the plurality of first interconnect layers being disposed on the first semiconductor substrate and electrically coupled to the first semiconductor devices, wherein the first bonding connector is disposed on the plurality of first interconnect layers and extends from the bonding interface between the first semiconductor die and the second semiconductor die to a first level of the plurality of first interconnect layers. In some embodiments, the second bonding connector of the first semiconductor die is disposed on the plurality of first interconnect layers and extends from the bonding interface to a second level of the plurality of first interconnect layers between the first semiconductor substrate and the first level of the plurality of first interconnect layers. In some embodiments, the first semiconductor die further comprises a first semiconductor through-hole, the first semiconductor through-hole penetrating through the first semiconductor substrate to contact any one of the plurality of first interconnect layers. In some embodiments, the first semiconductor die further comprises an external contact pad and an external terminal, the external contact pad being disposed on the first semiconductor substrate opposite to the plurality of first interconnect layers and being electrically coupled to the first semiconductor through-hole, the external terminal being disposed on the external contact pad and being electrically coupled to the external contact pad. In some embodiments, the second semiconductor die further comprises a second semiconductor substrate and a plurality of second interconnect layers, the second semiconductor substrate comprising a plurality of second semiconductor devices in the second semiconductor substrate, the plurality of second interconnect layers being disposed on the second semiconductor substrate and being electrically coupled to the second semiconductor devices, wherein the bonding interface between the first semiconductor die and the second semiconductor die is located between the second semiconductor substrate of the second semiconductor die and the first level of the plurality of first interconnect layers of the first semiconductor die. In some embodiments, the second semiconductor substrate of the second semiconductor die and the multiple first interconnection layers of the first semiconductor die are located between the multiple second interconnection layers of the second semiconductor die and the first semiconductor substrate of the first semiconductor die, and the third bonding connector and the fourth bonding connector of the second semiconductor die penetrate through the second semiconductor substrate to contact any one of the multiple second interconnection layers.

[0065] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor structure includes at least the following steps: forming a first surface dielectric layer on a first interconnect structure on a first semiconductor substrate; forming a first through-hole opening and a second through-hole opening, wherein the second through-hole opening penetrates through the first surface dielectric layer and extends further than the first through-hole opening to expose at least a portion of the first interconnect structure in a tangible manner, and the second through-hole opening is narrower than the first through-hole opening; and forming a conductive material in the first through-hole opening and the second through-hole opening to form a first bonding connector and a second bonding connector, respectively.

[0066] In some embodiments, the manufacturing method further includes bonding a second surface dielectric layer, a third bonding connector, and a fourth bonding connector to the first surface dielectric layer, the first bonding connector, and the second bonding connector, respectively, wherein the size of the third bonding connector and the size of the fourth bonding connector correspond to the size of the first bonding connector and the size of the second bonding connector. In some embodiments, a damascene process is performed to form the first through-hole opening and the second through-hole opening, wherein the aspect ratio of the second through-hole opening is greater than the aspect ratio of the first through-hole opening. In some embodiments, before forming the first surface dielectric layer, the manufacturing method further includes forming a portion of the first interconnect structure on the first semiconductor substrate, forming a semiconductor through-hole extending from the portion of the first interconnect structure to the first semiconductor substrate, and forming the remainder of the first interconnect structure on the portion of the first interconnect structure and the semiconductor through-hole.

[0067] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

[0068] [Explanation of Symbols]

[0069] 10, 20, 30: Semiconductor structure

[0070] 40: Structure

[0071] 42: First Component

[0072] 44: Second component

[0073] 44a: terminal

[0074] 110: First semiconductor substrate

[0075] 112: The first semiconductor device

[0076] 120: First internal connection structure

[0077] 122: First inner layer / inner layer

[0078] 124: First dielectric layer

[0079] 210: Second semiconductor substrate

[0080] 212: Second semiconductor device

[0081] 220: Second internal structure

[0082] 220a: Part I

[0083] 220b: Part 2

[0084] 222: Second inner layer

[0085] 224: Second dielectric layer

[0086] 230, 330: Semiconductor through-hole via (TSV)

[0087] 240: Isolation layer

[0088] 250: Rewiring Structure

[0089] 252, 252a, 252b: patterned conductive layer

[0090] 254, 254a: Patterned dielectric layer

[0091] 260: External terminal

[0092] AP1: First contact pad

[0093] AP2: Second contact pad

[0094] AP3: External contact pad

[0095] BC0, BC1, BC2, BC3, BC4, BF0, BF1, BF2, BF3, BF4: first joint connector

[0096] BD1: First surface dielectric layer / surface dielectric layer

[0097] BD2: Second surface dielectric layer

[0098] BD3: First surface dielectric layer

[0099] BD4: Third surface dielectric layer

[0100] BE0, BE1, BE2, BE3, BE4: Second joint connection

[0101] BG0, BG1, BG2: Third joint connection

[0102] DV1, DV2: opening depth

[0103] IF, IF': bonding interface

[0104] M1: Bottom inner connection layer

[0105] M2: Second level inner link layer

[0106] M3: The third level inner layer

[0107] Mt: Top inner layer

[0108] OP: Opening

[0109] PS1: First passivation layer

[0110] PS2: Second passivation layer

[0111] PS3: The third passivation layer

[0112] S1, S1': first surface

[0113] S2: Second surface

[0114] S3: Third surface

[0115] S4: Fourth Surface

[0116] S4': Thinned fourth surface

[0117] S5: The Fifth Surface

[0118] T1, T1': first layer

[0119] T2: Second layer

[0120] T3: The third layer

[0121] TD: Thickness direction

[0122] TR0, TR1, TR2, TR3, TR4: Groove

[0123] VO1, VO2, VO3, VO4: through hole opening

[0124] W1, W2, WT1, WT2, WV1, WV2: Top width

Claims

1. A semiconductor structure comprising: a semiconductor substrate including a plurality of semiconductor devices therein; a plurality of interconnect layers disposed on the semiconductor substrate and electrically coupled to the semiconductor device; a first connector disposed on the plurality of interconnect layers and extending to contact a first level of the plurality of interconnect layers; a second connector disposed above the plurality of interconnect layers and substantially flush with the first connector, the second connector extending further than the first connector to contact a second level of the plurality of interconnect layers between the first level of the plurality of interconnect layers and the semiconductor substrate, the first connector being wider than the second connector; as well as A semiconductor through-hole penetrates through the semiconductor substrate to contact any one of the plurality of interconnect layers, the semiconductor through-hole being electrically coupled to the semiconductor device of the semiconductor substrate through the plurality of interconnect layers, wherein a top surface of the semiconductor through-hole is located between a top surface of the semiconductor substrate and a top surface of the first level of the plurality of interconnect layers.

2. The semiconductor structure according to claim 1, further comprising: A contact pad is disposed on the first level of the plurality of interconnect layers and is electrically coupled to the semiconductor device of the semiconductor substrate through the plurality of interconnect layers.

3. The semiconductor structure according to claim 2, further comprising: A third connector, a top surface of the third connector is substantially flush with top surfaces of the first connector and the second connector, and the third connector extends to contact the contact pad. The semiconductor structure according to claim 3 , wherein the aspect ratio of the third connector is smaller than the aspect ratio of the second connector. The semiconductor structure according to claim 1 , wherein the aspect ratio of the second connecting member is in a range of 0.3 to 20.

6. The semiconductor structure according to claim 1, further comprising: A contact pad is electrically coupled to the plurality of semiconductor devices through the plurality of interconnect layers, wherein the contact pad is vertically disposed above a bottom surface of the first connector and the first level of the plurality of interconnect layers, and the bottom surface of the first connector is located between the contact pad and the first level of the plurality of interconnect layers. 7 . The semiconductor structure of claim 1 , wherein the semiconductor through via tapers from the plurality of interconnect layers to the semiconductor substrate.

8. A semiconductor structure comprising: A first semiconductor die comprising: a first semiconductor substrate, comprising a plurality of first semiconductor devices; a first joint connector and a second joint connector, wherein a ratio of height to width of the second joint connector is greater than a ratio of height to width of the first joint connector; a plurality of first interconnect layers disposed on the first semiconductor substrate and through which the first bonding connector and the second bonding connector are electrically coupled to the first semiconductor device; and a semiconductor through via extending from any one of the plurality of first interconnect layers to the first semiconductor substrate, wherein a top surface of the semiconductor through via is located between a bottom surface of the first bonding connector and a top surface of the first semiconductor substrate; and A second semiconductor die is stacked on and bonded to the first semiconductor die, the second semiconductor die comprising a third bonding connector bonded to the first bonding connector of the first semiconductor die and a fourth bonding connector bonded to the second bonding connector of the first semiconductor die, wherein a size of the third bonding connector and a size of the fourth bonding connector correspond to a size of the first bonding connector and a size of the second bonding connector, respectively. 9 . The semiconductor structure of claim 8 , wherein the first bonding connector of the first semiconductor die is substantially flush with the second bonding connector of the first semiconductor die at a bonding interface between the first semiconductor die and the second semiconductor die. 10 . The semiconductor structure of claim 9 , wherein the first bonding connector and the second bonding connector extend in a thickness direction of the first semiconductor die, the second bonding connector extending further from the bonding interface than the first bonding connector.

11. The semiconductor structure of claim 8, wherein the first bonding connector is disposed over the plurality of first interconnect layers and extends from a bonding interface between the first semiconductor die and the second semiconductor die to a first level of the plurality of first interconnect layers.

12. The semiconductor structure of claim 11, wherein the second bonding connector of the first semiconductor die is disposed over the plurality of first interconnect layers and extends from the bonding interface to a second level of the plurality of first interconnect layers between the first semiconductor substrate and the first level of the plurality of first interconnect layers.

13. The semiconductor structure of claim 11 , wherein the second semiconductor die further comprises: a second semiconductor substrate, comprising a plurality of second semiconductor devices therein; as well as a plurality of second interconnect layers disposed over the second semiconductor substrate and electrically coupled to the second semiconductor device, wherein the bonding interface between the first semiconductor die and the second semiconductor die is located between the second semiconductor substrate of the second semiconductor die and the first level of the plurality of first interconnect layers of the first semiconductor die.

14. The semiconductor structure of claim 13, wherein: the second semiconductor substrate of the second semiconductor die and the plurality of first interconnect layers of the first semiconductor die are located between the plurality of second interconnect layers of the second semiconductor die and the first semiconductor substrate of the first semiconductor die, and The third bonding connector and the fourth bonding connector of the second semiconductor die penetrate through the second semiconductor substrate to contact any one of the plurality of second interconnect layers.

15. The semiconductor structure of claim 8, wherein the first semiconductor die further comprises: A contact pad is disposed on the plurality of first interconnect layers, wherein the first bonding connector lands on a first level of the plurality of first interconnect layers, and a bottom surface of the first bonding connector is located between a top surface of the contact pad and a top surface of the first level of the plurality of first interconnect layers.

16. The semiconductor structure of claim 8, wherein the first semiconductor die further comprises: an external contact pad disposed on the first semiconductor substrate opposite the plurality of first interconnect layers and electrically coupled to the semiconductor through via; as well as An external terminal is disposed on the external contact pad and electrically coupled to the external contact pad.

17. A semiconductor structure comprising: A first semiconductor die comprising: a first semiconductor substrate, comprising a plurality of first semiconductor devices; a plurality of first interconnect layers stacked on the first semiconductor substrate and electrically coupled to the first semiconductor device; A first bonding connector and a second bonding connector are respectively disposed on a first level and a second level of the plurality of first interconnect layers, wherein the second level is between the first level and the first semiconductor substrate and the second bonding connector is narrower than the first bonding connector; and A second semiconductor die stacked on the first semiconductor die and comprising: a second semiconductor substrate including an active side, a back side opposite to the active side and facing the first semiconductor die, and a plurality of second semiconductor devices disposed on the active side; a plurality of second interconnect layers stacked on the second semiconductor substrate and electrically coupled to the second semiconductor device; and A first semiconductor through-via and a second semiconductor through-via extend from the plurality of second interconnect layers and through the second semiconductor substrate to the first semiconductor die, respectively, wherein a top surface of the second semiconductor through-via is between a top surface of the first semiconductor through-via and the active side of the second semiconductor substrate and a bottom surface of the second semiconductor through-via is bonded to the second bonding connector of the first semiconductor die.

18. The semiconductor structure of claim 17, wherein the first semiconductor die further comprises: a contact pad disposed on the first level of the plurality of first interconnect layers; as well as A third bonding connector includes a top surface bonded to the first semiconductor through-via of the second semiconductor die and a bottom surface landed on the contact pad, wherein the top surface of the third bonding connector is substantially flush with top surfaces of the first bonding connector and the second bonding connector. 19 . The semiconductor structure of claim 17 , wherein the first semiconductor through-via and the second semiconductor through-via are connected to a first level and a second level of the plurality of second interconnect layers, respectively, and the second level is between the first level and the second semiconductor substrate.

20. The semiconductor structure of claim 19, wherein: The first semiconductor die further includes a first bonding dielectric layer disposed on the plurality of first interconnect layers and laterally covering the first bonding connectors and the second bonding connectors; and The second semiconductor die also includes a second bonding dielectric layer disposed on the back side of the second semiconductor substrate and laterally covering the first semiconductor through-via and the second semiconductor through-via, and the second bonding dielectric layer is bonded to the first bonding dielectric layer.

21. A method for manufacturing a semiconductor structure, comprising: forming a first surface dielectric layer on the first interconnect structure over the first semiconductor substrate; forming a first through-hole opening and a second through-hole opening, wherein the second through-hole opening penetrates through the first surface dielectric layer and extends further than the first through-hole opening to expose at least a portion of the first interconnect structure in a touchable manner, and the second through-hole opening is narrower than the first through-hole opening; as well as Conductive material is formed in the first via opening and the second via opening to form a first bonding connector and a second bonding connector, respectively, wherein the second bonding connector extends further than the first bonding connector to contact the at least a portion of the first interconnect structure, and the first bonding connector is wider than the second bonding connector.

22. The manufacturing method according to claim 21, further comprising: A second surface dielectric layer, a third bonding connector and a fourth bonding connector are bonded to the first surface dielectric layer, the first bonding connector and the second bonding connector, respectively, wherein the size of the third bonding connector and the size of the fourth bonding connector correspond to the size of the first bonding connector and the size of the second bonding connector.

23. The method for manufacturing a semiconductor structure according to claim 21, wherein: A damascene process is performed to form the first via opening and the second via opening, wherein the second via opening has a greater aspect ratio than the first via opening.

24. The method for manufacturing a semiconductor structure according to claim 21, wherein before forming the first surface dielectric layer, the method further comprises: forming a portion of the first interconnect structure on the first semiconductor substrate; forming a semiconductor through via extending from the portion of the first interconnect structure to the first semiconductor substrate; as well as A remaining portion of the first interconnect structure is formed on the portion of the first interconnect structure and the semiconductor through via.

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