Pixel array substrate

Abstract

A pixel array substrate comprises a substrate, a plurality of data lines, a plurality of scan lines, a plurality of sub-pixels, and first and second auxiliary lines. The plurality of sub-pixels are arranged into a plurality of first rows arranged in a first direction and a plurality of second rows arranged in a second direction. The first auxiliary line and the plurality of scan lines belong to a first conductive layer. The second auxiliary line and the plurality of data lines belong to a second conductive layer. The first auxiliary line is located between two scan lines. The first end of the first auxiliary line is connected to one of the two scan lines. The second end of the first auxiliary line is separated from the other of the two scan lines. The second auxiliary line is electrically connected to the first auxiliary line at the second end through a conductive through hole.

Description

Technical Field

[0001] This invention relates to a pixel array substrate. Background Technology

[0002] To meet the diverse needs of electronic devices, it is sometimes necessary to connect horizontal scan lines via vertical auxiliary lines so that the gate drive circuit and data drive circuit are located on the same side of the display area. However, in such a design architecture, the pixel voltage of multiple sub-pixels adjacent to the auxiliary lines may be affected by coupling effects due to the opening or closing of the gate signal, causing variations in grayscale or brightness of the multiple sub-pixels and resulting in poor image quality. Summary of the Invention

[0003] The present invention provides a pixel array substrate that helps to improve the effect of coupling.

[0004] An embodiment of the present invention provides a pixel array substrate, comprising a substrate, a plurality of data lines, a plurality of scan lines, a plurality of sub-pixels, a first auxiliary line, and a second auxiliary line. The plurality of data lines are disposed on the substrate and arranged in a first direction. The plurality of scan lines are disposed on the substrate and arranged in a second direction, wherein the second direction intersects the first direction. The plurality of sub-pixels are disposed on the substrate and arranged in a plurality of first rows arranged in the first direction and a plurality of second rows arranged in the second direction. Each first row is electrically connected to at least one data line, and each second row is electrically connected to one scan line. The first auxiliary line is disposed on the substrate, wherein the first auxiliary line and the plurality of scan lines belong to a first conductive layer. The second auxiliary line is disposed on the substrate, wherein the second auxiliary line and the plurality of data lines belong to a second conductive layer. The first auxiliary line is located between two scan lines. The first auxiliary line has a first end and a second end opposite to the first end. The first end is connected to one of the two scan lines. The second end is separated from the other of the two scan lines. The second auxiliary line and the first auxiliary line are electrically connected at the second end through a conductive via.

[0005] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention. Attached Figure Description

[0006] Figure 1 This is a partial top view of a pixel array substrate according to an embodiment of the present invention.

[0007] Figure 2 yes Figure 1 A top-view schematic diagram of the central region R.

[0008] Figures 3 to 11 They are Figure 1 A top view of wiring units C2, C3, C4, C1, A, SS, SM, E, and A1.

[0009] Figure Labels

[0010] 1: Pixel array substrate

[0011] A, A1, C1, C2, C3, C4, E, SM, SS: Cabling Units

[0012] AL1: First Auxiliary Line

[0013] AL2: Second Auxiliary Line

[0014] AL3: Third Auxiliary Line

[0015] AL4: Fourth Auxiliary Line

[0016] AL5: Fifth Auxiliary Line

[0017] CH: Semiconductor layer

[0018] CL1, CL1A, CL1B: First common electrode line

[0019] CL2, CL2A, CL2B: Second common electrode wire

[0020] CL3: Third common electrode wire

[0021] CV1, CV2, CV3, CV4: Conductive through-holes

[0022] D1: First direction

[0023] D2: Second direction

[0024] D3: Normal direction

[0025] DE: Drain

[0026] DL: Data cable

[0027] DL1: First data line

[0028] DL2: Second data line

[0029] E1: First end

[0030] E2: Second end

[0031] GE: Gate

[0032] P1: Part 1

[0033] P2: Part Two

[0034] R1, R1-1 to R1-8: First row

[0035] R2, R2-1 to R2-12: Second row

[0036] SE: Source

[0037] SL: Scan line

[0038] SL1: First scan line

[0039] SL2: Second scan line

[0040] SP: Sub-Pixel

[0041] SP1: Active component

[0042] SP2: Pixel Electrode

[0043] SUB:Substrate

[0044] WAL1, WAL2, WAL3, WAL5: Line width Detailed Implementation

[0045] The structural and working principles of the present invention will be described in detail below with reference to the accompanying drawings:

[0046] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0047] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or an intermediate element may also be present. Conversely, when an element is referred to as being "directly on" or "directly connected" to another element, no intermediate element is present. As used herein, "connection" can refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" may involve the presence of other elements between the two elements.

[0048] As used herein, “about,” “approximately,” or “substantially” includes the value and the average value within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account the measurement under discussion and a particular number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0050] It should be understood that the figures in the accompanying drawings illustrate general features of the methods, structures, or materials used in specific embodiments. However, these figures should not be construed as defining or limiting the scope or nature covered by these embodiments. For example, for clarity, the relative dimensions, thicknesses, and locations of various films, regions, or structures may be reduced or enlarged, or some films or elements may be omitted from the drawing.

[0051] Figure 1 This is a partial top view of a pixel array substrate according to an embodiment of the present invention. Please refer to... Figure 1 The pixel array substrate 1 includes a substrate SUB, multiple sub-pixels SP, and multiple wiring units (such as wiring unit A, wiring unit A1, wiring unit C1, wiring unit C2, wiring unit C3, wiring unit C4, wiring unit E, wiring unit SS, and wiring unit SM).

[0052] The substrate SUB is mainly used to carry the film layers or components in the pixel array substrate 1. For example, the substrate SUB can be made of glass, quartz, organic polymers, such as wafers, ceramics, or other suitable materials.

[0053] Multiple subpixels SP are disposed on a substrate SUB. The multiple subpixels SP are arranged in multiple first rows R1 arranged in a first direction D1 and multiple second rows R2 arranged in a second direction D2. The second direction D2 intersects the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1, but is not limited thereto. Figure 1 The diagram schematically illustrates eight first rows R1 (e.g., R1-1 to R1-8) and twelve second rows R2 (e.g., R2-1 to R2-12), where each first row R1 contains twelve subpixels SP and each second row R2 contains eight subpixels SP. However, the number of subpixels SP and their arrangement can be changed as needed.

[0054] Multiple subpixels SP may include subpixels of various colors, such as multiple red subpixels, multiple green subpixels, and multiple blue subpixels, but are not limited to these. Multiple (e.g., twelve) subpixels SP in each first row R1 may have the same color, and multiple (e.g., eight) subpixels SP in each second row R2 may include subpixels of various colors arranged alternately in the first direction D1. However, the color types and arrangement of the multiple subpixels SP can be changed as needed.

[0055] Multiple wiring units are disposed on the substrate SUB and correspond to multiple sub-pixels SP. For example, the multiple wiring units and multiple sub-pixels SP can be arranged alternately in the first direction D1. The multiple wiring units may include various types of lines, such as auxiliary lines for transmitting gate signals, lines for voltage regulation, repair lines, or other lines. Depending on the wiring structure (such as the relative arrangement relationship of lines, connection relationship, or other structural design), the lines located around the multiple sub-pixels SP can be divided into various wiring units. Figure 1 Nine wiring units are schematically illustrated, such as wiring unit A, wiring unit A1, wiring unit C1, wiring unit C2, wiring unit C3, wiring unit C4, wiring unit E, wiring unit SS, and wiring unit SM. However, the types of wiring units in the pixel array substrate 1 can be increased or decreased as needed.

[0056] The relative arrangement and detailed structure between multiple wiring units and multiple sub-pixels (SPs) can be found in [reference]. Figures 2 to 11 . Figure 2 yes Figure 1 A top-view schematic diagram of the central region R. Figures 3 to 11 They are Figure 1 Top view of wiring units C2, C3, C4, C1, A, SS, SM, E, and A1. For ease of understanding, Figures 3 to 11 The two sub-pixels SP on the left and right sides of the wiring unit are also shown.

[0057] The following combinations Figures 2 to 11 This describes one embodiment of the pixel array substrate 1. In this embodiment, the pixel array substrate 1 includes a circuit structure (including a sub-pixel structure and a wiring structure) suitable for a two data lines and half gate line (2DHG) driving mode. However, it should be understood that the circuit structure of the pixel array substrate 1 can also be adapted to other driving modes, such as a one data lines and one gate line (1D1G) driving mode, with some adjustments, but is not limited thereto.

[0058] Please refer to the following: Figure 1 and Figure 2In addition to the substrate SUB, multiple sub-pixels SP, and multiple wiring units, the pixel array substrate 1 may further include multiple data lines DL, multiple scan lines SL, a first auxiliary line AL1, and a second auxiliary line AL2.

[0059] Multiple data lines DL and multiple scan lines SL are disposed on the substrate SUB, wherein the multiple data lines DL are arranged in the first direction D1 and the multiple scan lines SL are arranged in the second direction D2.

[0060] Multiple data lines DL and multiple scan lines SL belong to different conductive layers, and the multiple data lines DL and multiple scan lines SL can be separated by at least one insulating layer. For example, the multiple scan lines SL belong to a first conductive layer, while the multiple data lines DL belong to a second conductive layer.

[0061] For conductivity considerations, multiple data lines (DL) and multiple scan lines (SL) can be made of metallic materials. However, other conductive materials can also be used for multiple data lines (DL) and multiple scan lines (SL), such as alloys, nitrides of metallic materials, oxides of metallic materials, oxynitrides of metallic materials, or stacked layers of metallic materials and other conductive materials.

[0062] Each sub-pixel SP may include one or more active elements SP1 and one or more pixel electrodes SP2. Figures 2 to 11 The illustration schematically shows that each subpixel SP includes an active element SP1 and a pixel electrode SP2. However, the number of active elements SP1, the number of pixel electrodes SP2, or the relative arrangement of active elements SP1 and pixel electrodes SP2 included in the subpixel SP are not limited to this.

[0063] Taking thin-film transistors as an example, such as Figures 3 to 11 As shown, the active element SP1 may include a gate GE, a gate insulating layer (not shown), a semiconductor layer CH, an insulating layer (not shown), a source SE, and a drain DE. The gate GE is disposed on the substrate SUB and, for example, belongs to a first conductive layer. The gate insulating layer is disposed on the substrate SUB and covers the gate GE. The semiconductor layer CH is disposed on the gate insulating layer and located above the gate GE. The source SE and drain DE are disposed on the semiconductor layer CH and, for example, belong to a second conductive layer. The insulating layer covers the gate insulating layer, the semiconductor layer CH, and the second conductive layer. The pixel electrode SP2 is disposed on the insulating layer and, for example, belongs to a third conductive layer. The pixel electrode SP2 can be electrically connected to the drain DE through a conductive via CV1 located in the insulating layer. The third conductive layer is, for example, a transparent conductive layer. The material of the transparent conductive layer may include metal oxides, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stack of at least two of the above, but is not limited thereto.

[0064] Please refer to Figure 2 Each sub-pixel SP has its active element SP1 and pixel electrode SP2 arranged, for example, in the second direction D2. Furthermore, each first row R1 includes multiple sub-pixels SP arranged in the second direction D2. Each first row R1 is electrically connected to at least one data line DL. In other words, each first row R1 may be electrically connected to one data line DL, or each first row R1 may be electrically connected to multiple data lines DL (such as two data lines DL located on opposite sides of the first row R1). The electrical connection of the first row R1 to the data line DL means that multiple sources SE of the multiple sub-pixels SP in the first row R1 are electrically connected to the data line DL.

[0065] Additionally, each second row R2 includes a plurality of sub-pixels SP arranged in the first direction D1. Each second row R2 is electrically connected to a scan line SL. The electrical connection of the second row R2 to the scan line SL means that the gates GE of the plurality of sub-pixels SP located in the second row R2 are electrically connected to the scan line SL.

[0066] Taking the 2DHG driving mode (i.e., multiple active elements SP1 in two adjacent second rows R2 are simultaneously turned on and data signals are sequentially output to multiple first rows R1) as an example, such as Figure 2 As shown, multiple scan lines SL may include multiple first scan lines SL1 and multiple second scan lines SL2. The multiple first scan lines SL1 and multiple second scan lines SL2 are alternately arranged in the second direction D2 and electrically connected to multiple second rows R2 respectively. Each first scan line SL1 and its corresponding second scan line SL2 receive a scan signal at the same timing, causing multiple active elements SP1 in two adjacent second rows R2 to be simultaneously activated. Multiple data lines DL may include multiple first data lines DL1 and multiple second data lines DL2. The multiple first data lines DL1 and multiple second data lines DL2 are alternately arranged in the first direction D1, wherein there is one first data line DL1 and one second data line DL2 between any two adjacent first rows R1. A portion of the sub-pixels SP in each first row R1 are electrically connected to an adjacent first data line DL1, and another portion of the sub-pixels SP in each first row R1 are electrically connected to an adjacent second data line DL2.

[0067] by Figure 1 and Figure 2For example, the pixel array substrate 1 may include at least eight first rows R1 (such as first rows R1-1 to first rows R1-8), and each first row R1 includes at least 12 sub-pixels SP arranged from top to bottom (i.e., arranged in the opposite direction of the second direction D2). In the first row R1-1, first row R1-2, first row R1-5, or first row R1-6, the 9th and 12th sub-pixels SP are electrically connected to the adjacent first data line DL1, and the 10th and 11th sub-pixels SP are electrically connected to the adjacent second data line DL2. On the other hand, in the first row R1-3, first row R1-4, first row R1-7, or first row R1-8, the 9th and 12th sub-pixels SP are electrically connected to the adjacent second data line DL2, and the 10th and 11th sub-pixels SP are electrically connected to the adjacent first data line DL1.

[0068] A first auxiliary line AL1 and a second auxiliary line AL2 are disposed on the substrate SUB. The first auxiliary line AL1 and multiple scan lines SL belong to the first conductive layer, while the second auxiliary line AL2 and multiple data lines DL belong to the second conductive layer.

[0069] The first auxiliary line AL1 is positioned between two adjacent first rows R1 (such as first row R1-4 and first row R1-5), and the first auxiliary line AL1 can be located between two scan lines SL in the second direction D2. The two scan lines SL can be adjacent scan lines SL, or there can be other scan lines SL between the two scan lines SL. Figure 11 As shown, the first auxiliary line AL1 may be located between two adjacent first scan lines SL1, and there is, for example, a second scan line SL2 between the two adjacent first scan lines SL1.

[0070] The first auxiliary line AL1 has a first end E1 and a second end E2 opposite to the first end E1. The first end E1 is connected (or in contact) with one of the two scan lines SL (such as the two first scan lines SL1). The second end E2 is disconnected (i.e., not connected) from the other of the two scan lines SL (such as the two first scan lines SL1). In other words, the two scan lines SL are not connected or electrically connected by the first auxiliary line AL1.

[0071] The second auxiliary line AL2 is also located between the first row R1-4 and the first row R1-5. In some embodiments, the second auxiliary line AL2 may overlap the first auxiliary line AL1 in the normal direction D3 of the substrate SUB to reduce the spacing between the first row R1-4 and the first row R1-5, but is not limited thereto.

[0072] The second auxiliary line AL2 is electrically connected to the first auxiliary line AL1 at the second end E2 via a conductive via CV2. In some embodiments, the second auxiliary line AL2 may include a first portion P1 and a second portion P2. The first portion P1 and the second portion P2 are arranged in the second direction D2. The first portion P1 is connected to the gate signal terminal, for example, and extends from the gate signal terminal toward the second end E2, crossing the scan line SL (such as the first scan line SL1) that is separated from the first auxiliary line AL1 and located on opposite sides of the first auxiliary line AL1. The first portion P1 is electrically connected to the first auxiliary line AL1 at the second end E2 via a conductive via CV2. The second portion P2 is separated from the first portion P1 at the second end E2. In other words, the second portion P2 is not connected or electrically connected to the first portion P1. The second part P2 may overlap the first auxiliary line AL1 in the normal direction D3 of the substrate SUB and cross the scan line SL (such as the first scan line SL1) connected to the first auxiliary line AL1, and the second part P2 is electrically insulated from the first auxiliary line AL1 and the scan line SL (such as the first scan line SL1) connected to the first auxiliary line AL1.

[0073] With the above design, the gate signal is sequentially transmitted to the corresponding scan line SL via the first portion P1 of the second auxiliary line AL2 and the first auxiliary line AL1. Since the first auxiliary line AL1 terminates at the corresponding scan line SL and does not need to extend further to the two adjacent sub-pixels SP (such as the two sub-pixels SP located on opposite sides of the wiring unit C4) electrically connected to the corresponding scan line SL, grayscale or brightness variations caused by the coupling effect of the horizontal scan line SL (such as the first scan line SL1) and the vertical auxiliary line (first auxiliary line AL1) on the two sub-pixels SP located on opposite sides of the wiring unit C4 can be avoided.

[0074] Furthermore, during the transmission of the gate signal to the corresponding scan line SL, the gate signal is transmitted at the second terminal E2 to the first auxiliary line AL1 located in the first conductive layer. During the transmission of the gate signal by the first auxiliary line AL1, the second portion P2 of the second auxiliary line AL2, disposed above the first auxiliary line AL1, can shield the first auxiliary line AL1, thereby helping to reduce the capacitive coupling effect on multiple sub-pixels SP adjacent to the first auxiliary line AL1 (such as two sub-pixels SP located on opposite sides of wiring unit C2 and two sub-pixels SP located on opposite sides of wiring unit C3). In some embodiments, such as... Figure 3 and Figure 4As shown, within the overlap area between the second portion P2 of the second auxiliary line AL2 and the first auxiliary line AL1, the linewidth WAL2 of the second portion P2 can be greater than or equal to the linewidth WAL1 of the first auxiliary line AL1 to further enhance the shielding effect. In this document, the linewidth of a component refers to the maximum width of the component perpendicular to its extension direction. In some embodiments, the second portion P2 can be connected to a DC signal terminal (not shown) to provide a voltage regulation effect. In other embodiments, the potential of the second portion P2 can be floating.

[0075] It should be understood that, although Figure 2 A first auxiliary line AL1 and a second auxiliary line AL2 are schematically illustrated, but the pixel array substrate 1 may include multiple first auxiliary lines AL1 and multiple second auxiliary lines AL2. The multiple first auxiliary lines AL1 may be connected to multiple scan lines SL (such as multiple first scan lines SL1), and the multiple second auxiliary lines AL2 may be set corresponding to the multiple first auxiliary lines AL1.

[0076] Depending on the specific requirements, the pixel array substrate 1 may also include other components or films. For example... Figure 2 As shown, the pixel array substrate 1 may further include multiple first common electrode lines CL1, multiple second common electrode lines CL2, and multiple third common electrode lines CL3. The multiple first common electrode lines CL1, multiple second common electrode lines CL2, and multiple third common electrode lines CL3 are disposed on the substrate SUB and, for example, belong to the first conductive layer.

[0077] Multiple first common electrode lines CL1 and multiple second common electrode lines CL2 are arranged alternately in the second direction D2, wherein there is a first common electrode line CL1 and a second common electrode line CL2 between any two adjacent scan lines SL (such as a first scan line SL1 and an adjacent second scan line SL2). Each third common electrode line CL3 is connected between a first common electrode line CL1 and an adjacent second common electrode line CL2 (see wiring unit C4 and wiring unit SM). In other words, a first common electrode line CL1 and an adjacent second common electrode line CL2 are electrically connected through a third common electrode line CL3.

[0078] In some embodiments, there may be at least one first common electrode line CL1 and at least one second common electrode line CL2 between the two scan lines SL located at opposite ends of the first auxiliary line AL1. Figure 2The diagram schematically illustrates two first common electrode lines CL1 (e.g., first common electrode line CL1A), two second common electrode lines CL2 (e.g., second common electrode line CL2A), and one second scan line SL2 located at opposite ends of the first auxiliary line AL1. Since the first auxiliary line AL1, the first common electrode lines CL1A, CL2A, and SL2 belong to the same conductive layer (first conductive layer), each of the two first common electrode lines CL1A, the two second common electrode lines CL2A, and the second scan line SL2 must be disconnected at the point where the first auxiliary line AL1 passes (see wiring unit C2 and wiring unit C3) to avoid short-circuiting with the first auxiliary line AL1. Each disconnected first common electrode line CL1 and each disconnected second common electrode line CL2 can be electrically connected via multiple third common electrode lines CL3 (see wiring unit SM), and the disconnected second scan line SL2 can be electrically connected to a corresponding first scan line SL1 via multiple auxiliary lines (not shown). In some embodiments, the first auxiliary line AL1 may have at least one third common electrode line CL3 on each of its opposite sides in the first direction D1, so as to electrically connect the disconnected first common electrode line CL1 and the disconnected second common electrode line CL2.

[0079] In some embodiments, the pixel array substrate 1 may further include a plurality of third auxiliary lines AL3. The plurality of third auxiliary lines AL3 are disposed on the substrate SUB and, for example, belong to the second conductive layer.

[0080] The third auxiliary line AL3 can be used for voltage stabilization or repair, but is not limited thereto. Each third auxiliary line AL3 extends, for example, in the second direction D2, and at least one third auxiliary line AL3 is located between two adjacent first rows R1. Figure 2 As shown, each third auxiliary line AL3 can cross multiple scan lines SL and is electrically insulated from the multiple scan lines SL.

[0081] In some embodiments, each third common electrode line CL3 may overlap with a third auxiliary line AL3 in the normal direction D3 of the substrate SUB (see wiring unit SM). Furthermore, the number of third common electrode lines CL3 overlapping with the third auxiliary line AL3 may be greater than or equal to one. This wire stacking design reduces the spacing between two adjacent first rows R1, thereby contributing to miniaturization or improved resolution.

[0082] In some embodiments, at least one of the plurality of third common electrode lines CL3 may be electrically connected to a third auxiliary line AL3 (see wiring unit SM) that overlaps with it to reduce the conductor resistance. For example, the third common electrode line CL3 may be electrically connected to the third auxiliary line AL3 through a conductive via CV3. Figure 2The schematic diagram shows that each of the two third auxiliary lines AL3 located on opposite sides of the second auxiliary line AL2 overlaps with multiple (such as two) third common electrode lines CL3 in the normal direction D3 of the substrate SUB and is electrically connected to the multiple third common electrode lines CL3, but the present invention is not limited thereto.

[0083] In some embodiments, the pixel array substrate 1 may further include a plurality of fourth auxiliary lines AL4 (see wiring unit SS, wiring unit A and wiring unit A1). The plurality of fourth auxiliary lines AL4 are disposed on the substrate SUB and, for example, belong to the first conductive layer.

[0084] Each fourth auxiliary line AL4 is located in the second direction D2 between a first common electrode line CL1 and an adjacent second common electrode line CL2, and is separated from both the first common electrode line CL1 and the adjacent second common electrode line CL2. In other words, the fourth auxiliary line AL4 does not contact the first common electrode line CL1 or the second common electrode line CL2.

[0085] The fourth auxiliary line AL4 is used, for example, to reduce the resistance of the conductor. In some embodiments, at least one of the plurality of third auxiliary lines AL3 overlaps the plurality of fourth auxiliary lines AL4 in the normal direction D3 and is electrically connected to the plurality of fourth auxiliary lines AL4 (see wiring units SS, A, and A1). For example, the third auxiliary line AL3 can be electrically connected to the fourth auxiliary line AL4 through a conductive via CV4.

[0086] In some embodiments, the second auxiliary line AL2 overlaps with a plurality of fourth auxiliary lines AL4 (see wiring unit A) in the normal direction D3 and is electrically connected to the plurality of fourth auxiliary lines AL4.

[0087] In some embodiments, the pixel array substrate 1 may further include a fifth auxiliary line AL5 (see wiring unit E). The fifth auxiliary line AL5 is disposed on the substrate SUB and, for example, belongs to the first conductive layer. Figure 2 Two fifth auxiliary lines AL5 are schematically shown, but the number of fifth auxiliary lines AL5 included in the pixel array substrate 1 can be changed as needed.

[0088] The fifth auxiliary line AL5 is used, for example, to connect two adjacent scan lines SL (such as a first scan line SL1 and an adjacent second scan line SL2) to achieve a 2DHG driving mode. Figure 2As shown, the fifth auxiliary line AL5 is located, for example, between two adjacent first rows R1 in the first direction D1 (such as between first rows R1-1 and R1-2, and between first rows R1-7 and R1-8). Furthermore, the fifth auxiliary line AL5 and the first auxiliary line AL1 are respectively located on opposite sides of a first scan line SL1 electrically connected to the first auxiliary line AL1 in the second direction D2, and the fifth auxiliary line AL5 connects the first scan line SL1 electrically connected to the first auxiliary line AL1 to an adjacent second scan line SL2 (see wiring unit E and wiring unit A1).

[0089] In some embodiments, the fifth auxiliary line AL5 may overlap with the third auxiliary line AL3 in the normal direction D3 of the substrate SUB. During the transmission of the gate signal via the fifth auxiliary line AL5, the third auxiliary line AL3 positioned above the fifth auxiliary line AL5 can shield the fifth auxiliary line AL5, thereby helping to reduce the capacitive coupling effect on multiple sub-pixels SP adjacent to the fifth auxiliary line AL5 (such as two sub-pixels SP located on opposite sides of the wiring unit E). In some embodiments, such as Figure 10 As shown, the line width WAL3 of the third auxiliary line AL3 can be greater than or equal to the line width WAL5 of the fifth auxiliary line AL5 to further improve the shielding effect.

[0090] Refer to Figure 2 Between the first scan line SL1 and the second scan line SL2, which are connected by the fifth auxiliary line AL5, there is a first common electrode line CL1 (such as the first common electrode line CL1B) and a second common electrode line CL2 (such as the second common electrode line CL2B). Since the fifth auxiliary line AL5, the first common electrode line CL1B, and the second common electrode line CL2B belong to the same conductive layer (such as the first conductive layer), the first common electrode line CL1B and the second common electrode line CL2B must be disconnected at the point where the fifth auxiliary line AL5 passes to avoid short-circuiting with the fifth auxiliary line AL5. In some embodiments, the disconnected first common electrode line CL1B and the disconnected second common electrode line CL2B can be electrically connected through at least one third common electrode line CL3 (see wiring unit C4). In some embodiments, the at least one third common electrode line CL3 can overlap the second auxiliary line AL2 in the normal direction D3 of the substrate SUB and be electrically insulated from the second auxiliary line AL2.

[0091] Depend on Figure 1 and Figure 2 It can be seen that the multiple wiring units between the first row R1-4 where the first auxiliary line AL1 and the second auxiliary line AL2 are located, and the adjacent first row R1-5, include, for example, more than four wiring structures. Figure 1 and Figure 2In this embodiment, the multiple wiring units between the first row R1-4 containing the first auxiliary line AL1 and the second auxiliary line AL2, and the adjacent first row R1-5, include, for example, five wiring structures A, C1, C2, C3, and C4. However, in other embodiments, the types of wiring units between the first row R1-4 containing the first auxiliary line AL1 and the second auxiliary line AL2, and the adjacent first row R1-5, can be changed according to actual needs (such as the driving method). Furthermore, the types of wiring units included in the pixel array substrate can also be changed according to actual needs (such as the driving method).

[0092] For example, in a 1D1G driving mode with one data line and one gate line, multiple active elements SP1 located in the same first row R1 can be electrically connected to the same data line DL. Furthermore, the two scan lines SL located at opposite ends of the first auxiliary line AL1 can be adjacent scan lines SL, meaning there are no other scan lines SL between them. Therefore, the wiring unit C3 can be omitted from the pixel array substrate. Additionally, the number of first common electrode lines CL1 and second common electrode lines CL2 between the two scan lines SL located at opposite ends of the first auxiliary line AL1 can both be one, and both the first common electrode line CL1 and the second common electrode line CL2 are disconnected at the point where the first auxiliary line AL1 passes. Moreover, in the 1D1G driving mode, the fifth auxiliary line can be omitted from the pixel array substrate, therefore, wiring units E and A1 can be omitted from the pixel array substrate.

[0093] Furthermore, the pixel array substrate described herein can be applied, for example, to a display device (not shown). In addition to the pixel array substrate, the display device may further include a counter substrate, a display medium located between the counter substrate and the pixel array substrate 1, and a driving element for driving the pixel array substrate 1. For example, the driving element may include a chip. The chip may be bonded to the pixel array substrate 1 by a chip-on-film (COF) process, a chip-on-glass (COG) process, a tape-automated bonding (TAB) process, or other methods.

[0094] In summary, in the embodiments of the present invention, since the first auxiliary line terminates at a corresponding scan line and does not need to extend further to the two adjacent sub-pixels electrically connected to the corresponding scan line, grayscale or brightness variations caused by the coupling effect of the horizontal scan line and the vertical auxiliary line can be avoided. Furthermore, during the transmission of the gate signal to the corresponding scan line, the gate signal is transmitted at the second end to the first auxiliary line located in the first conductive layer. During the transmission of the gate signal to the first auxiliary line, the second portion of the second auxiliary line disposed above the first auxiliary line can shield the first auxiliary line, thereby helping to reduce the capacitive coupling effect on multiple sub-pixels adjacent to the first auxiliary line.

[0095] In some embodiments, within the overlap range between the second portion of the second auxiliary line and the first auxiliary line, the linewidth of the second portion of the second auxiliary line may be greater than or equal to the linewidth of the first auxiliary line to further enhance the shielding effect. In some embodiments, the second portion may be connected to a DC signal terminal, for example, to provide a voltage stabilization effect. In other embodiments, the potential of the second portion may be floating. In some embodiments, the disconnected first common electrode line and the disconnected second common electrode line may be electrically connected by multiple third common electrode lines. In some embodiments, the third common electrode line and the third auxiliary line may be designed to overlap to facilitate miniaturization or improve resolution. In some embodiments, the third common electrode line may be electrically connected to the third auxiliary line it overlaps with to reduce the conductor resistance. In some embodiments, the conductor resistance may be reduced by a design in which the third auxiliary line overlaps and is electrically connected to the fourth auxiliary line.

[0096] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A pixel array substrate, characterized in that: include: substrate; A plurality of data lines are disposed on the substrate and arranged in a first direction; a plurality of scanning lines disposed on the substrate and arranged in a second direction, wherein the second direction intersects the first direction; a plurality of sub-pixels, disposed on the substrate and arranged in a plurality of first rows arranged in the first direction and a plurality of second rows arranged in the second direction, wherein each of the first rows is electrically connected to at least one of the data lines, and each of the second rows is electrically connected to one of the scan lines; A first auxiliary line is disposed on the substrate, wherein the first auxiliary line and the plurality of scanning lines belong to a first conductive layer; and a second auxiliary line, disposed on the substrate, wherein the second auxiliary line and the plurality of data lines belong to the second conductive layer, The first auxiliary line is located between the two scanning lines, and when there are other scanning lines between the two scanning lines, the other scanning lines are disconnected at the point where the first auxiliary line passes; The first auxiliary line has a first end and a second end opposite to the first end, the first end is connected to one of the two scan lines, the second end is separated from the other of the two scan lines, and the second auxiliary line is electrically connected to the first auxiliary line at the second end through a conductive through hole.

2. The pixel array substrate according to claim 1, wherein: The second auxiliary line includes a first portion and a second portion, the first portion and the second portion are arranged in the second direction, the first portion crosses the scan line separated from the first auxiliary line among the two scan lines, and is electrically connected to the first auxiliary line through the conductive through hole at the second end, the second portion is separated from the first portion at the second end, the second portion overlaps the first auxiliary line in the normal direction of the substrate and crosses the one scan line connected to the first auxiliary line, and the second portion is electrically insulated from the first auxiliary line and the one scan line connected to the first auxiliary line.

3. The pixel array substrate according to claim 2, wherein: The line width of the second portion is greater than or equal to the line width of the first auxiliary line outside the second end.

4. The pixel array substrate according to claim 2, wherein: The first part is connected to the gate signal terminal, and the second part is connected to the DC signal terminal.

5. The pixel array substrate according to claim 1, wherein: Also includes: A plurality of first common electrode lines and a plurality of second common electrode lines are disposed on the substrate and arranged alternately in the second direction, wherein there is one first common electrode line and one second common electrode line between any two adjacent scanning lines; as well as A plurality of third common electrode lines are arranged on the substrate, wherein each of the third common electrode lines is connected between one of the first common electrode lines and an adjacent one of the second common electrode lines, wherein the plurality of first common electrode lines, the plurality of second common electrode lines and the plurality of third common electrode lines belong to the first conductive layer, and There is at least one first common electrode line and at least one second common electrode line between the two scanning lines located at opposite ends of the first auxiliary line, each of the at least one first common electrode line and the at least one second common electrode line is disconnected where the first auxiliary line passes, and the disconnected at least one first common electrode line and the disconnected at least one second common electrode line are electrically connected through the plurality of third common electrode lines.

6. The pixel array substrate according to claim 5, characterized in that: There is at least one third common electrode line on each of two opposite sides of the first auxiliary line in the first direction.

7. The pixel array substrate according to claim 5, wherein: The second auxiliary line overlaps with at least one of the third common electrode lines in the normal direction of the substrate, and is electrically insulated from at least one of the third common electrode lines.

8. The pixel array substrate according to claim 5, wherein: Also includes: A plurality of third auxiliary lines are arranged on the substrate, wherein at least one of the third auxiliary lines is located between two adjacent first rows, and each of the third auxiliary lines crosses the plurality of scan lines and is electrically insulated from the plurality of scan lines.

9. The pixel array substrate according to claim 8, wherein: The plurality of third auxiliary lines belong to the second conductive layer.

10. The pixel array substrate according to claim 8, wherein: Each of the third common electrode lines overlaps with one of the third auxiliary lines in the normal direction of the substrate, and at least one of the plurality of third common electrode lines is electrically connected to the third auxiliary line overlapping with the third common electrode line.

11. The pixel array substrate according to claim 8, wherein: At least one of the third auxiliary lines adjacent to the second auxiliary line overlaps with the plurality of third common electrode lines in the normal direction of the substrate and is electrically connected to the plurality of third common electrode lines.

12. The pixel array substrate according to claim 8, wherein: Also includes: A plurality of fourth auxiliary lines are arranged on the substrate, wherein each of the fourth auxiliary lines is located between one of the first common electrode lines and an adjacent one of the second common electrode lines, and is separated from the one of the first common electrode lines and the adjacent one of the second common electrode lines.

13. The pixel array substrate according to claim 12, wherein: The plurality of fourth auxiliary lines belong to the first conductive layer.

14. The pixel array substrate according to claim 12, wherein: At least one of the plurality of third auxiliary lines overlaps with the plurality of fourth auxiliary lines in the normal direction of the substrate and is electrically connected to the plurality of fourth auxiliary lines.

15. The pixel array substrate according to claim 12, wherein: The second auxiliary line overlaps with the plurality of fourth auxiliary lines in the normal direction of the substrate and is electrically connected to the plurality of fourth auxiliary lines.

16. The pixel array substrate according to claim 1, wherein: The plurality of scan lines include a plurality of first scan lines and a plurality of second scan lines, the plurality of first scan lines and the plurality of second scan lines are alternately arranged in the second direction and are electrically connected to the plurality of second rows respectively, the plurality of data lines include a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines are alternately arranged in the first direction, there is one first data line and one second data line between any two adjacent first rows, a portion of sub-pixels in each of the first rows are electrically connected to an adjacent first data line, and another portion of sub-pixels in each of the first rows are electrically connected to an adjacent second data line.

17. The pixel array substrate according to claim 16, wherein: The first auxiliary line is located between two adjacent first scan lines, the first end of the first auxiliary line is connected to one of the two adjacent first scan lines, the second end of the first auxiliary line is separated from the other of the two adjacent first scan lines, there is one second scan line between the two adjacent first scan lines, and the one second scan line is disconnected at the point where the first auxiliary line passes.

18. The pixel array substrate according to claim 17, wherein: Also includes: A fifth auxiliary line is arranged on the substrate and located between two adjacent first rows, wherein the fifth auxiliary line and the first auxiliary line are respectively located on opposite sides of the first scanning line electrically connected to the first auxiliary line in the second direction, and the fifth auxiliary line connects the first scanning line electrically connected to the first auxiliary line with an adjacent second scanning line.

19. The pixel array substrate according to claim 18, wherein: The fifth auxiliary line belongs to the first conductive layer.

20. The pixel array substrate according to claim 1, wherein: Also includes: A plurality of wiring units are arranged corresponding to the plurality of sub-pixels, wherein the plurality of wiring units between two adjacent first rows where the first auxiliary lines and the second auxiliary lines are located include more than four wiring structures.

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