Display device

Abstract

Disclosed is a display device including: a substrate including first regions and second regions arranged alternately in a plan view in a first direction; first electrodes and second electrodes located on the substrate and spaced apart from each other in a second direction intersecting the first direction; a first insulating layer located on the substrate and covering the first electrodes and the second electrodes; and light emitting elements located on the first insulating layer and electrically connected to the first electrodes and the second electrodes, the first insulating layer having a first thickness in the first regions and a second thickness thicker than the first thickness in the second regions, and the light emitting elements being located in the first regions.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0103055, filed on August 22, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to display devices. Background Technology

[0004] Display devices display images by using light-emitting elements (such as light-emitting diodes) as the light source for pixels. Light-emitting diodes exhibit relatively good durability even under harsh environmental conditions and demonstrate good performance in terms of lifespan and brightness.

[0005] Recently, research has been conducted on fabricating light-emitting diodes (LEDs) using materials with highly reliable inorganic crystal structures and placing them on the panels of display devices as next-generation pixel light sources. As part of this research, light-emitting display devices using LEDs as small as micrometers or nanometers and employing these LEDs as the light source for each pixel have been developed. Summary of the Invention

[0006] According to one aspect of an embodiment of the present invention, a display device including a light-emitting element is provided. According to another aspect of an embodiment of the present invention, a display device having a light-emitting element with improved alignment is provided.

[0007] According to another aspect of the embodiments of the present invention, a display device is provided in which manufacturing costs and manufacturing time are reduced by forming an insulating layer disposed below a light-emitting element and a dam pattern surrounding the light-emitting element in parallel (e.g., simultaneously).

[0008] However, the present invention is not limited to the aspects mentioned above, and other technical aspects not mentioned can be clearly understood by those skilled in the art from the following description.

[0009] According to one or more embodiments of the present invention, a display device includes: a substrate including a first region and a second region alternately arranged in a first direction in a plan view; a first electrode and a second electrode located on the substrate and spaced apart from each other in a second direction intersecting the first direction; a first insulating layer located on the substrate and covering the first electrode and the second electrode; and a light-emitting element located on the first insulating layer and electrically connected to the first electrode and the second electrode, the first insulating layer having a first thickness in the first region and a second thickness in the second region that is thicker than the first thickness, and the light-emitting element being located in the first region.

[0010] The substrate can further include a bank region located around the first and second regions, and the display device can further include a bank pattern located on the substrate and in the bank region.

[0011] The bank pattern can be integrally formed with the first insulating layer.

[0012] The bank pattern can have a third thickness thicker than each of the first and second thicknesses.

[0013] The display device can further include a third electrode located on the light emitting element and electrically connected to the first end portion of the light emitting element and the first electrode, and a fourth electrode located on the light emitting element and electrically connected to the second end portion of the light emitting element and the second electrode.

[0014] The substrate can further include a contact region, and the first insulating layer can expose at least a portion of the first electrode and at least a portion of the second electrode in the contact region.

[0015] In the contact region, the first electrode can contact the third electrode, and the second electrode can contact the fourth electrode.

[0016] The display device can further include a first bank layer located between the substrate and the first electrode and a second bank layer located between the substrate and the second electrode, wherein each of a thickness of the first bank layer and a thickness of the second bank layer is thicker than the second thickness of the first insulating layer.

[0017] The display device can further include a second insulating layer located on the substrate and covering the first insulating layer, the light emitting element, the third electrode, and the fourth electrode.

[0018] The first and second regions can extend in the second direction.

[0019] The first regions can be spaced apart from each other in the first direction, and the second region can surround the first regions.

[0020] The first insulating layer can have a fourth thickness on the first and second electrodes, and the fourth thickness can be thicker than the first thickness.

[0021] According to one or more embodiments of the present disclosure, a display device includes a substrate, first and second electrodes located on the substrate and spaced apart from each other in a first direction, a first insulating layer located on the substrate and covering the first and second electrodes, a light emitting element located on the first insulating layer and electrically connected to the first and second electrodes, and a bank pattern located on the substrate and disposed around the light emitting element, wherein the first insulating layer is integrally formed with the bank pattern.

[0022] The display device can further include a third electrode on the light emitting element and electrically connected to the first end portion of the light emitting element and the first electrode, and a fourth electrode on the light emitting element and electrically connected to the second end portion of the light emitting element and the second electrode.

[0023] The substrate can further include a contact area, and the first insulating layer can expose at least a portion of the first electrode and at least a portion of the second electrode in the contact area.

[0024] In the contact area, the first electrode can contact the third electrode, and the second electrode can contact the fourth electrode.

[0025] The display device can further include a first bank layer between the substrate and the first electrode and a second bank layer between the substrate and the second electrode, wherein each of a thickness of the first bank layer and a thickness of the second bank layer is thinner than a thickness of the bank pattern.

[0026] The display device can further include a second insulating layer on the substrate and covering the first insulating layer, the bank pattern, the light emitting element, the third electrode, and the fourth electrode.

[0027] Aspects of some other embodiments are included in the detailed description and the accompanying drawings.

[0028] According to an aspect of one or more embodiments of the present invention, there is provided a display device having improved alignment of light emitting elements.

[0029] Further, according to another aspect of embodiments of the present invention, there is provided a display device in which manufacturing costs and manufacturing time are reduced by forming an insulating layer disposed under a light emitting element and a bank pattern surrounding the light emitting element in parallel (e.g., simultaneously).

[0030] However, aspects and effects of the embodiments of the present invention are not limited to those described above, and further aspects and effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a perspective view of a light emitting element according to an exemplary embodiment.

[0032] Figure 2 is a plan view schematically showing a display device according to an exemplary embodiment.

[0033] Figure 3A and Figure 3B is a circuit diagram showing a pixel according to an exemplary embodiment.

[0034] Figure 4 is a circuit diagram showing a pixel according to another exemplary embodiment.

[0035] Figure 5 is a plan view of a pixel according to an exemplary embodiment.

[0036] Figure 6 is a cross-sectional view taken along line VI-VI' of Figure 5

[0037] Figure 7 is a cross-sectional view taken along line VII-VII' of Figure 5

[0038] Figure 8 is a cross-sectional view taken along line VIII-VIII' of Figure 5

[0039] Figure 9 is a cross-sectional view taken along line IX-IX' of Figure 5

[0040] Figure 10 is a plan view of a pixel according to another exemplary embodiment.

[0041] Figure 11 is a cross-sectional view taken along line XI-XI' of Figure 10 DETAILED DESCRIPTION

[0042] Aspects and features of the present application and implementations thereof will be set forth in some examples described with reference to the drawings. The present application may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and will fully convey the scope of the present application to those skilled in the art. Further, the present application is defined by the scope of the claims.

[0043] It should be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In this specification, like reference numerals designate like elements throughout the specification.

[0044] Although the terms "first", "second", etc. are used to describe various constituent elements, the constituent elements are not limited by these terms. The terms are used to distinguish one constituent element from another constituent element. Therefore, the first constituent element described below can be a second constituent element within the technical spirit of the present application. When explained in the singular, it can be interpreted as a plural meaning unless explicitly described to the contrary.

[0045] ​​​​​Further, some of the elements in the drawings can be exaggerated, not to scale or in slightly exaggerated scale, for the purpose of proper explanation. In addition, the same reference numerals and symbols can be provided to the same constituent elements throughout the whole drawings, and repetitive description can be omitted.

[0046] It will also be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, or components but do not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

[0047] In the embodiments set forth herein, when a layer, region, or component is connected to another layer, region, or component, the layers, regions, or components can be directly connected to each other, or the layers, regions, or components can also be indirectly connected to each other through another layer, region, or component therebetween.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments of the inventive concept belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] Hereinafter, some example embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view of a light emitting element according to an example embodiment of the present invention.

[0051] Referring to Figure 1 The light emitting element LD according to an example embodiment of the present invention includes a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD can be implemented as a stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0052] According to an example embodiment of the present invention, the light emitting element LD can be provided in a rod shape extending in one direction. When the extending direction of the light emitting element LD is referred to as a length direction, the light emitting element LD can have a first end and a second end in the length direction.

[0053] In an exemplary embodiment of the present application, one of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed at a first end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed at a second end of the light emitting element LD.

[0054] In an exemplary embodiment of the present application, the light emitting element LD can be disposed in a rod shape. Here, the term "rod shape" can include a bar shape or a rod shape that is long in a length direction (i.e., has an aspect ratio greater than 1), such as a cylinder or a polygonal cylinder. For example, the length of the light emitting element LD can be greater than the diameter of the light emitting element LD. However, the present application is not limited thereto. For example, the light emitting element LD can have a core-shell structure.

[0055] For example, the light emitting element LD can be manufactured to be small enough to have a diameter and / or a length of about a micron level or a nanometer level. For example, the diameter of the light emitting element LD can be 600 nm or less, and the length of the light emitting element LD can be 4 μm or less, but the size of the light emitting element LD is not limited thereto. The size of the light emitting element LD can be changed to satisfy the requirements of a display device to which the light emitting element LD is applied.

[0056] For example, the first semiconductor layer 11 can include at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include at least one of a semiconductor material such as InAlGaN, GaN, AlGaN, InGaN, AlN, or InN, and can include a semiconductor layer doped with a first dopant such as Si, Ge, Sn, or the like.

[0057] However, the material constituting the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 can be formed of any one of various materials other than the same.

[0058] The active layer 12 can be formed on the first semiconductor layer 11, and can be formed in a single quantum well structure or a multiple quantum well structure. In an embodiment, the active layer 12 can emit light having a wavelength of 400 nm to 900 nm, and a double hetero structure can be used. According to an exemplary embodiment of the present application, a cladding layer (not shown) doped with a dopant can be formed on and / or under the active layer 12. For example, the cladding layer can be implemented as an AlGaN layer or an InAlGaN layer. In addition, materials such as AlGaN and InAlGaN can also be used as the active layer 12. However, any one of various materials other than the same can form the active layer 12.

[0059] When an electric field of a predetermined voltage or an electric field of a larger voltage is applied to both ends of the light emitting element LD, the light emitting element LD emits light when an electron-hole pair is combined in the active layer 12. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source of various light emitting devices including pixels of a display device.

[0060] The second semiconductor layer 13 can be provided on the active layer 12, and can include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 can include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 can include at least one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, InN, and can include a semiconductor layer doped with a second dopant such as Mg. However, the material forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 can be formed of any one of various materials.

[0061] According to an exemplary embodiment of the present application, the light emitting element LD can further include a different phosphor layer, an active layer, a semiconductor layer, and / or an electrode layer on and / or under each layer, in addition to the above-described first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0062] Further, the light emitting element LD can further include the insulating layer 14. However, according to an exemplary embodiment of the present application, the insulating layer 14 can be omitted or can be provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the insulating layer 14 can be provided at a portion of the light emitting element LD other than both ends of the light emitting element LD, so that both ends of the light emitting element LD can be exposed.

[0063] For better understanding and ease of description, Figure 1 A shape is shown in which a portion of the insulating layer 14 is shown to be removed, but all sides of the light emitting element LD can be surrounded by the insulating layer 14.

[0064] According to an exemplary embodiment of the present application, the insulating layer 14 can include a transparent insulating material. For example, the insulating layer 14 can include at least one of insulating materials such as SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. The insulating layer 14 can include any one of various insulating materials.

[0065] The insulating layer 14 can prevent or substantially prevent an electrical short that can occur due to the active layer 12 contacting a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. Also, by forming the insulating layer 14, surface defects of the light emitting element LD can be minimized or reduced to improve the lifespan and efficiency. Also, when a plurality of light emitting elements LD are closely disposed, the insulating layer 14 can prevent or substantially prevent an undesired short that can occur between the light emitting elements LD.

[0066] The type, structure, and shape of the light emitting element LD according to the exemplary embodiment of the present application can be variously changed.

[0067] Figure 2 FIG. 1 is a plan view schematically illustrating a display device according to an exemplary embodiment.

[0068] Referring to Figure 1 and Figure 2 The display device 1000 according to the exemplary embodiment can include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. In more detail, the display device 1000 can include a display area DA for displaying an image and a non-display area NDA other than the display area DA.

[0069] The display area DA can be an area in which the pixels PXL for displaying an image are disposed. The non-display area NDA can be an area in which drivers for driving the pixels PXL of the display area DA and various line units (not shown) for connecting the pixels PXL and the drivers are disposed.

[0070] The display area DA can have any one of various shapes. For example, the display area DA can be disposed in any one of various shapes such as a closed polygon including sides formed of straight lines, a circular shape including sides formed of curved lines, an elliptical shape, or the like, or a semi-circular shape, a semi-elliptical shape, or the like including sides formed of straight lines and curved lines.

[0071] When the display area DA includes a plurality of areas, each area can also be disposed in any one of various shapes such as a closed polygon including sides formed of straight lines or a semi-circular shape, a semi-elliptical shape, or the like including sides formed of curved lines. Also, the areas of the plurality of areas can be the same as or different from each other.

[0072] In the exemplary embodiment of the present application, a case in which the display area DA is disposed as one area having a quadrangular shape including straight lines will be described as an example.

[0073] The non-display area NDA can be disposed at at least one side of the display area DA. In the exemplary embodiment of the present application, the non-display area NDA can surround the display area DA.

[0074] The pixels PXL can be provided on the substrate SUB in the display region DA. Each of the pixels PXL can include at least one light emitting element LD driven by a corresponding scan signal and a data signal.

[0075] The pixel PXL can include a light emitting element (e.g., "LD" in Figure 1 Each of the pixels PXL can emit any one of red light, green light, and blue light, but is not limited thereto. For example, each of the pixels PXL can emit any one of cyan light, magenta light, yellow light, and white light.

[0076] The pixels PXL can be provided in plural and arranged in a matrix form along rows extending in a first direction DR1 and columns extending in a second direction DR2 intersecting the first direction DR1. However, the arrangement form of the pixels PXL is not particularly limited and can be arranged in any one of various forms.

[0077] The driver can supply a signal to each of the pixels PXL through a line unit (not shown), thereby controlling the driving of the pixels PXL. For better understanding and ease of description, the line unit is omitted in Figure 2

[0078] In an embodiment, the driver can include a scan driver SDV supplying a scan signal to the pixels PXL through a scan line, an emission driver EDV supplying an emission control signal to the pixels PXL through an emission control line, a data driver DDV supplying a data signal to the pixels PXL through a data line, and a timing controller (not shown). The timing controller can control the scan driver SDV, the emission driver EDV, and the data driver DDV.

[0079] In an exemplary embodiment, each of the pixels PXL can be formed of an active pixel. However, the type, structure, and / or driving method of the pixel PXL applicable to the present application is not particularly limited.

[0080] Figure 3A Figure 3B are each a circuit diagram illustrating a pixel according to an exemplary embodiment. In particular, Figure 3A Figure 3B illustrates an example of a pixel PXL constituting an active type light emitting display panel. Figure 3A Figure 3B illustrates one pixel PXL connected to an jth data line Dj (here, j is a positive integer greater than 1) and an ith scan line Si (here, i is a positive integer greater than 1) for better understanding and ease of description.

[0081] Reference is made to Figure 3A ​​​​The pixel PXL can include at least one light emitting element LD and a pixel driving circuit DC connected thereto for driving the light emitting element LD.

[0082] A first electrode (e.g., an anode) of the light emitting element LD can be connected to the first driving power source VDD via the pixel driving circuit DC, and a second electrode (e.g., a cathode) of the light emitting element LD can be connected to the second driving power source VSS.

[0083] The first driving power source VDD and the second driving power source VSS can have different potentials from each other. For example, the potential of the second driving power source VSS can be lower than the potential of the first driving power source VDD by a threshold voltage of the light emitting element LD or more.

[0084] In an embodiment, the light emitting element LD can emit light having a luminance corresponding to a driving current controlled by the pixel driving circuit DC.

[0085] Figure 3A An exemplary embodiment in which only one light emitting element LD is included in one pixel PXL is illustrated, but the present application is not limited thereto. For example, the pixel PXL can include a plurality of light emitting elements LD connected in parallel and / or in series with each other.

[0086] According to an exemplary embodiment of the present application, the pixel driving circuit DC can include a first transistor M1, a second transistor M2, and a storage capacitor Cst. However, the structure of the pixel driving circuit DC is not limited to the exemplary embodiment shown in Figure 3A According to an exemplary embodiment, the pixel PXL can further include a pixel sensing circuit (not shown). The pixel sensing circuit can measure a value of a driving current of each pixel PXL, and transfer the measured value to an external circuit (e.g., a timing controller) to compensate for each pixel PXL.

[0087] A first electrode of the first transistor M1 (i.e., a switching transistor) is connected to the jth data line Dj, and a second electrode thereof is connected to a first node N1. Here, the first and second electrodes of the first transistor M1 can be different electrodes from each other, and when the first electrode is a source electrode, the second electrode can be a drain electrode. A gate electrode of the first transistor M1 can be connected to the ith scan line Si.

[0088] When a scan signal of which a voltage (e.g., a gate-on voltage) at which the first transistor M1 can be turned on is provided from the ith scan line Si, the first transistor M1 can be turned on to electrically connect the jth data line Dj and the first node N1. At this time, a data signal of a corresponding frame can be provided to the jth data line Dj, and thus, the data signal can be transferred to the first node N1. The data signal transferred to the first node N1 can be stored in the storage capacitor Cst.

[0089] The first electrode of the second transistor M2 (i.e., a drive transistor) can be connected to the first drive power source VDD, and its second electrode can be electrically connected to the first electrode (e.g., an anode) of the light emitting element LD. The gate electrode of the second transistor M2 can be connected to the first node N1. The second transistor M2 can control the amount of drive current provided to the light emitting element LD in response to the voltage of the first node N1.

[0090] One electrode of the storage capacitor Cst can be connected to the first drive power source VDD, and the other electrode thereof can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal provided to the first node N1, and maintain the charged voltage until the data signal of the next frame is provided.

[0091] For better understanding and ease of description, Figure 3A A relatively simple pixel driving circuit DC is shown, which includes a first transistor M1 for transferring a data signal into a pixel PXL, a storage capacitor Cst for storing the data signal, and a second transistor M2 for providing a drive current corresponding to the data signal to a light emitting element LD.

[0092] However, the present application is not limited thereto, and the structure of the pixel driving circuit DC can be variously changed. For example, the pixel driving circuit DC can further include at least one transistor (such as a transistor for compensating for the threshold voltage of the second transistor M2, a transistor for initializing the first node N1, and / or a transistor for controlling the emission time of the light emitting element LD) and / or other circuit elements (such as a boost capacitor for boosting the voltage of the first node N1, etc.).

[0093] Further, the transistors (e.g., both the first transistor M1 and the second transistor M2) included in the pixel driving circuit DC are shown as P-type transistors in Figure 3A , but the present application is not limited thereto. For example, at least one of the first transistor M1 and the second transistor M2 included in the pixel driving circuit DC can be an N-type transistor.

[0094] For example, with reference to Figure 3B , the first transistor M1 and the second transistor M2 of the pixel driving circuit DC can be implemented as N-type transistors. Except for the change in the connection position of some constituent elements due to the change in the type of transistor, Figure 3B the pixel driving circuit DC shown in Figure 3A is similar to the pixel driving circuit DC shown in in configuration and / or operation. Therefore, a further detailed description thereof will be omitted.

[0095] Figure 4is a circuit diagram illustrating a pixel according to another exemplary embodiment. For better understanding and ease of description, Figure 4 One pixel PXL connected to the jth data line Dj, the (i-1)th scan line Si-1, the ith scan line Si, and the (i+1)th scan line Si+1 is illustrated.

[0096] Referring to Figure 4 A pixel PXL according to another exemplary embodiment of the present application can include a light emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a storage capacitor Cst.

[0097] A first electrode (e.g., anode) of the light emitting element LD can be connected to the first transistor T1 via the sixth transistor T6, and a second electrode (e.g., cathode) of the light emitting element LD can be connected to the second driving power source VSS. The light emitting element LD can emit light having a luminance (e.g., predetermined luminance) corresponding to an amount of current supplied from the first transistor T1.

[0098] One electrode of the first transistor T1 (i.e., driving transistor) can be connected to the first driving power source VDD via the fifth transistor T5, and the other electrode thereof can be connected to the first electrode of the light emitting element LD via the sixth transistor T6. The first transistor T1 can control an amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1 connected to a gate electrode of the first transistor T1.

[0099] The second transistor T2 (i.e., switching transistor) can be connected between the jth data line Dj and one electrode of the first transistor T1. A gate electrode of the second transistor T2 can be connected to the ith scan line Si. The second transistor T2 can be turned on to electrically connect the jth data line Dj and one electrode of the first transistor T1 when a gate-on voltage scan signal is supplied to the ith scan line Si.

[0100] The third transistor T3 can be connected between the other electrode of the first transistor T1 and the first node N1. A gate electrode of the third transistor T3 can be connected to the ith scan line Si. The third transistor T3 can be turned on to electrically connect the other electrode of the first transistor T1 and the first node N1 when a gate-on voltage scan signal is supplied to the ith scan line Si.

[0101] The fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. A gate electrode of the fourth transistor T4 can be connected to the i-1th scan line Si-1. The fourth transistor T4 can be turned on to supply a voltage of the initialization power supply Vint to the first node N1 when a gate-on voltage scan signal is supplied to the i-1th scan line Si-1. Here, the initialization power supply Vint can be set to be lower than a voltage of a data signal.

[0102] The fifth transistor T5 can be connected between the first driving power supply VDD and one electrode of the first transistor T1. A gate electrode of the fifth transistor T5 can be connected to the i-th emission control line Ei. The fifth transistor T5 can be turned on when a gate-on voltage emission control signal is supplied to the i-th emission control line Ei, and can be turned off in other cases.

[0103] The sixth transistor T6 can be connected between the other electrode of the first transistor T1 and the first electrode of the light emitting element LD. A gate electrode of the sixth transistor T6 can be connected to the i-th emission control line Ei. The sixth transistor T6 can be turned on when a gate-on voltage emission control signal is supplied to the i-th emission control line Ei, and can be turned off in other cases.

[0104] The seventh transistor T7 can be connected between the initialization power supply Vint and the first electrode of the light emitting element LD (in Figure 4 , connected between the initialization power supply Vint and the second node N2 connected to the first electrode of the light emitting element LD). A gate electrode of the seventh transistor T7 can be connected to the i+1th scan line Si+1. The seventh transistor T7 can be turned on to supply a voltage of the initialization power supply Vint to the first electrode of the light emitting element LD (or the second node N2) when a gate-on voltage scan signal is supplied to the i+1th scan line Si+1.

[0105] The storage capacitor Cst can be connected between the first driving power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to a data signal and a threshold voltage of the first transistor T1.

[0106] In an embodiment, the transistors (e.g., the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7) included in the pixel driving circuit DC are all shown as P-type transistors in Figure 4 , but the present application is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be an N-type transistor.

[0107] Figure 5 is a plan view of a pixel according to an exemplary embodiment; Figure 6 is a cross-sectional view taken along Figure 5 line VI-VI' of Figure 7 is a cross-sectional view taken along Figure 5 line VII-VII' of Figure 8 is a cross-sectional view taken along Figure 5 line VIII-VIII' of Figure 9 is a cross-sectional view taken along Figure 5 line IX-IX' of

[0108] For better understanding and ease of description, each electrode is simplified and shown as a single electrode layer in Figure 6 to Figure 9 , but the present application is not limited thereto. In an embodiment of the present application, "formed and / or disposed in the same layer" can mean that they are formed in the same process.

[0109] For better understanding and ease of description, a plurality of light emitting elements LD aligned in a first direction DR1 are shown in Figure 5 , but the arrangement of the light emitting elements LD is not limited thereto. For example, the light emitting elements LD can be aligned in an oblique direction between the first pixel electrode REL1 and the second pixel electrode REL2.

[0110] Referring to Figure 1 to Figure 9 , the display device 1000 according to an exemplary embodiment can include a substrate SUB, first and second bank layers BNK1 and BNK2, first and second pixel electrodes REL1 and REL2, first and second contact electrodes CNE1 and CNE2, first and second insulating layers INS1 and INS2.

[0111] The substrate SUB can include an insulating material such as glass, an organic polymer, quartz, or the like. In an embodiment, the substrate SUB can be formed of a material having flexibility to be bent or folded, and can have a single-layer structure or a multi-layer structure.

[0112] The first and second bank layers BNK1 and BNK2 can be disposed on the substrate SUB. A space for disposing the light emitting elements LD can be provided between the first and second bank layers BNK1 and BNK2. In an exemplary embodiment, the first and second bank layers BNK1 and BNK2 can be spaced apart on the substrate SUB in the first direction DR1 by a length greater than one light emitting element LD.

[0113] The first and second bank layers BNK1 and BNK2 can be an insulating material including an organic material or an inorganic material, but the material of the first and second bank layers BNK1 and BNK2 is not limited thereto.

[0114] In an embodiment, each of the first bank BNK1 and the second bank BNK2 can have a trapezoidal shape with sides inclined at an angle (e.g., a predetermined angle). However, the shape of the first bank BNK1 and the second bank BNK2 is not limited thereto, and can have any one of various shapes such as a semi-elliptical shape, a circular shape, and a quadrangular shape.

[0115] The thickness HB of each of the first bank BNK1 and the second bank BNK2 can be thicker than the first thickness H1 and the second thickness H2 of the first insulating layer INS1 described later. Accordingly, the light emitting element LD can be stably aligned in a space provided between the first bank BNK1 and the second bank BNK2.

[0116] Each of the first pixel electrode REL1 (or the first electrode) and the second pixel electrode REL2 (or the second electrode) can be disposed on the corresponding bank BNK1 and BNK2. For example, the first pixel electrode REL1 can be disposed on the first bank BNK1, and the second pixel electrode REL2 can be disposed on the second bank BNK2.

[0117] The first pixel electrode REL1 and the second pixel electrode REL2 can be disposed corresponding to the shape of the first bank BNK1 and the second bank BNK2. Accordingly, the first pixel electrode REL1 can have a shape corresponding to the inclination of the first bank BNK1, and the second pixel electrode REL2 can have a shape corresponding to the inclination of the second bank BNK2.

[0118] In an embodiment, the first pixel electrode REL1 and the second pixel electrode REL2 can be disposed on the substrate SUB to be spaced apart from each other in the first direction DR1 with one light emitting element LD therebetween, and the first pixel electrode REL1 and the second pixel electrode REL2 can extend on the substrate SUB in a second direction DR2 crossing the first direction DR1.

[0119] In an exemplary embodiment, the first pixel electrode REL1 can be disposed adjacent to the first end portion EP1 of each of the light emitting elements LD, and can be electrically connected with each of the light emitting elements LD through the first contact electrode CNE1 (or the third electrode), and the second pixel electrode REL2 can be disposed adjacent to the second end portion EP2 of each of the light emitting elements LD, and can be electrically connected with each of the light emitting elements LD through the second contact electrode CNE2 (or the fourth electrode).

[0120] In an embodiment, the first pixel electrode REL1 and the second pixel electrode REL2 can be disposed on the same plane and can have the same height. When the first pixel electrode REL1 and the second pixel electrode REL2 have the same height, the light emitting element LD can be more stably connected to the first pixel electrode REL1 and the second pixel electrode REL2.

[0121] The first pixel electrode REL1 and the second pixel electrode REL2 can be formed of a conductive material. In an embodiment, the conductive material can include any one of metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof.

[0122] Further, the first pixel electrode REL1 and the second pixel electrode REL2 can be formed as a single layer, but are not limited thereto, and can be formed as multiple layers.

[0123] Here, the materials of the first pixel electrode REL1 and the second pixel electrode REL2 are not limited to the materials described above. For example, the first pixel electrode REL1 and the second pixel electrode REL2 can be formed of a conductive material having a constant reflectance so that light emitted from both end portions EP1 and EP2 of the light emitting element LD travels in a direction (e.g., a front direction) in which an image is displayed therealong.

[0124] In an embodiment, since the first pixel electrode REL1 and the second pixel electrode REL2 have shapes corresponding to the shapes of the first bank layer BNK1 and the second bank layer BNK2, light emitted from both end portions EP1 and EP2 of each of the light emitting elements LD can be reflected by the first pixel electrode REL1 and the second pixel electrode REL2 to further travel in the third direction DR3. Accordingly, emission efficiency of light emitted from each of the light emitting elements LD can be improved.

[0125] In an exemplary embodiment, the first bank layer BNK1 and the second bank layer BNK2 can function as a reflection member that improves emission efficiency of light emitted from each of the light emitting elements LD together with the first pixel electrode REL1 and the second pixel electrode REL2 disposed thereon.

[0126] One of the first pixel electrode REL1 and the second pixel electrode REL2 can be an anode, and the other can be a cathode. In an exemplary embodiment of the present disclosure, the first pixel electrode REL1 can be an anode, and the second pixel electrode REL2 can be a cathode.

[0127] For better understanding and ease of description, the first pixel electrode REL1 and the second pixel electrode REL2 are illustrated as being disposed directly on the substrate SUB, but are not limited thereto. For example, constituent elements for driving the display device 1000 with a passive matrix or an active matrix can be further disposed between the first pixel electrode REL1 and the second pixel electrode REL2 and the substrate SUB.

[0128] The first pixel electrode REL1 can be connected to the first connection line CNL1, and the second pixel electrode REL2 can be connected to the second connection line CNL2. In an embodiment, the first connection line CNL1 can be disposed integrally with the first pixel electrode REL1, and the second connection line CNL2 can be disposed integrally with the second pixel electrode REL2.

[0129] The first connection line CNL1 can be electrically connected to a first power line (not shown) through a first contact hole CT1. The second connection line CNL2 can be electrically connected to a second power line DVL through a second contact hole CT2.

[0130] In an embodiment, a first cover electrode CPL1 can be disposed on the first pixel electrode REL1, and a second cover electrode CPL2 can be disposed on the second pixel electrode REL2.

[0131] Each of the first cover electrode CPL1 and the second cover electrode CPL2 prevents or substantially prevents damage to the first pixel electrode REL1 and the second pixel electrode REL2 that can occur during a manufacturing process of the display device 1000. The first cover electrode CPL1 and the second cover electrode CPL2 can be formed of a transparent conductive material, but are not limited thereto.

[0132] In an embodiment, the first cover electrode CPL1 can be disposed directly on the first pixel electrode REL1 to be electrically connected to the first pixel electrode REL1, and the second cover electrode CPL2 can be disposed directly on the second pixel electrode REL2 to be electrically connected to the second pixel electrode REL2.

[0133] A first insulating layer INS1 can be disposed on the first cover electrode CPL1 and the second cover electrode CPL2. In an exemplary embodiment, the first insulating layer INS1 can be disposed entirely on the substrate SUB to cover the above-described first bank BNK1 and second bank BNK2, the first pixel electrode REL1 and the second pixel electrode REL2, and the first cover electrode CPL1 and the second cover electrode CPL2.

[0134] Further, the first insulating layer INS1 can be disposed between the substrate SUB and each of the light emitting elements LD. The first insulating layer INS1 can fill a space between the substrate SUB and the light emitting elements LD, and can stably support the light emitting elements LD.

[0135] In an implementation, the first insulating layer INS1 may include one or more layers of a photosensitive organic layer formed from a photoresist-based organic material, but is not limited thereto.

[0136] In the planar view, each pixel PXL can be divided into a light-emitting region EA and a dam region BA. The light-emitting region EA can be the area including the light-emitting element LD that emits light from the light-emitting element LD to the outside, and the dam region BA can be the area arranged around the light-emitting region EA to distinguish or separate the light-emitting regions EA of each pixel PXL from each other. The dam region BA can be the area in which the dam pattern BNK3, which will be described later, is set.

[0137] The light-emitting region EA may include a first region VA and a second region RA. The first region VA may be a region in which a light-emitting element LD is disposed, and the second region RA may be a region disposed around the first region VA to align the light-emitting element LD in the first region VA. In other words, the light-emitting element LD can be aligned in the first region VA through the second region RA. In a plan view, the first region VA and the second region RA may be disposed in a direction (e.g., the first direction DR1) that intersects the extending directions of the first pixel electrode REL1 and the second pixel electrode REL2 (e.g., the second direction DR2). Furthermore, the first region VA and the second region RA may be disposed alternately in the second direction DR2.

[0138] The first insulating layer INS1 can have a different thickness in each region. In this case, the thickness of the first insulating layer INS1 can refer to the thickness of the stack on the third-direction DR3 starting from the substrate SUB.

[0139] like Figure 6 and Figure 7 As shown, the first insulating layer INS1 can be provided in the first region VA with a first thickness H1, and the first insulating layer INS1 can be provided in the second region RA with a second thickness H2.

[0140] like Figure 9 As shown, the first thickness H1 of the portion of the first insulating layer INS1 disposed in the first region VA and the second thickness H2 of the portion of the first insulating layer INS1 disposed in the second region RA can be different from each other. In an embodiment, the first thickness H1 of the first insulating layer INS1 can be thinner than the second thickness H2 of the first insulating layer INS1. In other words, the first insulating layer INS1 can have a non-uniform pattern formed on the surface in the second direction DR2.

[0141] In an embodiment, the light emitting elements LD provided on the first insulating layer INS1 can be prepared in a form dispersed in a solution (e.g., a predetermined solution), and can be provided to the light emitting region EA of each pixel PXL through an inkjet printing method. For example, the light emitting elements LD can be mixed with a volatile solvent and fall into each light emitting region EA.

[0142] At this time, when a voltage (e.g., a predetermined voltage) is provided through the first pixel electrode REL1 and the second pixel electrode REL2 of each pixel PXL, an electric field can be formed between the first pixel electrode REL1 and the second pixel electrode REL2, and then the light emitting elements LD can be aligned between the first pixel electrode REL1 and the second pixel electrode REL2. After the light emitting elements LD are aligned, the solvent can be evaporated or otherwise removed to stably arrange the light emitting elements LD between the first pixel electrode REL1 and the second pixel electrode REL2.

[0143] As described above, when the first insulating layer INS1 has different thicknesses in the first region VA and the second region RA of the light emitting region EA, the light emitting elements LD provided in a form dispersed in a solution can be aligned in the first region VA in which the first insulating layer INS1 has a relatively low thickness. Accordingly, the light emitting elements LD can be uniformly distributed throughout the light emitting region EA, rather than being provided on only one side of the light emitting region EA.

[0144] For better understanding and ease of description, although a structure in which the light emitting elements LD are not provided in the second region RA is shown in Figure 5 to Figure 9 However, the number of light emitting elements LD provided in the second region RA can be less than the number of light emitting elements LD provided in the first region VA.

[0145] In an embodiment, a contact region CA can be further provided in the light emitting region EA. The contact region CA can be provided adjacent to one side of the light emitting region EA.

[0146] As shown in Figure 8 The contact region CA can be a region in which the first insulating layer INS1 is not provided, as shown in

[0147] In the contact area CA, the first cover electrode CPL1 can contact the first contact electrode CNE1, and the first cover electrode CPL1 can be electrically connected to an end (e.g., a first end EP1) of each of the light emitting elements LD through the first contact electrode CNE1. Also, the second cover electrode CPL2 can contact the second contact electrode CNE2, and the second cover electrode CPL2 can be electrically connected to the other end (e.g., a second end EP2) of each of the light emitting elements LD through the second contact electrode CNE2.

[0148] According to an exemplary embodiment, when the first cover electrode CPL1 and the second cover electrode CPL2 are not included, the first pixel electrode REL1 and the second pixel electrode REL2 can be exposed to the outside, the first pixel electrode REL1 can contact the first contact electrode CNE1, and the second pixel electrode REL2 can contact the second contact electrode CNE2.

[0149] In an embodiment, the bank pattern BNK3 can be disposed in the bank area BA. In an embodiment, in a plan view, at least one light emitting element LD disposed in the light emitting area EA can be surrounded by the bank pattern BNK3 in the corresponding pixel PXL.

[0150] In an embodiment, as shown in FIG. 1A, the bank pattern BNK3 can be integrally connected and disposed. Also, the bank pattern BNK3 can be formed in parallel (e.g., simultaneously) with the first insulating layer INS1 through the same process as the first insulating layer INS1. In other words, the bank pattern BNK3 can be integrally formed with the first insulating layer INS1, and the bank pattern BNK3 can include the same material as the first insulating layer INS1. Figure 5

[0151] In an embodiment, the bank pattern BNK3 can have a trapezoidal cross-section that narrows toward the top, similar to the first bank layer BNK1 and the second bank layer BNK2, but is not limited thereto. In another example, the bank pattern BNK3 can have a curved surface having a cross-section such as a semi-circular or semi-elliptical shape that narrows toward the top. In the present disclosure, the shape and / or inclination of the bank pattern BNK3 are not particularly limited and can vary differently.

[0152] The third thickness H3 of the bank pattern BNK3 can be thicker than the first thickness H1 and the second thickness H2 of the first insulating layer INS1 described above. Also, the bank pattern BNK3 can be formed thicker than the first bank layer BNK1 and the second bank layer BNK2.

[0153] ​The bank pattern BNK3 can be disposed along the boundary of each pixel PXL to prevent or substantially prevent light leakage between adjacent pixels PXL. In addition, the bank pattern BNK3 can prevent or substantially prevent leakage of a solution including the light emitting element LD to an adjacent pixel PXL in the process of aligning the light emitting element LD in the light emitting area EA.

[0154] As described above, the bank pattern BNK3 can be formed in parallel (e.g., simultaneously) with the first insulating layer INS1, thereby reducing manufacturing costs and manufacturing time of the display device 1000.

[0155] The first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the first insulating layer INS1 and the light emitting element LD.

[0156] The first contact electrode CNE1 can cover the first pixel electrode REL1 and can overlap the first pixel electrode REL1 in a plan view.

[0157] In addition, the first contact electrode CNE1 can partially overlap one of the two end portions EP1 and EP2 of each light emitting element LD. For example, the first contact electrode CNE1 can partially overlap the first end portion EP1 of each light emitting element LD.

[0158] In the contact area CA, the first contact electrode CNE1 can be electrically connected to the first cover electrode CPL1. Since the first cover electrode CPL1 is electrically connected to the first pixel electrode REL1, the first contact electrode CNE1 can be connected to the first pixel electrode REL1.

[0159] The second contact electrode CNE2 can cover the second pixel electrode REL2 and can overlap the second pixel electrode REL2 in a plan view.

[0160] In the contact area CA, the second contact electrode CNE2 can be electrically connected to the second cover electrode CPL2. Since the second cover electrode CPL2 is electrically connected to the second pixel electrode REL2, the second contact electrode CNE2 can be connected to the second pixel electrode REL2.

[0161] According to an exemplary embodiment, when the second cover electrode CPL2 is omitted, the second contact electrode CNE2 can be directly connected to the second pixel electrode REL2 through the contact area CA in which the first insulating layer INS1 is not disposed.

[0162] In an embodiment, each of the first contact electrode CNE1 and the second contact electrode CNE2 can be formed of a transparent conductive material so that light emitted from each of the light emitting elements LD can travel in the front direction without loss. For example, the transparent conductive material can include ITO, IZO, ITZO, or the like. However, the material of the first contact electrode CNE1 and the second contact electrode CNE2 is not limited to the above-described material.

[0163] In an exemplary embodiment of the present application, the first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on the same plane.

[0164] The second insulating layer INS2 can be disposed on the first contact electrode CNE1 and the second contact electrode CNE2. The second insulating layer INS2 can prevent or substantially prevent the first contact electrode CNE1 and the second contact electrode CNE2 from being exposed to the outside to prevent or substantially prevent the first contact electrode CNE1 and the second contact electrode CNE2 from being corroded.

[0165] The second insulating layer INS2 can function as an encapsulation layer that prevents or substantially prevents oxygen, moisture, or the like from penetrating into the light emitting elements LD.

[0166] The second insulating layer INS2 can include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment, the second insulating layer INS2 can be formed as a single layer as shown in the drawing, but is not limited thereto, and the second insulating layer INS2 can be formed of multiple layers.

[0167] According to an exemplary embodiment, an outer coating layer (not shown) can be further disposed on the second insulating layer INS2. The outer coating layer can be a planarization layer that alleviates steps generated by the first bank layer BNK1 and the second bank layer BNK2, the first pixel electrode REL1 and the second pixel electrode REL2, and the first contact electrode CNE1 and the second contact electrode CNE2 disposed thereunder. In addition, the outer coating layer can function as an encapsulation layer that prevents or substantially prevents oxygen, moisture, or the like from penetrating into the light emitting elements LD.

[0168] As described above, the first insulating layer INS1 disposed in the light emitting area EA can have different thicknesses in each region. A first thickness H1 of a portion of the first insulating layer INS1 disposed in the first region VA can be thinner than a second thickness H2 of a portion of the first insulating layer INS1 disposed in the second region RA, and the first region VA and the second region RA can be alternately disposed to form a non-uniform pattern.

[0169] The light emitting elements LD can be aligned in the first region VA in which the first insulating layer INS1 is relatively thinly disposed. Due to the different thicknesses of the first insulating layer INS1, the light emitting elements LD can be uniformly distributed, rather than being disposed only on one side of the light emitting region EA. In other words, in each of the pixels PXL, due to the uneven pattern of the first insulating layer INS1, the alignment of the light emitting elements LD can be improved.

[0170] Further, the bank pattern BNK3 disposed in the bank region BA surrounding the light emitting region EA can be integrally formed in parallel (e.g., simultaneously) with the first insulating layer INS1. Accordingly, the manufacturing cost of the display device 1000 including the first insulating layer INS1 and the bank pattern BNK3 can be reduced, and the manufacturing time of the display device 1000 can be reduced.

[0171] Here, another exemplary embodiment of the display device 1000 will be described. In the following exemplary embodiment, components identical to those of the aforementioned embodiments are denoted by identical reference numerals, and the description thereof can be omitted or simplified.

[0172] Figure 10 is a plan view of a pixel according to another exemplary embodiment; and Figure 11 is a cross-sectional view taken along Figure 10 line XI-XI’ of Figure 10 and Figure 11 the exemplary embodiment of Figure 5 to Figure 9 differs from the exemplary embodiment of

[0173] In the embodiment, the cross-sectional view taken along Figure 10 line XII-XII’ of Figure 5 is substantially identical to Figure 7 as the cross-sectional view taken along Figure 10 line VII-VII’ of Figure 5 is substantially identical to Figure 8 as the cross-sectional view taken along Figure 10 line VIII-VIII’ of Figure 5 is substantially identical to Figure 9 as the cross-sectional view taken along Figure 10 line IX-IX’ of Figure 11 .

[0174] Referring to Figure 5 to Figure 11According to another exemplary embodiment, a pixel PXL_1 can include an emission area EA_1 and a bank area BA in a plan view, where light emitted from the light emitting element LD is emitted in the emission area EA_1, and the bank area BA surrounds a perimeter of the emission area EA_1. The emission area EA_1 can include a plurality of first areas VA_1 in which the light emitting element LD is disposed and a second area RA_1 surrounding the first areas VA_1.

[0175] A first insulating layer INS1_1 including a non-uniform pattern formed on a surface thereof can be disposed in the emission area EA_1. The first insulating layer INS1_1 can have a first thickness H1 in the first areas VA_1 and a second thickness H2 in the second area RA_1 (see FIG. 4B). Figure 7 ).

[0176] In an embodiment, a bank pattern BNK3 can be disposed in the bank area BA to surround the light emitting element LD. The bank pattern BNK3 can have a third thickness H3 thicker than the first thickness H1 and the second thickness H2. In an embodiment, the bank pattern BNK3 can be formed in parallel (e.g., simultaneously) with the first insulating layer INS1_1 by the same process as the first insulating layer INS1_1, and can include the same material as the first insulating layer INS1_1.

[0177] In an embodiment, the first insulating layer INS1_1 can be continuously disposed in the emission area EA_1, and can also be disposed on the first bank layer BNK1 and the second bank layer BNK2. A portion of the first insulating layer INS1_1 disposed on the first bank layer BNK1 and the second bank layer BNK2 can have a fourth thickness H4. In an embodiment, the first thickness H1 of the first insulating layer INS1_1 can be different from the fourth thickness H4. For example, the fourth thickness H4 of the first insulating layer INS1_1 can be thicker than the first thickness H1. In an embodiment, the fourth thickness H4 can be equal to or less than the second thickness H2.

[0178] Figure 10 to Figure 11 The first insulating layer INS1_1 in the exemplary embodiment shown in FIG. 4A can be disposed on the first bank layer BNK1 and the second bank layer BNK2 to be thicker than the first insulating layer INS1_1 in the exemplary embodiment shown in FIG. 4B. Figure 5 to Figure 9 Thus, the light emitting element LD can be easily disposed between the first bank layer BNK1 and the second bank layer BNK2, and the alignment of the light emitting element LD can be further improved in the pixel PXL_1.

[0179] While some example embodiments of the present application have been described with reference to the accompanying drawings, it is to be understood that the present application is not limited to the particular examples disclosed, but rather is to cover modifications, equivalents and alternatives within the scope of the application.

Claims

1. A display device comprising: a substrate including first regions and second regions arranged alternately in a plan view in a first direction; first and second electrodes located over the substrate and spaced apart from each other in a second direction intersecting the first direction; a first insulating layer located over the substrate and covering the first and second electrodes; and a light-emitting element located over the first insulating layer and electrically connected to the first and second electrodes, wherein the first insulating layer has a first thickness in the first regions and a second thickness thicker than the first thickness in the second regions, and the light-emitting element is located in the first regions.

2. The display device according to claim 1, wherein the substrate further includes a bank region located around the first and second regions, and the display device further includes a bank pattern located over the substrate and in the bank region. The bank pattern is integrally formed with the first insulating layer.

3. The display device of claim 2, wherein, The bank pattern has a third thickness thicker than each of the first and second thicknesses.

4. The display device according to claim 3, wherein 5. The display device according to claim 1, further comprising: a third electrode located over the light-emitting element and electrically connected to a first end portion of the light-emitting element and the first electrode; and a fourth electrode located over the light-emitting element and electrically connected to a second end portion of the light-emitting element and the second electrode.

6. The display device according to claim 5, wherein the substrate further includes a contact region, and the first insulating layer exposes at least a portion of the first electrode and at least a portion of the second electrode in the contact region. In the contact region, the first electrode contacts the third electrode, and the second electrode contacts the fourth electrode.

8. The display device according to claim 5, further comprising:

7. The display device of claim 6, wherein, a first bank layer located between the substrate and the first electrode, and a second bank layer located between the substrate and the second electrode, wherein each of a thickness of the first bank layer and a thickness of the second bank layer is thicker than the second thickness of the first insulating layer. further comprising a second insulating layer located over the substrate and covering the first insulating layer, the light-emitting element, the third electrode, and the fourth electrode. The first regions and the second regions extend in the second direction.

9. The display device according to claim 5, wherein The first regions are spaced apart from each other in the first direction, and the second regions surround the first regions.

10. The display device according to claim 1, wherein The first insulating layer has a fourth thickness over the first and second electrodes, and the fourth thickness is thicker than the first thickness.

11. The display device according to claim 1, wherein 13. A display device comprising:

12. The display device of claim 11, wherein, a substrate; first and second electrodes located over the substrate and spaced apart from each other in a first direction; a first insulating layer located over the substrate and covering the first and second electrodes; a light-emitting element located over the first insulating layer and electrically connected to the first and second electrodes; and a bank pattern located over the substrate and arranged around the light-emitting element, wherein the first insulating layer and the bank pattern are integrally formed. ​ ​ ​ 14. The display device according to claim 13, further comprising: a third electrode over the light-emitting element and electrically connected to a first end portion of the light-emitting element and the first electrode; and a fourth electrode over the light-emitting element and electrically connected to a second end portion of the light-emitting element and the second electrode.

15. The display device according to claim 14, wherein the substrate further comprises a contact region, and the first insulating layer exposes at least part of the first electrode and at least part of the second electrode in the contact region. In the contact region, the first electrode contacts the third electrode, and the second electrode contacts the fourth electrode.

16. The display device of claim 15, wherein, 17. The display device according to claim 14, further comprising: a first bank layer between the substrate and the first electrode, and a second bank layer between the substrate and the second electrode, wherein each of a thickness of the first bank layer and a thickness of the second bank layer is thinner than a thickness of the bank pattern.

18. The display device according to claim 14, further comprising a second insulating layer over the substrate and covering the first insulating layer, the bank pattern, the light-emitting element, the third electrode, and the fourth electrode. ​

Images