Display device

Abstract

A display device includes: a substrate including a display area and a peripheral area adjacent to the display area; a first conductive layer including a first layer portion of a first power line and a second power line disposed in the peripheral area of ​​the substrate; and a second conductive layer including a second layer portion of the first power line and a second power line disposed in the peripheral area of ​​the substrate. The first layer portion and the second layer portion of the first power line overlap and are electrically connected to each other, and the first layer portion and the second layer portion of the second power line overlap and are electrically connected to each other. A portion of the first power line and a portion of the second power line overlap each other.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device. More specifically, embodiments of the present invention relate to an organic light-emitting display device including a first power line and a second power line. Background Technology

[0002] In recent years, lightweight and compact display devices have been manufactured. Cathode ray tube (“CRT”) display devices are used due to their performance and competitive price. However, CRT display devices have drawbacks in terms of size and portability. Therefore, display devices such as plasma display devices, liquid crystal display devices, and organic light-emitting diode (OLED) display devices are widely used due to their small size, light weight, and low power consumption. Summary of the Invention

[0003] Organic light-emitting diode (OLED) display devices may include a display area for displaying an image and a peripheral area that serves as a non-display area surrounding the display area. Wiring for driving pixels in the display area may be formed in the peripheral area. On the other hand, it is desirable to design the wiring structure to prevent display quality from being degraded due to external light reflection from the wiring.

[0004] One or more embodiments of the present invention provide a display device having a larger display area and improved display quality by preventing uneven visibility of wiring.

[0005] According to an embodiment of the present invention, a display device includes: a substrate including a display area and a peripheral area, the peripheral area being a non-display area and disposed adjacent to the display area; a first conductive layer including a first layer portion of a first power line and a first layer portion of a second power line disposed on the peripheral area of ​​the substrate; and a second conductive layer including a second layer portion of the first power line and a second layer portion of the second power line disposed on the peripheral area of ​​the substrate. In such an embodiment, the second layer portion of the first power line overlaps with and is electrically connected to the first layer portion of the first power line, and the second layer portion of the second power line overlaps with and is electrically connected to the first layer portion of the second power line. In such an embodiment, a portion of the first power line and a portion of the second power line overlap each other.

[0006] In one embodiment, a first power supply voltage can be applied to a first power supply line, and a second power supply voltage different from the first power supply voltage can be applied to a second power supply line.

[0007] In one embodiment, the display device may further include a first through-hole insulating layer disposed between the first conductive layer and the second conductive layer. The first through-hole insulating layer may include an organic insulating material.

[0008] In one embodiment, a portion of the second layer of the first power line may overlap with a portion of the first layer of the second power line.

[0009] In an embodiment, the display device may further include a cover electrode disposed on a first layer portion of the first power line and a first layer portion of the second power line to cover portions of the first layer portion of the first power line and the first layer portion of the second power line that are spaced apart from each other.

[0010] In one embodiment, the display device may further include: a pixel electrode disposed in a display area on a substrate, a light-emitting layer disposed on the pixel electrode, and a counter electrode disposed on the light-emitting layer. In such an embodiment, the cover electrode may be disposed in the same layer as the pixel electrode and may comprise the same material as the pixel electrode.

[0011] In an embodiment, the display device may further include a cover window comprising a light-shielding pattern arranged in a peripheral area. When viewed in a plan view, the light-shielding pattern may be spaced apart from the display area and may partially overlap with the first power line and the second power line.

[0012] In one embodiment, the display device may further include a first through-hole insulating layer disposed between the first conductive layer and the second conductive layer. In such an embodiment, the first through-hole insulating layer may include an organic insulating material.

[0013] In one embodiment, the display device may further include spider lines arranged in a peripheral region on a substrate. The spider lines may be arranged between the substrate and at least one line selected from a first power line and a second power line.

[0014] In one embodiment, the spiderweb may include a first layer of spiderweb and a second layer of spiderweb. In such an embodiment, the display device may further include an insulating layer disposed between the first layer of spiderweb and the second layer of spiderweb.

[0015] In one embodiment, the display device may further include: an active pattern disposed on a display area on a substrate, a gate electrode overlapping the active pattern, and a memory electrode overlapping the gate electrode. In such an embodiment, the first conductive layer may further include a source electrode and a drain electrode electrically connected to the active pattern. In such an embodiment, the second conductive layer may further include contact pads. In such an embodiment, the display device may further include: a pixel electrode disposed on the display area and electrically connected to the contact pads, a light-emitting layer located on the pixel electrode, and a counter electrode disposed on the light-emitting layer.

[0016] According to an embodiment of the present invention, a display device includes: a substrate including a display area and a peripheral area, the peripheral area being a non-display area and disposed adjacent to the display area; a light-emitting structure disposed on the substrate in the display area; a first power line disposed on the substrate in the peripheral area, wherein the first power line supplies a first power supply voltage to the light-emitting structure; a second power line disposed on the substrate in the peripheral area, wherein the second power line supplies a second power supply voltage to the light-emitting structure; and an electrode that at least partially overlaps with the first power line and the second power line.

[0017] In this embodiment, the electrode can be floated.

[0018] In one embodiment, the light-emitting structure may include a pixel electrode, a light-emitting layer on the pixel electrode, and a counter electrode on the light-emitting layer. In such an embodiment, the electrode may be disposed in the same layer as the pixel electrode and may comprise the same material as the pixel electrode.

[0019] In one embodiment, the first power line may include a first layer portion and a second layer portion overlapping and electrically connected to the first layer portion. In such an embodiment, the second power line may include a first layer portion and a second layer portion overlapping and electrically connected to the first layer portion of the second power line. In such an embodiment, the first layer portion of the first power line and the first layer portion of the second power line may be defined by a first conductive layer and may comprise the same material as each other. In such an embodiment, the second layer portion of the first power line and the second layer portion of the second power line may be defined by a second conductive layer and may comprise the same material as each other.

[0020] In an embodiment, the electrode may be defined by a first conductive layer or a second conductive layer.

[0021] In one embodiment, the electrode may be defined by a second conductive layer and may partially overlap with a first layer portion of the first power line and a first layer portion of the second power line, or the electrode may be defined by a first conductive layer and may partially overlap with a second layer portion of the first power line and a second layer portion of the second power line.

[0022] In one embodiment, the display device may further include a cover window comprising a light-shielding pattern arranged in a peripheral area. In such an embodiment, when viewed from a plan view, the light-shielding pattern may be spaced apart from the display area and may partially overlap with the first power line and the second power line.

[0023] In one embodiment, the display device may further include spider lines arranged in a peripheral region on the substrate. In such an embodiment, the spider lines may be arranged between the substrate and at least one line selected from a first power line and a second power line.

[0024] In one embodiment, the spiderweb may include a first layer of spiderweb and a second layer of spiderweb. In such an embodiment, the display device may further include an insulating layer disposed between the first layer of spiderweb and the second layer of spiderweb.

[0025] According to an embodiment of the present invention, the display device includes a first power line and a second power line. In such an embodiment, the first and second power lines of the display device are adjacent to the display area, and in the peripheral area not covered by a light-shielding pattern, the first and second power lines may overlap each other or be covered by a cover electrode. Therefore, by reducing wiring non-uniformity that may be detected due to external light reflection, display quality can be improved, and the curved area can be bent to minimize the non-display area, thereby providing a display device in which the display area is enlarged. Attached Figure Description

[0026] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, wherein:

[0027] Figure 1 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention;

[0028] Figure 2 It is shown in the figure. Figure 1 An equivalent circuit diagram of an exemplary embodiment of the pixels shown;

[0029] Figure 3 It is shown in the figure. Figure 1 A partial enlarged view of the first and second power lines in part A;

[0030] Figure 4 It is along Figure 3 A cross-sectional view taken from line I-I';

[0031] Figure 5 It is along Figure 3 A cross-sectional view taken from line II-II';

[0032] Figure 6 Is with Figure 1 A cross-sectional view of a portion corresponding to the pixels of the display device;

[0033] Figure 7 This is a partial enlarged view of a display device according to an alternative exemplary embodiment of the present invention;

[0034] Figure 8 It is along Figure 7 A cross-sectional view taken from line I-I';

[0035] Figure 9 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention;

[0036] Figure 10 It is along Figure 9 A cross-sectional view taken from line I-I';

[0037] Figure 11 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention;

[0038] Figure 12 It is along Figure 11 A cross-sectional view taken from line I-I';

[0039] Figure 13 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention;

[0040] Figure 14 It is along Figure 13 A cross-sectional view taken from line I-I';

[0041] Figure 15 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention;

[0042] Figure 16 It is along Figure 15 A cross-sectional view taken from line I-I';

[0043] Figure 17 Is with Figure 15 A cross-sectional view of a portion corresponding to the pixels of the display device;

[0044] Figure 18 This is a block diagram illustrating an electronic device according to an exemplary embodiment;

[0045] Figure 19A This diagram illustrates a device implemented as a television set. Figure 18 Figures illustrating exemplary embodiments of the electronic device; and

[0046] Figure 19B This diagram illustrates what is implemented as a smartphone. Figure 18 A diagram illustrating an exemplary embodiment of an electronic device. Detailed Implementation

[0047] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure exhaustive and thorough, and will fully convey the scope of the invention to those skilled in the art. Throughout the text, the same reference numerals refer to the same elements.

[0048] What will be understood is that when an element is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element between the two. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0049] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part without departing from the teachings of this document.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. The singular forms “a” and “the (described)” as used herein are intended to include the plural forms (including “at least one”) unless the context clearly indicates otherwise. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations shown in the drawings, relative terms are intended to also include different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of another element will be oriented to be “up” of that element. Thus, depending on the specific orientation of the drawing, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” another element will be oriented to be “above” that element. Thus, the exemplary terms “below” and “under” can encompass both “up” and “down” orientations.

[0052] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms defined, for example, in common dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0053] In this document, embodiments are described with reference to cross-sectional views, which are schematic illustrations of rationalized embodiments. Therefore, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions illustrated herein, but will include deviations in shape due to, for example, manufacturing processes. For example, regions illustrated or described as flat may generally have rough and / or non-linear characteristics. Furthermore, illustrated sharp corners may be rounded. Therefore, the regions illustrated in the figures are substantially schematic, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

[0054] In the following description, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

[0056] refer to Figure 1 An embodiment of the display device may include a display area DA in which an image is displayed and a peripheral area PA that is a non-display area surrounding the display area DA.

[0057] The display device may include a first power line 200, a second power line 300, and a pad PAD arranged in a peripheral region PA. The peripheral region PA may include a curved region BA.

[0058] The display device may include scan lines Si, data lines Dj, driving voltage lines PL, and pixels PX arranged in the display area DA. Each of the scan lines Si, data lines Dj, driving voltage lines PL, and pixels PX may be provided in multiples.

[0059] The scan line Si can extend in the first direction D1. The data line Dj can extend in the second direction D2, which intersects the first direction D1. The drive voltage line PL can extend in the second direction D2 and can be electrically connected to the first power supply line 200.

[0060] Pixel PX can be electrically connected to scan line Si, data line Dj, and drive voltage line PL.

[0061] In an embodiment, the pixel PX may include a self-emissive element. In such an embodiment, the self-emissive element may include at least one selected from organic light-emitting diodes, quantum dot light-emitting diodes, and inorganic ultra-small light-emitting diodes (e.g., micro LEDs). Hereinafter, for ease of description, embodiments in which the self-emissive element is an organic light-emitting diode will be described in detail.

[0062] In one embodiment, pixel PX may emit one of red, green, and blue light. However, the invention is not limited thereto. In one embodiment, for example, pixel PX may emit light of a predetermined color (e.g., cyan, magenta, yellow, or white).

[0063] The pixel PX will be described in more detail later.

[0064] The first power line 200 can be electrically connected to the drive voltage line PL to supply a first power supply voltage to the pixel PX, wherein the first power supply voltage is Figure 2 The driving voltage ELVDD is shown in the figure.

[0065] The second power line 300 can provide a second power supply voltage to the pixel PX, and this second power supply voltage is Figure 2 The common voltage ELVSS is shown. In an embodiment, the second power line 300 is electrically connected in the peripheral region PA to the counter electrode 183, which serves as the cathode electrode (see [link]). Figure 6 Therefore, the common voltage ELVSS can be provided to the counter electrode 183.

[0066] The second power line 300 may be configured to at least partially surround the peripheral region PA. In an embodiment, such as Figure 1 As shown, the second power line 300 can be configured to surround the display area DA.

[0067] The display device can be bent within the curved region BA, allowing the pads PAD to be positioned on the rear surface of the display region DA. By bending a portion of the peripheral region PA to face the rear surface of the display device, the area of ​​the non-display area perceived by the user can be reduced.

[0068] Figure 2 It is shown in the figure. Figure 1 An equivalent circuit diagram of an exemplary embodiment of the pixels shown. Figure 2 For ease of illustration and description, the pixel PX connected to the j-th data line Dj, the (i-1)-th scan line Si-1, the ith scan line Si, and the (i+1)-th scan line Si+1 is shown in the figure.

[0069] refer to Figure 2 The embodiment of the pixel PX includes an organic light-emitting diode (OLED), a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0070] The anode of the organic light-emitting diode (OLED) can be connected to the first transistor T1 via a sixth transistor T6, and the cathode of the OLED can be connected to a common power supply provided with a common voltage ELVSS. The OLED can produce light with a brightness level corresponding to the amount of current supplied from the first transistor T1.

[0071] The driving voltage ELVDD can be a voltage higher than the common voltage ELVSS, allowing current to flow through the organic light-emitting diode (OLED). Here, the driving voltage ELVDD is also referred to as the first power supply voltage, and the common voltage ELVSS is also referred to as the second power supply voltage.

[0072] The seventh transistor T7 is connected between the initialization power supply, which is provided with the initialization voltage Vint, and the anode of the organic light-emitting diode (OLED). The gate electrode of the seventh transistor T7 is connected to the (i+1)th scan line Si+1. When the scan signal is transmitted to the (i+1)th scan line Si+1, the seventh transistor T7 is turned on to supply the initialization voltage Vint to the anode of the OLED. Here, the initialization voltage Vint can be a voltage lower than the data voltage supplied to the j-th data line Dj.

[0073] The sixth transistor T6 is connected between the first transistor T1 and the anode of the organic light-emitting diode (OLED). The gate electrode of the sixth transistor T6 is connected to the i-th emission control wiring Ei. When an emission control signal is supplied to the i-th emission control wiring Ei, the sixth transistor T6 is turned off; otherwise, it is turned on.

[0074] The fifth transistor T5 is connected between the drive power supply, which is supplied with the drive voltage ELVDD, and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the i-th emitter control line Ei. When an emitter control signal is supplied to the i-th emitter control line Ei, the fifth transistor T5 is turned off; otherwise, it is turned on.

[0075] The first electrode of the first transistor T1 (or driving transistor) is connected to the driving power supply provided with the driving voltage ELVDD via the fifth transistor T5, and the second electrode of the first transistor T1 is connected to the anode of the organic light-emitting diode (OLED) via the sixth transistor T6. Additionally, the gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 controls the amount of current flowing from the driving power supply provided with the driving voltage ELVDD through the OLED to the common power supply provided with the common voltage ELVSS based on the voltage of the first node N1.

[0076] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 to the first node N1. Therefore, when the third transistor T3 is turned on, the first transistor T1 is connected in diode form.

[0077] The fourth transistor T4 is connected between the first node N1 and the initialization power supply, which is provided with the initialization voltage Vint. The gate electrode of the fourth transistor T4 is connected to the (i-1)th scan line Si-1. When the scan signal is transmitted to the (i-1)th scan line Si-1, the fourth transistor T4 is turned on to supply the initialization voltage Vint of the initialization power supply to the first node N1.

[0078] The second transistor T2 is connected between the j-th data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the second transistor T2 is turned on to electrically connect the j-th data line Dj to the first electrode of the first transistor T1.

[0079] The storage capacitor Cst is connected between the drive power supply, which is supplied with the drive voltage ELVDD, and the first node N1. The storage capacitor Cst stores a voltage corresponding to the data voltage and the threshold voltage of the first transistor T1.

[0080] Figure 3 It is shown in the figure. Figure 1 A partial enlarged view of the first and second power lines in part A.

[0081] refer to Figures 1 to 3In an embodiment of the display device, a first power line 200 may be arranged in a peripheral region PA. The first power line 200 may include a first layer portion 210 and a second layer portion 220 that overlaps with and is electrically connected to the first layer portion 210. A second power line 300 may include a first layer portion 310 and a second layer portion 320 that overlaps with and is electrically connected to the first layer portion 310.

[0082] In such an embodiment, when viewed from a plan view in a direction perpendicular to the first direction D1 and the second direction D2 (or the thickness direction of the display device), a portion of the first power line 200 and a portion of the second power line 300 overlap each other. In the peripheral region PA adjacent to the display area DA, the lower wiring of the first power line 200 and the second power line 300 (e.g., spider line) (see...) Figure 4 The SPL can be covered by either the first power line 200 or the second power line 300.

[0083] In such an embodiment, the light-shielding pattern BM is arranged in the peripheral region PA, spaced apart from the display region DA, and partially overlaps with the second layer portion 220 of the first power line 200 and the second layer portion 320 of the second power line 300. Therefore, the display device can have a structure where the underlying wiring is not visible to the user in the peripheral region PA.

[0084] In such embodiments, the problem of uneven visibility of wiring caused by reflections from the underwire (spider web, etc.) is reduced, and display quality can be improved.

[0085] In one embodiment, a first power supply voltage may be applied to a first power supply line 200, and a second power supply voltage, different from the first power supply voltage, may be applied to a second power supply line 300. The first power supply line 200 and the second power supply line 300 are arranged spaced apart from each other and are electrically disconnected or electrically insulated from each other.

[0086] If the first power line 200 and the second power line 300 are spaced apart on the same plane and the lower wiring is not covered, the lower wiring may be identified as a spot due to external light reflection. Specifically, a portion of the first power line 200 and the second power line 300 are arranged in the peripheral area PA very close to the display area DA and may not be covered by the light-shielding pattern BM.

[0087] According to an embodiment of the present invention, the first power line 200 and the second power line 300 of the display device are adjacent to the display area DA, and the first power line 200 and the second power line 300 can overlap each other in the peripheral area PA not covered by the light-shielding pattern BM. Therefore, by reducing wiring non-uniformity that may be detected due to external light reflection, the display quality can be improved, and the curved area BA can be curved to minimize the non-display area, thereby providing a display device in which the display area DA is enlarged.

[0088] Figure 4 It is along Figure 3 The cross-sectional view taken from line I-I'. Figure 5 It is along Figure 3 The cross-sectional view taken from line II-II'. Figure 6 Is with Figure 1 A cross-sectional view of a portion corresponding to the pixels of a display device.

[0089] refer to Figures 1 to 6 An embodiment of the display device may include a substrate 100, a buffer layer 110, an active layer including an active pattern ACT of a thin-film transistor (TFT), a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a first source-drain conductive layer, a first through-hole insulating layer VIA1, a second source-drain conductive layer, a second through-hole insulating layer VIA2, a pixel defining layer PDL, a light-emitting structure 180, a thin-film encapsulation layer TFE, and a cover window CW.

[0090] Refer again Figure 4 and Figure 5 The substrate 100 may be provided, comprising a transparent or opaque insulating material. In one embodiment, for example, the substrate 100 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluoride-doped quartz substrate, a soda-lime glass substrate, or a non-alkali glass substrate. Alternatively, the substrate 100 may include a flexible transparent material such as a flexible transparent resin substrate (e.g., a polyimide substrate).

[0091] The buffer layer 110 can be disposed on the substrate 100.

[0092] The first insulating layer 120 may be disposed on the buffer layer 110. The first insulating layer 120 may include an inorganic insulating material. In one embodiment, for example, the first insulating layer 120 may include a silicon compound or a metal oxide, etc. The first insulating layer 120 may be formed by multiple layers or have a multilayer structure.

[0093] The first gate conductive layer may be disposed on the first insulating layer 120. The first gate conductive layer may include a first layer of spider lines SPL1. The first gate conductive layer may be formed using metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials.

[0094] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is disposed. The second insulating layer 130 may include an inorganic insulating material. In one embodiment, for example, the second insulating layer 130 may include a silicon compound or a metal oxide, etc. The second insulating layer 130 may be formed by multiple layers or have a multilayer structure. The second insulating layer 130 may cover the first gate conductive layer on the first insulating layer 120 and may be arranged to have a substantially constant or uniform thickness along the contour of the first gate conductive layer.

[0095] The second gate conductive layer can be disposed on the second insulating layer 130. The second gate conductive layer may include a second spider wire SPL2. The second gate conductive layer can be formed using metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials.

[0096] The first layer of spider lines SPL1 and the second layer of spider lines SPL2 can be alternately arranged in the plan view and spread out (fan-shaped) in the opposite direction to the second direction D2 to form spider line SPLs. Spider line SPLs can be signal wiring used to transmit signals from pads PAD to pixels PX. Spider line SPLs can be arranged between the substrate 100 and at least one line selected from the first power line 200 and the second power line 300.

[0097] The third insulating layer 140 may be disposed on the second insulating layer 130 on which the second gate conductive layer is disposed. The third insulating layer 140 may comprise inorganic or organic insulating materials. The third insulating layer 140 may be formed of multiple layers or have a multilayer structure.

[0098] The first source-drain conductive layer can be disposed on the third insulating layer 140. The first source-drain conductive layer may include a first layer portion 210 of the first power line 200 and a first layer portion 310 of the second power line 300. The first layer portion 210 of the first power line 200 and the first layer portion 310 of the second power line 300 may be spaced apart from each other. The first source-drain conductive layer may be formed using metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials.

[0099] The first via insulating layer VIA1 may be disposed on the third insulating layer 140 on which the first source / drain conductive layer is disposed. The first via insulating layer VIA1 may have a single-layer structure or a multilayer structure comprising at least two insulating films. The first via insulating layer VIA1 may be formed using an organic material. In one embodiment, for example, the first via insulating layer VIA1 may comprise at least one material selected from photoresist, acrylic resin, polyimide resin, polyamide resin, siloxane resin, and combinations thereof. In another embodiment, the first via insulating layer VIA1 may comprise an inorganic material such as a silicon compound, metal oxide, etc.

[0100] The second source / drain conductive layer can be disposed on the first via insulating layer VIA1. The second source / drain conductive layer may include a second layer portion 220 of the first power line 200 and a second layer portion 320 of the second power line 300. The second layer portion 220 of the first power line 200 and the second layer portion 320 of the second power line 300 may be spaced apart from each other. The second source / drain conductive layer can be formed using metals, alloys, metal nitrides, conductive metal oxides, or transparent conductive materials.

[0101] The second via insulating layer VIA2 can be disposed on the first via insulating layer VIA1 on which the second source / drain conductive layer is disposed. The second via insulating layer VIA2 can have a single-layer structure or a multilayer structure including at least two insulating films. The second via insulating layer VIA2 can be formed using organic materials. In one embodiment, for example, the second via insulating layer VIA2 can include at least one material selected from photoresist, acrylic resin, polyimide resin, polyamide resin, siloxane resin, and combinations thereof. In another embodiment, the second via insulating layer VIA2 can include inorganic materials such as silicon compounds, metal oxides, etc.

[0102] Although not shown, the second layer portion 220 of the first power line 200 can be connected to the first layer portion 210 of the first power line 200 through a contact hole defined through the first through-hole insulation layer VIA1. The second layer portion 320 of the second power line 300 can be connected to the first layer portion 310 of the second power line 300 through a contact hole defined through the first through-hole insulation layer VIA1.

[0103] In one embodiment, a portion of the second layer portion 220 of the first power line 200 may be arranged to overlap with a portion of the first layer portion 310 of the second power line 300. In such an embodiment, since the first power line 200 and the second power line 300 can be unspaced in the plan view, the spider web SPL (spider web surface layer) serving as the lower wiring of the first power line 200 and the second power line 300 is not exposed. Therefore, the non-uniformity of the wiring, which might be identifiable due to the reflection of external light by the spider web SPL, may not be perceived by the user, and display quality can be improved.

[0104] The cover window CW can be disposed on the second through-hole insulating layer VIA2 and the thin-film encapsulation layer TFE, and can include a light-shielding pattern BM. The light-shielding pattern BM can be disposed in the peripheral area PA. The light-shielding pattern BM can be spaced apart from the display area DA and partially overlap with the first power line 200 and the second power line 300. Therefore, the under-wiring can be covered, making under-wiring such as spider lines SPL invisible.

[0105] refer to Figure 6 In the display area DA, the buffer layer 110 can be disposed on the substrate 100.

[0106] A buffer layer 110 can be disposed over the entire substrate 100 in the display area DA. The buffer layer 110 can effectively prevent metal atoms and / or impurities from diffusing from the substrate 100 into the active layer. In such an embodiment, the buffer layer 110 can control the rate of heat transfer during the crystallization process used to form the active layer, thereby obtaining a substantially uniform active layer.

[0107] An active layer may be disposed on buffer layer 110. The active layer may comprise amorphous silicon or polycrystalline silicon. In embodiments, the active layer may comprise an oxide of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The active layer may comprise a drain region and a source region doped with impurities, and a channel region located between the drain region and the source region.

[0108] The first insulating layer 120 may be disposed on the buffer layer 110 and the active layer on the buffer layer 110. The first insulating layer 120 covers the active layer on the buffer layer 110 and may be arranged to have a substantially constant or uniform thickness along the contour of the active layer.

[0109] A first gate conductive layer may be disposed on a first insulating layer 120. The first gate conductive layer may further include a gate electrode GE of a thin-film transistor (TFT). The gate electrode GE may be disposed to overlap with the channel region of the active layer.

[0110] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is disposed.

[0111] A second gate conductive layer may be disposed on the second insulating layer 130. The second gate conductive layer may further include a storage electrode STE. The storage electrode STE may overlap with the gate electrode GE to form a storage capacitor Cst together with the second insulating layer 130 therebetween.

[0112] The third insulating layer 140 may be disposed on the second insulating layer 130 and the second gate conductive layer on the second insulating layer 130.

[0113] The first source-drain conductive layer may be disposed on the third insulating layer 140. The first source-drain conductive layer may further include the source electrode SE and the drain electrode DE of the thin-film transistor TFT.

[0114] The first through-hole insulating layer VIA1 can be disposed on the third insulating layer 140 on which the first source and drain conductive layers are disposed.

[0115] The second source / drain conductive layer can be disposed on the first via insulating layer VIA1. The second source / drain conductive layer may further include contact pads CP.

[0116] The second via insulating layer VIA2 can be disposed on the first via insulating layer VIA1 on which the second source / drain conductive layer is disposed.

[0117] The light-emitting structure 180 may include a pixel electrode 181, a light-emitting layer 182, and a counter electrode 183.

[0118] Pixel electrode 181 may be disposed on the second via insulating layer VIA2. Pixel electrode 181 may be electrically connected to contact pad CP through a contact hole defined through the second via insulating layer VIA2. Depending on the emission type of the display device, pixel electrode 181 may include a reflective or transmissive material. In one embodiment, for example, pixel electrode 181 may include a transmissive or reflective material depending on the emission type of the display device. In one embodiment, for example, pixel electrode 181 may include at least one material selected from aluminum, aluminum-containing alloys, aluminum nitride, silver, silver-containing alloys, tungsten, tungsten nitride, copper, copper-containing alloys, nickel, chromium, chromium nitride, molybdenum, titanium-containing alloys, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, and indium zinc oxide. In embodiments, pixel electrode 181 may have a single-layer structure or a multi-layer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0119] A pixel defining layer (PDL) may be disposed on a second via insulating layer (VIA2) on which pixel electrodes 181 are disposed. The PDL may be formed using an organic material. In one embodiment, for example, the PDL may comprise at least one material selected from photoresist, acrylic resin, polyimide resin, polyamide resin, siloxane resin, and combinations thereof. In an embodiment, the opening exposing the pixel electrodes 181 may be formed by etching the PDL. The emitting and non-emitting regions of the display device may be defined by the openings in the PDL. In one embodiment, for example, a portion of the PDL containing the openings may correspond to the emitting region, and the non-emitting region may correspond to a portion adjacent to the openings in the PDL.

[0120] A light-emitting layer 182 may be disposed on a pixel electrode 181 exposed through an opening in the pixel defining layer PDL. In an embodiment, the light-emitting layer 182 may extend on the sidewall of the opening in the pixel defining layer PDL. In an embodiment, the light-emitting layer 182 may include an organic light-emitting layer, a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. In one embodiment, for example, the layers of the light-emitting layer 182 other than the organic light-emitting layer (i.e., the hole injection layer, hole transport layer, electron transport layer, and electron injection layer) may be formed together to correspond to multiple pixels. In an embodiment, multiple organic light-emitting layers may be formed using light-emitting materials for generating different colors of light, such as red, green, and blue, according to the color pixels of the display device. In an embodiment, the organic light-emitting layer of the light-emitting layer 182 may include multiple stacked light-emitting materials for generating red, green, and blue light, thereby emitting white light. Here, the elements of the light-emitting layer 182 are formed together to correspond to multiple pixels, and each pixel may be divided or defined by a color filter layer.

[0121] Counter electrode 183 may be disposed on pixel defining layer PDL and light-emitting layer 182. Depending on the emission type of the display device, counter electrode 183 may include a transmissive material or a reflective material. In one embodiment, for example, counter electrode 183 may include at least one material selected from aluminum, aluminum-containing alloys, aluminum nitride, silver, silver-containing alloys, tungsten, tungsten nitride, copper, copper-containing alloys, nickel, chromium, chromium nitride, molybdenum, titanium-containing alloys, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, indium zinc oxide, and combinations thereof. In embodiments, counter electrode 183 may also have a single-layer structure or a multi-layer structure, which may include a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and / or a transparent conductive film.

[0122] A thin-film encapsulation layer (TFE) can be disposed on the counter electrode 183. The TFE prevents moisture and oxygen from penetrating from the outside. The TFE may include organic and inorganic layers. The organic and inorganic layers may be stacked alternately and repeatedly on top of each other. In one embodiment, for example, the TFE may include a first inorganic layer, a second inorganic layer, and an organic layer between the first and second inorganic layers, but is not limited thereto. In an embodiment, a sealing substrate for blocking external air and moisture from penetrating into the display device may be provided instead of the TFE.

[0123] Although not in Figure 6 As shown, however, the cover window CW can be arranged on the thin-film encapsulation layer TFE.

[0124] Figure 7 This is a partial enlarged view of a display device according to an alternative exemplary embodiment of the present invention. Figure 8 It is along Figure 7 The cross-sectional view taken from line I-I'.

[0125] refer to Figure 7 and Figure 8 Apart from the overlapping structure of the first power line 200 and the second power line 300 in the peripheral area PA, the display device is... Figures 1 to 6 The display devices are basically the same. Figure 7 and Figure 8 The same or similar elements shown above utilize the same elements used to describe the above reference. Figures 1 to 6 The same reference numerals are used in the accompanying drawings of the described embodiments of the display device, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0126] In an embodiment, the display device may include a substrate 100, a buffer layer 110, a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a first source / drain conductive layer, a first via insulating layer VIA1, a second source / drain conductive layer, and a second via insulating layer VIA2.

[0127] The buffer layer 110 can be disposed on the substrate 100. The first insulating layer 120 can be disposed on the buffer layer 110.

[0128] The first gate conductive layer may be disposed on the first insulating layer 120. The first gate conductive layer may include a first layer of spider lines SPL1.

[0129] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is disposed.

[0130] The second gate conductive layer may be disposed on the second insulating layer 130. The second gate conductive layer may include a second spider wire SPL2.

[0131] The first layer of spider lines SPL1 and the second layer of spider lines SPL2 can be alternately arranged in the plan view and spread out in the opposite direction to the second direction D2 (spreading out in a fan shape) to form spider lines SPL.

[0132] The third insulating layer 140 may be disposed on the second insulating layer 130 on which the second gate conductive layer is disposed.

[0133] The first source-drain conductive layer may be disposed on the third insulating layer 140. The first source-drain conductive layer may include a first layer portion 210 of the first power line 200, an electrode 250, and a first layer portion 310 of the second power line 300.

[0134] The first through-hole insulating layer VIA1 can be disposed on the third insulating layer 140 on which the first source and drain conductive layers are disposed.

[0135] The second source / drain conductive layer may be disposed on the first via insulating layer VIA1. The second source / drain conductive layer may include the second layer portion 220 of the first power line 200 and the second layer portion 320 of the second power line 300.

[0136] In such an embodiment, electrode 250 may partially overlap with the second layer portion 220 of the first power line 200 and the second layer portion 320 of the second power line 300. Electrode 250 may be floating or in a floating state.

[0137] The second via insulating layer VIA2 can be disposed on the first via insulating layer VIA1 on which the second source / drain conductive layer is disposed.

[0138] Figure 9 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention. Figure 10 It is along Figure 9 The cross-sectional view taken from line I-I'.

[0139] refer to Figure 9 and Figure 10 Apart from the overlapping structure of the first power line 200 and the second power line 300 in the peripheral area PA, the display device is... Figures 1 to 6 The display devices are basically the same. Figure 9 and Figure 10 The same or similar elements shown above utilize the same elements used to describe the above reference. Figures 1 to 6 The same reference numerals are used in the accompanying drawings of the described embodiments of the display device, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0140] In an embodiment, the display device may include a substrate 100, a buffer layer 110, a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a first source / drain conductive layer, a first via insulating layer VIA1, a second source / drain conductive layer, a second via insulating layer VIA2, and a cover electrode CV.

[0141] The buffer layer 110 can be disposed on the substrate 100. The first insulating layer 120 can be disposed on the buffer layer 110.

[0142] The first gate conductive layer may be disposed on the first insulating layer 120. The first gate conductive layer may include a first layer of spider lines SPL1.

[0143] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is disposed.

[0144] The second gate conductive layer may be disposed on the second insulating layer 130. The second gate conductive layer may include a second spider wire SPL2.

[0145] The first layer of spider lines SPL1 and the second layer of spider lines SPL2 can be alternately set in the plan view and spread out in the opposite direction of the second direction D2 (spreading out in a fan shape) to form spider lines SPL.

[0146] The third insulating layer 140 may be disposed on the second insulating layer 130 on which the second gate conductive layer is disposed.

[0147] The first source-drain conductive layer may be disposed on the third insulating layer 140. The first source-drain conductive layer may include a first layer portion 210 of the first power line 200 and a first layer portion 310 of the second power line 300.

[0148] The first through-hole insulating layer VIA1 can be disposed on the third insulating layer 140 on which the first source and drain conductive layers are disposed.

[0149] The second source / drain conductive layer may be disposed on the first via insulating layer VIA1. The second source / drain conductive layer may include the second layer portion 220 of the first power line 200 and the second layer portion 320 of the second power line 300.

[0150] The second via insulating layer VIA2 can be disposed on the first via insulating layer VIA1 on which the second source / drain conductive layer is disposed.

[0151] The cover electrode CV can be disposed on the second through-hole insulating layer VIA2. The cover electrode CV can be disposed on the portion of the first layer portion 210 of the first power line 200 and the first layer portion 310 of the second power line 300 that are spaced apart from each other. The cover electrode CV can partially overlap with the second layer portion 220 of the first power line 200 and the second layer portion 320 of the second power line 300.

[0152] Cover electrode CV can be used with pixel electrode (see Figure 6 (181) are arranged in the same layer and may include the same material as the pixel electrode.

[0153] Figure 11 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention. Figure 12 It is along Figure 11 The cross-sectional view taken from line I-I'.

[0154] refer to Figure 11 and Figure 12 Apart from the overlapping structure of the first power line 200 and the second power line 300 in the peripheral area PA, the display device is... Figures 1 to 6 The display devices are basically the same. Figure 11 and Figure 12 The same or similar elements shown above utilize the same elements used to describe the above reference. Figures 1 to 6 The same reference numerals are used in the accompanying drawings of the described embodiments of the display device, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0155] The display device may include a substrate 100, a buffer layer 110, a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a first source / drain conductive layer, a first via insulating layer VIA1, a second source / drain conductive layer, and a second via insulating layer VIA2.

[0156] The buffer layer 110 can be disposed on the substrate 100. The first insulating layer 120 can be disposed on the buffer layer 110.

[0157] The first gate conductive layer may be disposed on the first insulating layer 120. The first gate conductive layer may include a first layer of spider lines SPL1.

[0158] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the first gate conductive layer is disposed.

[0159] The second gate conductive layer may be disposed on the second insulating layer 130. The second gate conductive layer may include a second spider wire SPL2.

[0160] The first layer of spider lines SPL1 and the second layer of spider lines SPL2 can be alternately arranged in the plan view and spread out in the opposite direction to the second direction D2 (spreading out in a fan shape) to form spider lines SPL.

[0161] The third insulating layer 140 may be disposed on the second insulating layer 130 on which the second gate conductive layer is disposed.

[0162] The first source-drain conductive layer may be disposed on the third insulating layer 140. The first source-drain conductive layer may include a first layer portion 210 of the first power line 200 and a first layer portion 310 of the second power line 300.

[0163] The first through-hole insulating layer VIA1 can be disposed on the third insulating layer 140 on which the first source and drain conductive layers are disposed.

[0164] The second source / drain conductive layer can be disposed on the first via insulating layer VIA1. The second source / drain conductive layer may include the second layer portion 220 of the first power line 200, the electrode 260, and the second layer portion 320 of the second power line 300.

[0165] Here, electrode 260 may partially overlap with the first layer portion 210 of the first power line 200 and the first layer portion 310 of the second power line 300. Electrode 260 may be floating or in a floating state.

[0166] The second via insulating layer VIA2 can be disposed on the first via insulating layer VIA1 on which the second source / drain conductive layer is disposed.

[0167] Figure 13 This is a partial enlarged view of a display device according to another alternative exemplary embodiment of the present invention. Figure 14 It is along Figure 13 The cross-sectional view taken from line I-I'.

[0168] refer to Figure 13 and Figure 14 In addition to the display device further including a cover electrode CV, the display device and Figures 1 to 6 The display devices are basically the same. Figure 13 and Figure 14 The same or similar elements shown above utilize the same elements used to describe the above reference. Figures 1 to 6 The same reference numerals are used in the accompanying drawings of the described embodiments of the display device, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0169] The display device may include a substrate 100, a buffer layer 110, a first insulating layer 120, a first gate conductive layer, a second insulating layer 130, a second gate conductive layer, a third insulating layer 140, a first source / drain conductive layer, a first via insulating layer VIA1, a second source / drain conductive layer, a second via insulating layer VIA2, and a cover electrode CV.

[0170] A cover electrode CV can be disposed on the portion where the second layer portion 220 of the first power line 200 extends to overlap with the first layer portion 310 of the second power line 300. The first power line 200 and the second power line 300 can partially overlap each other. The cover electrode CV can be associated with a pixel electrode (see [link to pixel electrode]). Figure 6 The 181) are arranged in the same layer and include the same material as the pixel electrode.

[0171] Meanwhile, in other embodiments (e.g., the above references) Figure 7 , Figure 9 , Figure 11 In the embodiments described above, a covering electrode may be further provided.

[0172] Figure 15 This is a partial enlarged view of a display device according to an exemplary embodiment of the present invention. Figure 16 It is along Figure 15 The cross-sectional view taken from line I-I'. Figure 17 Is with Figure 15 A cross-sectional view of a portion corresponding to the pixels of a display device.

[0173] refer to Figures 15 to 17 In the peripheral region PA, the display device may include: a substrate 100, a buffer layer 110, a first insulating layer 120, a gate conductive layer including spider lines SPL, a second insulating layer 130, a source / drain conductive layer including a first power line 200 and a second power line 300, a via insulating layer VIA, and a cover electrode CV.

[0174] The buffer layer 110 can be disposed on the substrate 100.

[0175] The first insulating layer 120 can be arranged on the buffer layer 110.

[0176] The gate conductive layer, including the spider wire SPL, can be disposed on the first insulating layer 120.

[0177] The second insulating layer 130 may be disposed on the first insulating layer 120 on which the gate conductive layer is disposed.

[0178] The source and drain conductive layers, including the first power line 200 and the second power line 300, can be arranged on the second insulating layer 130.

[0179] The via insulating layer (VIA) can be placed on the source / drain conductive layer.

[0180] The cover electrode CV can be disposed on the through-hole insulating layer VIA. The cover electrode CV can be disposed on the portion of the first power line 200 and the second power line 300 that are separated from each other, and partially cover the first power line 200 and the second power line 300.

[0181] In the display area DA, the display device may include a substrate 100, a buffer layer 110, an active layer including an active pattern ACT of a thin-film transistor TFT, a first insulating layer 120, a gate conductive layer including a gate electrode GE of a thin-film transistor TFT, a second insulating layer 130, a source-drain conductive layer including a source electrode SE and a drain electrode DE of a thin-film transistor TFT, a via insulating layer VIA, a pixel defining layer PDL, a light-emitting structure 180 including a pixel electrode 181, a light-emitting layer 182 and a counter electrode 183, and a thin-film encapsulation layer TFE.

[0182] In an embodiment, the pixel electrode 181 and the cover electrode CV may be arranged in the same layer and comprise the same material as each other.

[0183] Figure 18 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Figure 19A This diagram illustrates a device implemented as a television set. Figure 18 A diagram illustrating an exemplary embodiment of an electronic device. Figure 19B This diagram illustrates what is implemented as a smartphone. Figure 18 A diagram illustrating an exemplary embodiment of an electronic device.

[0184] refer to Figures 18 to 19B Embodiments of electronic device 500 may include processor 510, storage device 520, storage device 530, input / output (“I / O”) device 540, power supply 550, and display device 560. In such embodiments, display device 560 may be connected to… Figure 1 Corresponding to the display device. In such an embodiment, the electronic device 500 may further include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc. In an embodiment, such as Figure 19A As shown, the electronic device 500 can be implemented as a television set. In alternative embodiments, such as Figure 19B As shown, electronic device 500 can be implemented as a smartphone. However, electronic device 500 is not limited to this. In one embodiment, for example, electronic device 500 can be implemented as a cellular phone, video phone, smartpad, smartwatch, tablet PC (“PC”), car navigation system, computer monitor, portable computer, head-mounted display (“HMD”), etc.

[0185] Processor 510 can perform various computing functions. Processor 510 can be a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), etc. In embodiments, processor 510 can be coupled to other components via address buses, control buses, data buses, etc. In embodiments, processor 510 can be coupled to an expansion bus such as a peripheral component interconnect (“PCI”) bus. Storage device 520 can store data for the operation of electronic device 500. In one embodiment, for example, storage device 520 may include at least one non-volatile storage device (e.g., an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.), and / or at least one volatile storage device (e.g., a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.). Storage device 530 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. I / O device 540 may include input devices such as a keyboard, keypad, mouse device, touchpad, touch screen, etc., and output devices such as a printer, speaker, etc. Power supply 550 can provide power for the operation of electronic equipment 500.

[0186] Display device 560 can be coupled to other components via a bus or other communication link. In an embodiment, display device 560 may be included in I / O device 540. In such an embodiment, as described above, the first power line and the second power line of display device 560 may be adjacent to the display area and have a structure that overlaps with each other in the peripheral area not covered by the light-shielding pattern. Therefore, display non-uniformity can be improved by reducing wiring non-uniformity caused by reflection of external light, and non-display areas can be minimized by bending the curved areas, thereby providing a display device in which the display area is expanded. In such an embodiment, any repeated detailed descriptions of elements that are the same as or similar to the elements of the display device described above will be omitted.

[0187] The embodiments of the present invention can be applied to organic light-emitting display devices and various electronic devices including organic light-emitting display devices, such as mobile phones, smartphones, video phones, smart panels, smartwatches, tablet PCs, car navigation systems, televisions, computer monitors, and portable computers.

[0188] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, comprising: A substrate includes a display area and a peripheral area, wherein the peripheral area is a non-display area and is arranged adjacent to the display area; The first conductive layer includes a first layer portion of a first power line and a first layer portion of a second power line disposed in the peripheral region on the substrate. The second conductive layer includes a second layer portion of the first power line and a second layer portion of the second power line disposed in the peripheral region on the substrate. as well as Covering electrodes are disposed on the first layer portion of the first power line and the first layer portion of the second power line to cover the portions of the first layer portion of the first power line and the first layer portion of the second power line that are spaced apart from each other. The second layer portion of the first power line overlaps with the first layer portion of the first power line and is electrically connected to the first layer portion of the first power line. The second layer portion of the second power line overlaps with the first layer portion of the second power line and is electrically connected to the first layer portion of the second power line. A portion of the first power line and a portion of the second power line overlap each other.

2. The display device according to claim 1, wherein A first power supply voltage is applied to the first power supply line, and A second power supply voltage, different from the first power supply voltage, is applied to the second power supply line.

3. The display device according to claim 1, further comprising: A first through-hole insulating layer is disposed between the first conductive layer and the second conductive layer, and The first through-hole insulating layer comprises an organic insulating material.

4. The display device according to claim 3, wherein a portion of the second layer portion of the first power line overlaps with a portion of the first layer portion of the second power line.

5. The display device according to claim 1, further comprising: Pixel electrodes are disposed on the substrate in the display area; The light-emitting layer is located on the pixel electrode; as well as The counter electrode is located on the light-emitting layer, and The cover electrode and the pixel electrode are arranged in the same layer and include the same material as the pixel electrode.

6. The display device according to claim 1, further comprising: Covering the window, including a light-blocking pattern arranged in the peripheral area, When viewed from a plan view, the light-blocking pattern is spaced apart from the display area, and The light-shielding pattern partially overlaps with the first power line and the second power line.

7. The display device according to claim 1, further comprising: Spider wires are arranged in the peripheral region on the substrate. The spider wire is arranged between the substrate and at least one wire selected from the first power line and the second power line.

8. The display device according to claim 7, wherein The spider web comprises a first layer of spider web and a second layer of spider web, and The display device further includes an insulating layer disposed between the first layer of spider webs and the second layer of spider webs.

9. The display device according to claim 1, further comprising: An active pattern is arranged in the display area on the substrate. The gate electrode overlaps with the active pattern; as well as The storage electrode overlaps with the gate electrode, and The first conductive layer further includes a source electrode and a drain electrode electrically connected to the active pattern. The second conductive layer further includes contact pads. The display device further includes: Pixel electrodes are disposed in the display area and electrically connected to the contact pads; A light-emitting layer is located on the pixel electrode; and The electrodes are arranged on the light-emitting layer.

10. A display device, comprising: A substrate includes a display area and a peripheral area, wherein the peripheral area is a non-display area and is arranged adjacent to the display area; A light-emitting structure is arranged in the display area on the substrate. A first power line is disposed in the peripheral region on the substrate, wherein the first power line supplies a first power voltage to the light-emitting structure. A second power line is disposed in the peripheral region on the substrate, wherein the second power line supplies a second power voltage to the light-emitting structure. as well as The electrodes overlap with portions of the first power line and the second power line that are spaced apart from each other.

11. The display device according to claim 10, wherein the electrode is floated.

12. The display device according to claim 10, wherein The light-emitting structure includes a pixel electrode, a light-emitting layer located on the pixel electrode, and a counter electrode located on the light-emitting layer. The electrode is arranged in the same layer as the pixel electrode and comprises the same material as the pixel electrode.

13. The display device according to claim 10, wherein The first power line includes a first layer portion and a second layer portion that overlaps with and is electrically connected to the first layer portion. The second power line includes a first layer portion and a second layer portion that overlaps with and is electrically connected to the first layer portion of the second power line. The first layer portion of the first power line and the first layer portion of the second power line are defined by a first conductive layer and comprise the same material as each other. The second layer portion of the first power line and the second layer portion of the second power line are defined by a second conductive layer and comprise the same material as each other.

14. The display device of claim 13, wherein the electrode is defined by the first conductive layer or the second conductive layer.

15. The display device according to claim 14, wherein The electrode is defined by the second conductive layer and partially overlaps with the first layer portion of the first power line and the first layer portion of the second power line, or The electrode is defined by the first conductive layer and partially overlaps with the second layer portion of the first power line and the second layer portion of the second power line.

16. The display device according to claim 10, further comprising: Covering the window, including a light-blocking pattern arranged in the peripheral area, When viewed from a plan view, the light-blocking pattern is spaced apart from the display area, and The light-shielding pattern partially overlaps with the first power line and the second power line.

17. The display device according to claim 10, further comprising: Spider wires are arranged in the peripheral region on the substrate, and The spider wire is arranged between the substrate and at least one wire selected from the first power line and the second power line.

18. The display device according to claim 17, wherein The spider web comprises a first layer of spider web and a second layer of spider web, and The display device further includes an insulating layer disposed between the first layer of spider webs and the second layer of spider webs.

Images