Semiconductor packaging structure and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor packaging structure and a manufacturing method thereof. A specific embodiment of the semiconductor packaging structure includes: a circuit substrate having a first surface and a second surface opposite to the first surface, a first packaging layer disposed on the first surface, including a first electronic component and a first packaging material, and a first buffer layer disposed between the first surface and the first packaging layer, wherein the thermal expansion coefficient CTE of the circuit substrate is greater than the CTE of the first packaging layer, and the CTE of the first buffer layer is greater than the CTE of the first packaging material. The semiconductor packaging structure can reduce warping.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] With the increasing demand for miniaturization, multi-function and high efficiency of electronic product systems, the requirements for small, thin and light electronic components and high-density packaging of systems are also increasing.

[0003] During the semiconductor packaging manufacturing process, various high-temperature manufacturing processes may be included, and the components may be in a high-temperature state. For example, in the process where the plastic packaging material is cured into a thermosetting plastic by heating to overmold the component, the semi-solid and solid plastics are in a high-temperature state. When the components are in a high-temperature environment, the components formed by different materials may have different coefficients of thermal expansion (CTE), which may cause warping due to CTE mismatch between the components, resulting in delamination at the interface between the components. Summary of the invention

[0004] The present disclosure provides a semiconductor package structure and a method for manufacturing the same.

[0005] In a first aspect, the present disclosure provides a semiconductor packaging structure, which includes: a circuit substrate having a first surface and a second surface opposite to the first surface; a first packaging layer, arranged on the first surface, including a first electronic component and a first packaging material; a first buffer layer, arranged between the first surface and the first packaging layer; wherein the coefficient of thermal expansion CTE of the circuit substrate is greater than the CTE of the first packaging layer, and the CTE of the first buffer layer is greater than the CTE of the first packaging material.

[0006] In some optional embodiments, it further includes: a second packaging layer, which is disposed on the second surface and includes a second electronic component and a second packaging material, wherein the CTE of the first packaging layer is smaller than the CTE of the second packaging layer.

[0007] In some optional embodiments, the present invention further includes: a second buffer layer disposed between the second surface and the second encapsulation layer, and a CTE of the second buffer layer is a negative value.

[0008] In some optional implementations, the second buffer layer is closer to the edge of the circuit substrate than the first buffer layer.

[0009] In some optional embodiments, the circuit substrate further has a third surface, a fourth surface, a fifth surface and a sixth surface adjacent to the first surface, and the second buffer layer is coplanar with at least one of the third surface, the fourth surface, the fifth surface and the sixth surface.

[0010] In some optional implementations, the first buffer layer is embedded in the circuit substrate and the first packaging material.

[0011] In some optional embodiments, the volume of a portion of the first buffer layer embedded in the circuit substrate is less than or equal to the volume of a portion of the first buffer layer embedded in the first packaging material.

[0012] In some optional embodiments, a height of a portion of the first buffer layer embedded in the circuit substrate is less than or equal to a height of a portion of the first buffer layer embedded in the first packaging material.

[0013] In some optional implementations, the second buffer layer is embedded in the circuit substrate and the second packaging material.

[0014] In some optional embodiments, the volume of a portion of the second buffer layer embedded in the circuit substrate is less than or equal to the volume of a portion of the second buffer layer embedded in the second packaging material.

[0015] In some optional embodiments, a height of a portion of the second buffer layer embedded in the circuit substrate is less than or equal to a height of a portion of the second buffer layer embedded in the second packaging material.

[0016] In some optional embodiments, the semiconductor packaging structure further includes: a first circuit layer, disposed on the first packaging layer; and a second circuit layer, disposed on the second packaging layer.

[0017] In some optional embodiments, the semiconductor packaging structure further includes: a conductive connector disposed on the first surface.

[0018] In some optional embodiments, the radial cross-section of the first buffer layer and the second buffer layer is any one of a semicircle, a rectangle, a square, a trapezoid, and a triangle.

[0019] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor packaging structure, the method comprising: providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to the first surface; forming a first buffer layer on the first surface; forming a first packaging layer on the first surface, covering the first buffer layer; forming a second buffer layer on the second surface, wherein the second buffer layer is closer to an edge of the circuit substrate relative to the first buffer layer; forming a second packaging layer on the second surface, covering the second buffer layer, wherein the CTE of the circuit substrate is greater than the CTE of the first packaging layer, and the CTE of the first buffer layer is greater than the CTE of the first packaging material.

[0020] In some optional embodiments, forming a first buffer layer on the first surface includes: drilling a hole in the first surface to form a first cavity; forming the first buffer layer in the first cavity so that the first buffer layer is embedded in the circuit substrate and the first packaging material.

[0021] In some optional embodiments, the method further includes: drilling a hole in the first packaging layer to form a first through hole; plating metal on the first packaging layer to fill the first through hole and form a first circuit layer.

[0022] In some optional embodiments, the method further includes: forming a second buffer layer on the second surface.

[0023] In some optional embodiments, forming a second buffer layer on the second surface includes: drilling a hole in the second surface to form a second cavity; forming the second buffer layer in the second cavity so that the second buffer layer is embedded in the circuit substrate and the second packaging material.

[0024] In some optional embodiments, the method further includes: placing a second electronic component on the second surface and electrically connecting the second electronic component to the circuit substrate; injecting a second packaging material into the second surface to cover the second electronic component to form a second packaging layer.

[0025] In some optional embodiments, the method further includes: drilling a hole in the second packaging layer to form a second through hole; plating metal on the second packaging layer to fill the second through hole and form a second circuit layer.

[0026] In some optional embodiments, the method further includes: electrically connecting the conductive connector to the electrical contact point of the circuit substrate.

[0027] In order to solve the problems of warping and delamination caused by CTE mismatch of the overall structure in the semiconductor packaging structure or the semiconductor double-sided packaging structure in the prior art, the semiconductor packaging structure and the manufacturing method provided by the present disclosure adopt materials with different CTEs to combine so that the CTE of the semiconductor packaging structure is adapted to avoid warping and delamination. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0029] Figure 1 is a structural schematic diagram of an embodiment of a semiconductor package structure according to the present disclosure;

[0030] Figure 2 is a structural schematic diagram of another embodiment of a semiconductor package structure according to the present disclosure;

[0031] Figure 3A is a structural schematic diagram of another embodiment of a semiconductor package structure according to the present disclosure;

[0032] Figure 3B yes Figure 3AA schematic structural diagram of an optional implementation of the first buffer layer and the second buffer layer in the embodiment;

[0033] Figure 4 is a structural schematic diagram of another embodiment of a semiconductor package structure according to the present disclosure;

[0034] Figure 5 is a structural schematic diagram of another embodiment of a semiconductor package structure according to the present disclosure;

[0035] Figure 6 is a structural schematic diagram of another embodiment of a semiconductor package structure according to the present disclosure;

[0036] FIG. 7A to FIG. 7N yes Figure 6 A schematic structural diagram of a semiconductor package structure during the manufacturing process of an embodiment.

[0037] Explanation of symbols:

[0038] 10-circuit substrate, 11-first buffer layer, 12-first packaging layer, 12a-first electronic component, 12b-first packaging material, 13-second packaging layer, 13a-second electronic component, 13b-second packaging material, 14-second buffer layer, 15-first circuit layer, 16-second circuit layer, 17-conductive connector, 18-first cavity, 19-second cavity, 20-first through hole, 21-second through hole. DETAILED DESCRIPTION

[0039] The specific implementation methods of the present disclosure are described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant inventions, rather than to limit the inventions. In addition, for ease of description, only the parts related to the relevant inventions are shown in the accompanying drawings.

[0040] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present disclosure, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present disclosure, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present disclosure. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present disclosure without substantially changing the technical content.

[0041] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of an embodiment of a semiconductor packaging structure according to the present disclosure is shown. The semiconductor packaging structure 100 may include a circuit substrate 10, a first packaging layer 12, and a first buffer layer 11. The circuit substrate 10 may have a first surface and a second surface opposite to the first surface. The first packaging layer 12 may be disposed on the first surface and may include a first electronic component 12a and a first packaging material 12b. The first buffer layer 11 may be disposed between the first surface and the first packaging layer 12. The CTE of the circuit substrate 10 may be greater than the CTE of the first packaging layer 12, and the CTE of the first buffer layer 11 may be greater than the CTE of the first packaging material 12b.

[0042] The circuit substrate 10 may be a redistribution layer including at least one conductive trace.

[0043] The first packaging material 12b may be an organic material, for example, it may include silicon filler, epoxy resin and other additives. In some optional embodiments, the first packaging material 12b includes: 70-85% inorganic filler (silica filler), 15-25% resin and other additives such as hardener, release agent, colorant, stress relaxant, flame retardant, etc.

[0044] The first electronic component 12a may be an active component, such as a chip, etc., or may be a passive component, such as a capacitor, an inductor, a resistor, etc. Here, there may be at least one first electronic component 12a.

[0045] The first buffer layer 11 may be made of an organic material, such as epoxy resin, polyimide, BT resin (Bismaleimide Triazine Resin), etc., or may be made of an inorganic material, such as silicon dioxide (quartz), glass, etc.

[0046] In some optional embodiments, the radial cross-section of the first buffer layer 11 can be any one of a semicircular shape, a rectangular shape, a square shape, a trapezoid shape, and a triangle shape.

[0047] The semiconductor packaging structure 100 is provided with a first buffer layer 11 between the first surface and the first packaging layer 12, wherein the CTE of the first buffer layer 11 is greater than the CTE of the first packaging material 12b or the CTE of the first buffer layer 11 is less than the CTE of the first packaging layer 12, wherein the CTE of the first packaging layer 12 may be the equivalent CTE of the first electronic component 12a and the first packaging material 12b combined, thereby reducing the degree of CTE mismatch of the semiconductor packaging structure 100 caused by the CTE of the circuit substrate 10 being greater than the CTE of the first packaging layer 12.

[0048] In the case of temperature changes, the volume of each component of the semiconductor package structure 100 may expand or shrink, resulting in deformation. For example, during the cooling process or at room temperature, if the CTE of the first packaging material 12b is less than the CTE of the circuit substrate 10, the semiconductor package structure 100 (excluding the first buffer layer 11) will bend downward relative to the central axis. At this time, the first buffer layer 11 can be provided between the first surface and the first packaging layer 12 to improve the CTE matching degree of the semiconductor package structure 100, so that the deformation amount of each component of the semiconductor package structure 100 is matched and the stress is balanced, thereby reducing the possible warping degree of the semiconductor package structure 100.

[0049] Continue to refer Figure 2 , relative to Figure 1 The semiconductor package structure 100, Figure 2 A semiconductor double-sided packaging structure is shown. The semiconductor packaging structure 200 may further include: a second packaging layer 13. The second packaging layer 13 may be disposed on the second surface, including a second electronic component 13a and a second packaging material 13b. The CTE of the first packaging layer 12 may be smaller than the CTE of the second packaging layer 13.

[0050] The second encapsulation material 13 b may be an organic material, such as epoxy resin, polyimide, BT resin, etc. The first encapsulation material 12 b and the second encapsulation layer 13 may be the same.

[0051] The second electronic component 13a may be an active component, such as a chip, etc., or a passive component, such as a capacitor, an inductor, a resistor, etc. Here, the second electronic component 13a may be at least one. The first electronic component 12a and the second electronic component 13a may be different.

[0052] The semiconductor package structure 200 can reduce the degree of CTE mismatch of the semiconductor package structure 200 caused by the CTE of the first package layer 12 being smaller than the CTE of the second package layer 13 by disposing the first buffer layer 11 between the first surface and the first package layer 12 .

[0053] In the event of temperature changes, the volume of each component of the semiconductor packaging structure 200 may expand or shrink, resulting in deformation. The semiconductor packaging structure 200 improves the CTE matching of the semiconductor packaging structure 200 by setting a first buffer layer 11 between the first surface and the first packaging layer 12, so that the deformation of each component of the semiconductor packaging structure 200 is matched and the stress is balanced, thereby reducing the degree of warping that may occur in the semiconductor packaging structure 200.

[0054] Continue to refer Figure 3A , relative to Figure 2The semiconductor package structure 200 of the present invention may further include: a second buffer layer 14. The circuit substrate 10 may further include a third surface, a fourth surface, a fifth surface, and a sixth surface adjacent to the first surface. The second buffer layer 14 may be disposed between the second surface and the second package layer 13, and may extend to the third surface, the fourth surface, the fifth surface, and the sixth surface, wherein the CTE of the second buffer layer 14 may be a negative value.

[0055] The second buffer layer 14 can be made of a material with a negative CTE, such as a composite material or a structural material with a negative CTE. A material with a negative CTE (such as graphene -8ppm / C to -10ppm / C) can be made into fibers, and then mixed into a material with a lower CTE value (such as PET: 2ppm / C to 4ppm / C, PVC: 3ppm / C to 5ppm / C) according to a preset ratio to prepare a composite material with a negative CTE. A porous structural material (such as ZrW2O8: -5ppm / C to -9ppm / C or BNFO (egBiNi1-xFexO3) can also be made into nanoparticles, which are then dissolved in an organic solvent and coated on the surface of the object and sintered at low temperature to prepare a structural material with a negative CTE.

[0056] In some optional embodiments, the radial cross-section of the second buffer layer 14 can be any one of a semicircular shape, a rectangular shape, a square shape, a trapezoid shape, and a triangle shape.

[0057] The semiconductor package structure 300 can further reduce the degree of CTE mismatch of the semiconductor package structure 300 caused by the CTE of the first package layer 12 being smaller than the CTE of the second package layer 13 by disposing the second buffer layer 14 between the second surface and the second package layer 13 .

[0058] In the event of temperature changes, the volume of each component of the semiconductor packaging structure 300 may expand or shrink, resulting in deformation. The semiconductor packaging structure 300 improves the CTE matching of the semiconductor packaging structure 300 by setting a second buffer layer 14 between the second surface and the second packaging layer 13, so that the deformation of each component of the semiconductor packaging structure 300 is matched and the stress is balanced, thereby reducing the degree of warping that may occur in the semiconductor packaging structure 300.

[0059] Please refer to Figure 3B , Figure 3B yes Figure 3A A schematic diagram of the structure of an optional implementation of the first buffer layer and the second buffer layer in the embodiment. Figure 3BAs shown, in some optional embodiments, the second buffer layer 14 can be disposed closer to the edge of the circuit substrate 10 than the first buffer layer 11 , which can further reduce the warping degree of the semiconductor package structure 300 .

[0060] In some optional embodiments, the side surface of the second buffer layer 14 may be substantially aligned or substantially coplanar with at least one of the third surface, the fourth surface, the fifth surface, and the sixth surface of the semiconductor package structure 300. In the bottom view, the second buffer layer 14 is coplanar with the third surface, the fourth surface, the fifth surface, and the sixth surface of the semiconductor package structure 300. Here, the coplanarity may be substantially aligned or substantially coplanar.

[0061] like Figure 3B As shown, in some optional embodiments, the first buffer layer 11 and the second buffer layer 14 may be designed in a ring shape, and may be a closed ring or disposed at intervals.

[0062] Continue to refer Figure 4 , relative to Figure 3A In the semiconductor package structure 300 , the first buffer layer 11 in the semiconductor package structure 400 may be embedded in the circuit substrate 10 and the first packaging material 12 b.

[0063] In some optional embodiments, the volume of the portion of the first buffer layer 11 embedded in the circuit substrate 10 is less than or equal to the volume of the portion of the first buffer layer 11 embedded in the first packaging material 12b. Since the coefficient of thermal expansion CTE of the circuit substrate 10 may be greater than the CTE of the first packaging layer 12, the volume of the portion of the first buffer layer 11 embedded in the circuit substrate 10 is less than or equal to the volume of the portion of the first buffer layer 11 embedded in the first packaging material 12b, which can better balance the deformation degree of the first surface.

[0064] In some optional embodiments, the height of the portion of the first buffer layer 11 embedded in the circuit substrate 10 is less than or equal to the height of the portion of the first buffer layer 11 embedded in the first packaging material 12 b .

[0065] The semiconductor packaging structure 400 can further enhance the adhesion between the circuit substrate 10 and the first packaging material 12 by embedding the first buffer layer 11 between the circuit substrate 10 and the first packaging material 12b. In addition to resisting warping, it can also buffer the shear force generated at the interface between the first packaging material 12b and the circuit substrate 10 due to the warping of the semiconductor packaging structure 400.

[0066] Continue to refer Figure 5 , relative to Figure 4In the semiconductor package structure 400 , the second buffer layer 14 in the semiconductor package structure 500 may be embedded in the circuit substrate 10 and the second packaging material 13 b.

[0067] In some optional embodiments, the volume of the portion of the second buffer layer 14 embedded in the circuit substrate 10 is less than or equal to the volume of the portion of the second buffer layer 14 embedded in the second packaging material 13b. Since the coefficient of thermal expansion CTE of the circuit substrate 10 can be less than the CTE of the second packaging layer 13, and the CTE of the second buffer layer 14 is a negative value, the volume of the portion of the second buffer layer 14 embedded in the circuit substrate 10 is less than or equal to the volume of the portion of the second buffer layer 14 embedded in the second packaging material 13b, which can better balance the deformation degree of the second surface.

[0068] In some optional embodiments, the height of the portion of the second buffer layer 14 embedded in the circuit substrate 10 is less than or equal to the height of the portion of the second buffer layer 14 embedded in the second packaging material 13 b .

[0069] The semiconductor packaging structure 500 can further enhance the adhesion between the circuit substrate 10 and the second packaging material 13 by embedding the second buffer layer 14 into the circuit substrate 10 and the second packaging material 13b, and can provide shear force to resist warping, thereby further reducing the degree of warping that may occur in the semiconductor packaging structure 500, and can further avoid stratification at the interface between components (for example, between the second packaging material 13b and the circuit substrate 10).

[0070] Continue to refer Figure 6 , relative to Figure 5 The semiconductor package structure 500 and the semiconductor package structure 600 may further include: a first circuit layer 15 and a second circuit layer 16. The first circuit layer 15 is disposed on the first package layer 12; and the second circuit layer 16 is disposed on the second package layer 13.

[0071] In some optional implementations, the semiconductor package structure 600 may further include a conductive connection member 17. The conductive connection member 17 is disposed on the first surface. The conductive connection member 17 may be, for example, a solder ball.

[0072] In some optional implementations, the first packaging material 12 b may cover the conductive connector 17 and expose a portion of the conductive connector 17 for external connection.

[0073] In some optional implementations, the first packaging material 12 b may not cover the conductive connection member 17 , that is, the first packaging material 12 b exposes a portion of the first surface of the circuit substrate 10 .

[0074] In some optional implementations, the first packaging material 12 b may not cover the first buffer layer 11 and may be adjacent to the conductive connection member 17 .

[0075] The semiconductor package structure 600 is connected to other external devices by providing a first circuit layer 15 , a second circuit layer 16 and a conductive connection member 17 .

[0076] In some optional embodiments, the first circuit layer 15 and the second circuit layer 16 may be antenna patterns. The first buffer layer 11 and the second buffer layer 14 can reduce the warping degree of the semiconductor package structure 600 without affecting the default electromagnetic wave (electric field) radiation direction of the antenna pattern.

[0077] FIG. 7A to FIG. 7N yes Figure 6 A schematic diagram of a semiconductor package structure during manufacturing of an embodiment. In order to better understand various aspects of the present disclosure, the drawings have been simplified.

[0078] Please refer to Fig. 7A , providing a circuit substrate 10. The circuit substrate 10 has a first surface and a second surface opposite to the first surface. For example, the circuit substrate 10 may be a rewiring layer, and a through hole, a buried hole or a blind hole may be provided to realize the connection of each conductive trace to form the circuit substrate 10.

[0079] Please refer to Figure 7B , drilling a hole on the first surface to form a first cavity 18. Various processes can be used to drill a hole on the first surface to form the first cavity 18. For example, the first cavity 18 can be formed by laser drilling or photolithography.

[0080] Please refer to Figure 7C , drilling holes on the second surface to form a second cavity 19. Various processes can be used to drill holes on the second surface to form the second cavity 19. For example, the second cavity 19 can be formed by laser drilling or photolithography.

[0081] Please refer to Fig.7D , forming the first buffer layer 11 in the first cavity 18. Various processes may be used to form the first buffer layer 11 in the first cavity 18. For example, the first buffer layer 11 may be formed by injection molding.

[0082] Please refer to Fig. 7E , forming the second buffer layer 14 in the second cavity 19. Various processes may be used to form the second buffer layer 14 in the second cavity 19. For example, the second buffer layer 14 may be formed by injection molding.

[0083] Please refer to Figure 7F , placing a first electronic component 12 a on the first surface and electrically connecting the first electronic component 12 a to the circuit substrate 10 .

[0084] In some optional embodiments, the first electronic component 12a may be placed on the first surface and electrically connected to the circuit substrate 10, and then the first buffer layer 11 may be formed in the first cavity 18. In this way, the risk of the first electronic component 12a hitting the first buffer layer 11 due to process errors when picking and placing the first electronic component 12a can be avoided.

[0085] Please refer to Figure 7G , inject the first packaging material 12b into the first surface to cover the first electronic component 12a to form the first packaging layer 12. Various processes can be used to inject the first packaging material 12b into the first surface to cover the first electronic component 12a to form the first packaging layer 12. For example, a first mold can be placed on the first surface, the first packaging material 12b can be filled into the space formed by the first mold and the first surface to form the first packaging layer 12, and the first mold can be removed.

[0086] Please refer to Figure 7H , placing a second electronic component 13 a on the second surface and electrically connecting the second electronic component 13 a to the circuit substrate 10 .

[0087] In some optional embodiments, the second electronic component 13a may be placed on the second surface and electrically connected to the circuit substrate 10, and then the second buffer layer 14 may be formed in the second cavity 19. In this way, the risk of the second electronic component 13a hitting the second buffer layer 14 due to process errors when picking and placing the second electronic component 13a can be avoided.

[0088] Please refer to Fig.7I , inject the second packaging material 13b into the second surface to cover the second electronic component 13a to form the first packaging layer 12. Various processes can be used to inject the second packaging material 13b into the second surface to cover the second electronic component 13a to form the second packaging layer 13. For example, a second mold can be placed on the second surface, the second packaging material 13b can be filled into the space formed by the second mold and the second surface to form the second packaging layer 13, and the second mold can be removed.

[0089] Please refer to Figure 7J , drilling a hole in the first packaging layer 12 to form a first through hole 20. Various processes may be used to drill a hole in the first packaging layer 12 to form the first through hole 20. For example, the first through hole 20 may be formed by laser drilling or photolithography.

[0090] Please refer to Figure 7K, drilling a hole in the second packaging layer 13 to form a second through hole 21. Various processes may be used to drill a hole in the second packaging layer 13 to form the second through hole 21. For example, the second through hole 21 may be formed by laser drilling or photolithography.

[0091] Please refer to Figure 7L , metal is plated on the first encapsulation layer 12 to fill the first through hole 20, and the first circuit layer 15 is formed. For example, various processes can be used to plate metal on the first encapsulation layer 12 to fill the first through hole 20, and the first circuit layer 15 is formed. Specifically, metal is plated on the first encapsulation layer 12 to fill the first groove and form a first metal layer, a first photoresist layer is laminated on the first metal layer, and a first mask is placed on the first photoresist layer, and exposure, development, and etching are performed to remove the photoresist to form the first circuit layer 15.

[0092] Please refer to Figure 7M , metal is plated on the second encapsulation layer 13 to fill the second through hole 21, and the second circuit layer 16 is formed. For example, various processes can be used to plate metal on the second encapsulation layer 13 to fill the second through hole 21, and the second circuit layer 16 is formed. Specifically, metal is plated on the second encapsulation layer 13 to fill the second groove and form a second metal layer, a second photoresist layer is laminated on the second metal layer, and a second mask is placed on the second photoresist layer, and exposure, development, and etching are performed to remove the photoresist to form the second circuit layer 16.

[0093] Please refer to Figure 7N , electrically connecting the conductive connecting member 17 to the electrical contact point of the circuit substrate 10 .

[0094] In some optional embodiments, after the steps of placing a second electronic component 13a on the second surface of the circuit substrate 10, forming a second buffer layer 14 in the second cavity 19, and injecting a second packaging material 13b, a first electronic component 12a is placed on the first surface of the circuit substrate 10, a first buffer layer 11 is formed in the first cavity 18, and a first packaging material 12b is injected. In this way, since the second packaging material 13b completely covers the second surface of the circuit substrate 10, the lower surface of the second packaging material 13b is a continuous plane, so that the second packaging material 13b can be used as a carrier when the first surface of the circuit substrate 10 is packaged, which helps to improve the process yield of the steps of placing the first electronic component 12a, forming the first buffer layer 11, and injecting the first packaging material 12b.

[0095] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and that equivalent components may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction in the present disclosure and the actual device. There may be other embodiments of the present disclosure that are not specifically described. The specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the goals, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging structure, comprising: A circuit substrate having a first surface and a second surface opposite to the first surface; A first packaging layer, disposed on the first surface, comprising a first electronic component and a first packaging material; A first buffer layer, disposed between the first surface and the first encapsulation layer; A second packaging layer, disposed on the second surface, comprising a second electronic component and a second packaging material; A second buffer layer, disposed between the second surface and the second encapsulation layer; Among them, the coefficient of thermal expansion CTE of the circuit substrate is greater than the CTE of the first packaging layer, the CTE of the first buffer layer is greater than the CTE of the first packaging material, the CTE of the first packaging layer is less than the CTE of the second packaging layer, and the CTE of the second buffer layer is a negative value.

2. The semiconductor package structure according to claim 1, wherein: The second buffer layer is closer to the edge of the circuit substrate than the first buffer layer.

3. The semiconductor package structure according to claim 1, wherein: The circuit substrate further has a third surface, a fourth surface, a fifth surface and a sixth surface adjacent to the first surface, and the second buffer layer is coplanar with at least one of the third surface, the fourth surface, the fifth surface and the sixth surface.

4. The semiconductor package structure according to claim 1, wherein: The first buffer layer is embedded in the circuit substrate and the first packaging material, and the volume of a portion of the first buffer layer embedded in the circuit substrate is smaller than or equal to the volume of a portion of the first buffer layer embedded in the first packaging material.

5. The semiconductor package structure according to any one of claims 1 to 4, wherein: The second buffer layer is embedded in the circuit substrate and the second packaging material.

6. A method for manufacturing a semiconductor package structure, comprising: Providing a circuit substrate, wherein the circuit substrate has a first surface and a second surface opposite to the first surface; forming a first buffer layer on the first surface; forming a first encapsulation layer on the first surface, covering the first buffer layer; forming a second buffer layer on the second surface, wherein the second buffer layer is closer to the edge of the circuit substrate than the first buffer layer; A second encapsulation layer is formed on the second surface to cover the second buffer layer.

7. The method according to claim 6, wherein: The forming of a first buffer layer on the first surface comprises: Drilling a hole in the first surface to form a first cavity; The first buffer layer is formed in the first cavity so that the first buffer layer is embedded in the circuit substrate and the first packaging material.

8. The method according to claim 6 or 7, wherein: The forming of a second buffer layer on the second surface comprises: Drilling a hole in the second surface to form a second cavity; The second buffer layer is formed in the second cavity so that the second buffer layer is embedded in the circuit substrate and the second packaging material.

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