Hydrogen trap layer for display device and display device

Abstract

The present disclosure relates to a hydrogen trap layer for a display device and a display device. The present invention describes a display panel having a hydrogen trap layer. The hydrogen trap layer can be incorporated into a variety of locations to absorb or block hydrogen diffusion into a semiconductor oxide layer of an oxide transistor.

Description

[0001] Related patent applications

[0002] This patent application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 62 / 892,299, filed on August 27, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments described herein relate to display devices, and more particularly to the incorporation of hydrogen trap layers. Background Art

[0004] Display panels such as liquid crystal display (LCD) and organic light emitting diode (OLED) display panels are commonly found in electronic devices such as cellular phones, portable computers, televisions, wearable devices, etc. Both LCD and OLED technologies utilize thin film transistors (TFTs) to form pixel circuits or gate driver circuits (e.g., gate in panel) present within the display panel.

[0005] Conventional TFT technologies include amorphous silicon (a-Si) TFTs and low temperature polycrystalline silicon (LTPS) TFTs. LTPS offers greater charge carrier mobility than a-Si, which can be used to scale to high-resolution displays. However, the LTPS process can include a greater number of mask steps than the a-Si process.

[0006] Semiconductor oxide TFTs have been proposed as a new version of LTPS, which have higher charge carrier mobility than a-Si and fewer mask steps than the LTPS process. LTPS TFTs may have properties such as higher switching speed and drive current compared to semiconductor oxide TFTs, while semiconductor oxide TFTs may have properties such as lower leakage current and better TFT uniformity compared to LTPS TFTs.

[0007] Recently, LTPS transistors have been combined with semiconducting oxide TFTs in a hybrid TFT arrangement called low temperature polysilicon and oxide (LTPO). In this arrangement, the semiconducting oxide transistor can be any sub-pixel TFT including a switching TFT, a driving TFT, a buffer TFT, a demultiplexer TFT, etc. Summary of the invention

[0008] Display structures and methods of forming including hydrogen trap layers are described. In one embodiment, a display panel includes a gate-in-panel (GIP) region adjacent to an edge of the display panel and a pixel region containing a subpixel array. Each subpixel includes an oxide transistor including a transistor hydrogen trap layer formed of a transistor material characterized by a negative dissolution entropy of hydrogen. A dummy subpixel region is located between the GIP region and the pixel region, wherein the dummy subpixel region includes a plurality of dummy subpixels. In one embodiment, each dummy subpixel includes a dummy hydrogen trap layer formed of a dummy material characterized by a negative dissolution entropy of hydrogen. In such an embodiment, dummy subpixels or alternative structures may be used to block / absorb hydrogen diffusion from the edge of the display panel. Additional other structures may also be used to block / absorb hydrogen diffusion, including an intermediate wiring layer or a top layer (such as a touch metal wiring layer of a touch cell).

[0009] In one embodiment, a display panel includes a pixel region including an array of sub-pixels, each sub-pixel including an oxide transistor gate layer including a gate hydrogen trap layer. In one embodiment, a gate width of the gate layer is smallest for a sub-pixel closest to a center of the pixel region, and a gate width of the gate layer is widest for a sub-pixel closest to a periphery of the pixel region. In such an embodiment, the gate width may be modulated to adjust oxide transistor characteristics due to increased hydrogen diffusion from the edge of the display panel.

[0010] In one embodiment, a display panel includes a pixel region including an array of sub-pixels, wherein each sub-pixel includes an oxide transistor including a bottom gate layer, an oxide buffer layer on the bottom gate layer, a semiconductor oxide layer on the oxide buffer layer, a gate dielectric layer on the semiconductor oxide layer, and a top gate layer on the gate dielectric layer. In one embodiment, the top gate layer has a gate width wider than the bottom gate layer. In this configuration, the top gate layer can act as a shielding layer for hydrogen diffusion.

[0011] In one embodiment, a display panel includes a pixel region including an array of subpixels, wherein each subpixel includes an oxide transistor including a bottom gate layer, an oxide buffer layer on the bottom gate layer, a semiconductor oxide layer on the oxide buffer layer, a gate dielectric layer on the semiconductor oxide layer, and a top gate layer on the gate dielectric layer. In one embodiment, the bottom gate layer has a gate width wider than the top gate layer. In this configuration, the bottom gate layer can act as a shielding layer for hydrogen diffusion.

[0012] Various structures according to embodiments may be incorporated into a hybrid thin film transistor structure in order to protect the semiconductor oxide layer of the oxide transistor from hydrogen diffusion.Such structures may be repeated across pixels or sub-pixels of a display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a schematic cross-sectional side view illustration of a top gate oxide transistor including a multi-layer gate layer with a hydrogen trap layer according to one embodiment.

[0014] Figure 1B is a schematic cross-sectional side view illustration of a dual gate oxide transistor including a multi-layer gate layer with a hydrogen trap layer according to one embodiment.

[0015] Figure 2A is a schematic cross-sectional side view illustration of a top gate oxide transistor including a plurality of gate hydrogen trap layers according to one embodiment.

[0016] Figure 2B is a schematic cross-sectional side view illustration of a dual gate oxide transistor including a plurality of gate hydrogen trap layers in a top gate layer according to one embodiment.

[0017] Figure 3A is a schematic cross-sectional side view illustration of a top gate oxide transistor including an upper gate hydrogen trap layer according to one embodiment.

[0018] Figure 3B is a schematic cross-sectional side view illustration of a dual gate oxide transistor including an upper gate hydrogen trap layer in a top gate layer according to one embodiment.

[0019] Figure 4A is a schematic cross-sectional side view illustration of a top gate oxide transistor including an alloyed gate hydrogen trap layer according to one embodiment.

[0020] Figure 4B is a schematic cross-sectional side view illustration of a dual gate oxide transistor including an alloyed gate hydrogen trap layer according to one embodiment.

[0021] Figure 5 is a schematic cross-sectional side view illustration of a sub-pixel including a silicon transistor and an oxide transistor according to one embodiment.

[0022] Fig. 6A is a flow chart of a method of forming an oxide transistor having doped source / drain junctions according to one embodiment.

[0023] Figure 6Bis a schematic cross-sectional side view illustration of an oxide transistor having doped source / drain junctions after source / drain plasma treatment and before annealing according to one embodiment.

[0024] Figure 6C is a schematic cross-sectional side view illustration of an oxide transistor having doped source / drain junctions after annealing according to one embodiment.

[0025] Figure 7 is a schematic cross-sectional side view illustration of a dual gate oxide transistor including a protective top gate layer according to one embodiment.

[0026] Fig. 8A is a schematic top view illustration of a display panel according to one embodiment.

[0027] Figure 8B is a schematic cross-sectional side view illustration of a dual gate oxide transistor with variable top gate layer width according to one embodiment.

[0028] Figure 8C is a graph showing the continuous variation of the gate width of a dual gate oxide transistor from the center to the edge of a display panel according to one embodiment.

[0029] Fig.8D is a graph showing a discontinuous change in gate width of a dual gate oxide transistor from the center to the edge of a display panel according to one embodiment.

[0030] Fig. 9A is a schematic top view illustration of a display panel according to one embodiment.

[0031] Fig. 9B is a schematic cross-sectional side view illustration of a display panel including dummy sub-pixels according to one embodiment.

[0032] Fig. 9C is a schematic top view illustration of a display panel including dummy sub-pixels according to one embodiment.

[0033] Fig.9D is a schematic top plan view of an active sub-pixel according to one embodiment.

[0034] FIG. 9E to FIG. 9G is a schematic top plan view of a dummy sub-pixel according to an embodiment.

[0035] Figure 9H is a schematic top plan view illustration of a set of interconnected dummy sub-pixels according to one embodiment.

[0036] Fig. 10Ais a schematic cross-sectional side view illustration of a display system including a touch layer according to one embodiment.

[0037] Fig. 10B is a schematic top view illustration of touch metal wiring between sub-pixels according to one embodiment.

[0038] Fig. 10C is a schematic cross-sectional side view illustration of a touch metal wiring stack according to one embodiment. DETAILED DESCRIPTION

[0039] The embodiment describes a display structure and a method for forming a hydrogen trap layer that protects the semiconductor oxide layer of the oxide transistor from hydrogen diffusion. It has been observed that conventional oxide thin film transistors (TFTs) degrade with reliability testing in LTPO display technology. In one aspect, LTPS can adapt to hydrogen-rich environments, while oxide transistors are more sensitive to ambient hydrogen diffusion, which can make them unstable. It is believed that low-temperature hydrogen diffusion from adjacent hydrogen-containing layers (e.g., silicon nitride or silicon oxynitride encapsulation layers) can recombine with weakly bound oxygen in the semiconductor oxide layer of the oxide TFT, thereby producing a huge threshold voltage (Vth) drift during the product life cycle, resulting in display failures, color shifts, or uneven brightness. According to the embodiment, a hydrogen trap layer is introduced at the sub-pixel or panel level to absorb hydrogen in order to control and manage the amount of hydrogen diffusion. In this regard, the hydrogen diffusion mechanism is determined by the process integration design. According to the embodiment, a hydrogen trap layer is introduced into the non-channel region of the oxide transistor to tune the device characteristics.

[0040] In some embodiments, the gate layer stack includes a hydrogen trapping metal (e.g., Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb, Ta) or an alloy thereof to provide a shielding function to prevent hydrogen from diffusing into the semiconductor oxide channel of the oxide TFT. In addition, the hydrogen trapping metal or its alloy may be included as part of the source, drain or other layer to provide a shielding function. For example, the hydrogen trapping metal or its alloy may be a separate hydrogen trap layer located on the top or bottom of the metal gate layer (or source / drain layer), or may be included in an alloyed gate layer (or source / drain layer). Therefore, the gate layer may be a single alloyed layer or a multi-layer stack. In addition, multiple hydrogen trap layers may be included in the multi-layer stack.

[0041] In some embodiments, the hydrogen trap layer is located in the bottom gate layer of the dual gate oxide transistor, where the bottom gate layer is wider than the top gate layer. In this way, the bottom gate layer can block the diffusion of hydrogen from the underlying layer into the channel of the dual gate oxide transistor. In addition, this self-aligned structure can form an N+, N- junction in the semiconductor oxide layer. In this configuration, the N- region is in the shadow of the bottom gate layer, and the N+ region is formed due to hydrogen diffusion. In this configuration, the N- region can provide an ohmic contact with the semiconductor oxide (e.g., indium gallium zinc oxide IGZO) channel, which can reduce charge injection and transistor reliability.

[0042] In some embodiments, the hydrogen trap layer is located in the top gate layer of the dual gate oxide transistor, wherein the top gate layer is wider than the bottom gate layer. In this way, the top gate layer can block the diffusion of hydrogen from the overlying layer into the channel of the dual gate oxide transistor. In addition, a step structure can be integrated into the transistor structure so that the outer edge of the top gate layer is stepped down from the inner portion of the top gate layer. Such a step structure can provide additional protection from lateral diffusion of hydrogen into the semiconductor oxide layer channel region. The bottom gate layer can play a dual role, in addition to acting as the bottom gate layer, it also provides a template for the step structure.

[0043] In some embodiments, the oxide transistor gate width is modulated from the center (shorter) to the edge (wider) of the display panel. Thus, a wider gate width may correspond to a larger hydrogen trap layer to prevent hydrogen diffusion. Depending on the configuration, gate width modulation may correspond to channel length modulation, but there may be multiple arrangements where a continued increase in gate width does not cause an increase in channel length for a dual-gate transistor structure. In a specific embodiment, the gate width of the top gate layer is modulated. Alternatively, the gate width of the bottom layer or both may be modulated.

[0044] In some embodiments, the dummy hydrogen trap layer or sub-pixel is located in the peripheral area of ​​the display panel around the active sub-pixel. In one embodiment, the dummy sub-pixel area is located between the gate-in-panel (GIP) area and the pixel area. Such a dummy sub-pixel area may include non-functional pixels, wherein the dummy hydrogen trap layer may be incorporated into a variety of structures or layers. In this way, the dummy pattern design may be arranged throughout the active area (pixel area) and around the border to macro-manage the amount of hydrogen diffusion to the active area of ​​the display panel, thereby achieving front-screen uniformity and performance.

[0045] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details or in combination with other known methods and configurations. In the following description, many specific details such as specific configurations, sizes and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. "One embodiment" mentioned throughout the specification refers to the specific features, structures, configurations or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" that appears in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, configurations or characteristics can be combined in one or more embodiments in any appropriate manner.

[0046] As used herein, the terms "on," "over," "to," "between," "spanning," and "over" may refer to the relative position of one layer relative to other layers. A layer that is "on," "over," "spanning," or "on" relative to another layer, or bonded "to," or "in contact with," may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0047] Reference now Figure 1A , provides a cross-sectional side view illustration of a top gate oxide transistor 100 including a lower gate hydrogen trap layer according to one embodiment. Figure 1B is a schematic cross-sectional side view illustration of a dual gate oxide transistor 100 including a lower gate hydrogen trap layer in a top gate layer according to one embodiment.

[0048] like Figure 1A As shown, an oxide buffer layer 104 may be formed on a hydrogen-containing layer 102 (such as SiNx or SiONx or a combination thereof), which may contain a high hydrogen (H) content. A semiconductor oxide layer 106 is then formed on the oxide buffer layer 104. In one embodiment, the semiconductor oxide layer 106 is formed of a material such as indium gallium zinc oxide (IGZO), but this is merely exemplary, and a variety of other semiconductor oxide materials may be used, such as but not limited to zinc tin oxide (ZTO) and zinc indium oxide (ZIO). The semiconductor oxide layer 140 may be amorphous. In one embodiment, the semiconductor oxide layer 140 is formed using a suitable technique such as sputtering.

[0049] A gate dielectric layer 108 may then be formed over the semiconductor oxide layer 106. For example, the gate dielectric layer 120 may be a silicon oxide SiOx layer formed using a suitable deposition technique such as CVD. A patterned gate layer 110 may then be formed over the gate dielectric layer 108. The gate layer 110 may be a single layer or include a multi-layer stack. Figure 1A In the embodiment shown, the gate layer 110 includes a bottom metal gate layer 112 and an upper hydrogen trap layer 114. The bottom metal gate layer 112 can be formed of a metal material with good conductivity (e.g., Mo, Ag, Pl, etc.) to ensure low signal noise and crosstalk. The hydrogen trap layer 114 is formed of a conductive material and a material characterized by a negative dissolution entropy of hydrogen. Suitable materials include Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb and Ta. In a specific embodiment, the hydrogen trap layer 114 is formed of Ti.

[0050] The various hydrogen trap layers 114 (including dummy layers) described herein may be characterized by a higher hydrogen solubility than the metal gate layer 112. In the final product, after hydrogen diffusion / outgassing has occurred from the surrounding layers, the hydrogen trap layer 114 (eg, Ti) may contain greater than 1E 21 / cm 3 Such as greater than 1E 22 / cm 3 The hydrogen (atomic) concentration of the adjacent metal gate layer 112 (eg, Mo) is less than 1E 21 / cm 3 The hydrogen solubility / concentration of the gate layer 110 can be determined by a secondary ion mass spectrometry (SIMS) analysis. An interlayer dielectric (ILD) 120 can then be formed over the gate layer 110 and any underlying layers. The ILD 120 can include one or more dielectric layers. In one embodiment, the ILD 120 is formed of a material with a low hydrogen concentration, such as SiOx, and is formed using a suitable deposition technique, such as CVD.

[0051] Source and drain contact openings are then formed through the ILD 120 to expose the semiconductor oxide layer 106, after which a metal layer is formed on the ILD 120 and within the source and drain contact openings to form source / drain contacts 124 (vias) and a wiring layer 122. The source / drain contacts 124 and the wiring layer 122 may be formed from the same metal layer or multiple metal layers. Additional processing layers are then formed according to display manufacturing techniques, including an additional passivation layer 126, which may be a material containing a high hydrogen concentration, such as SiNx, SiONx, etc. It should be understood that although the high hydrogen content passivation layer 126 is shown as being directly on top of the IDL 120 and the wiring layer 122, there may be several intermediate layers. The high hydrogen content passivation layer 126 may be a top passivation layer located above an emission layer in a display panel (e.g., an organic emission layer of an OLED).

[0052] Reference now Figure 1B , the dual gate oxide transistor 100 structure is shown as having Figure 1A A similar top gate layer 110 is formed. As shown, a bottom gate layer 130 may be formed between the hydrogen-containing layer 102 and the oxide buffer layer 104. The bottom gate layer 130 according to the embodiment may have a variety of configurations and include a single layer or multiple layers. Figure 1B In the particular embodiment shown, the bottom gate layer 130 includes a metal gate layer 132 similar to the metal gate layer 112 and a top hydrogen trap layer 134 similar to the hydrogen trap layer 114 .

[0053] according to Figure 1A to Figure 1B In the embodiment shown, the oxide transistor 100 may include a semiconductor oxide layer 106, a gate dielectric layer 108 on the semiconductor oxide layer 106, and a gate layer 110 on the gate dielectric layer 108. In the embodiment shown, the gate layer 110 includes a gate hydrogen trap layer 114 and a metal gate layer 112 directly in contact with the gate hydrogen trap layer 114. More specifically, the metal gate layer 112 is directly above the gate hydrogen trap layer 114. The dual gate oxide transistor 100 structure may also include a bottom gate layer 130 below the semiconductor oxide layer 106. Figure 1B In the illustrated embodiment, the bottom gate layer 130 includes a bottom gate hydrogen trap layer 134 directly above the bottom metal gate layer 132 .

[0054] The hydrogen trap layer may be incorporated into the oxide transistor 100 structure in a number of different ways. Figure 2A is a schematic cross-sectional side view illustration of a top gate oxide transistor 100 including a plurality of gate hydrogen trap layers according to one embodiment. Figure 2Bis a schematic cross-sectional side view illustration of a dual gate oxide transistor 100 according to one embodiment, the dual gate oxide transistor including multiple gate hydrogen trap layers in the top gate layer. As shown, FIG. 2A to FIG. 2B The embodiment shown is similar to Figure 1A to Figure 1B Those shown, but with the addition of an additional hydrogen trap layer 114 in the top gate 110. Thus, the top gate 110 comprises a multi-layer stack, wherein the metal gate layer 112 is directly above the gate hydrogen trap layer 114, and the second gate hydrogen trap layer 114 is directly above the metal gate layer 112. FIG. 3A to FIG. 3B Another variation is shown in the illustrated embodiment, where the hydrogen trap layer 114 is positioned directly above the metal gate layer 112 in the top gate layer 110 .

[0055] Reference now FIG. 4A to FIG. 4B , shows yet another additional variation of these embodiments, wherein one or both of the top gate layer 110 and the bottom gate layer 130 are alloyed gate layers including hydrogen trap layers 114, 134. Thus, hydrogen trapping materials (e.g., Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb, Ta) may be allowed to be combined with metal gate layer materials (e.g., Mo, Ag, Pl, Al, etc.). For example, the alloyed gate layers 110, 130 may include Mo-Ti or Al-Ti alloys or Al alloys containing dopants such as Ti, Ce, Zr, Hf, Nd, Ta, etc.

[0056] Reference now Figure 5 , provides a schematic cross-sectional side view illustration of a hybrid sub-pixel including a silicon transistor 150 and an oxide transistor 100 according to one embodiment. Figure 5 The specific structures shown include Figure 1B The dual gate oxide transistor 100 is exemplary only and Figures 1A to 4B Any other oxide transistor arrangement may be included in the hybrid sub-pixel structure.

[0057] As shown, the hybrid pixel structure may include a hydrogen-containing layer 102 (e.g., SiNx, SiONx, polyimide, etc.), an oxide buffer layer 103 (e.g., SiOx), and a silicon channel layer 156 (e.g., polysilicon). A gate dielectric layer 158 is formed over the silicon channel layer 156, followed by a gate layer 160 of the silicon transistor 150. The gate layer 160 may be formed of a variety of conductive materials (including polysilicon, metal materials, etc.), and may be a multilayer stack. The same material used to prepare the gate layer 160 may also be used to form an additional conductive layer, which may include a capacitor plate layer 142, which may be used to form a capacitor 140 in a sub-pixel circuit. In one embodiment, the gate layer 160 and / or the capacitor plate layer 142 may include a hydrogen trap layer. An ILD 152 may then be formed over the gate layer 160 and the optional capacitor plate layer 142. The ILD 152 may be formed of a suitable insulating material and may serve as a capacitor dielectric layer. Suitable materials include SiOx, Al2O3, etc.

[0058] The bottom gate layer 130 may then be formed as previously described. In one embodiment, the material used to form the bottom gate layer 130 may also be used to form the top capacitor plate layer 170. For example, this may include a metal layer 172 and a hydrogen trap layer 174. The oxide buffer layer 104 may then be formed as previously described. Figure 5 Many of the layers shown are shown with level top surfaces. Therefore, these layers may optionally be planarized after deposition.

[0059] Compared with the previous Figure 1A to Figure 1B The remainder of the dual gate oxide transistor 100 is fabricated in a similar manner as described above. In addition, the metal layer used to form the source / drain contacts 124 and the wiring layer 122 may also be used to form the source / drain contacts 154 and the wiring layer 122 of the silicon transistor 150 and the contacts 144 and the wiring layer 122 of the capacitor 140. In one embodiment, either or both of the source / drain contacts or the wiring layer 122 may include a metal trap layer.

[0060] After forming the source / drain contacts and wiring layer 122, additional build-up structures may be formed, including wiring layer 176 and passivation layers 126, 127 (e.g., planarization layers), which may or may not be sources of hydrogen diffusion / outgassing. In one embodiment, wiring layer 176 may include a plate of a capacitor structure. The manufacturing sequence may then continue with forming an anode 180, followed by a patterned bank layer 182 and spacers 184, followed by deposition of an organic layer 186 and cathode 187 (e.g., indium tin oxide, etc.). Additional passivation layers 188, 190, 192 may then be formed. Depending on the embodiment, any of the passivation layers 188, 190, 192 may be a hydrogen-containing layer for hydrogen diffusion / outgassing.

[0061] Reference now FIG. 6A to FIG. 6C , Fig. 6A is a flow chart of a method of forming an oxide transistor having doped source / drain junctions according to one embodiment. Figure 6B shows an oxide transistor after source / drain plasma treatment and before annealing, and Figure 6C The oxide transistor after annealing is shown. For completeness, reference will be made to Figure 5 The hybrid transistor structure is Fig. 6A The processing sequence and FIG. 6B to FIG. 6C The oxide transistor structure is described below.

[0062] At operation 610, a silicon channel of the silicon channel layer 156 of the silicon transistor 150 is formed, followed by the formation of the top gate layer 160 of the silicon transistor 150 at operation 615. Now referring to Figure 5 and FIG. 6B to FIG. 6C , at operation 620, a bottom gate 130 of the oxide transistor 100 is formed. Figures 1A to 4B It should be understood that there may not be FIG. 6B to FIG. 6C All layers are shown in the diagram of FIG, and some layers may be omitted (such as some layers in Figure 5 is shown in FIG. 6B to FIG. 6C ) and relative to Figure 1A to Figure 1B Similar to the process described above, an oxide buffer layer 104 is formed over the bottom gate 130 at operation 630, and a semiconductor oxide layer 106 is formed over the oxide buffer layer 104 at operation 640. After forming the gate dielectric layer 108, a top gate layer 110 of the oxide transistor 100 is formed at operation 650.

[0063] Reference now Figure 6B, a doping process plasma treatment is performed at operation 655 to complete the top-down doping of the exposed portion of the semiconductor oxide layer 106. For example, this can be a plasma treatment or an ion implantation such as with Ar or He. In one embodiment, a nitrogen plasma treatment is performed to form an N-doping of the exposed portion of the semiconductor oxide layer 106. The top gate 110 (or a mask layer thereon) can be used to mask the doping concentration. After the plasma treatment, an ILD 120 can be formed over the top gate layer 110 and the underlying structure at operation 660, followed by the formation of source / drain contacts 124 at operation 670. Brief Reference Figure 5 , which may optionally include forming source / drain contacts 154 for silicon transistor 150 and contacts 144 for capacitor plate layer 170 .

[0064] An annealing process is then performed at operation 680. The annealing process can have a dual role. In one aspect, the annealing can be used for contact formation of the source / drain contacts 154 of the transistor source / drain, particularly the polysilicon source / drain contacts in the silicon channel layer 156 of the silicon transistor 150. In addition, the annealing can drive hydrogen diffusion from the bottom hydrogen-containing layer 102 (e.g., SiNx, SiONx) of the oxide transistor 100 toward the semiconductor oxide layer 106. Figure 6C In the particular configuration shown, the bottom gate layer 130 blocks hydrogen diffusion from the channel region of the semiconductor oxide layer 106 and from the N-doped regions in the shadow of the bottom gate layer 130. Therefore, the bottom-up diffusion of hydrogen preferentially dopes the regions of the semiconductor oxide layer 106 that are outside the shadow of the bottom gate layer 130 to form N+ regions. The passivation layer 120 may then be formed at operation 690, followed by additional processing sequences as already described. In one embodiment, source / drain contacts 124 will be formed to the N+ regions.

[0065] According to the embodiment, hydrogen trap layers 114, 134, etc. may be formed in various locations to block hydrogen from diffusing toward the channel region of the semiconductor oxide layer 106. FIG. 6B to FIG. 6C In the illustrated embodiment (and other embodiments), the bottom gate layer 130 has a gate width that is wider than the top gate layer 110. In this structure, the wider width of the bottom gate layer 130 can shield the channel region within the shadow of the bottom gate layer 130 from bottom-up hydrogen diffusion from the underlying layers. In addition, the width of the bottom gate layer 130 (including the hydrogen trap layer 134) can be tailored to control the N+ / N- doped junction in the semiconductor oxide layer 106. Figure 6C In the embodiment shown, the presence of the lower gate layer 130 can cause a step height in the semiconductor oxide layer 106, so that the channel region is in a planar region directly above the bottom gate layer 130, and the N+ region is a step below the channel region. The N- region can span the stepped portion of the semiconductor oxide layer 106.

[0066] It should be understood that the N- / N+ regions may also be formed by hydrogen diffusion from upper / lower hydrogen containing layers and thermal treatment. For example, in addition to plasma treatment, the N- region may be formed by H diffusion from overlying layers (including but not limited to hydrogen containing passivation layers 126, 127) while the N+ region is formed by additional diffusion from the hydrogen containing layer 102 as previously described. Hydrogen doping may be accomplished in a variety of sequences with the N- / N+ regions and concentrations self-aligned with the top gate layer 110 and the bottom gate layer 130. N-hydrogen doping may also be accomplished with plasma treatment or diffusion from a temporary hydrogen containing layer (e.g., SiNx or SiONx).

[0067] In one embodiment, a display panel includes a pixel region including an array of sub-pixels, wherein each sub-pixel includes an oxide transistor 100, the oxide transistor including a bottom gate layer 130, an oxide buffer layer 104 on the bottom gate layer 130, a semiconductor oxide layer 106 on the oxide buffer layer 104, a gate dielectric layer 108 on the semiconductor oxide layer 106, and a top gate layer 110 on the gate dielectric layer 108. In this embodiment, the bottom gate layer 130 has a gate width wider than the top gate layer 110. Figure 6C As shown, a first portion of the semiconductor oxide layer 106 directly below the shadow of the top gate layer 110 corresponds to the oxide transistor channel. A second portion of the semiconductor oxide layer 106 directly above the shadow of the bottom gate layer 130 and excluding the first portion is N-doped. A third portion of the semiconductor oxide layer 106 outside the shadow of the bottom gate layer is N+ doped. In one embodiment, the N-doped and N+ doped interface is characterized by a (higher) hydrogen dopant concentration in the third portion. For example, the third portion (N+ region) of the semiconductor oxide layer 106 may have a higher hydrogen dopant concentration than the second portion (N- region).

[0068] Similar to the bottom gate 130 used to block hydrogen diffusion from lower hydrogen diffusion sources, the top gate 110 can also be used to block hydrogen diffusion from upper hydrogen diffusion sources while optionally also providing lateral protection. Figure 71 is a schematic cross-sectional side view illustration of a dual gate oxide transistor according to one embodiment, the dual gate oxide transistor including a protective top gate layer 110. Although only a single top gate layer 110 is shown, it should be understood that both the top gate layer 110 and the bottom gate layer 130 may have multiple layers and include a separate hydrogen trap layer, as previously described. In the illustrated embodiment, the oxide transistor 100 includes a bottom gate layer 130, an oxide buffer layer 104 on the bottom gate layer 130, a semiconductor oxide layer 106 on the oxide buffer layer 104, a gate dielectric layer 108 on the semiconductor oxide layer 106, and a top gate layer 110 on the gate dielectric layer 106. In this embodiment, the top gate layer 110 has a gate width (W) that is wider than the bottom gate layer 110 by a certain difference (ΔW). In one embodiment, the top gate layer 110 includes a gate hydrogen trap layer characterized by a negative dissolution entropy of hydrogen. The gate hydrogen trap layer may be a separate layer or an alloyed layer, as previously described. In one embodiment, the top gate layer includes a gate hydrogen trap layer (e.g., 114) in direct contact with the metal gate layer (e.g., 112), wherein the gate hydrogen trap layer is characterized by a negative dissolution entropy of hydrogen. Figure 7 In the embodiment shown, the outer edges of the top gate layer 110 are stepped down from the inner portion of the top gate layer. This arrangement can provide some additional protection from lateral hydrogen diffusion, as well as providing further protection from hydrogen diffusion from the upper layers by further isolating the semiconductor oxide layer channel region (which is in the shadow of the bottom gate layer 130). In one embodiment, the difference in gate width ΔW / 2 on each side is 1-2 μm.

[0069] Up to this point, transistor gate structures have been described in which hydrogen trap layers can be located at various locations and the gate layer width can be adjusted to block hydrogen diffusion from specific directions. It has also been observed that hydrogen diffusion from the edge of the display panel can be particularly problematic and adversely affect pixels closest to the edge of the display panel. According to some embodiments, the gate layer width can be modulated between a center position and an edge position of the display panel. Fig. 8A is a schematic top view illustration of a display panel 800 according to one embodiment, the display panel including a central area and an edge area. Figure 8B is a schematic cross-sectional side view illustration of a dual gate oxide transistor 100 with a variable top gate layer 110 width according to one embodiment. Figure 8B Similar to Figure 1B , Figure 2B , Figure 3B , Figure 4B The previous dual gate oxide transistor structure described and shown. According to the embodiment, the top gate layer 110 width (W) can be modulated according to the transistor position in the display panel 800 to block hydrogen diffusion. For example, in Figure 8C In the embodiment shown, the gate layer width (W) can be modulated continuously from the center to the edge, with a larger gate layer 110 width at the edge of the display panel. Fig.8D In the embodiment shown, the modulation need not be continuous and may be step-wise.

[0070] In one embodiment, the display panel 800 includes a pixel area 802 including an array of sub-pixels, each sub-pixel including a gate layer 110 of an oxide transistor 100 including a gate hydrogen trap layer. In such an embodiment, the gate width (W) of the gate layer 110 is smallest for the sub-pixel closest to the center of the pixel area, and the gate width (W) of the gate layer 110 is widest for the sub-pixel closest to the periphery of the pixel area. Various configurations of oxide transistors 100 may be used with such a modulation structure. In one embodiment, each oxide transistor 100 includes a semiconductor oxide layer 106, a gate dielectric layer 108 on the semiconductor oxide layer 106, and a gate layer 110. The gate layer 110 may include a gate hydrogen trap layer 114 and a metal gate layer 112 in direct contact with the gate hydrogen trap layer 114. The metal gate layer 112 may be directly above the gate hydrogen trap layer 114 (e.g., as Figure 1A to Figure 1B ) or directly below the gate hydrogen trap layer 114 (e.g., as FIG. 3A to FIG. 3B In one embodiment, the gate hydrogen trap layer 114 is located directly below and directly above the metal gate layer 112 in a stacked arrangement, such as FIG. 2A to FIG. 2B As shown. In some embodiments, the oxide transistor 100 includes a bottom gate layer 130 below the semiconductor oxide layer 106. Similarly, the bottom gate layer 130 may include a bottom gate hydrogen trap layer 134 directly above the bottom metal gate layer (e.g., 132). According to an embodiment, the top gate layer 110. In one embodiment, for sub-pixels closest to the center and periphery of the pixel area, the bottom gate layer 130 has a gate width (W) wider than the top gate layer 110. In an alternative embodiment, for sub-pixels closest to the center and periphery of the pixel area, the top gate layer 110 has a gate width (W) wider than the bottom gate layer 130 (e.g., Figure 7 In addition, although the above description has been shown with respect to modulation of the gate width of the top gate layer 110, the gate width of the bottom gate layer 130 may alternatively be modulated or modulated simultaneously.

[0071] In yet another aspect, embodiments may include a dummy pattern design for macro-management of hydrogen diffusion in a display panel. In this arrangement, the dummy sub-pixels may serve as shielding layers for the pixel region as well as the GIP region. Fig. 9Ais a schematic top view illustration of a display panel 800 according to one embodiment, the display panel including a central area and an edge area. Fig. 9B is a schematic cross-sectional side view illustration according to one embodiment, which simultaneously spans Fig. 9A The central area and the edge area of ​​​​the device include dummy sub-pixels. Fig. 9C is a schematic top view illustration of an edge region of a display panel 800 including dummy sub-pixels according to one embodiment. In the particular embodiment shown, the hydrogen-containing layer 102 and the passivation layers 188, 192 are shaded to illustrate the high hydrogen concentration and the tendency of hydrogen to diffuse from the edges. Fig. 9B , the different regions identified are, from center to edge, the pixel region 802, the dummy region 710 (including the dummy transistor 714), the first GIP region 720 (which may optionally include an active oxide transistor 724), the dummy region 710, the second GIP region 720 (which may optionally include an active oxide transistor 724), the dummy region 710, and the dam region 40 (including the dam structure 742).

[0072] like 9A to 9C As shown, the pixel area 802 may span from the center to the edge of the display panel 800. The dummy area 710 including the dummy sub-pixel 712 may be located at the edge boundary of the active pixel area 802. The dummy sub-pixel 712 may be non-functional and may not have an organic emission layer (e.g., 186). In addition, the dummy sub-pixel 712 may have a layout and symmetry similar to the active sub-pixel 702 so as not to introduce stress to the system. Therefore, the dummy sub-pixel 712 may simulate the metal wiring, gate and capacitor in the active sub-pixel 702 to reduce the load effect and process variation. The dummy sub-pixel 712 may additionally include a higher concentration of hydrogen trap layer material than the active sub-pixel 702.

[0073] In one embodiment, the display panel 800 includes a GIP region 720 (or 730) adjacent to an edge of the display panel 800. The pixel region 802 includes a sub-pixel array 702, wherein each sub-pixel includes an oxide transistor 100, the oxide transistor including a transistor hydrogen trap layer, the transistor hydrogen trap layer being formed of a transistor material characterized by a negative dissolution entropy of hydrogen. The dummy sub-pixel region 710 is located between the GIP region 720 and the pixel region 802, and the dummy sub-pixel region 710 includes a plurality of dummy sub-pixels 712, wherein each dummy sub-pixel 712 includes a dummy hydrogen trap layer, the dummy hydrogen trap layer being formed of a dummy material characterized by a negative dissolution entropy of hydrogen. In one embodiment, the volume of the dummy hydrogen trap layer dummy material included in each dummy sub-pixel 712 is greater than the volume of the hydrogen trap layer material in each sub-pixel. The dummy hydrogen trap layer dummy material and the hydrogen trap layer material may be the same material, such as Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb, and Ta.

[0074] In one embodiment, the dummy sub-pixels 712 are arranged symmetrically around the entire periphery of the pixel area 802. The dummy hydrogen trap layer can be located in a variety of locations in each dummy sub-pixel. Exemplary locations can include dummy oxide transistor gate layers, dummy capacitor layers, dummy plates, and dummy source / drain wiring layers.

[0075] Reference now Fig.9D , provides a schematic top plan view of certain layers within an active sub-pixel 702 according to one embodiment. FIG. 9E to FIG. 9G is a schematic top plan view of specific layers within a dummy sub-pixel according to an embodiment to illustrate exemplary locations of dummy hydrogen trap layer dummy materials.

[0076] Reference now Figure 5 and Fig.9D , an exemplary active sub-pixel 702 may include a Vdd (power) line 754 and a Vdata (data) line 756. For example, these may correspond to Figure 5 The source / drain wiring layer 122 is shown. Additional wiring layers include scan lines 750, emission control lines 752, other lines not shown, and may be included in various wiring layers. The oxide transistor gate layers 110, 130 and the source / drain wiring layer 122 are also shown.

[0077] Reference now Fig.9E In the dummy sub-pixel 712, various wiring layers such as the scan line 750, the emission control line 752, etc. are removed. In this example, the top gate layer 110 and / or the bottom gate layer 130 containing the dummy hydrogen trap layer are retained. Optionally, the capacitor plate layer 170 containing the dummy hydrogen trap layer is retained. Fig.9FThe dummy sub-pixel 712 in the embodiment retains the source / drain wiring layer 122 including the dummy hydrogen trap layer. Figure 9G In the embodiment shown, the wiring layer 176 is retained and includes a dummy hydrogen trap layer. In one embodiment, the wiring layer 176 includes a plate from a capacitor structure. Similarly, the source / drain wiring layer 122 may also include a plate from a capacitor structure. It should be understood that the separate FIG. 9E to FIG. 9G Embodiments are shown to illustrate the retention of dummy hydrogen trap layers in different layers of the sub-pixel stack. It should be understood that these embodiments can be combined in any suitable manner and are not mutually exclusive. Therefore, any combination of dummy hydrogen trap layers shown can be envisioned.

[0078] The dummy sub-pixels 712 within the dummy region 710 may be floating or interconnected. Figure 9H is a diagram of a group of dummy sub-pixels 712 connected to each other within a dummy region 710 . Figure 9H The dummy sub-pixel 712 shown is intended to be generic and may be any of the dummy sub-pixels 712 described. In an exemplary passive drive mode, the dummy hydrogen trap layers within the dummy sub-pixel 712 may be interconnected to a ground potential (Vground). In an exemplary active drive mode, the dummy hydrogen trap layers within the dummy sub-pixel 712 may be interconnected to a control voltage such as a constant DC voltage V DC or AC V AC In this configuration, the applied voltage attracts the hydrogen ions.

[0079] In another aspect, the metal wiring used for touch control can also be used for hydrogen gettering. Fig. 10A FIG. 1 is a schematic cross-sectional side view illustration of a display system including a touch layer according to one embodiment. As shown, the display system includes a display panel stack 1010 below an organic emission layer 186 and passivation layers 188-192. A touch layer 1020 may be located on the passivation layer 188 instead of a separate touch panel. The touch layer 1020 may include a touch metal wiring 1030, such as Fig. 10B As shown, the touch metal wiring is interwoven between the sub-pixel emission areas 1040A, 1040B, 1040C, but is not directly located over the emission areas of the various sub-pixels A, B, C. It should be understood that a specific sub-pixel and pixel arrangement is shown, but this is exemplary and a variety of sub-pixel and pixel arrangements are possible. Fig. 10C As shown, the touch metal wiring 1030 may include a stack of layers including one or more hydrogen trap layers 1034 and a conductive layer 1032 .

[0080] When utilizing various aspects of the embodiments, it will be apparent to those skilled in the art that combinations or variations of the above embodiments are possible for integrating a hydrogen trap layer into a display structure. For example, multiple embodiments may be used with Figure 5 In one embodiment, the hybrid thin film transistor structure includes a substrate (eg, including a hydrogen-containing layer 102),

[0081] An oxide buffer layer over the substrate (the oxide buffer layer 103 spans the silicon transistor 150 region and the oxide transistor 130 region), a silicon channel layer 156 (e.g., LTPS) over the oxide buffer layer 103 in the silicon transistor region, a gate dielectric layer 158 over the silicon channel layer 156 in the silicon transistor region, and a top gate layer 160 over the gate dielectric layer 158 in the silicon transistor region. This portion of the hybrid structure may describe the silicon transistor 150.

[0082] The bottom gate layer 130 is located above the oxide buffer layer 103 in the oxide transistor region. The second oxide buffer layer 104 is located above the bottom gate layer 130 in the oxide transistor region, wherein the second oxide buffer layer 104 spans the silicon transistor region and the oxide transistor region. The semiconductor oxide layer 106 is located above the second oxide buffer layer 104 in the oxide transistor region, wherein the second gate dielectric layer 108 is located above the semiconductor oxide layer 106 in the oxide transistor region, and the second top gate layer 110 is located above the second gate dielectric layer 108 in the oxide transistor region. This portion of the hybrid structure may describe the dual gate oxide transistor 100.

[0083] The top gate layer 110 according to an embodiment may include a multilayer stack. For example, the multilayer stack may include a metal gate layer 112 and a gate hydrogen trap layer 114, the gate hydrogen trap layer being characterized by a negative dissolution entropy of hydrogen. For example, the gate hydrogen trap layer 114 may include a hydrogen trapping material such as Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb, and Ta, or be substantially formed of the hydrogen trapping material. In the configuration shown, the metal gate layer 112 is located above the gate hydrogen trap layer 114, but other configurations are contemplated. In one embodiment, the metal gate layer 112 includes a Mo layer, and the gate hydrogen trap layer 114 includes a Ti layer. In one embodiment, the hydrogen trap layer 114 includes greater than 1E 21 / cm 3 of hydrogen concentration.

[0084] An ILD layer 152 may be formed over the top gate layer 160 of the silicon transistor 150 and spans both the silicon transistor region and the oxide transistor region, wherein the bottom gate layer 130 of the double-gate oxide transistor 100 is now located over the ILD layer 152 in the oxide transistor region.

[0085] In one embodiment, the substrate includes a hydrogen-containing layer 102, and a hydrogen-containing planarization layer (e.g., passivation layers 126, 127) is located above the second top gate layer 110 and spans the silicon transistor region and the oxide transistor region. Various structures according to embodiments may include a hydrogen trap layer to protect the semiconductor oxide layer of the oxide transistor 100 from hydrogen diffusion from such layers and other hydrogen source layers.

[0086] The hybrid thin film transistor structure according to the embodiment may include a first pair of source / drain contacts 154 on the silicon channel layer 156 of the silicon transistor 150 and a second pair of source / drain contacts 124 on the semiconductor oxide layer 106 of the oxide transistor 100, wherein the first pair of source / drain contacts 154 and the second pair of source / drain contacts 124 each include a hydrogen trap layer characterized by a negative dissolution entropy of hydrogen. The wiring layer 122 may similarly include a hydrogen trap layer. Such a hydrogen trap layer may be formed of the same material as the gate hydrogen trap layer 114 (e.g., Ti).

[0087] In one embodiment, the bottom gate layer 130 of the dual gate oxide transistor 100 has a gate width wider than the second top gate layer 110. The semiconductor oxide layer 106 may include doped source / drain regions. For example, the source / drain regions may be n-type. For example, the n-type source / drain regions may be optionally doped with H and / or Ar, but the embodiment is not so limited. FIG. 6A to FIG. 6B As shown, a first portion of the semiconductor oxide layer 106 directly below the shadow of the second top gate layer 110 may correspond to an oxide transistor channel, a second portion of the semiconductor oxide layer 106 directly above the shadow of the bottom gate layer 130 and excluding the first portion is N-doped, and a third portion of the semiconductor oxide layer 160 outside the shadow of the bottom gate layer is N+ doped. In one embodiment, the N-doped and N+ doped interfaces are characterized by the concentration of hydrogen dopants in the third portion.

[0088] Although the embodiments have been described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Rather, the specific features and acts disclosed should be understood as illustrative embodiments of the claims.

Claims

1. A hybrid thin film transistor structure, comprising: substrate; An oxide buffer layer above the substrate, the oxide buffer layer spanning the silicon transistor region and the oxide transistor region; a silicon channel layer above the oxide buffer layer in the silicon transistor region; A gate dielectric layer over the silicon channel layer in the silicon transistor region a top gate layer over the gate dielectric layer in the silicon transistor region; a bottom gate layer above the oxide buffer layer in the oxide transistor region; a second oxide buffer layer over the bottom gate layer in the oxide transistor region, the second oxide buffer layer spanning the silicon transistor region and the oxide transistor region; a semiconductor oxide layer over the second oxide buffer layer in the oxide transistor region; The semiconductor oxide layer includes an n-type source / drain region, and: A first portion of the semiconductor oxide layer directly below the shadow of the second top gate layer corresponds to an oxide transistor channel; A second portion of the semiconductor oxide layer directly above the shadow of the bottom gate layer and excluding the first portion is N-doped; and A third portion of the semiconductor oxide layer outside the shadow of the bottom gate layer is N+ doped; a second gate dielectric layer over the semiconductor oxide layer in the oxide transistor region; and A second top gate layer is over the second gate dielectric layer in the oxide transistor region. 2 . The hybrid thin film transistor structure of claim 1 , wherein the second top gate layer comprises a multi-layer stack. 3 . The hybrid thin film transistor structure of claim 2 , wherein the multi-layer stack comprises a metal gate layer and a gate hydrogen trap layer, the gate hydrogen trap layer being characterized by a negative dissolution entropy of hydrogen. 4 . The hybrid thin film transistor structure according to claim 3 , wherein the metal gate layer is located above the gate hydrogen trap layer.

5. The hybrid thin film transistor structure of claim 4, wherein the gate hydrogen trap layer comprises a hydrogen trapping material selected from the group consisting of Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb and Ta.

6. The hybrid thin film transistor structure according to claim 5, wherein the gate hydrogen trap layer comprises more than 1E 21 / cm 3 of hydrogen concentration.

7. The hybrid thin film transistor structure according to claim 3 further comprises an interlayer dielectric ILD layer, wherein the ILD layer is located above the top gate layer and spans the silicon transistor region and the oxide transistor region, wherein the bottom gate layer is located above the ILD layer in the oxide transistor region.

8. The hybrid thin film transistor structure of claim 3, wherein the substrate comprises a hydrogen containing layer. 9 . The hybrid thin film transistor structure according to claim 8 , further comprising a hydrogen-containing planarization layer located above the second top gate layer, the hydrogen-containing planarization layer spanning the silicon transistor region and the oxide transistor region.

10. The hybrid thin film transistor structure according to claim 3 further comprises a first pair of source / drain contacts on the silicon channel layer and a second pair of source / drain contacts on the semiconductor oxide layer, wherein the first pair of source / drain contacts and the second pair of source / drain contacts both comprise a hydrogen trap layer characterized by a negative dissolution entropy of hydrogen. 11 . The hybrid thin film transistor structure according to claim 10 , wherein the hydrogen trap layer is formed of the same material as the gate hydrogen trap layer. 12 . The hybrid thin film transistor structure of claim 3 , wherein the bottom gate layer has a gate width wider than that of the second top gate layer.

13. The hybrid thin film transistor structure of claim 1, wherein the N-doped and N+ doped interfaces are characterized by a hydrogen dopant concentration in the third portion.

14. The hybrid thin film transistor structure of claim 1, wherein the n-type source / drain regions are doped with a dopant selected from the group consisting of: H and Ar.

15. The hybrid thin film transistor structure according to claim 1, further comprising a first pair of source / drain contacts on the silicon channel layer and a second pair of source / drain contacts on the semiconductor oxide layer, wherein the first pair of source / drain contacts and the second pair of source / drain contacts both comprise a hydrogen trap layer characterized by a negative dissolution entropy of hydrogen.

16. The hybrid thin film transistor structure according to claim 1: wherein the second top gate layer comprises a multi-layer stack; wherein the multilayer stack includes a metal gate layer and a gate hydrogen trap layer, the gate hydrogen trap layer being characterized by a negative dissolution entropy of hydrogen; wherein the metal gate layer is located above the gate hydrogen trap layer; wherein the gate hydrogen trap layer comprises a hydrogen capture material selected from the group consisting of: Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb and Ta; The gate hydrogen trap layer contains more than 1E 21 / cm 3 The hydrogen concentration; The hybrid thin film transistor structure further includes an interlayer dielectric ILD layer, the ILD layer is located above the top gate layer and spans the silicon transistor region and the oxide transistor region, wherein the bottom gate layer is located above the ILD layer in the oxide transistor region; wherein the substrate comprises a hydrogen-containing layer; The hybrid thin film transistor structure further includes a hydrogen-containing planarization layer located above the second top gate layer, the hydrogen-containing planarization layer spanning the silicon transistor region and the oxide transistor region; The hybrid thin film transistor structure further includes a first pair of source / drain contacts on the silicon channel layer and a second pair of source / drain contacts on the semiconductor oxide layer, wherein the first pair of source / drain contacts and the second pair of source / drain contacts each include a hydrogen trap layer characterized by a negative dissolution entropy of hydrogen; wherein the hydrogen trap layer is formed of the same material as the gate hydrogen trap layer; wherein the bottom gate layer has a gate width wider than that of the second top gate layer; wherein the semiconductor oxide layer includes an n-type source / drain region; in: A first portion of the semiconductor oxide layer directly below a shadow of the second top gate layer corresponds to an oxide transistor channel; A second portion of the semiconductor oxide layer directly above the shadow of the bottom gate layer and excluding the first portion is N-doped; and A third portion of the semiconductor oxide layer outside the shadow of the bottom gate layer is N+ doped; wherein the N-doped and N+ doped interfaces are characterized by the concentration of hydrogen dopants in the third portion; wherein the n-type source / drain region is doped with a dopant selected from the group consisting of: H and Ar; The hybrid thin film transistor structure further includes a first pair of source / drain contacts on the silicon channel layer and a second pair of source / drain contacts on the semiconductor oxide layer, wherein the first pair of source / drain contacts and the second pair of source / drain contacts each include a hydrogen trap layer characterized by a negative dissolution entropy of hydrogen; and The hydrogen trap layer is formed of the same material as the gate hydrogen trap layer.

17. A display panel, comprising: A pixel region including an array of sub-pixels, each sub-pixel including an oxide transistor, the oxide transistor including: bottom gate layer; an oxide buffer layer on the bottom gate layer; a semiconductor oxide layer on the oxide buffer layer; a gate dielectric layer on the semiconductor oxide layer; and a top gate layer on the gate dielectric layer; wherein the bottom gate layer has a gate width wider than that of the top gate layer; and in: A first portion of the semiconductor oxide layer directly below the shadow of the top gate layer corresponds to the oxide transistor channel; A second portion of the semiconductor oxide layer directly above the shadow of the bottom gate layer and excluding the first portion is N-doped; and A third portion of the semiconductor oxide layer outside the shadow of the bottom gate layer is N+ doped.

18. The display panel of claim 17, wherein the N-doped and N+ doped interfaces are characterized by a concentration of hydrogen dopants in the third portion. The display panel of claim 17 , wherein the top gate layer comprises a multi-layer stack.

20. The display panel of claim 19, wherein the multi-layer stack comprises a metal gate layer and a gate hydrogen trap layer, the gate hydrogen trap layer being characterized by a negative dissolution entropy of hydrogen.

21. The display panel of claim 20, wherein the hydrogen trap layer comprises a hydrogen capture material selected from the group consisting of Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb, and Ta.

22. The display panel of claim 17, wherein a gate width of the top gate layer is smallest for a sub-pixel closest to a center of the pixel region, and the gate width of the top gate layer is widest for a sub-pixel closest to a periphery of the pixel region.

23. The display panel of claim 17, wherein the bottom gate layer comprises a bottom multi-layer stack.

24. The display panel of claim 23, wherein the bottom multi-layer stack comprises a bottom metal gate layer and a bottom gate hydrogen trap layer, the bottom gate hydrogen trap layer being characterized by a negative dissolution entropy of hydrogen.

25. The display panel according to claim 17: wherein the N-doped and N+ doped interfaces are characterized by the concentration of hydrogen dopants in the third portion; wherein the top gate layer comprises a multi-layer stack; wherein the multilayer stack includes a metal gate layer and a gate hydrogen trap layer, the gate hydrogen trap layer being characterized by a negative dissolution entropy of hydrogen; wherein the hydrogen trap layer comprises a hydrogen capture material selected from the group consisting of: Li, Sc, Y, La, Ce, Ti, Zr, Hf, V, Nb and Ta; wherein the gate width of the top gate layer is smallest for the sub-pixel closest to the center of the pixel region, and the gate width of the top gate layer is widest for the sub-pixel closest to the periphery of the pixel region; wherein the bottom gate layer comprises a bottom multilayer stack; and The bottom multilayer stack includes a bottom metal gate layer and a bottom gate hydrogen trap layer, wherein the bottom gate hydrogen trap layer is characterized by a negative dissolution entropy of hydrogen.

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