Monolithic LED arrays and precursors thereof

Abstract

The present invention provides a monolithic LED array precursor, comprising: a plurality of LED structures sharing a first semiconductor layer, wherein the first semiconductor layer defines a plane of the LED array precursor, and each LED structure comprises: (i) a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross section perpendicular to the upper surface portion, so that the second semiconductor layer has an inclined side surface; (ii) a third semiconductor layer on the second semiconductor layer, the third semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross section perpendicular to the upper surface portion, so that the third semiconductor layer has an inclined side surface perpendicular to the second semiconductor layer; (iii) a fourth semiconductor layer on the third semiconductor layer, the fourth semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the fourth semiconductor layer has an inclined side parallel to the inclined side of the third semiconductor layer; and (iv) a main electrical contact on the fourth semiconductor layer, wherein the contact is only on the upper surface portion of the fourth semiconductor layer parallel to the plane of the LED array precursor, wherein the third semiconductor layer includes a plurality of quantum well sublayers, the portion of the quantum well sublayer parallel to the plane of the LED array precursor has a greater thickness, and the portion of the quantum well sublayer not parallel to the plane of the LED array precursor has a reduced thickness.

Description

Technical Field

[0001] The present disclosure relates to a monolithic LED array, an LED device including the monolithic LED array, and a method of manufacturing the same. In particular, the present disclosure provides a monolithic LED array with improved light emission. Background Art

[0002] A micro-LED array can be defined as a 100×100 μm 2 Or smaller LED arrays. Micro-LED arrays are being developed for many commercial and military applications, such as self-emissive micro-displays and projectors, which can be incorporated into a variety of devices (e.g., wearable displays, head-up displays, camcorders, viewfinders, multi-site excitation sources, and micro-projectors).

[0003] III-nitride-based micro-LEDs are inorganic semiconductor LEDs that contain GaN and its alloys as well as InN and AlN in the active light-emitting region. III-nitride-based micro-LEDs are popular because they can be driven at significantly higher current densities and emit higher light power densities than conventional large-area LEDs, specifically organic light-emitting diodes (OLEDs) in which the light-emitting layer is an organic compound. Thus, higher luminescence (brightness) is defined as the amount of light emitted per unit area of ​​a light source in a given direction, also measured in candela per square meter (cd / m 2 ) metric and is often referred to as Nit(nt), this higher luminescence makes micro-LEDs suitable for applications that require or benefit from high brightness, such as displays in high-brightness environments or projections.

[0004] In addition, the high luminous efficacy of III-nitride micro-LEDs, expressed in lumens per watt (lm / W), allows lower power usage compared to other light sources and makes micro-LEDs particularly suitable for portable devices. In addition, due to the inherent material properties of III-nitrides, micro-LEDs can operate under extreme conditions (e.g., high or low temperatures and high or low humidity), providing performance and reliability advantages in wearable and outdoor applications.

[0005] There are currently two main approaches to producing inorganic micro-LED arrays. In the first approach, individual micro-LED devices are produced using techniques similar to those used for conventionally sized LEDs, which are then assembled into arrays onto a substrate, which can be an active matrix backplane including drive circuits for addressing the individual micro-LEDs, using pick-and-place techniques. This first approach allows LEDs with different characteristics (e.g., different emission wavelengths) that have been manufactured on different growth substrates to be transferred to a product substrate to achieve a full-color display. In addition, it allows faulty devices to be discarded before they become part of the array, potentially increasing the final yield of the array. On the other hand, the resolution (small pitch) and array size (large number of micro-LEDs) required for various applications present severe challenges to this approach, namely the accuracy of pick-and-place and transfer time, which affect the reliability of the process and its throughput, respectively.

[0006] The second approach uses monolithic integration to manufacture micro-LED arrays on a single growth substrate, allowing higher integration density, smaller LEDs, and smaller pitch (i.e., higher array resolution). The second approach relies on coloring technology to achieve full-color display. The coloring technology used for micro-LEDs depends on the pitch of the micro-LED array. Traditional phosphor materials for lighting applications are currently only suitable for large pitch and low resolution arrays, while quantum dot-based wavelength conversion materials are required for higher resolution applications. Regardless of which method is used, the periphery of the active area of ​​a single micro-LED in the array is typically formed by an etching process that removes a portion of the light-emitting active area, thereby electrically isolating the individual micro-LEDs to allow current to be injected independently in each micro-LED and to adjust the amount of radiative recombination within each micro-LED in the array.

[0007] A less common manufacturing process uses selective area growth (SAG) to achieve electrically isolated portions of the active region that can be independently injected with current without using an etching step as disclosed in US 7,087,932. In the selective area growth technique, a mask is patterned over the buffer layer. The material in the mask is such that under growth conditions, additional material does not grow directly on the mask, but only grows in holes that expose surface portions of the underlying buffer layer.

[0008] The brightness of III-nitride LEDs increases with the increase of operating current, but the luminous efficiency depends on the current density (A / cm 2), initially increases with increasing current density, reaches a maximum, and then decreases due to a phenomenon known as "efficiency droop." Many factors contribute to the luminous efficiency of an LED device, including the ability to generate photons internally, known as the internal quantum efficiency (IQE). The external quantum efficiency (EQE) is defined as the number of photons emitted in the active region divided by the number of electrons injected. EQE is a function of IQE and the light extraction efficiency (LEE) of the LED device. At low current densities, the efficiency is very low due to the strong influence of defects or other processes in which electrons recombine with holes without producing light, known as non-radiative recombination. As those defects become saturated, radiative recombination dominates and efficiency improves. As the injected current density exceeds the characteristic value of the LED device, "efficiency droop" or a gradual decrease in efficiency begins.

[0009] Surface recombination is believed to be the main cause of non-radiative recombination in micro-LEDs. Defects and dangling bonds around the active region of a micro-LED interrupt the atomic lattice and introduce electronic energy levels within the normally forbidden semiconductor band gap. This can enhance non-radiative recombination by acting as a stepping stone for charge carrier transitions between the conduction band and the valence band.

[0010] Surface recombination is particularly important in inorganic micro-LEDs due to the large perimeter to surface ratio and the dry etching techniques typically used to define the perimeter around the active area. A variety of techniques are known to those skilled in the art, including surface treatment with wet etchants or high temperature treatment or perimeter coverage with a suitable "passivation layer" as disclosed in US 9,601,659, which aims to mitigate damage and reduce dangling bonds around the active light emitting area.

[0011] However, there remains a need for micro-LED arrays and LED array precursors, and methods of making the same, having high integration density, smaller LEDs, and smaller pitches while avoiding problems associated with non-radiative recombination, particularly surface recombination. Summary of the invention

[0012] It is an object of the present invention to provide an improved LED array precursor which solves at least one problem associated with prior art arrays, or at least provides a commercially useful alternative thereto.

[0013] According to a first aspect, the present disclosure provides a method of forming a monolithic LED array precursor, the method comprising:

[0014] (i) providing a substrate having a surface;

[0015] (ii) forming a continuous first semiconductor layer on the surface of the substrate;

[0016] (iii) selectively masking the first semiconductor layer by depositing a mask layer on the first semiconductor layer, the mask layer comprising a plurality of holes;

[0017] (iv) growing a second semiconductor layer on the unmasked portion of the first semiconductor layer through the holes of the mask layer to form a plurality of pillars, each pillar having a regular trapezoidal cross-section perpendicular to the substrate and a substantially flat upper surface portion;

[0018] (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer includes one or more quantum well sublayers and has a substantially flat upper surface portion;

[0019] (vi) forming a fourth semiconductor layer covering the third semiconductor layer so that the fourth semiconductor layer has a substantially flat upper surface portion;

[0020] (vii) forming a primary electrical contact on a substantially planar upper surface portion of the fourth semiconductor layer; and

[0021] The first to fourth semiconductor layers include group III nitrides.

[0022] The present invention will now be further described. In the following paragraphs, different aspects of the present invention are defined in more detail. Unless clearly indicated to the contrary, each aspect so defined can be combined with any other one or more aspects. Specifically, any feature indicated as preferred or advantageous can be combined with any other one or more features indicated as preferred or advantageous.

[0023] The present disclosure provides methods for forming monolithic LED array precursors, thereby making it possible to manufacture electronically isolated LED structures that exhibit improved light emitting characteristics and reduced non-radiative recombination. The inventors have discovered that by growing the specific structures disclosed and providing electrical contacts only on specific areas of the LED structures, it is possible to form LED array precursors that provide LED devices with improved characteristics.

[0024] The present invention relates to a method of forming a monolithic LED array precursor.LED is well known in the art and refers to a light emitting diode.

[0025] Monolithic array refers to providing a plurality of LED structures formed as a single piece. Array means that the LEDs are intentionally spaced across the monolithic structure, and typically form a regular array, such as a hexagonal close-packing array or a square-packed array of LEDs.

[0026] By the term "precursor", it is noted that the described LED array does not have the necessary relative electrical contacts for each LED, e.g. to allow light emission, nor the associated circuitry. The described array is therefore a precursor to a monolithic LED array that will be formed once the necessary further steps have been performed (e.g. including the counter electrode and any light extraction surfaces, such as may be achieved by removing the substrate).

[0027] The method involves a number of numbered steps. It will be understood that these steps can be performed simultaneously or in parallel where possible.

[0028] The first step involves providing a substrate having a surface. Suitable substrates include sapphire, SiC, and silicon. Other suitable substrates are well known in the art.

[0029] The second step involves forming a continuous first semiconductor layer on the surface of the substrate. The first semiconductor layer can be used as a buffer layer. The first semiconductor layer and indeed other semiconductor layers include group III nitrides. Preferably, the group III nitrides include one or more of AlInGaN, AlGaN, InGaN and GaN.

[0030] As used herein, any reference to a species by its constituent components includes all available stoichiometries thereof. Thus, for example, AlGaN includes all alloys thereof (e.g., Al x Ga 1-x N, where x is not equal to 1 or 0). The preferred stoichiometry will vary depending on the function of the particular layer.

[0031] The third step involves selectively masking the first semiconductor layer by depositing a mask layer on the first semiconductor layer, the mask layer comprising a plurality of holes. Preferably, the mask layer comprises SiO2 and / or SiN x . SiO2 and / or SiN x The mask layer can be deposited ex-situ using standard deposition techniques (e.g., plasma enhanced chemical vapor deposition). Alternatively, SiN can be deposited in-situ in a reaction chamber. x Masking layers, suitable reaction chambers (eg, MOCVD reactors) are well known in the art.

[0032] Optionally, the plurality of holes form a regularly spaced array. This can be similar to any configuration of closely packed circles, such as square packing or hexagonal packing.

[0033] The preferred way to implement the third step is:

[0034] (a) depositing successive mask layers, and

[0035] (b) selectively removing portions of the mask layer to provide a plurality of holes.

[0036] Optionally, selectively removing portions of the mask layer comprises selectively removing corresponding portions of the first semiconductor layer. This means that a second, optional, discontinuous layer is then formed within the wells of the first semiconductor layer.

[0037] The fourth step involves growing an optional discontinuous second semiconductor layer on the unmasked portion of the first semiconductor layer through the holes of the mask layer to form a plurality of pillars, each pillar having a regular trapezoidal cross-section perpendicular to the substrate and a substantially flat upper surface portion. The flat upper portion is in a plane parallel to the plane of the substrate surface on which the layer is formed.

[0038] "Regular trapezoidal cross-section" means that the tops of the columns are narrower than the bottoms, and that they have substantially flat upper and lower parallel surfaces and inclined linear sides. This can result in a truncated pyramid, or more likely, a truncated pyramid with three or more sides (typically 6 sides). The description of a "regular trapezoidal cross-section" refers to the portion of the second semiconductor layer that extends above the first semiconductor layer. The bottommost portion of the second semiconductor layer is within the hole defined by the first semiconductor layer, so the bottom typically has a constant cross-section rather than a tapering cross-section. The tapered sides of the columns are referred to herein as sides or facets. In the case where the second layer is continuous, the trapezoidal cross-section is a discontinuous portion of the second semiconductor layer that extends above a continuous planar portion of the second semiconductor layer.

[0039] Preferably, the side of the pillar has a substantially consistent angle (α) with a plane parallel to the first semiconductor layer. That is, the angle between the side of the pillar and the plane parallel to the first semiconductor does not vary significantly. Preferably, the angle α is between 50° and 70°, more preferably between 58° and 64°, and most preferably about 62°.

[0040] Preferably, each of the plurality of pillars in the second semiconductor layer is a truncated hexagonal pyramid.

[0041] The fifth step involves forming an optionally discontinuous third semiconductor layer overlying the optionally discontinuous second semiconductor layer, wherein the third semiconductor layer includes one or more quantum well sublayers and has a substantially flat upper surface portion.

[0042] "Substantially planar upper surface portion" is understood to mean that the upper portion of the particular semiconductor layer is generally parallel to the first semiconductor layer (ie provides a plane parallel to the plane of the substrate).

[0043] The inventors have found that deposition of material of the third semiconductor layer on the second semiconductor layer has a thicker uppermost surface, but has significantly thinner layers deposited on the facets. This arises automatically due to the growth rates in various directions relative to the crystal structure.

[0044] Layers deposited on the inclined plane surrounding the mask hole are generally thinner than layers deposited on the c-plane-oriented surface portion. Specifically, the InGaN multiple quantum well (MQW) deposited between the n-type doping and the p-type doping in the pn junction within the LED is thinner in the portion deposited in contact with the inclined surface than in the portion deposited in contact with the c-plane-oriented surface.

[0045] It is known to those skilled in the art that emission from tilted GaN planes can provide a means to improve the efficiency of lighting devices due to the reduction of the polarization field in the semi-polar plane. In addition, the presence of different MQW thicknesses at the tilted planes compared to the flat surface portion can also enable phosphor-free multi-wavelength emission from a single device for color tuning purposes.

[0046] In contrast, it is an object of the present invention to confine the generation of light to a substantially planar surface region to prevent carrier injection and / or diffusion into the tilted plane and to prevent potential non-radiative recombination around the active region where the periodic arrangement of atoms in the crystal terminates. Confinement of carriers to the top planar region is achieved by confining the formation of the electrical contact region to a portion of the top planar surface that is distal to the tilted plane.

[0047] The thickness of the MQW is understood to refer to the average shortest distance between the upper and lower surfaces of the quantum well sublayer. Preferably, the thickness of each quantum well sublayer in a specific portion (e.g., a c-plane or a tilted facet) is substantially the same. The thickness of the MQW is preferably substantially constant across the specific portion in which it is deposited, so that the upper surface is substantially parallel to the lower surface.

[0048] Preferably, the thickness of the portion of the MQW oriented along the c-plane is greater than 1 nm, greater than 1.5 nm, greater than 2 nm, greater than 2.5 nm. Preferably, the thickness of the portion of the MQW oriented along the c-plane is less than 15 nm, less than 12 nm, less than 8 nm, less than 5 nm. In a preferred embodiment, the thickness of the portion of the MQW oriented along the c-plane is between 1 nm and 15 nm, more preferably between 2 nm and 12 nm, and most preferably between 2.5 nm and 8 nm.

[0049] Preferably, the thickness of the portion of the MQW on the tilted facet is greater than 0.05 nm, greater than 0.1 nm, greater than 0.15 nm, greater than 0.2 nm. Preferably, the thickness of the portion of the MQW on the tilted facet is less than 5 nm, less than 2 nm, less than 1 nm, less than 0.8 nm. In a preferred embodiment, the thickness of the portion of the MQW on the tilted facet is between 0.1 nm and 1 nm, more preferably between 0.15 nm and 0.6 nm, and most preferably between 0.2 nm and 0.5 nm.

[0050] In addition, the MQW thickness difference between the MQW portion oriented along the c-plane and the portion of the MQW on the tilted facet corresponds to the band gap difference between the two MQW portions, which effectively prevents carriers from diffusing from the flat MQW portion to the tilted MQW portion. This is similar to the mechanism that occurs around threading dislocations in III-nitride LEDs, in which case the injected carriers are confined away from the threading dislocation core, thereby preventing the possibility of non-radiative recombination. Incidentally, the composition of the MQW deposited in the region on the facet can also be different from the composition of the MQW in the thicker uppermost surface, so that carrier confinement still occurs in the thicker uppermost surface. Therefore, uniform and relatively narrow wavelength emission is expected.

[0051] The inventors have recognized that when the band gap difference effectively prevents diffusion of carriers from the flat MQW portion into the tilted MQW portion. Such confinement of carriers requires a barrier of several times kT (where kT is the Boltzmann constant multiplied by the temperature, approximately equal to 25.7 meV at room temperature of 298K). The difference between the MQW thickness between the portion of the MQW oriented along the c-plane and the portion of the MQW on the tilted facet is required so that a barrier of several times kT is achieved (which varies with the composition of the MQW and can be easily calculated by the skilled person). Preferably, the barrier to confine carriers as electrons and / or holes is greater than 2kT, greater than 3kT, greater than 4kT, most preferably greater than 5kT. Preferably, the temperature is room temperature (298K).

[0052] In a preferred embodiment, the thickness of the portion of the MQW oriented along the c-plane is greater than 2 nm, and the thickness of the portion of the MQW on the tilted facet is less than 2 nm. In a more preferred embodiment, the thickness of the portion of the MQW oriented along the c-plane is greater than 2.5 nm, and the thickness of the portion of the MQW on the tilted facet is less than 1.5 nm.

[0053] The sixth step involves forming an optionally discontinuous fourth semiconductor layer overlying the optionally discontinuous third semiconductor layer, whereby the fourth semiconductor layer has a substantially flat upper surface portion. Likewise, deposition of material of the fourth semiconductor layer on the third semiconductor layer occurs as a thicker uppermost surface, while thinner layers are deposited on the facets.

[0054] Preferably, the fourth semiconductor layer is doped with magnesium. Optionally, the doping density of Mg is higher in the thicker uppermost surface but much lower in the layer deposited on the facets, further helping to confine carrier injection to the thicker uppermost surface of the third semiconductor layer.

[0055] Preferably, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are discontinuous. Although preferably, the mask method of the first aspect produces discontinuous layers, in some embodiments, the third semiconductor layer, the fourth semiconductor layer and the fifth semiconductor layer with particularly close spacing can be fused. This forms a continuous or partially continuous portion, where these layers are shared by multiple LED structures.

[0056] The first semiconductor may have a thickness between 100 nm and 8 um and preferably between 3 um and 5 um.

[0057] The pillars of the second semiconductor layer may have a thickness between 500 nm and 4 um and preferably between 1 um and 2 um.

[0058] The substantially flat upper surface portion of the third semiconductor layer may have a thickness between 30 nm and 150 nm and preferably between 40 nm and 60 nm.

[0059] The substantially flat upper surface portion of the fourth semiconductor layer may have a thickness between 50 nm and 300 nm and preferably between 100 nm and 150 nm.

[0060] The thickness of the portion of the semiconductor layer not aligned with the hole in the mask is from 0 nm to the minimum value of the above-mentioned respective layers. Although the mask area is relatively unfavorable for the growth of the subsequent semiconductor layer, this may not be completely prevented.

[0061] The seventh step involves forming a main electrical contact on a substantially planar upper surface portion of the optionally discontinuous fourth semiconductor layer.Any conventional electrode material may be used and it may be applied by conventional techniques such as thermal evaporation or electron beam evaporation.

[0062] Each of the above layers may be formed of one or more sub-layers. For example, the first semiconductor layer may be formed of Al x Ga 1- x A composition gradient layer of N is formed.

[0063] Optionally, the first semiconductor layer includes a sublayer adjacent to the second semiconductor, the sublayer comprising silicon-doped GaN. Preferably, the first semiconductor layer is substantially undoped except for the silicon-doped sublayer. In one embodiment, the first semiconductor layer includes a plurality of undoped (Al)GaN sublayers and silicon-doped sublayers. x Ga 1-x The N sublayer may have a thickness between 100 nm and 1 um, preferably between 300 nm and 500 nm. Preferably, the Al composition is between x=0 and 0.2, more preferably between 0.05 and 0.1. Preferably, the doping level is between 1×10 18 at / cm 3 With 1×10 21 at / cm 3 between 1×10 20 at / cm 3 With 2×10 20 at / cm 3 between.

[0064] Preferably, where the first semiconductor layer includes a silicon doped sublayer, the silicon doped sublayer is partially removed when the plurality of holes are formed, so that the second semiconductor layer is formed directly on the undoped portion of the first semiconductor layer. Advantageously, since the (Al)GaN:Si sublayer is removed where the second semiconductor is grown, the structure allows the use of a highly silicon doped layer for beneficial current spreading without degrading material quality.

[0065] All of the above deposition steps may be performed using conventional semiconductor formation systems.The formation of semiconductor layers for LED production is well known in the art, such as MOCVD.

[0066] It will be appreciated that each of the second semiconductor layer columns provides a base for a single LED structure formed from the associated layer in the final monolithic LED array precursor.

[0067] Another aspect of the invention provides a similar method, but with an alternative method of forming the second semiconductor layer.All aspects of the first aspect discussed above can be freely combined with this embodiment.

[0068] In this other aspect, the first semiconductor layer is processed to provide a pattern of amorphous material that is less favorable for subsequent layer growth. This means that the second semiconductor layer is preferentially formed on the untreated crystalline areas, thereby forming pillars. Depending on the relative growth achieved in the treated and untreated areas, the layer can be continuous or discontinuous. The trapezoidal cross section is a discontinuous portion of the second semiconductor layer that extends above a continuous planar portion of the second semiconductor layer.

[0069] Specifically, this other aspect provides a method of forming a monolithic LED array precursor, the method comprising:

[0070] (i) providing a substrate having a surface;

[0071] (ii) forming a continuous first semiconductor layer on the surface of the substrate;

[0072] (iii) selectively processing the first semiconductor layer to form an amorphous surface region, wherein the amorphous surface region defines a plurality of unprocessed portions of the first semiconductor layer;

[0073] (iv) growing a second semiconductor layer on the untreated portion of the first semiconductor layer to form a plurality of pillars, each pillar having a regular trapezoidal cross-section perpendicular to the substrate and a substantially flat upper surface portion;

[0074] (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer includes one or more quantum well sublayers and has a substantially flat upper surface portion;

[0075] (vi) forming a fourth semiconductor layer covering the third semiconductor layer so that the fourth semiconductor layer has a substantially flat upper surface portion; and

[0076] (vii) forming a primary electrical contact on a substantially planar upper surface portion of the fourth semiconductor layer,

[0077] The first to fourth semiconductor layers include group III nitrides.

[0078] Optionally, the first semiconductor layer comprises a sublayer adjacent to the second semiconductor, the sublayer comprising silicon-doped GaN. Preferably, the first semiconductor layer is substantially undoped except for the silicon-doped sublayer. That is, preferably, the first semiconductor layer comprises a plurality of undoped (Al)GaN sublayers and silicon-doped sublayers.

[0079] Preferably, selectively treating the first semiconductor layer comprises amorphizing a surface portion of the first semiconductor layer by ion implantation. Preferably, the selective treatment comprises the steps of photolithographic patterning and etching, followed by ion implantation. Suitable ions for implantation may be selected from N + , H + and Ar + Advantageously, photolithographic patterning and etching with an appropriate mask pattern can prevent ions from damaging unetched areas of the first semiconductor layer.

[0080] Optionally, in the method of the second aspect, step (iii) comprises:

[0081] (a) depositing a continuous mask layer comprising a mask layer material on the continuous first semiconductor layer;

[0082] (b) selectively removing the mask layer material to provide a plurality of mask regions of the first semiconductor layer;

[0083] (c) treating the first semiconductor layer by ion implantation to form an amorphous material in said layer (except in the masked area), and

[0084] (d) removing remaining mask layer material and, optionally, removing corresponding portions of the first semiconductor layer to provide unprocessed portions of the first semiconductor layer.

[0085] Preferably, where the first semiconductor layer includes a silicon doped sublayer, the silicon doped sublayer is partially removed when the plurality of holes are formed, so that the second semiconductor layer is formed directly on the undoped portion of the first semiconductor layer. Advantageously, since the AlGaN:Si sublayer is removed where the second semiconductor is grown, the structure allows the use of a highly silicon doped layer for beneficial current spreading without degrading material quality.

[0086] Preferably, in the method of the second aspect, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are discontinuous.

[0087] The following disclosure relates to preferred features which are equally applicable to both aspects discussed above.

[0088] Preferably, the second semiconductor layer is n-doped. Preferably, the second semiconductor layer is n-doped with silicon or germanium (preferably silicon).

[0089] Preferably, the third semiconductor layer is undoped.

[0090] Preferably, the fourth semiconductor layer is p-type doped, and preferably, the fourth semiconductor layer is doped with magnesium.

[0091] Advantageously, the above layer compositions provide an LED active area having good light generation and light emission characteristics.

[0092] Preferably, the pixel pitch of the monolithic LED precursor is 10 nm or less, even more preferably 8 nm or less. The pixel pitch may be from 1 nm to 10 nm, more preferably from 4 nm to 8 nm.

[0093] Preferably, the width of each LED structure (pixel) is less than 10nm. When the pixel has a truncated hexagonal pyramid shape, the width of each pixel is the maximum length across the base of the hexagonal pyramid. The length is the distance across the base of the hexagonal pyramid from one corner to the opposite corner. In the case where the layer is continuous, the base of the hexagon is the base of the discontinuous portion of the topmost semiconductor layer extending above the continuous planar portion of the second semiconductor layer. Preferably, the width is less than 9nm, less than 8nm, less than 7nm, less than 6nm, less than 5nm. Preferably, the width of each LED structure is between 2nm and 8nm, even more preferably between 3nm and 6nm.

[0094] Preferably, the first semiconductor layer has a wurtzite crystal structure with a (0001) plane, and a substantially flat upper surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer. Similarly, each flat upper surface of the second semiconductor layer and the third semiconductor layer should be parallel to the (0001) plane of the first semiconductor layer.

[0095] Preferably, the method also includes removing the substrate to facilitate extraction of light from the bottom of the manufactured device (which is turned over in use). Alternatively, at least a portion of the substrate is removed corresponding to each of the above-mentioned individual LED structures to expose a portion of the first semiconductor layer for extracting light from the array precursor. Preferably, the substrate is completely removed and a roughened surface layer is optionally adhered to the exposed first semiconductor layer. The substrate (also referred to as a growth substrate) provides a surface on which the LED array is grown, but does not generally constitute part of the final device. Preferably, the substrate is substantially completely removed to minimize absorption in the case of a non-transparent substrate such as Si, and to minimize crosstalk between LED structures in the array in the case of a transparent substrate such as SiC or sapphire.

[0096] Optionally, the substrate is selectively removed to form a plurality of alignment channels, each alignment channel being aligned with a main contact formed on a substantially planar upper surface portion of the fourth semiconductor layer.

[0097] Optionally, the method further comprises providing the steps of at least partially removing the substrate and at least partially removing the first semiconductor layer to form a plurality of dome or lens structures corresponding to and aligned with each of the plurality of columns of the second semiconductor layer. Preferably, the method comprises completely removing the substrate and partially removing the first semiconductor layer to provide a plurality of convex domes on the far side of the second semiconductor layer. Each dome is aligned with one of the plurality of LED structures of the array.

[0098] Advantageously, the dome structures can improve light extraction and collimation of the LED structure without the need for additional added materials.Preferably, the plurality of dome structures may be coated with a dielectric coating or a transparent epoxy layer to minimize reflections on the dome surfaces.

[0099] Preferably, the method may further include the following steps: providing one or more transparent insulating layers on the fourth semiconductor layer away from at least the portion of the third semiconductor layer where the main electrical contact is not provided, and then providing one or more reflective layers. Preferably, the insulating layer comprises SiO2 and / or SiN x Advantageously, such coatings can improve light extraction from LED structures by reducing light losses within the array, and can improve the collimation of the extracted light.

[0100] Optionally, the method further includes forming one or more auxiliary electrical contacts that are electrically connected to the main electrical contacts across the quantum well sublayers to form a monolithic LED array. By providing the auxiliary electrical contacts, all functions required for the LED array to function are provided. That is, applying a potential difference across the main contacts and the auxiliary contacts will cause one or more LED structures to emit light.

[0101] Preferably, one or more auxiliary electrical contacts are formed on the first semiconductor layer.

[0102] The formed monolithic LED array precursor preferably includes at least four LED structures, each LED structure corresponding to a different second semiconductor layer portion, a corresponding third semiconductor layer portion formed thereon, a corresponding fourth semiconductor layer portion formed thereon, and a corresponding primary electrical contact formed thereon. The LED array precursor is preferably a micro-LED array.

[0103] Preferably, the monolithic LED array precursor comprises at least a first sub-array and a second sub-array of LED structures, each sub-array being capable of emitting light at a different dominant wavelength.

[0104] In another aspect, the present disclosure provides a monolithic LED array precursor. Preferably, this can be obtained by one of the methods described in the above aspects. Therefore, all aspects described in relation to the structure formed by the above method are equally applicable to the precursor described herein.

[0105] In another aspect, the present disclosure provides a monolithic LED array precursor comprising:

[0106] A plurality of LED structures share a first semiconductor layer, wherein the first semiconductor layer defines a plane of an LED array precursor, each LED structure comprising:

[0107] (i) a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the second semiconductor layer has an inclined side surface;

[0108] (ii) a third semiconductor layer, on the second semiconductor layer, the third semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the third semiconductor layer having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the third semiconductor layer has an inclined side surface parallel to the inclined side surface of the second semiconductor layer;

[0109] (iii) a fourth semiconductor layer, on the third semiconductor layer, the fourth semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the fourth semiconductor layer having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the fourth semiconductor layer has an inclined side surface parallel to the inclined side surface of the third semiconductor layer; and

[0110] (iv) a primary electrical contact on the fourth semiconductor layer, wherein the contact is only on a portion of an upper surface of the fourth semiconductor layer that is parallel to the plane of the LED array precursor;

[0111] The third semiconductor layer includes a plurality of quantum well sublayers, the portions of the quantum well sublayers parallel to the plane of the LED array precursor have a greater thickness, and the portions of the quantum well sublayers not parallel to the plane of the LED array precursor have a reduced thickness.

[0112] Preferably, the LED array precursor comprises a mask portion at the interface between the first semiconductor layer and the second semiconductor layer. The mask portion of the LED precursor may be the same as those discussed with respect to the first aspect above. Alternatively, the LED array precursor may have an amorphized portion of the first semiconductor layer produced by ion implantation.

[0113] Preferably, a distance between the inclined side surface of the third semiconductor layer and the inclined side surface of the second semiconductor layer is smaller than a distance between an upper surface portion of the third semiconductor layer and an upper surface portion of the second semiconductor layer.

[0114] Preferably, a distance between the inclined side surface of the fourth semiconductor layer and the inclined side surface of the third semiconductor layer is smaller than a distance between an upper surface portion of the fourth semiconductor layer and an upper surface portion of the third semiconductor layer.

[0115] Optionally, the second, third and fourth semiconductor layers are shared between LED structures in the array.This may occur when the second aspect described above is used to produce a precursor having an amorphous base pattern that prevents subsequent overgrowth.

[0116] Preferably, the plurality of LED structures form a regularly spaced array. Preferably, the second to fourth layers of the LED structures are truncated hexagonal pyramids.

[0117] Advantageously, the above layer compositions provide an LED active area with good light generation and light extraction properties.

[0118] Preferably, the first semiconductor layer has a wurtzite crystal structure with a (0001) plane, and a substantially flat upper surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer.

[0119] Preferably, the LED structure of the LED array precursor comprises a shared light extraction layer on the surface of the first semiconductor layer away from the second semiconductor layer. In one embodiment, the shared light extraction layer comprises a plurality of collimating channels, each collimating channel being aligned with the main contact. Alternatively, the first semiconductor layer forms a plurality of dome or lens structures corresponding to and aligned with the plurality of LED structures on the surface away from the second semiconductor layer.

[0120] In another aspect, the present disclosure provides a monolithic LED array comprising a monolithic LED array precursor as described herein, and further comprising one or more auxiliary electrical contacts in electrical communication with the primary electrical contacts across the quantum well sublayers. The array is based on the precursor as described above, and preferably, as obtained from the method as described herein. Therefore, all features described in those aspects apply equally to this other aspect.

[0121] Preferably, the monolithic LED array comprises at least four LED structures. The LED array is preferably a micro-LED array. Preferably, the monolithic LED array comprises at least a first sub-array and a second sub-array of LED structures, each sub-array being capable of emitting light at a different dominant wavelength. Preferably, the light generating layer in each sub-array emits light with a narrow wavelength bandwidth, preferably in the range between 370 nm and 680 nm, more preferably in the range between 420 nm and 520 nm.

[0122] In another aspect, the present disclosure provides a display device comprising the monolithic LED array disclosed herein.Preferably, the method of the present disclosure is suitable for producing the LED array precursor and the LED array disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0123] The present invention will now be described in conjunction with the following non-limiting drawings. Other advantages of the present disclosure will become apparent by reference to the detailed description when considered in conjunction with the accompanying drawings, which are not drawn to scale in order to more clearly show details, wherein like reference numerals throughout the several views indicate like elements, and wherein:

[0124] Figure 1a and Figure 1b An LED array precursor according to a first aspect is shown, wherein:

[0125] Figure 1a A plan view of an LED array precursor is shown.

[0126] Figure 1b A cross section of an LED array precursor is shown.

[0127] Figure 2 A cross section of a portion of an LED array precursor according to the second aspect is shown.

[0128] Figure 3 A cross section through an embodiment of an LED array precursor is shown, wherein the first semiconductor layer comprises a silicon doped surface layer.

[0129] Figures 4a to 4e Further details of the LED array precursor and LED structure according to the first aspect are shown. Figure 4d and Figure 4e , the light path within a micro-LED with and without a convex dome according to the present invention is shown.

[0130] Figure 5a to Figure 5c Simulated light extraction efficiency values ​​and full width at half maximum beam angle (in degrees) are shown for LEDs of the present disclosure.

[0131] Figures 6a to 6c Scanning electron microscope (SEM) images and atomic force microscope (AFM) measurements of the micro-LEDs of the present disclosure are shown.

[0132] Figure 7 An LED array of the present disclosure is shown. DETAILED DESCRIPTION

[0133] Figure 1a A plan view showing a portion of an LED array precursor according to the first aspect of the present disclosure. Figure 1b A vertical cross section along line S1 is shown.

[0134] Figure 1a and Figure 1b The LED array precursor includes a growth substrate (100); a first semiconductor layer (110); a mask layer (120); a discontinuous second semiconductor layer (130) including a plurality of pillars; a discontinuous third semiconductor layer (140) including a plurality of quantum well sublayers (141); a discontinuous fourth semiconductor layer (150); and a main electrical contact (160) on a substantially flat upper surface portion of the discontinuous fourth semiconductor layer (150).

[0135] The regular trapezoidal cross section of the second semiconductor layer (130) can be seen in the cross section. In the embodiment shown, the inclined portions of the third semiconductor layer (140) and the fourth semiconductor layer (150) are thinner than the portions parallel to the substantially flat upper surface portion. Similarly, the inclined portions of the quantum well sublayer (141) are thinner than the portions parallel to the substantially flat upper surface portion of the second semiconductor layer (130).

[0136] exist Figure 1b In a plan view of FIG. 1 , the hexagonal shape of the pillars can be viewed as the upper surface of the fourth semiconductor layer ( 150 ), wherein the main electrical contact ( 160 ) is isolated in the center of each pillar. The area between the pillars is the upper surface of the mask layer ( 120 ).

[0137] Figure 2 The LED array precursor includes a growth substrate (100); a first semiconductor layer (110); an amorphous surface region (121) of the first semiconductor layer; a second semiconductor layer (130) including a plurality of pillars; a third semiconductor layer (140) including a plurality of quantum well sublayers (not shown); a fourth semiconductor layer (150); and a main electrical contact (160) on a substantially flat upper surface portion of the discontinuous fourth semiconductor layer (150).

[0138] exist Figure 2 In the embodiment of FIG. 1 , the second semiconductor layer 130 , the third semiconductor layer 140 , and the fourth semiconductor layer 150 are continuous.

[0139] Figure 3 The invention discloses a cross section of a single LED structure of an LED array precursor, wherein the first semiconductor layer (110) includes a silicon-doped sublayer (190) near the surface of the second semiconductor layer (130). In addition, when forming the mask layer (120), the first semiconductor layer is partially removed below the hole in the mask layer, so that the second semiconductor layer (130) penetrates into the first semiconductor layer (110) through the silicon-doped sublayer (190).

[0140] Figure 4a A single LED structure of the LED array precursor of the first aspect is shown, wherein the growth substrate has been completely removed and the first semiconductor layer (110) has been shaped into the form of a dome aligned with the LED structure. Figure 4b In the LED structure, the surface of the dome has been coated with a dielectric coating or a transparent epoxy layer (115) to minimize reflection at the surface of the convex dome. Figure 4c In, as in Figure 4b The dome is coated as in the embodiment of the present invention and the surface of the pillar is coated with SiO2 and / or SiN xThe fourth semiconductor layer (150) is provided with a transparent layer and a reflective layer (170). Specifically, the exposed surface of the inclined portion of the fourth semiconductor layer (150) is coated. Advantageously, these features (dome, dome coating and coating of the sides of the pillars) improve light extraction and collimation.

[0141] The inventors have discovered that Figures 4a to 4c As shown, adding a dome-shaped region aligned with the base of the pyramid can enhance light extraction from the pyramid. Advantageously, this complements the collimation effect obtained by total internal reflection at the sidewalls of the pyramid. Preferably, the dome-shaped region has a radius of curvature that matches the size of the base of the pyramid. That is, the base of the dome-shaped region and the base of the pyramid are preferably approximately the same size.

[0142] Figure 4d and Figure 4e An illustrative optical path within a micro-LED according to the present invention is shown. Figure 4d and Figure 4e It is clear that the addition of a convex dome aligned with the base of the pyramid reduces the amount of light reflected back inside the micro-LED at the light extraction surface (the surface from which light escapes the LED), further improving the light extraction efficiency.

[0143] Figure 5a to Figure 5c The simulated light extraction efficiency values ​​and the full width at half maximum beam angle (in degrees) of three model LEDs of the present disclosure are shown. Specifically, Figure 5a The LEDs on the sides of the column are not coated. Figure 5b In the case of Figure 5c In the figure, the side is coated with Ag / Si3N4.

[0144] Compared to known structures designed to improve light extraction from conventional LEDs, in which pyramids are etched away from an otherwise flat and borderless light generating area, the light generating area in the disclosed invention is completely contained within the pyramidal structure, thereby substantially preventing lateral (parallel to the LED layers) propagation of light.

[0145] Compared to another class of known similar structures in which the light generating area is completely contained within an inclined surface obtained by dry etching in order to improve light extraction (see, for example, US 7518149), the inclined facets obtained by the selective area growth process have advantages in light extraction because they are smoother than the surfaces obtained by dry etching, thereby promoting total internal reflection on the inclined sidewalls and causing a higher percentage of the generated light to be collimated toward the light extraction surface intersecting at a near-normal angle.

[0146] Figure 6a SEM images are shown and Figure 6bAFM measurements of micro-LEDs according to the present disclosure are shown. Figure 6c yes Figure 6b The AFM-measured cross-section in FIG. 4 shows the morphology of the micro-LED corresponding to the sidewall in more detail. These images demonstrate that the disclosed method produces smooth micro-LED sidewalls.

[0147] Compared with anisotropic dry etching, more consistent and reproducible sidewall tilt angles (usually the angle at the base of the pyramid) are obtained due to the advantage of different growth rates on different crystal planes. Figure 4a α in the equation is close to 62°. This is due to Figure 6c An AFM cross section is shown.

[0148] It will be appreciated by those skilled in the art that, while the improvement in light extraction obtained by the presence of the inclined sidewalls around the light emitting region is attributed to the effect of total internal reflection, the enhancement in light extraction obtained by adding the dome-shaped region comes from the reduction in total internal reflection of the light extraction surface, since most of the light has been partially collimated by the inclined facets and therefore intersects the internal dome surface at a near normal angle. Therefore, obtaining the dome by dry etching does not constitute a detriment to the operating principles disclosed thereby, given the fact that light extracted from the dome-shaped surface does not rely on total internal reflection.

[0149] Figure 7 Shown is a cross section through an LED array of the present disclosure. Figure 7 The LED array includes Figure 1a and Figure 1b The LED array precursor has been flipped over and bonded to a base plate including a base plate substrate (200) and a base plate contact pad (202). The growth substrate of the LED array precursor has been removed, and a roughening layer (112) is laminated onto the exposed surface of the first semiconductor layer (110). In addition, an auxiliary electrical contact (180) is applied to the first semiconductor layer. The main electrical contact and the auxiliary electrical contact are in electrical contact with each other through the LED structure.

[0150] Those skilled in the art will appreciate that the various embodiments discussed above may be combined in a single LED backlight. Figure 4c As shown, the dome, dome coating 115 and coated side (170) of the column may be Figure 3 The silicon doped sublayer (190) is combined.

[0151] Although preferred embodiments of the present invention have been described in detail herein, those skilled in the art will appreciate that modifications may be made thereto without departing from the scope of the invention or the appended claims.

Claims

1. A monolithic LED array precursor, comprising: A plurality of LED structures share a first semiconductor layer, wherein the first semiconductor layer defines a plane of the LED array precursor, each LED structure comprising: (i) a second semiconductor layer, on the first semiconductor layer, the second semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, the second semiconductor layer having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the second semiconductor layer has an inclined side surface; (ii) a third semiconductor layer, on the second semiconductor layer, the third semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, wherein the third semiconductor layer and the second semiconductor layer form a structure having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the third semiconductor layer has an inclined side surface parallel to the inclined side surface of the second semiconductor layer; (iii) a fourth semiconductor layer, on the third semiconductor layer, the fourth semiconductor layer having an upper surface portion parallel to the plane of the LED array precursor, wherein the fourth semiconductor layer, the third semiconductor layer and the second semiconductor layer form a structure having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the fourth semiconductor layer has an inclined side surface parallel to the inclined side surface of the third semiconductor layer; and (iv) a primary electrical contact on the fourth semiconductor layer, wherein the contact is only on a portion of the upper surface of the fourth semiconductor layer that is parallel to the plane of the LED array precursor; The third semiconductor layer includes a plurality of quantum well sublayers, portions of the quantum well sublayers parallel to the plane of the LED array precursor have a greater thickness, and portions of the quantum well sublayers not parallel to the plane of the LED array precursor have a reduced thickness.

2. The monolithic LED array precursor according to claim 1, wherein: The distance between the inclined side surface of the third semiconductor layer and the inclined side surface of the second semiconductor layer is smaller than the distance between the upper surface portion of the third semiconductor layer and the upper surface portion of the second semiconductor layer, and / or The distance between the inclined side surface of the fourth semiconductor layer and the inclined side surface of the third semiconductor layer is smaller than the distance between the upper surface portion of the fourth semiconductor layer and the upper surface portion of the third semiconductor layer.

3. The monolithic LED array precursor according to claim 1 or 2, wherein: The inclined side surfaces of each layer form a plurality of planar facets.

4. The monolithic LED array precursor according to claim 1, wherein: The second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are shared between LED structures.

5. The monolithic LED array precursor according to claim 1, wherein: The first semiconductor layer has a wurtzite crystal structure having a (0001) plane, and a flat upper surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer.

6. The monolithic LED array precursor according to claim 1, wherein: The first semiconductor layer includes a plurality of lens structures corresponding to and aligned with the plurality of LED structures.

7. A monolithic LED array comprising the monolithic LED array precursor according to any one of claims 1 to 6, and further comprising one or more auxiliary electrical contacts in electrical communication with the primary electrical contact across the quantum well sublayer.

8. The monolithic LED array of claim 7, wherein: The monolithic LED array includes at least a first sub-array and a second sub-array of LED structures, each sub-array being capable of emitting light at a different dominant wavelength.

9. A display device comprising the monolithic LED array according to any one of claims 7 and 8.

10. A method of forming a monolithic LED array precursor, the method comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively masking the first semiconductor layer by depositing a mask layer on the first semiconductor layer, the mask layer comprising a plurality of holes; (iv) growing a second semiconductor layer through the holes of the mask layer on the unmasked portion of the first semiconductor layer to form a plurality of pillars, each pillar having a regular trapezoidal cross section perpendicular to the substrate and a flat upper surface portion, so that the second semiconductor layer has an inclined side surface; (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer includes a plurality of quantum well sublayers and has a flat upper surface portion, wherein the third semiconductor layer and the second semiconductor layer form a structure having a regular trapezoidal cross-section perpendicular to the upper surface portion, so that the third semiconductor layer has an inclined side surface portion parallel to the inclined side surface of the second semiconductor layer, and wherein the flat upper surface portion of the quantum well sublayer has a greater thickness and a portion of the inclined side surface portion has a reduced thickness; (vi) forming a fourth semiconductor layer covering the third semiconductor layer, so that the fourth semiconductor layer has a flat upper surface portion; (vii) forming a primary electrical contact only on the flat upper surface portion of the fourth semiconductor layer; and Wherein, the first semiconductor layer to the fourth semiconductor layer include group III nitride.

11. The method according to claim 10, wherein: The second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are discontinuous.

12. The method according to claim 10 or 11, wherein: Step (iii) comprises: (a) depositing successive mask layers, and (b) selectively removing portions of the mask layer to provide a plurality of holes, wherein selectively removing portions of the mask layer comprises selectively removing corresponding portions of the first semiconductor layer.

13. A method of forming a monolithic LED array precursor, the method comprising: (i) providing a substrate having a surface; (ii) forming a continuous first semiconductor layer on the surface of the substrate; (iii) selectively processing the first semiconductor layer to form an amorphous surface pattern, wherein the amorphous surface pattern defines a plurality of unprocessed portions of the first semiconductor layer; (iv) growing a second semiconductor layer on the untreated portion of the first semiconductor layer to form a plurality of pillars, each pillar having a regular trapezoidal cross-section perpendicular to the substrate and a flat upper surface portion; (v) forming a third semiconductor layer covering the second semiconductor layer, wherein the third semiconductor layer includes one or more quantum well sublayers and has a flat upper surface portion, wherein the third semiconductor layer and the second semiconductor layer form a structure having a regular trapezoidal cross section perpendicular to the upper surface portion, such that the third semiconductor layer has an inclined side surface portion parallel to the inclined side surface of the second semiconductor layer, and wherein the flat upper surface portion of the quantum well sublayer has a greater thickness and a portion of the inclined side surface portion has a reduced thickness; (vi) forming a fourth semiconductor layer covering the third semiconductor layer so that the fourth semiconductor layer has a flat upper surface portion; and (vii) forming a primary electrical contact on the flat upper surface portion of the fourth semiconductor layer; Wherein, the first semiconductor layer to the fourth semiconductor layer include group III nitride.

14. The method according to claim 13, wherein: The plurality of holes form a regularly spaced array.

15. The method according to claim 13, wherein: The first semiconductor layer has a wurtzite crystal structure having a (0001) plane, and the flat upper surface portion of the fourth semiconductor layer is parallel to the (0001) plane of the first semiconductor layer.

16. The method according to claim 13, further comprising: One or more auxiliary electrical contacts are formed across the quantum well sublayers in electrical communication with the primary electrical contacts to form a monolithic LED array, wherein the one or more auxiliary electrical contacts are formed on the first semiconductor layer.

17. The method according to claim 13, wherein: The monolithic LED array precursor includes at least a first sub-array and a second sub-array of LED structures, each sub-array being capable of emitting light at a different dominant wavelength.

18. The method according to claim 13, further comprising the steps of: The substrate is at least partially removed, and the first semiconductor layer is at least partially removed to form a plurality of dome or lens structures corresponding to and aligned with each of the plurality of pillars of the second semiconductor layer.

19. The method according to claim 13, wherein: The substrate is selectively removed to form a plurality of alignment channels, each alignment channel being aligned with a main contact formed on the planar upper surface portion of the fourth semiconductor layer.

20. A monolithic LED array precursor or LED array obtainable by the method of any one of claims 10 to 19.

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