Dynamic sleep of display panel

Abstract

Techniques for a display controller are described. When the display controller is in a dynamic sleep state, the display controller can detect a frame update. The display controller can wake up from the dynamic sleep state at a programmed vertical blanking interrupt (VBI) before the actual VBI and enter a selective update state. The display controller can perform a scanout of a display panel during the selective update state. After the scanout is completed, the display controller can return to the dynamic sleep state within the same time frame. The display controller can not include timing logic for sending a VBI to the display panel in each time frame to maintain time synchronization between the display controller and the display panel.

Description

[0001] This application is a divisional application of the invention patent application with the application date of May 29, 2019, application number 201910457806.6, and name “Dynamic Sleep of Display Panel”. Background Art

[0002] Display interfaces can allow audio / video to be sent from a source device to a display device. Common types of display interfaces include, but are not limited to, High Definition Multimedia Interface (HDMI), DisplayPort (DP), embedded DisplayPort (eDP), or Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI). HDMI is a proprietary audio / video interface for sending uncompressed video data and compressed / uncompressed digital audio data from an HDMI-compatible source device (such as a display controller) to a compatible computer monitor, video projector, digital television, or digital audio device. HDMI is a digital replacement for analog video standards. DisplayPort is a digital display interface standardized by the Video Electronics Standards Association (VESA). DisplayPort is an interface for connecting a video source to a display device (such as a computer monitor) and is capable of carrying audio and other forms of data. DisplayPort is designed to replace Video Graphics Array (VGA) and Digital Visual Interface (DVI). The DisplayPort interface is backward compatible with other interfaces, such as HDMI and DVI. eDP defines a standardized display panel interface for internal connections, for example, a graphics card to a notebook display panel. MIPI DSI defines a high-speed serial interface between a host processor and a display module. MIPI DSI enables manufacturers to integrate displays to achieve high performance and improved image and video scenarios. MIPI DSI is commonly used for displays in smartphones, tablets, laptops and vehicles. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Features and advantages of the technical embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which together illustrate the technical features by way of example; and wherein:

[0004] Figure 1 illustrates a panel self-refresh 2 (PSR2) state machine according to an example embodiment;

[0005] Figure 2 illustrates a programmed vertical blanking interrupt (VBI) according to an example embodiment;

[0006] Figure 3 illustrates an improved PSR2 state machine with dynamic sleep states according to an example embodiment;

[0007] Figure 4 illustrates dynamic sleep simulation results according to an example embodiment;

[0008] Figure 5 illustrates a PSR2 default flow according to an example embodiment;

[0009] Figure 6 illustrates a dynamic sleep flow utilizing synchronous operation according to an example embodiment;

[0010] Figure 7 illustrates a dynamic sleep flow utilizing asynchronous operation according to an example embodiment;

[0011] Figure 8 illustrates a dynamic sleep flow utilizing asynchronous transfer agnostic display (TAD) operation according to an example embodiment;

[0012] Fig. 9 illustrates a display accelerator utilizing dynamic sleep according to an example embodiment;

[0013] Fig.10 illustrates a display system according to an example embodiment;

[0014] Fig.11 is a flow chart illustrating operations for making a display system according to an example embodiment; and

[0015] Fig.12 is a flow chart illustrating operations at a display controller for operating in a dynamic sleep state according to an example embodiment; and

[0016] Fig.13 A computing system including a data storage device according to an example embodiment is illustrated.

[0017] Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. However, it will be understood that no limitation of the scope of the technology is intended thereby. DETAILED DESCRIPTION

[0018] Before describing the disclosed technical embodiments, it will be understood that the present disclosure is not limited to the specific structures, process steps, or materials disclosed herein, but extends to their equivalents as will be recognized by those skilled in the art. It should also be understood that the terms used herein are only used for the purpose of describing specific embodiments or implementations and are not restrictive. The same reference numerals in different figures represent the same elements. The numbers provided in the flow charts and processes are provided for the purpose of clearly illustrating the steps and operations and do not necessarily imply a specific order or sequence.

[0019] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, a large number of specific details are provided, such as examples of layouts, distances, network examples, etc., to provide a thorough understanding of various technical embodiments. However, those skilled in the art will recognize that these detailed embodiments do not limit the overall technical concept set forth herein, but are merely representative thereof.

[0020] As used in the written description, the singular forms "a," "an," and "the" include explicit support for plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a circuit" includes a plurality of such circuits.

[0021] References to "examples" throughout this specification mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one embodiment of the present technology. Thus, the phrases "in an example" or "an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment.

[0022] As used herein, for convenience, multiple items, structural elements, constituent elements, and / or materials can be presented in the same list. However, these lists should be interpreted as if each member in the list is individually identified as an independent and unique member. Thus, any single member in such a list should not be understood as being in fact equivalent to any other member in the same list based only on their appearance in the same group without contrary instructions. In addition, here, various embodiments and examples of the present technology can be mentioned together with substitutes of its various components. It is understood that such embodiments, examples, and substitutes should not be interpreted as actual equivalents to each other, but are regarded as separate and autonomous representatives under the present disclosure.

[0023] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, a large number of specific details are provided, such as examples of layouts, distances, network examples, etc., to provide a thorough understanding of the technical embodiments. However, those skilled in the art will recognize that the technology can be practiced without one or more specific details or using other methods, components, layouts, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0024] In the present disclosure, "comprises", "comprising", "including", "having", etc. can have the meanings assigned to them in the Chinese Patent Law and can mean "includes", "including", etc., and are generally interpreted as open terms. The term "consisting of" or "consists of" is a closed term and only includes components, structures, steps, etc. specifically listed in conjunction with such terms, as well as those in accordance with the Chinese Patent Law. "Substantially consisting of" or "substantially consisting of" have the meanings generally assigned to them in the Chinese Patent Law. In particular, such terms are generally closed terms, but allow the inclusion of other items, materials, components, steps, or elements that do not substantially affect the basic and novel features or functions of the (one or more) terms used in conjunction with them. For example, if there is "substantially consisting of" language, trace elements present in the composition but not affecting the properties or characteristics of the composition are allowed, even if there is no explicit record in the list of items following such a term. When open-ended terminology such as "comprsing" or "including" is used in this written description, it should be understood that "consisting essentially of" language as well as "consisting of" language should also be directly supported as if explicitly stated, and vice versa.

[0025] If any, the terms "first", "second", "third", "fourth", etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a particular order or timing. It will be understood that any terms so used are interchangeable where appropriate, such that the embodiments described herein are capable of operating in an order other than that set forth or otherwise described herein, for example. Similarly, if a method is described herein as comprising a series of steps, the order of the steps given herein is not necessarily the only order in which the steps may be performed, and certain recorded steps may be omitted and / or certain other steps not described herein may be added to the method.

[0026] As used herein, comparative terms such as "increase", "decrease", "better", "worse", "higher", "lower", "enhance", "minimize", "maximize", etc., refer to the properties of devices, components, or activities that are measurably different from other devices, components, or activities in surrounding or adjacent areas, in a single device or in multiple comparable devices, in a group or class, in multiple groups or classes, or compared to known prior art. For example, a data area with an "increased" risk of damage can refer to an area of ​​a memory device that is more likely to have a write error than other areas in the same memory device. Many factors can lead to such an increased risk, including location, manufacturing process, the number of program pulses applied to the area, etc.

[0027] As used herein, the term "substantially" refers to the complete or nearly complete degree or degree of an action, characteristic, property, state, structure, item, or result. For example, an object that is "substantially" closed means that the object is completely or almost completely closed. In some cases, the exact degree of deviation from the absolute complete permission can depend on the specific context. However, in general, the degree of closeness completely will have the same overall result, as obtaining absolute and total completeness. When used in a negative connotation, the use of "substantially" can also be applied to refer to the complete or almost complete lack of action, characteristic, property, state, structure, item, or result. For example, a composition that is "substantially free of" particles either does not have particles completely, or does not have particles almost completely so that the effect is the same as the effect of not having particles completely. In other words, a composition that is "substantially free of" ingredients or elements can actually still contain such items, as long as there is no measurable effect thereof.

[0028] As used herein, the term "about" is used to provide flexibility to numerical range endpoints by specifying that a given value may be "slightly above" or "slightly below" the endpoint. However, it will be understood that even when the term "about" is used in conjunction with a specific numerical value in this specification, support is provided for precise numerical values ​​that are different from the "about" term.

[0029] Numerical quantities and data can be expressed or given in range format here.It will be understood that such range format is only used for convenience and simplicity, and thus should be flexibly interpreted as not only including the numerical value clearly listed as range limitation, but also including all individual numerical values ​​or sub-data included in this range, as each numerical value and sub-range are clearly recorded.As an illustration, the numerical range of "about 1 to about 5" should be interpreted as not only including the value of about 1 to about 5 clearly recorded, but also including a single value and sub-range in the indicated range.Thus, included in this numerical range are single values ​​(such as 2,3 and 4) and sub-ranges (such as 1-3, 2-4 and 3-5, etc.), and single 1,1.5,2,2.3,3,3.8,4,4.6,5 and 5.1.

[0030] This same principle applies to ranges reciting only one numerical value as a minimum or maximum. Furthermore, such an interpretation should apply regardless of the breadth of the range or the properties being described.

[0031] A preliminary overview of the technical embodiments is provided below, and then specific technical embodiments are described in further detail later. This preliminary overview is intended to help the reader understand the technology more quickly, but is not intended to identify key or basic technical features, nor is it intended to limit the scope of the claimed subject matter. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by ordinary technicians in the field to which this disclosure belongs.

[0032] The present technology relates to dynamic sleep states for embedded display panels (eDP), mobile industry processor interfaces (MIPI), and transport agnostic displays (TAD) to reduce the power consumption of a central processing unit (CPU) or a system on chip (SoC). For key uses such as web browsing, office efficiency, video playback, etc., the power consumption of the CPU / SoC can be reduced. In existing solutions, for these use cases, due to the low efficiency of the CPU / SoC, the display engine (DE) (also referred to as the display controller here) blocks certain package (PKG) CPU states (or C-states). In other words, in existing solutions, some deeper PKG C-states (e.g., PKG C10) will be prevented and only reduced PKG C-states (e.g., PKG C8) can be achieved, thereby not allowing the SoC to enter the deepest PKG C-state and achieve the highest level of power efficiency. For example, the range of PKG C-states can be from C0 to C10, where C0 is the lowest sleep state (i.e., the state with the most activity) and C10 is the deepest sleep state (i.e., the state with the least activity). Thus, in the present technology, the panel self-refresh 2 (PSR2) mechanism can be enhanced to eliminate the CPU / SoC's dependency on DE, thereby achieving lower power states (e.g., PKG C10) and improving the efficiency of DE for active frames. A dynamic sleep state can be used to achieve a lower power state, which can provide a competitive low-power CPU / SoC and meet the power targets of the next generation CPU / SoC. In addition, the dynamic sleep state can also be extended to MIPI and TAD protocols.

[0033] Figure 1An example of a PSR2 state machine, such as an eDP PSR2 state machine, is illustrated. The DE can start in a reset state, and after 1-16 programmed idle frames, the DE can enter a capture state. The DE can remain in the capture state for a frame time, where the panel can copy the frame in its remote frame buffer for panel self-refresh. During the capture state, the panel can refresh the panel or accept updates. After the capture frame time, the DE can enter a sleep state. The DE can remain in the sleep state for another 1-16 programmed idle frames before entering a deep sleep state. When the DE is in the deep sleep state, the CPU / SoC can enter a lower power state (e.g., PKG C10). When in the deep sleep state, a vertical blanking interrupt (VBI) or a frame update (flip) can prompt the DE to return to the reset state. During a long cycle, the DE can be in a reset state, a capture state, a sleep state, and a deep sleep state. On the other hand, when in the sleep state and there is a frame update (flip), the DE can enter a selective update state and send the updated scan lines to the panel. The DE can enter a selective update state during a short cycle. During the short cycle, a partial frame can be sent and not necessarily the entire frame. During the short cycle, if there is no update, the panel can update from its own frame buffer. While in sleep state, when there is an update, the DE can enter the selective update state and then return to sleep state.

[0034] In one example, during the short cycle, the DE can maintain time synchronization with the panel, while in the deep sleep state of the long cycle, time synchronization is not maintained between the DE and the panel. Thus, from the panel's perspective, the panel is in a refresh state in both the long cycle and the short cycle, but whether time synchronization is maintained can depend on the type of cycle the DE enters (i.e., long cycle or short cycle).

[0035] In one configuration, the previous PSR2 implementation has various problems that prevent the CPU / SoC from entering a lower power state (e.g., PKG C10). In the previous PSR2 implementation, PKG C8 is the lowest power consumption state that the CPU / SoC can reach when the DE enters the sleep state. The reason for implementing only PKG C8 is that PSR2 requires the DE to maintain time synchronization with the panel in the sleep state, which causes the DE to keep the phase-locked loop (PLL) and timing generator circuits working. By keeping the PLL and timing generator circuits working at the DE, the DE and CPU / SoC are prevented from entering the deepest PKG C-state (e.g., PKG C10) during the sleep state. On the contrary, the DE and CPU / SoC can only enter a lower PKG C-state (e.g., PKG C8) during the sleep state, which is not as power-efficient as the deepest PKG C-state. In the previous PSR2 implementation, the deepest PKG C-state (e.g., PKG C10) can only be achieved when the DE enters a deep sleep state.

[0036] In one example, the advantage of the sleep state is that the DE can perform frame updates during a short cycle and then return to the sleep state without additional frame overhead. Analysis of one hour battery life (HoBL) workloads showed that the sleep state residence time was 25% for office productivity and 50% for web browsing and video playback. This high sleep state residence time is an opportunity for the CPU / SoC to enter the deepest PKG C-state (e.g., PKG C10). As discussed in further detail below, dynamic sleep states can be enabled for the DE so that the PKG can enter C10 during dynamic sleep states to reduce CPU / SoC power consumption.

[0037] In one example, in previous PSR2 implementations, there was a deep sleep state exit penalty to re-enter the sleep / selective update state (or long cycle penalty). When the DE is in the deep sleep state, the DE will be awakened by VBI or frame update (flip) in the reset state. In the reset state, the DE will read and scan out the full frame and remain in the reset state for a programmed number of idle frames. For example, the DE will wait 1-16 frames before it can re-enter the sleep / selective update state, thereby incurring a long cycle penalty. Analysis of the HoBL workload shows that office productivity is affected by the long cycle penalty because the workload has enough idle time to enter deep sleep, but frequent wake-ups result in increased reset state dwell time (e.g., a 20% increase in reset state dwell time), which is a large portion of the lost power optimization opportunities.

[0038] In one example, previous PSR2 implementations suffered from inefficiencies with active frames and partial updates. In previous PSR2 implementations, the DE would operate during two active states, a reset state and a selective update state, during which frame updates would occur. In both active states, the DE would remain active for the entire frame time, even if there was a single pixel change, which can be inefficient. Analysis of HoBL workloads shows that the actual percentage of changes within a frame is much lower. For example, for web browsing, an average of 10% of the frames change when flipped. For office productivity, an average of 4% of the frames change when flipped. Telemetry data shows that users are browsing or running productivity workloads 70% of the time. Therefore, this is a significant opportunity to improve the efficiency of active frames. For example, as described in further detail below, the DE can remain active for only a portion of a "dirty" frame, meaning that the DE can be active for only a portion of a frame that has changes or updates.

[0039] In one example, in a previous CPU / SoC design, MIPI command mode does not support PKG C10 state because the DE does not have deep sleep support for MIPI. The MIPI command mode specification does enable panel self-refresh, selective read, and selective scan output, but due to the software implementation of MIPI command mode, the DE has a limited power feature set. Therefore, dynamic sleep state technology can be applied to the DE hardware implementation of MIPI command mode, thereby ensuring that the CPU / SoC provides a lower power MIPI solution.

[0040] In previous solutions, eDP PSR1 and PSR2 technologies for CPU / SoC power saving only supported deep sleep in long cycles. However, in this technology, DE can support deep sleep even in short cycles, thereby achieving higher PKG C10 residence time and lower power.

[0041] In one configuration, the eDP PSR2 can achieve lower power states (e.g., PKG C10) by offloading the DE's phase-locked loop (PLL) and timer logic to a separate, low-power, always-on power rail. The always-on power rail can be associated with a separate power domain (or a power domain "more on it"). In other words, the PLL and timer logic can be moved from the DE to a separate, always-on power rail. The PSR2 specification requires the DE to keep the panel (e.g., eDP panel) time synchronized by sending a VBI every frame time. In previous solutions, the DE would use the PLL and timer logic to generate the VBI beat. The DE can stop the VBI beat to save power, and the panel can run with its own timing only in a deep sleep state. Based on the PSR2 specification requirements, in previous solutions, the CPU / SoC in sleep state could not achieve a lower power state (e.g., PKG C10) because the DE had to maintain time synchronization with the panel. However, by offloading the PLL and timer logic to a separate power domain, it is possible to enable a deep sleep state in PSR2 sleep and a selective update state in a short cycle so that the UE can only be woken up for selective read and scan-out.

[0042] In one example, the MIPI command mode can define a VBI signal from the panel to the CPU / SoC to maintain timing. Here, the VBI signal from the CPU / SoC to the panel can be used to achieve time synchronization and improved power management. The PLL and timer logic can act as a scheduler for the DE by scheduling VBI and wake-up frame updates (flips).

[0043] In one configuration, the PLL and timer logic can be offloaded from the DE to a separate always-on power rail. The PLL and timer logic can include a timing generator that indicates when the VBI occurs. The PLL and timer logic can run on a transmit clock. In past solutions, the PLL and timer logic would be part of the DE. In this solution, a copy of the PLL and timer logic can be placed in a separate power rail (without a pipeline around the PLL and timer logic). In this case, the always-on power rail can be used to maintain the PLL and timer logic. The always-on power rail can remain on even when the DE is turned off. Thus, as required by the PSR2 specification, when the DE is turned off and a lower power state (e.g., PKG C10) is achieved, the timing between the DE and the panel can still be maintained by the always-on power rail associated with a separate power domain. By offloading the PLL and timer logic to the always-on power rail, a lower power state (e.g., PKG C10) can be achieved because the definition of PKG C10 is that all power rails except the always-on power rail will be turned off. When the panel rejoins the flow, the panel can still operate at the same frequency, such as 60 Hertz (Hz). If time synchronization is not maintained, when the panel wakes up, the panel can still run at 60 Hz, but can be phase-shifted for a period of time (e.g., phase-shifted by half a frame). In one example, when the DE is on (e.g., in a capture state), a local timing generator can be used to maintain time synchronization, and PLL and timer logic offloaded to an always-on power rail can take over and be responsible for time synchronization when the DE and CPU / SoC are in a lower sleep state, and timing can be synchronized between the local timing generator and the PLL and timer logic offloaded to the always-on power rail.

[0044] In one configuration, the eDP PSR2 can program the VBI beat timer to wake up earlier than the actual VBI to account for hardware latency, variable SW latency, and / or software jitter. Since the deep sleep state is enabled in a short loop, the DE will warm up the hardware every time it leaves the deep sleep state. This hardware latency can cause timer drift, resulting in visual artifacts. Thus, hardware and software latency can be calculated, and the timer can be programmed to wake up in advance before the calculated time to avoid timer drift. Examples of hardware latency can include hardware wake-up and recovery, input / output (IO) buffer enable, and link training latency. Examples of software latency can include reprogramming timers.

[0045] Figure 2An example of a programmed vertical blanking interrupt (VBI) is illustrated. The programmed VBI can occur earlier than the actual VBI to account for hardware and software latency issues. The hardware and software latency can be calculated to form a calculated time, and the programmed VBI can occur earlier than the actual VBI by the calculated time.

[0046] In one configuration, eDP PSR2 can include a new deep sleep definition for the dynamic sleep state. With the PLL and timer logic offloaded to a separate power rail, the DE can support deep sleep in the sleep state with the VBI beat turned on, and this new state can be called the dynamic sleep state. Thus, there can be two deep sleep states - the first deep sleep state can include the VBI beat and can be called the dynamic sleep state, and the second deep sleep state can be without the VBI beat and can be called the deep sleep state (such as Figure 1 ). Both deep sleep states are comparable in power consumption of the CPU / SoC and can enable PKG C10. The dynamic sleep state can enable deep sleep in short cycles, so the DE can be programmed to operate in short cycles indefinitely. When the DE completes selective fetches and updates, the DE can transition back to the dynamic sleep state in the same frame time. The DE can enter the deep sleep state only in connected standby / modern standby and panel on / off.

[0047] Figure 3An example of an improved PSR2 state machine with a dynamic sleep state is illustrated. The DE can start in a reset state, and after 1-16 programmed idle frames, the DE can enter a capture state. The DE can stay in the capture state for a frame time, where the panel can copy frames in its remote frame buffer for panel self-refresh. During the capture state, the panel can refresh the panel or accept updates. After the capture frame, the DE can enter a dynamic sleep state. During the dynamic sleep state, the CPU / SoC can achieve a lower power state (e.g., PKG C10). Before entering a deep sleep state, the DE can maintain another 1-16 programmed idle frames in the dynamic sleep state. When the DE is in the deep sleep state, the CPU / SoC remains in a lower power state (e.g., PKG C10). When in the deep sleep state, a vertical blanking interrupt (VBI) or a frame update (flip) can prompt the DE to return to the reset state. During a long cycle, the DE can be in a reset state, a capture state, a dynamic sleep state, and a deep sleep state. On the other hand, when in the Dynamic Sleep state and there is a frame update (flip), the DE can enter the Selective Update state and send the updated scan lines to the panel. During the short cycle, the DE can enter the Selective Update state. During the short cycle, a partial frame can be sent, and the entire frame does not have to be sent. During the short cycle, if there is no update, the panel can update from its own frame buffer. When in the Dynamic Sleep state, if there is an update, the DE can enter the Selective Update state and then go back to the Dynamic Sleep state.

[0048] In one configuration, the dynamic sleep techniques described above can be extended to MIPI command mode, and TAD to reduce CPU / SoC power consumption. In one example, some PSR2 eDP panels can have higher power for scenarios such as full-screen video playback. In addition, in past solutions, the CPU / SoC did not have short-term low-power support for MIPI command mode. Therefore, the techniques described above can be extended with the help of a display accelerator (DA), which can provide the lower power of MIPI command mode panels and the PSR2 features of non-PSR panels (which can reduce panel costs).

[0049] In one example, the media playback power consumption of the CPU / SoC can be monitored. By determining whether the CPU / SoC can achieve the lowest power state of media playback of 30 frames per second (FPS) on alternating frames (frames without updates), the unloading of the PLL and timer logic that can be unloaded in the DE can be detected. In another example, the VBI timer beat is programmed to wake up earlier than the actual VBI, which can be detected by monitoring the CPU / SoC waking up from the sleep state on alternating frames in 30FPS media playback. When the SoC is programmed to wake up early, the CPU / SoC can wake up before the VBI interrupt, and in the previous solution, the VBI interrupt will wake up the CPU / SoC. In another example, by monitoring the active CPU / SoC power for windowed media playback, dynamic sleep states can be detected. The active power can be proportional to the window size of the media playback, and when the window size changes, the CPU / SoC power can increase or decrease respectively.

[0050] In one example, analysis of HoBL web browsing and office productivity has shown that over 60% of frames are idle, when there is a frame update, 99% of frames have a partial update, and only 5%-10% of frames change. Thus, the dynamic sleep state feature can bring significant CPU / SoC power savings (e.g., an additional 20-30% CPU / SoC power savings).

[0051] Figure 4 An example of dynamic sleep simulation results is illustrated. The simulation is for the DE PSR2 state machine and the new proposed state. As shown, for HoBL web browsing and efficiency, the new dynamic sleep state can have a 90+% residence time during no other activity, where the PKG can be in C10. In addition, the dynamic sleep state can significantly reduce DE read and eDP input / output (IO) bandwidth (BW). For HoBL web browsing, the DE read BW can be reduced by 60%, and the eDP IOBW can drop by 30%. For HoBL efficiency, there can be an 80% drop in both DE read BW and eDP IO BW. The bandwidth reduction can provide additional power savings from the CPU / SoC and memory, thereby enabling the delivery of a competitive low-power CPU / SoC for typical use.

[0052] In one configuration, the eDP PSR2 state machine can be enhanced to include a dynamic sleep state to reduce CPU / SoC power consumption. To enable the dynamic sleep state, the PLL and timer logic can be unloaded from the DE to a separate, always-on power rail for VBI beat generation, the VBI beat timer can be programmed to wake up earlier than the actual VBI to cope with hardware latency and software jitter, and a new sleep state called a dynamic sleep state can be defined, which enables deep sleep with a VBI beat. In addition, the operating system (OS) can provide "dirty" area coordinates together with flips for selective extraction and selective update. The dirty area coordinates can indicate the area in the new frame that has been changed or updated relative to the previous frame. Thus, the DE can only take dirty areas and send these dirty areas to the panel. In addition, with respect to the panel (e.g., an eDP panel), further power enhancement can be achieved when the panel is asynchronous. For example, a signal can notify the panel of dirty scan lines, which allows frame updates to be sent at the VBI, and the link can be closed after the dirty scan lines are transmitted to reduce the power consumption of the CPU / SoC and the panel.

[0053] In one example, the DE can start in the reset state, and after a corresponding idle frame (which is programmed by the panel), the DE can enter the capture state, and then enter a new dynamic sleep state. While in the dynamic sleep state, the CPU / SoC can enter a lower power state (e.g., PKG C10) and will remain in the lower power state until an interrupt wakes up the CPU / SoC. With the dynamic sleep state, the DE VBI interrupt will no longer wake up the CPU / SoC.

[0054] In one example, the eDP PSR2 state machine can be programmed to stay in the dynamic sleep state indefinitely (e.g., for scene display) so that the DE does not pay the long cycle burden when it wakes up from a deep sleep state. With dynamic sleep state, the DE can wake up and enter a selective state and can return to sleep immediately after a frame update. The DE can exit the short cycle only for connected standby / modern standby and screen off scenarios.

[0055] In one example, the display driver can use the reported dirty region coordinates (e.g., from the OS) to calculate the dirty scan lines, and program the DE to read and scan out only those dirty scan lines, so that the DE can enter the dynamic sleep state after processing the last active scan line. The dynamic sleep state can seamlessly support scenarios with multiple dirty regions in a single surface or multiple surfaces.

[0056] In one example, by using TAD to asynchronously present the timestamp frame, the DE can process frame updates immediately after flipping, which can improve energy efficiency when combining CPU / SoC activities, thereby leading to longer dynamic sleep. In addition, the display accelerator (DA) can be used for display and other low-power features, and can enable low-power MIPI command mode and PSR2 for non-PSR panels.

[0057] In one configuration, with respect to the default PSR2, the DE can wake up at every VBI, and the DE can check if there are any pending flips. For example, when there is a flip, the DE can wake up and start acquiring the frame and check for dirty scan lines. As an example, the DE can determine that the dirty scan lines are in the middle of the frame, and the DE can scan out those lines. The DE can remain in a selective state throughout the frame time, because the DE can acquire the entire frame to search for dirty areas.

[0058] Figure 5 An example of a PSR2 default flow is illustrated. When the DE is in the dynamic sleep state, rollover can be suspended after the first VBI. After the second VBI, the DE can enter the selective update state. During the selective update state, the DE can read the full frame, identify the "dirty" scan lines (e.g., areas that have changed or updated relative to the previous frame) and scan out only the dirty scan lines. In this example, it can be assumed that the DE is in the PSR2 dynamic sleep state, and there can be a rollover with 25% dirty scan lines in the middle of the frame.

[0059] In one configuration, with respect to the synchronized dynamic sleep state, the panel (e.g., eDP PSR2 panel) can be synchronized, and the time synchronization can be driven by the DE. In this case, when there is a pending flip, the DE can be woken up at a calculated VBI (e.g., a calculated time earlier than the actual VBI), and the DE can read and scan out dirty scan lines in synchronization with the panel timing. When the DE completes scan out of the last dirty scan line, the DE can enter the dynamic sleep state.

[0060] Figure 6 An example of a dynamic sleep flow with synchronous operation is illustrated. When the DE is in the dynamic sleep state, flipping can be suspended after the first VBI. The DE can enter the selective update state at the calculated VBI, which can be earlier than the second VBI (actual VBI). The DE can use synchronous reading to identify the first dirty scan line. The DE can identify the dirty scan line and scan out the dirty scan line. In this example, 25% of the frame may be dirty. When the DE completes scan out of the last dirty scan line, the DE can return to the dynamic sleep state.

[0061] In one configuration, with respect to the asynchronous dynamic sleep state, a signal can be sent from the DE to the panel (e.g., eDP PSR2 panel) to notify a dirty update and the update can be sent immediately. When there is a pending rollover, the DE can be programmed to wake up and operate before the actual VBI (e.g., a calculated delay earlier than the actual VBI). The DE can start acquiring dirty scan lines, and the DE can start scanout at the second VBI. When all dirty scan lines are sent, the DE can enter the dynamic sleep state, and the eDP link can be shut down.

[0062] In one example, the asynchronous dynamic sleep state can be more power efficient than the synchronous dynamic sleep state, but the asynchronous dynamic sleep state requires sending a signal to the panel to notify a dirty scan line.

[0063] In one example, the MIPI command mode can benefit from the asynchronous dynamic sleep state because the MIPI command mode supports asynchronous operation.

[0064] Figure 7 An example of a dynamic sleep flow utilizing asynchronous operation is illustrated. When the DE is in the dynamic sleep state, flipping can be suspended after the first VBI. The DE can enter the selective update state at the calculated VBI, which can be earlier than the second VBI (actual VBI). The DE can identify the first dirty scan line with asynchronous read. The DE can identify the dirty scan line and perform asynchronous scan out of the dirty scan line. Scan out can start from the second VBI. In this example, 25% of the frame may be dirty. When the DE completes scan out of the last dirty scan line, the DE can return to the dynamic sleep state.

[0065] In one example, with respect to the synchronous dynamic sleep state, the panel can expect data to arrive at its exact time. In other words, the panel can expect data to be sent immediately when the data is to be presented, and is therefore considered to be synchronous. When a certain percentage of the frame is dirty and the dirty portion is in the middle of the frame, the DE will remain awake and read and scan out when the time comes. After the reading and scanning out are completed, the DE can enter the dynamic sleep state. In contrast, with the asynchronous dynamic sleep state, the panel has the ability to accept dirty areas at the beginning of the frame, which enables the cycle of dynamic sleep to be extended. For example, the DE can wake up, read dirty scan lines and scan out, and then be able to return to the dynamic sleep state.

[0066] In one configuration, regarding the dynamic sleep state of asynchronous TAD, TAD can be used to further improve power efficiency and extend the dynamic sleep state to the next generation TAD compatible external displays. TAD can allow display asynchrony by defining a presentation timestamp (PTS) for each frame instead of being driven by VBI. With TAD, because each frame can have a PTS, the DE can scan the output frame when flipping instead of waiting for the VBI. As a result, CPU / SoC activities can be combined, resulting in higher power efficiency. As an example, with TAD, the DE can read and scan the output frame immediately after the flip, instead of the DE operating at the VBI. In this example, it can be ensured that the OS sends the flip on all sides once or within a fixed time window (e.g., a few milliseconds).

[0067] Figure 8 An example of a dynamic sleep flow utilizing asynchronous TAD operation is illustrated. When the DE is in the dynamic sleep state, flipping can be suspended after the first VBI. The DE can enter the selective update state immediately after flipping. The DE can identify dirty scan lines and scan out the dirty scan lines. In this example, 25% of the frame may be dirty. When the DE completes scan out of the last dirty scan line, the DE can return to the dynamic sleep state. In this example, because the DE can enter the selective update state immediately after flipping, the DE can complete reading and scan out before the second VBI.

[0068] In one configuration, a display accelerator (DA) can be used to implement dynamic sleep states. For example, some existing PSR2 panels may have additional power costs in PSR2 mode. The DA can support MIPI command mode and PSR2 without additional panel cost and power. The DA can have a full frame buffer to drive the panel, and the DA can be located between the DE and the panel. The DA can be an asynchronous device to the DE and can drive eDP / MIPI panels. Further, by using PTS to combine CPU / SoC activities and increase dynamic sleep, CPU / SoC power advantages similar to TAD can be achieved.

[0069] Fig. 9 An example of a display accelerator (DA) is illustrated. The DA can be located between the DE and a panel (e.g., an eDP / MIPI panel). The DA can support MIPI command mode and PSR2. The DA can be an asynchronous device to the DE and can drive an eDP / MIPI panel.

[0070] Fig.10A display system 1000 is illustrated. The display system 1000 can include a display panel 1010, a display controller 1020 coupled to the display panel 1010, a central processing unit (CPU) 1030 coupled to the display controller 1020, an always-on power rail 1040, and timing logic 1050. The CPU 1030 can be associated with the always-on power rail 1040. The display controller 1020 can include logic for detecting a frame update when the display controller 1020 is in a dynamic sleep state. The display controller 1020 can include logic for waking up from the dynamic sleep state at a programmed vertical blanking interrupt (VBI) earlier than an actual VBI and entering a selective update state. The display controller 1020 can include logic for performing a scanout of the display panel 1010 during the selective update state. The display controller 1020 can include logic for returning to the dynamic sleep state in the same time frame after the scanout is completed. In addition, the timing logic 1050 can send the VBI to the display panel 1010 in each time frame to maintain time synchronization between the display controller 1020 and the display panel 1010 , and the timing logic 1050 can be included in the power rail 1040 that is always on.

[0071] Another example provides a method 1100 for making a display system. The method can be executed as instructions on a machine, wherein the instructions are included on at least one computer-readable medium or a non-transitory machine-readable storage medium. The method can include the following operations: as in block 1110, providing a display controller that does not include timing logic for sending a vertical blanking interrupt (VBI) to a display panel in each time frame to maintain time synchronization between the display controller and the display panel. The method can include the following operations: as in block 1120, coupling the display controller to the display panel. The method can include the following operations: as in block 1130, coupling the display controller to a central processing unit (CPU). The method can include the following operations: as in block 1140, configuring the display controller with logic to: detect frame updates when the display controller is in a dynamic sleep state; wake up from the dynamic sleep state at a programmed VBI earlier than the actual VBI and enter a selective update state; perform scanout of the display panel during the selective update state; and, return to the dynamic sleep state in the same time frame after completing the scanout.

[0072] Another example provides a method 1200 for operating in a dynamic sleep state when a display controller is in a display controller. The method can be executed as instructions on a machine, wherein the instructions are included on at least one computer-readable medium or a non-transitory machine-readable storage medium. The method can include the following operations: as in block 1210, when the display controller is in the dynamic sleep state, a frame update is detected at the display controller. The method can include the following operations: as in block 1220, the display controller is awakened from the dynamic sleep state at a vertical blanking interrupt (VBI) that is programmed earlier than the actual VBI and enters a selective update state. The method can include the following operations: as in block 1230, during the selective update state, a scanout of a display panel is performed at the display controller. The method can include the following operations: as in block 1240, within the same time frame after completing the scanout, a dynamic sleep state is returned at the display controller, wherein the display controller does not include timing logic for sending a VBI to the display panel in each time frame to maintain time synchronization between the display controller and the display panel.

[0073] Fig.13 A general purpose computing device 1300 capable of being used in the present technology is illustrated. The computing device 1300 can include a processor 1302 in communication with a memory 1304. The memory 1304 can include any device, combination of devices, circuitry, etc. capable of storing, accessing, organizing, and / or retrieving data. Non-limiting examples include SAN (storage area network), cloud storage networks, volatile or non-volatile RAM, phase change memory, optical media, hard drive type media, etc., including combinations thereof.

[0074] Additionally, computing device 1300 includes a local communications interface 1306 for connection between the various components of the system. For example, local communications interface 1306 can be a local data bus and / or any related address or control bus as desired.

[0075] The computing device 1300 can also include an I / O (input / output) interface 1308 for controlling the I / O functions of the system and for connecting to the I / O of devices outside the computing device 1300. A network interface 1310 can also be included for network connection. The network interface 1310 can control network communications within and outside the system. The network interface can include a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc., including appropriate combinations thereof. In addition, the computing device 1300 can additionally include a user interface 1312, a display device 1314, and various other components that are beneficial to such a system.

[0076] Processor 1302 can be a single or multiple processors, and memory 1304 can be a single or multiple memories. Local communication interface 1306 can serve as a path to facilitate communications between any of a single processor, multiple processors, a single memory, multiple memories, various interfaces, etc., in any useful combination.

[0077] Various technologies or some aspects or parts thereof can be in the form of program codes (i.e., instructions) embodied in tangible media, such as floppy disks, CD-ROMs, hard drives, non-transitory computer-readable storage media, or any other machine-readable storage media, wherein when the program code is loaded into and executed by a machine such as a computer, the machine becomes a device for practicing various technologies. Circuits can include hardware, firmware, program codes, executable codes, computer instructions, and / or software. Non-transitory computer-readable storage media can be computer-readable storage media that do not include signals. In the case of executing program codes on a programmable computer, a computing device can include a processor, a storage medium (including volatile and non-volatile memory and / or storage elements) readable by a processor, at least one input device, and at least one output device. Volatile and non-volatile memory and / or storage elements can be RAM, EPROM, flash drives, optical drives, magnetic hard drives, solid-state drives, or other media for storing electronic data. Nodes and wireless devices can also include transceiver modules, counter modules, processing modules, and / or clock modules or timer modules. One or more programs that can implement or utilize the various technologies described herein can use application program interfaces (APIs), reusable controls, etc. Such programs can be implemented with high-level processes or object-oriented programming languages ​​to communicate with computer systems. However, if necessary, (one or more) programs can be implemented in assembly language or machine language. In any case, the language can be a compiled or interpreted language and combined with hardware implementation. Exemplary systems or devices can include but are not limited to laptop computers, tablet computers, desktop computers, smart phones, computer terminals and servers, storage databases, and other electronic devices utilizing circuits and programmable memories, such as household appliances, smart televisions, digital video disks (DVD) playback devices, preheating, ventilation and air conditioning (HVAC) controllers, light switches, etc.

[0078] Example

[0079] The following examples relate to specific technical embodiments and indicate specific features, elements or steps that can be used or combined in implementing such embodiments.

[0080] In one example, a display controller is provided, comprising: logic for: detecting a frame update when the display controller is in a dynamic sleep state; waking up from the dynamic sleep state at a programmed vertical blanking interrupt (VBI) before an actual VBI and entering a selective update state; performing a scanout of a display panel during the selective update state; and returning to the dynamic sleep state within the same time frame after completing the scanout, wherein the display controller does not include timing logic for sending a VBI to the display panel in each time frame to maintain time synchronization between the display controller and the display panel.

[0081] In one example of a display controller, timing logic not included in the display controller to send the VBI to the display panel every time frame is associated with a separate power domain with an always-on power rail accessible to the display controller.

[0082] In one example of a display controller, when the display controller is in a dynamic sleep state, the display controller and a central processing unit (CPU) coupled to the display controller enter a reduced power package (PKG) CPU state (C-state).

[0083] In one example of a display controller, a reduced power consumption PKG C-state is achieved when all power rails are turned off except for an always-on power rail that includes timing logic for sending a VBI to a display panel in each time frame, thereby enabling the display controller and the CPU to enter the reduced power consumption PKG C-state during a dynamic sleep state while using the always-on power rail to solely maintain time synchronization between the display controller and the display panel.

[0084] In one example of a display controller, the display controller further includes: logic for: starting scanout after the actual VBI when the display panel operates in synchronous mode, or starting scanout at the actual VBI when the display panel operates in asynchronous mode; and, completing scanout after the actual VBI.

[0085] In one example of a display controller, a programmed VBI that is earlier in time than an actual VBI is determined based on the calculated hardware latency and software latency.

[0086] In one example of the display controller, the display controller further includes: logic to: begin performing scanout immediately after detecting a frame update and before an actual VBI; and complete the scanout before the actual VBI.

[0087] In one example of a display controller, the logic to perform scanout during a selective update state further includes logic to: acquire a new frame; identify changed scan lines of the new frame; and send the changed scan lines of the new frame to the display panel.

[0088] In one example of a display controller, the display controller is coupled to a display accelerator that drives a display panel.

[0089] In one example of a display controller, the display controller is configured for a dynamic sleep state using one or more of: an embedded DisplayPort (eDP) protocol, a Mobile Industry Processor Interface (MIPI) protocol, or a Transport Agnostic Display (TAD) protocol.

[0090] In one example, a display system is provided, comprising: a display panel; a display controller coupled to the display panel; and a central processing unit (CPU) coupled to the display controller, wherein the CPU is associated with an always-on power rail; wherein the display controller comprises: logic for: detecting a frame update when the display controller is in a dynamic sleep state; waking up from the dynamic sleep state and entering a selective update state at a programmed vertical blanking interrupt (VBI) earlier than the time of an actual VBI; performing a scanout of the display panel during the selective update state; and, after the scanout is completed, returning to the dynamic sleep state within the same time frame, wherein timing logic for sending the VBI to the display panel in each time frame to maintain time synchronization between the display controller and the display panel is included in the always-on power rail.

[0091] In one example of a display system, timing logic for sending a VBI to a display panel every time frame to maintain time synchronization between the display controller and the display panel is not included in the display controller and is associated with a separate power domain having an always-on power rail accessible to the display controller.

[0092] In one example of a display system, when the display controller is in a dynamic sleep state, the display controller and the CPU enter a reduced power consumption PKG CPU state (C-state).

[0093] In one example of a display system, a reduced power consumption PKG C-state is achieved when all power rails except an always-on power rail including timing logic for sending a VBI to a display panel in each time frame are turned off, thereby enabling a display controller and a CPU to enter a reduced power consumption PKG C-state during a dynamic sleep state while solely maintaining time synchronization between the display controller and the display panel using the always-on power rail.

[0094] In one example of a display system, the display controller further includes: logic for: starting scanout after the actual VBI when the display panel operates in synchronous mode, or starting scanout at the actual VBI when the display panel operates in asynchronous mode; and completing scanout after the actual VBI.

[0095] In one example of a display system, a programmed VBI that is earlier in time than an actual VBI is determined based on the calculated hardware latency and software latency.

[0096] In one example of a display system, the display controller further includes: logic to: begin performing scanout immediately after detecting a frame update and before an actual VBI; and complete the scanout before the actual VBI.

[0097] In one example of a display system, logic in a display controller for performing scanout during a selective update state further includes logic for: acquiring a new frame; identifying changed scan lines of the new frame; and sending the changed scan lines of the new frame to a display panel.

[0098] In one example of the display system, the display system further includes a display accelerator located between the display controller and the display panel.

[0099] In one example of a display system, a display controller is configured for a dynamic sleep state using one or more of: an embedded DisplayPort (eDP) protocol, a Mobile Industry Processor Interface (MIPI) protocol, or a Transport Agnostic Display (TAD) protocol.

[0100] In one example, a method of manufacturing a display system is provided, the method comprising: providing a display controller that does not include timing logic for sending a vertical blanking interrupt (VBI) to a display panel in each time frame to maintain synchronization between the display controller and the display panel; coupling the display controller to the display panel; coupling the display controller to a central processing unit (CPU); and, configuring the display controller with logic to: detect frame updates when the display controller is in a dynamic sleep state; wake up from the dynamic sleep state and enter a selective update state at a programmed VBI that is earlier than the time of an actual VBI; perform scan output of the display panel during the selective update state; and, after the scan output is completed, return to the dynamic sleep state within the same time frame.

[0101] In one example of a method of manufacturing a display system, the method further includes configuring a CPU to be associated with an always-on power rail that includes timing logic for sending a VBI to a display panel at each time frame, wherein the timing logic is associated with a separate power domain having the always-on power rail accessible to a display controller.

[0102] In one example of a method of manufacturing a display system, the method further includes configuring the display controller and the CPU to enter a reduced power package (PKG) CPU state (C-state) when the display controller is in the dynamic sleep state.

[0103] In one example of a method of manufacturing a display system, a reduced power consumption PKG C-state is achieved when all power rails except an always-on power rail including timing logic for sending a VBI to a display panel in each time frame are turned off, thereby enabling a display controller and a CPU to enter a reduced power consumption PKG C-state during a dynamic sleep state while solely maintaining time synchronization between the display controller and the display panel using the always-on power rail.

[0104] In one example of a method of manufacturing a display system, a programmed VBI that is earlier in time than an actual VBI is determined based on a calculated hardware latency and a software latency.

[0105] In one example of a method of manufacturing a display system, the method further includes coupling a display accelerator to a display controller to drive the display panel.

[0106] In one example of a method of making a display system, a display controller is configured for a dynamic sleep state using one or more of: an embedded DisplayPort (eDP) protocol, a Mobile Industry Processor Interface (MIPI) protocol, or a Transport Agnostic Display (TAD) protocol.

[0107] In one example, at least one non-transitory machine-readable storage medium is provided having instructions thereon for operating in a dynamic sleep state, which when executed by a display controller perform the following operations: detecting a frame update at a display controller while the display controller is in the dynamic sleep state; waking up from the dynamic sleep state and entering a selective update state at a programmed vertical blanking interrupt (VBI) earlier than the time of an actual VBI at the display controller; performing a scanout of a display panel at the display controller during the selective update state; and, after the scanout is completed, returning to the dynamic sleep state at the display controller within the same time frame, wherein the display controller does not include timing logic for sending the VBI to the display panel in each time frame to maintain time synchronization between the display controller and the display panel.

[0108] In one example of the at least one non-transitory machine-readable storage medium, timing logic for sending a VBI to a display panel at each time frame not included in the display controller is associated with a separate power domain having an always-on power rail accessible to the display controller.

[0109] In one example of the at least one non-transitory machine-readable storage medium, when the display controller is in a dynamic sleep state, the display controller and a central processing unit (CPU) coupled to the display controller enter a reduced power package (PKG) CPU state (C-state).

[0110] In one example of the at least one non-transitory machine-readable storage medium, a reduced power consumption PKG C-state is achieved when all power rails except an always-on power rail including timing logic for sending a VBI to a display panel in each time frame are turned off, thereby enabling a display controller and a CPU to enter a reduced power consumption PKG C-state during a dynamic sleep state while solely maintaining time synchronization between the display controller and the display panel using the always-on power rail.

[0111] In one example of the at least one non-transitory machine-readable storage medium, the at least one non-transitory machine-readable storage medium further includes instructions that, when executed, perform the following operations: when the display panel operates in synchronous mode, start scanning out after the actual VBI, or when the display panel operates in asynchronous mode, start scanning out at the actual VBI; and complete scanning out after the actual VBI.

[0112] In one example of the at least one non-transitory machine-readable storage medium, a programmed VBI that is earlier in time than an actual VBI is determined based on the calculated hardware latency and software latency.

[0113] In one example of the at least one non-transitory machine-readable storage medium, the at least one non-transitory machine-readable storage medium further includes instructions that, when executed, perform the following operations: start scanning out immediately after detecting a frame update and before an actual VBI; and complete scanning out before the actual VBI.

[0114] In one example of the at least one non-temporary machine-readable storage medium, the at least one non-temporary machine-readable storage medium further includes instructions that, when executed, perform the following operations: perform scan output during a selective update state by: acquiring a new frame; identifying changed scan lines of the new frame; and sending the changed scan lines of the new frame to a display panel.

[0115] Although the foregoing examples illustrate the principles of technical embodiments in one or more specific applications, it is apparent to those skilled in the art that numerous modifications can be made to the form, use, and implementation details without inventive effort without departing from the principles and concepts of the present disclosure.

Claims

1. A system comprising: Display device; as well as A circuit for: sending a signal to a display device to cause the display device to accept a selective update region at a first time corresponding to the start of a frame, the display device to perform a self-refresh based on the selective update region at a second time after the first time, the selective update region being associated with at least one set of coordinates; as well as The selective update region is sent to the display device over the embedded DisplayPort interface at a first time corresponding to the start of the frame.

2. The system according to claim 1, wherein: The circuit enters a sleep state after sending the selective update region to the display device.

3. The system according to claim 1, wherein: The selective update region includes a plurality of scan lines, and the circuit will enter a sleep state after sending the plurality of scan lines to the display device.

4. The system according to claim 1, wherein: The circuit will transition out of the sleep state before a first time corresponding to the start of the frame.

5. The system according to claim 1, wherein: The display device is a display panel.

6. A display controller comprising: Memory; as well as A circuit for: sending a signal to a display panel to cause the display panel to accept a selective update region at a first time corresponding to the start of a frame, the display panel to perform a self-refresh based on the selective update region at a second time after the first time, the selective update region being associated with at least one set of coordinates; as well as The selective update region is sent to the display panel over the embedded DisplayPort interface at a first time corresponding to the start of the frame.

7. The display controller according to claim 6, wherein: The circuit will enter a sleep state after sending the selective update region to the display panel.

8. The display controller according to claim 6, wherein: The selective update region includes a plurality of scan lines, and the circuit will enter a sleep state after sending the plurality of scan lines to the display panel.

9. The display controller according to claim 6, wherein: The circuit will transition out of the sleep state before a first time corresponding to the start of the frame.

10. At least one storage device comprising computer readable instructions that, when executed, cause a display controller to at least: sending a signal to a display device to cause the display device to accept a selective update region at a first time corresponding to the start of a frame, the display device performing a self-refresh based on the selective update region at a second time after the first time, the selective update region being associated with at least one set of coordinates; and The selective update region is sent to the display device over the embedded DisplayPort interface at a first time corresponding to the start of a frame.

11. The at least one storage device of claim 10, wherein: After sending the selective update region to the display device, the instructions cause the display controller to enter a sleep state.

12. The at least one storage device of claim 10, wherein: The selective update region includes a plurality of scan lines, and the instruction causes the display controller to enter a sleep state after the plurality of scan lines are sent to the display device.

13. The at least one storage device of claim 10, wherein: The instructions cause the display controller to transition out of the sleep state before a first time corresponding to the start of the frame.

14. The at least one storage device of claim 10, wherein: The display device is a display panel.

15. At least one storage device comprising computer readable instructions that, when executed, cause a circuit to at least: sending a signal to a display device to cause the display device to accept a selective update region at a first time corresponding to the start of a frame, the display device to perform a self-refresh based on the selective update region at a second time after the first time, the selective update region being associated with at least one set of coordinates; and The selective update region is sent to the display device through the embedded DisplayPort interface at a first time corresponding to the beginning of a frame.

16. The at least one storage device of claim 15, wherein: The instructions cause the circuit to enter a sleep state after sending the selective update region to the display device.

17. The at least one storage device of claim 15, wherein: The selective update region includes a plurality of scan lines, and the instructions cause the circuit to enter a sleep state after the plurality of scan lines are sent to the display device.

18. The at least one storage device of claim 15, wherein: The instructions cause the circuit to transition out of the sleep state before a first time corresponding to a start of the frame.

19. The at least one storage device of claim 15, wherein: The display device is a display panel.

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