Semiconductor structure, packaging structure and method for forming semiconductor structure

Abstract

A semiconductor structure including an integrated circuit die and a plurality of conductive bumps. The integrated circuit die includes a plurality of bump pads. The plurality of conductive bumps are disposed on the plurality of bump pads. Each of the plurality of conductive bumps includes a first column portion disposed on one of the plurality of bump pads and a second column portion disposed on the first column portion. The second column portion is electrically connected to one of the plurality of bump pads via the first column portion, wherein a first width of the first column portion is greater than a second width of the second column portion. A packaging structure including the semiconductor structure is also provided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor structure, a packaging structure, and a method for forming the semiconductor structure. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density is due to the continuous reduction in minimum feature size, which allows more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize a smaller area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFP), pin grid arrays (PGA) packages, ball grid arrays (BGA) packages, and the like. Currently, Chip-On-Wafer-On-Substrate (CoWoS) packaging technology has been developed to promote energy conservation and high-speed computing. In the packaging process of CoWoS packaging, heat dissipation of the integrated circuit (IC) die is an important issue. Summary of the invention

[0003] According to an embodiment of the present disclosure, a semiconductor structure includes an integrated circuit die and a plurality of conductive bumps. The integrated circuit die includes a plurality of bump pads. A plurality of conductive bumps are arranged on the plurality of bump pads, and each of the plurality of conductive bumps includes a first column portion and a second column portion. The first column portion is arranged on one of the plurality of bump pads. The second column portion is arranged on the first column portion, the second column portion is electrically connected to one of the plurality of bump pads via the first column portion, and the first width of the first column portion is greater than the second width of the second column portion.

[0004] According to an embodiment of the present disclosure, a packaging structure includes a circuit substrate, a semiconductor structure, a memory cube, and an insulating encapsulation. The semiconductor structure includes an integrated circuit die and a plurality of conductive bumps. The integrated circuit die includes a plurality of bump pads. A plurality of conductive bumps are arranged on the plurality of bump pads, each of the plurality of conductive bumps respectively includes a first column portion arranged on one of the plurality of bump pads and a second column portion arranged on the first column portion, the second column portion is electrically connected to one of the plurality of bump pads via the first column portion, the first width of the first column portion is greater than the second width of the second column portion, and the integrated circuit die is arranged on the circuit substrate and electrically connected to the circuit substrate via the plurality of conductive bumps. The memory cube is arranged on the circuit substrate and electrically connected to the circuit substrate. The insulating encapsulation laterally encapsulates the integrated circuit die and the memory cube, and the rear surface of the integrated circuit die is accessible and exposed from the insulating encapsulation.

[0005] According to an embodiment of the present disclosure, a method for forming a semiconductor structure includes: forming a seed layer on an integrated circuit die including a plurality of bump pads; forming a first patterned photoresist layer on the seed layer, a plurality of first openings of the first patterned photoresist layer exposing the plurality of bump pads of the integrated circuit die; forming a plurality of first column portions on a plurality of portions of the seed layer exposed by the plurality of first openings of the first patterned photoresist layer; forming a second patterned photoresist layer on the first patterned photoresist layer, a plurality of second openings of the second patterned photoresist layer exposing the plurality of first column portions; and forming a plurality of second column portions on a plurality of portions of the plurality of first column portions exposed by the plurality of second openings of the second patterned photoresist layer, wherein a first width of the plurality of first column portions is greater than a second width of the plurality of second column portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 6 The process flow of manufacturing a semiconductor structure according to some embodiments of the present invention is schematically illustrated.

[0008] Figure 7 and Figure 8 Another process flow for fabricating a semiconductor structure according to some embodiments of the present invention is schematically illustrated.

[0009] Figures 9 to 11The process flow of manufacturing a package structure according to some embodiments of the present invention is schematically illustrated.

[0010] Fig.12 Schematically illustrate Fig. 9 An enlarged cross-sectional view of area X is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to make the present invention concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be directly contacted. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not essentially specify the relationship between the various embodiments and / or configurations described.

[0012] Additionally, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0013] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3D-IC) device. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate, which allows the 3D package or 3D-IC to be tested using a probe and / or a probe card. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes verifying a known good die at an intermediate stage to improve yield and reduce cost.

[0014] Figures 1 to 6 The process flow of manufacturing a semiconductor structure according to some embodiments of the present invention is schematically illustrated.

[0015] refer to Figure 1 , a semiconductor wafer W including, for example, a plurality of semiconductor dies or integrated circuit dies 100 arranged in an array is provided. Before performing a wafer sawing process on the semiconductor wafer W, the integrated circuit dies 100 included in the semiconductor wafer W are physically connected to each other. In some embodiments, the semiconductor wafer W includes: a semiconductor substrate 110; an interconnect structure 120 formed on the semiconductor substrate 110; a passivation layer 130 formed on the interconnect structure 120; a plurality of bump pads 140 formed on the passivation layer 130 and electrically connected to the interconnect structure 120; and a post-passivation layer 150 covering the passivation layer 130 and the bump pads 140. The semiconductor substrate 110 may be a silicon substrate in which active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) are formed. The interconnect structure 120 may include a plurality of interconnect wiring layers and a plurality of dielectric layers alternately stacked. The passivation layer 130 covers the interconnect structure 120 and includes a plurality of contact openings so that the topmost interconnect wiring layer of the interconnect structure 120 is exposed through the contact openings of the passivation layer 130. In some embodiments, the passivation layer 130 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. The bump pad 140 is formed in the contact opening of the passivation layer 130 and is electrically connected to the topmost interconnect wiring layer of the interconnect structure 120 through the contact opening of the passivation layer 130. In some embodiments, the bump pad 140 is an aluminum pad, a copper pad, or other suitable metal pad. The rear passivation layer 150 may include a plurality of contact openings so that the contact openings of the rear passivation layer 150 partially expose the bump pad 140. In some embodiments, the rear passivation layer 150 is a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers.

[0016] like Figure 1As shown in , a seed layer 160 for plating is formed on the rear passivation layer 150 and the bump pad 140 exposed by the contact opening of the rear passivation layer 150 by, for example, a sputtering process. In some embodiments, the seed layer 160 includes a bottom seed layer 160a, which is completely formed on the semiconductor wafer W to cover the rear passivation layer 150 and the bump pad 140 exposed by the contact opening of the rear passivation layer 150, and the seed layer 160 may also include a top seed layer 160b formed on the bottom seed layer 160a. For example, the bottom seed layer 160a includes a sputtered titanium layer, and the top seed layer 160b includes a sputtered copper layer. In some embodiments, the thickness of the bottom seed layer 160a is in a range from about 0.05 microns to about 0.1 microns, and the thickness of the top seed layer 160b is in a range from about 0.1 microns to about 0.5 microns.

[0017] In some embodiments, the seed layer 160 may include a plurality of sputtered layers stacked on the semiconductor wafer W. In some alternative embodiments, the seed layer may include a single sputtered layer that completely covers the semiconductor wafer W.

[0018] refer to Figure 2 , for example, a first patterned photoresist layer PR1 is formed on the top seed layer 160b of the seed layer 160 via spin coating, baking, photolithography, and development processes. The first patterned photoresist layer PR1 includes a plurality of openings arranged in an array, and the plurality of openings expose a plurality of portions of the top seed layer 160b corresponding to the plurality of bump pads 140. In other words, the openings of the first patterned photoresist layer PR1 are located above the bump pads 140. Then, the semiconductor wafer W having the first patterned photoresist layer PR1 formed thereon may be immersed in a plating solution contained in a plating tank, so that a plurality of first pillar portions 170a are plated in the openings of the first patterned photoresist layer PR1. The first pillar portions 170a are plated on portions of the top seed layer 160b corresponding to the bump pads 140. The height of the first pillar portion 170a is determined by the thickness of the first patterned photoresist layer PR1, and the width of the first pillar portion 170a is determined by the opening of the first patterned photoresist layer PR1. Fig.12 The dimensions (eg, height and width) of the first pillar portion 170a are described in detail. In some embodiments, the first pillar portion 170a is a copper-plated pillar or other suitable conductive pillar.

[0019] refer to Figure 3After forming the first column portion 170a on the top seed layer 160b of the seed layer 160, a second patterned photoresist layer PR2 is formed on the first patterned photoresist layer PR1 to partially cover the top surface of the first column portion 170a. For example, the second patterned photoresist layer PR2 is formed by spin coating, baking, photolithography and development processes. The second patterned photoresist layer PR2 includes a plurality of openings arranged in an array, and the plurality of openings are used to expose a plurality of portions of a plurality of top surfaces of a plurality of first column portions 170a. The opening of the second patterned photoresist layer PR2 is located above the bump pad 140. In some embodiments, the width of the opening defined in the second patterned photoresist layer PR2 is smaller than the width of the opening defined in the first patterned photoresist layer PR1, and the opening defined in the second patterned photoresist layer PR2 is substantially aligned with the opening defined in the first patterned photoresist layer PR1 and the first column portion 170a.

[0020] Then, the semiconductor wafer W on which the first patterned photoresist layer PR1, the first pillar portion 170a and the second patterned photoresist layer PR2 are formed can be immersed in the plating solution contained in the plating tank so that a plurality of second pillar portions 170b are plated in the openings defined in the second patterned photoresist layer PR2. The second pillar portions 170b are plated and landed on the top surface of the first pillar portion 170a so that a plurality of conductive bumps 170 are formed. The height of the second pillar portion 170b is determined by the thickness of the second patterned photoresist layer PR2, and the width of the second pillar portion 170b is determined by the opening of the second patterned photoresist layer PR2. Fig.12 The dimensions (eg, height and width) of the second column portion 170b are described in more detail.

[0021] like Figure 3 , the width of the second column portion 170b is less than the width of the first column portion 170a, and the height of the second column portion 170b is less than the height of the first column portion 170a. Each of the plurality of second column portions 170b may be substantially aligned with one of the plurality of first column portions 170a, respectively. In some embodiments, the first column portion 170a and the second column portion 170b may be cylindrical columns, and each of the plurality of second column portions 170b is concentrically stacked on one of the plurality of first column portions 170a.

[0022] In some embodiments, the second column portion 170b is a multilayer column including a plating layer 170b1, a plating layer 170b2, a plating layer 170b3, and a plating layer 170b4, wherein the plating layer 170b1 includes a copper plating layer, the plating layer 170b2 includes a nickel plating layer, the plating layer 170b3 includes another copper plating layer, and the plating layer 170b3 includes a lead-free solder layer. For example, the thickness of the plating layer 170b1 (e.g., the copper plating layer) is in a range from about 10 microns to about 100 microns, the thickness of the plating layer 170b2 (e.g., the nickel plating layer) is in a range from about 3 microns to about 10 microns, the thickness of the plating layer 170b3 (e.g., the copper plating layer) is in a range from about 3 microns to about 10 microns, and the thickness of the plating layer 170b4 (e.g., the lead-free solder layer) is in a range from about 3 microns to about 30 microns.

[0023] refer to Figure 3 and Figure 4 After forming the first pillar portion 170a and the second pillar portion 170b, the first patterned photoresist layer PR1 and the second patterned photoresist layer PR2 are removed to expose a portion of the seed layer 160 that is not covered by the first pillar portion 170a. In some embodiments, the first patterned photoresist layer PR1 and the second patterned photoresist layer PR2 are removed simultaneously by a stripping process.

[0024] In some embodiments, the Figure 2 and Figure 3 The two-step plating process described in the above-described embodiment forms the conductive bumps 170 each including the first column portion 170a and the second column portion 170b. In other words, the bumping process for forming the conductive bump 170 is Figure 2 and Figure 3 In some alternative embodiments, each of the plurality of conductive bumps 170 may include a plurality of stacked column portions (e.g., three or more stacked column portions), and the stacked column portions may be formed via a multi-step plating process. Taking the three-step plating process as an example, a first patterned photoresist layer is used to form a plurality of stacked column portions. Figure 2 A plurality of first pillar portions are selectively plated on the seed layer 160 described in the embodiment of the present invention, a plurality of second pillar portions are selectively plated on the first pillar portions using the second patterned photoresist layer, and a plurality of third pillar portions are selectively plated on the second pillar portions using the third patterned photoresist layer. Then, the first patterned photoresist layer, the second patterned photoresist layer, and the third patterned photoresist layer can be simultaneously removed through a stripping process.

[0025] refer to Figure 4 and Figure 5, using the first pillar portion 170a and the second pillar portion 170b as a hard mask, for example, by an etching process, the portion of the seed layer 160 not covered by the first pillar portion 170a and the second pillar portion 170b is removed until the rear passivation layer 150 is exposed. After removing the portion of the seed layer 160 not covered by the first pillar portion 170a and the second pillar portion 170b, a plurality of seed patterns 160' are formed, wherein each of the plurality of seed patterns 160' includes a first seed pattern 160a' and a second seed pattern 160b'. The first seed pattern 160a' covers some portions of the rear passivation layer 150 and lands on the central portion of the bump pad 140, and the second seed pattern 160b' is located between the first seed pattern 160a' and the first pillar portion 170a.

[0026] refer to Figure 5 and Figure 6 After performing a bump forming process on the semiconductor wafer W, the semiconductor wafer W having the conductive bumps 170 and the seed pattern 160' formed thereon is singulated to obtain a plurality of singulated integrated circuit dies 100a. Fig. 9 The thickness of the memory cube 300 described in FIG. 1 matches that of the memory cube 300 , and no thinning process is required to thin the semiconductor wafer W downward before singulating the semiconductor wafer W. Figure 6 As described in the figure, each singulated integrated circuit die 100a includes a singulated semiconductor substrate 110', a singulated interconnect structure 120', a singulated passivation layer 130', a bump pad 140, a singulated back passivation layer 150', a seed pattern 160', and a conductive bump 170. In the singulated integrated circuit die 100a, the singulated interconnect structure 120' is disposed on the singulated semiconductor substrate 110'; the singulated passivation layer 130' covers the singulated interconnect structure 120'; the bump pad 140 is disposed on the singulated interconnect structure 120' and is electrically connected to the singulated interconnect structure 120'; the singulated back passivation layer 150' covers the singulated passivation layer 130' and covers some portions of the conductive bump 170; and the seed pattern 160' and the conductive bump 170 are disposed on the bump pad 140 and are electrically connected to the bump pad 140.

[0027] Figure 7 and Figure 8 Another process flow for fabricating a semiconductor structure according to some embodiments of the present invention is schematically illustrated.

[0028] refer to Figure 7 , in execution Figure 5After the bump formation process described in , a dielectric material layer 180 may be formed on the back passivation layer 150 of the semiconductor wafer W. For example, the dielectric material layer 180 is formed by first performing a dispensing process and then a curing process. In some embodiments, the dielectric material layer 180 may laterally encapsulate the seed pattern 160' and extend upward along the sidewall of the conductive bump 170. Figure 7 , in some embodiments, the sidewalls of the first pillar portion 170a are partially covered by the dielectric material layer 180, so that the dielectric material layer 180 can enhance the reliability of the conductive bump 170 with a high aspect ratio (e.g., greater than 5). In some alternative embodiments, the dielectric material layer 180 can further extend to cover some portions of the sidewalls of the second pillar portion 170b.

[0029] refer to Figure 7 and Figure 8 After performing the bump forming process on the semiconductor wafer W, the semiconductor wafer W having the seed pattern 160', the conductive bumps 170 and the dielectric material layer 180 formed thereon is singulated to obtain a plurality of singulated integrated circuit dies 100b. Figure 8 As described in the figure, each individualized integrated circuit die 100b includes an individualized semiconductor substrate 110', an individualized interconnect structure 120', an individualized passivation layer 130', a bump pad 140, an individualized post-passivation layer 150', a seed pattern 160', a conductive bump 170 and an individualized dielectric material layer 180'. In the singulated integrated circuit die 100b, the singulated interconnect structure 120' is disposed on the singulated semiconductor substrate 110'; the singulated passivation layer 130' covers the singulated interconnect structure 120'; the bump pad 140 is disposed on the singulated interconnect structure 120' and electrically connected to the singulated interconnect structure 120'; the singulated post-passivation layer 150' covers the singulated passivation layer 130' and covers some portions of the conductive bump 170; the seed pattern 160' and the conductive bump 170 are disposed on the bump pad 140 and electrically connected to the bump pad 140; and the singulated dielectric material layer 180' covers the singulated post-passivation layer 150' and contacts at least some portions of the sidewalls of the seed pattern 160' and the first pillar portion 170a. In some embodiments, the singulated dielectric material layer 180' can be a dielectric material without a filler.

[0030] Figures 9 to 11 The process flow of manufacturing a package structure according to some embodiments of the present invention is schematically illustrated. Fig.12 Schematically illustrate Fig. 9 An enlarged cross-sectional view of area X is shown.

[0031] refer to Fig. 9, an interposer wafer 200 having a plurality of conductive bumps 220 formed thereon is provided, and the integrated circuit die is picked up and flipped onto the interposer wafer 200. After the integrated circuit die is picked up and flipped onto the interposer wafer 200, a reflow process is performed to bond the integrated circuit die to the interposer wafer 200. In some embodiments, Figure 8 One of the plurality of integrated circuit dies 100b singulated as described in the embodiment of the present invention is picked up and placed onto the interposer wafer 200, so that the singulated integrated circuit die 100b is electrically connected to the interposer wafer 200, for example, via a reflow process. The present application does not limit the number of singulated integrated circuit dies 100b. Other types of integrated circuit dies including conductive bumps with a high aspect ratio may be picked up and placed onto the interposer wafer 200. For example, Figure 6 One of the singulated integrated circuit dies 100a described in the embodiment is picked up and placed onto the interposer wafer 200 so that the singulated integrated circuit die 100a is electrically connected to the interposer wafer 200, for example, via a reflow process. The present application does not limit the number of singulated integrated circuit dies 100a.

[0032] After the singulated integrated circuit die 100b is bonded to the interposer wafer 200, one or more memory cubes 300 (e.g., high-bandwidth memory cubes) are provided and placed on the interposer wafer 200. After the memory cubes 300 are picked up and placed on the interposer wafer 200, a reflow process is performed to bond the memory cubes 300 to the interposer wafer 200. In some embodiments, each of the plurality of memory cubes 300 includes a plurality of stacked memory dies 310 (or memory integrated circuit chips) and conductive bumps 320, wherein a plurality of through semiconductor vias (TSVs) 312 are respectively formed in each memory die 310, and the semiconductor through semiconductor vias 312 located in different levels of the stacked memory dies 310 are electrically connected via the conductive bumps 320. In some other embodiments, Fig. 9 It is not described in the specification that each of the plurality of memory cubes includes a logic die (or a logic integrated circuit chip), a plurality of stacked memory dies disposed on the logic die, and conductive bumps, wherein a plurality of semiconductor through-holes are formed in each of the logic die and the memory die, respectively, the logic die is electrically connected to the bottommost level of the memory die via the conductive bumps, and the semiconductor through-holes located in different levels of the stacked memory die are electrically connected via the conductive bumps. In some alternative embodiments, Fig. 9It is not described in the embodiment that each of the plurality of memory cubes includes a logic die, a plurality of stacked memory dies disposed on the logic die, conductive bumps, and an insulating encapsulant (e.g., a molding compound), wherein a plurality of semiconductor through-holes are formed in each of the logic die and the memory die, respectively, the logic die is electrically connected to the bottommost level of the memory die via the conductive bumps, the semiconductor through-holes located in different levels of the stacked memory die are electrically connected via the conductive bumps, and the insulating encapsulant encapsulates the logic die and the stacked memory die. The configuration of the memory cube 300 is for illustration only and is not limited by the present application.

[0033] In some embodiments, the memory cube 300 includes more than eight memories (for example, 9 to 12 stacked memory dies are included in each memory cube 300), and the total thickness of the memory cube 300 is in the range of about 875 microns to about 925 microns, wherein the thickness of each memory die 310 is in the range of about 20 microns to about 200 microns, and the bump height of the conductive bump 320 is in the range from about 20 microns to about 80 microns.

[0034] like Fig. 9 and Fig.12 As described in FIG. 1 , after the reflow process is performed, the singulated integrated circuit die 100 b is physically and electrically connected to the interposer wafer 200 via the conductive bumps 170 and the conductive bumps 220 . Fig.12 As illustrated in , the interposer wafer 200 includes a plurality of conductive wires 202, a passivation layer 204, a plurality of bump pads 206, and a rear passivation layer 208. The passivation layer 204 includes a plurality of contact openings for exposing some portions of the conductive wires 202. In some embodiments, the passivation layer 204 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. The bump pads 206 are formed on the passivation layer 204 and the exposed portions of the conductive wires 202, so that the bump pads 206 are electrically connected to the conductive wires 202 via the contact openings in the passivation layer 204. The rear passivation layer 208 may include a plurality of contact openings, so that the contact openings of the rear passivation layer 208 partially expose the bump pads 206. For example, the rear passivation layer 208 is a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers.

[0035] like Fig.12As illustrated, a plurality of seed patterns 210 each including a plurality of stacked seed patterns are formed to cover the exposed bump pads 206 and to cover some portions of the back passivation layer 208. In some embodiments, each seed pattern includes a first seed pattern 210a and a second seed pattern 210b, wherein the first seed pattern 210a covers the exposed bump pads 206 and covers some portions of the back passivation layer 208, and the second seed pattern 210b is disposed on the first seed pattern 210a. For example, the first seed layer (first seed pattern 210a) includes a sputtered titanium layer, and the second seed layer (second seed pattern 210b) includes a sputtered copper layer. In some embodiments, the thickness of the first seed layer (first seed pattern 210a) is in a range from about 0.05 micrometers to about 0.1 micrometers, and the thickness of the second seed layer (second seed pattern 210b) is in a range from about 0.1 micrometers to about 0.5 micrometers. In addition, a plurality of conductive bumps 220 are formed on the seed pattern 210 through, for example, a plating process. In some embodiments, the conductive bumps 220 are multi-layer pillars, each of which includes a plating layer 220a, a plating layer 220b, and a plating layer 220c, wherein the plating layer 220a includes a copper plating layer, the plating layer 220b includes a nickel plating layer, and the plating layer 220c includes another copper plating layer. In some embodiments, each of the plurality of conductive bumps 220 further includes a lead-free solder layer disposed on the plating layer 220c. For example, the thickness of the plating layer 220a (e.g., the copper plating layer) is in the range of about 3 microns to about 20 microns, the thickness of the plating layer 220b (e.g., the nickel plating layer) is in the range of about 3 microns to about 10 microns, the thickness of the plating layer 220c (e.g., the copper plating layer) is in the range of about 3 microns to about 10 microns, and the thickness of the lead-free solder layer is in the range of about 3 microns to about 20 microns.

[0036] like Fig.12 As described in FIG. 1 , after performing the reflow process, the plating layer 170 b 4 (eg, Figure 3 The lead-free solder layer described in FIG. 1 and the lead-free solder layer of the conductive bump 220 are melted and reshaped to form a soldering layer or bonding layer 170b4′ between the plating layer 170b3 and the plating layer 220c.

[0037] In some embodiments, the first width W1 of the first pillar portion 170a is proportional to the arrangement pitch P of the conductive bumps 170 (eg, Fig. 9) is in a range from about 0.7 to about 0.8. For example, the arrangement pitch P of the conductive bump 170 is in a range from about 10 micrometers to about 100 micrometers, the first width W1 of the first pillar portion 170a is in a range from about 5 micrometers to about 80 micrometers, the first height H1 of the first pillar portion 170a is in a range from about 30 micrometers to about 300 micrometers, and the aspect ratio of the first pillar portion 170a is in a range from about 0.5 to about 8.

[0038] In some embodiments, the second width W2 of the second pillar portion 170b has a significant effect on the arrangement pitch P of the conductive bumps 170 (eg, Fig. 9 ) is in a range from about 0.4 to about 0.6. For example, the arrangement pitch P of the conductive bump 170 is in a range from about 10 micrometers to about 100 micrometers, the second width W2 of the second pillar portion 170b is in a range from about 3 micrometers to about 70 micrometers, the second height H2 of the second pillar portion 170b is in a range from about 10 micrometers to about 100 micrometers, and the aspect ratio of the second pillar portion 170b is in a range from about 0.5 to about 8.

[0039] In some embodiments, the first width W1 of the first column portion 170a is greater than the second width W2 of the second column portion 170b. For example, the ratio of the second width W2 of the second column portion 170b to the first width W1 of the first column portion 170a is greater than about 0.5 and less than about 1.

[0040] In some embodiments, the first height H1 of the first column portion 170a is substantially equal to or greater than the second height H2 of the second column portion 170b. For example, the ratio of the first height H1 of the first column portion 170a to the second height H2 of the second column portion 170b is in a range from about 1 to about 5.

[0041] In some embodiments, the height H of the conductive bump 170 is in a range from about 20 microns to about 400 microns, and the thickness T of the integrated circuit die 100 b is in a range from about 300 microns to about 800 microns. For example, the ratio of the height H of the conductive bump 170 to the thickness T of the integrated circuit die 100 b is in a range from about 0.05 to about 1.

[0042] In some embodiments, a ratio of a height H of the conductive bump 170 to a first width W1 of the first pillar portion 170 a (ie, an aspect ratio of the conductive bump 170 ) is in a range from about 2 to about 10.

[0043] In some embodiments, the second width W2 of the second pillar portion 170b of the conductive bump 170 is less than the third width W3 of the conductive bump 220, and the third width W3 of the conductive bump 220 is substantially equal to the first width W1 of the first pillar portion 170a. For example, the third width W3 of the conductive bump 220 is in a range from about 3 micrometers to about 70 micrometers, the height H3 of the conductive bump 220 is in a range from about 5 micrometers to about 30 micrometers, and the aspect ratio of the conductive bump 220 is in a range from about 0.5 to about 5. In addition, the height H of the conductive bump 170 is greater than the height H3 of the conductive bump 220.

[0044] In some embodiments, Fig.12 It is not illustrated that the second width W2 of the second pillar portion 170b of the conductive bump 170 is smaller than the third width W3 of the conductive bump 220, and the third width W3 of the conductive bump 220 is larger than or smaller than the first width W1 of the first pillar portion 170a.

[0045] like Fig.12 , the height H of the conductive bump 170 may be about 1 / 2 to about 10 times the thickness of each memory die 310. In addition, the sum of the height H of the conductive bump 170 and the height H3 of the conductive bump 220 may be about 1 / 10 to about 3 times the thickness of each memory die 310. For example, the thickness of each memory die 310 is in the range from about 20 microns to about 200 microns.

[0046] refer to Fig.10 After the memory cube 300 and the singulated integrated circuit die 100b are bonded to the interposer wafer 200, a filling underfill material 400 is formed on the interposer wafer 200 through, for example, a dispensing process. The filling underfill material 400 is formed to encapsulate the conductive bumps 170 and the conductive bumps 220. In some embodiments, the filling underfill material 400 not only fills the space between the singulated integrated circuit die 100b and the interposer wafer 200, but also laterally encapsulates the sidewalls of the singulated integrated circuit die 100b and the sidewalls of the memory cube 300. Depending on the amount of dispensing, the filling underfill material 400 may partially fill or completely fill the gap between the singulated integrated circuit die 100b and the memory cube 300.

[0047] After forming the filling underfill 400 on the interposer wafer 200, an insulating encapsulation 500 is formed to laterally encapsulate the singulated integrated circuit die 100b and the memory cube 300, so that the rear surface of the integrated circuit die 100b is accessibly exposed from the insulating encapsulation 500. After forming the insulating encapsulation 500, a plurality of conductive bumps 700 (e.g., controlled collapse chip connection (C4) bumps) are formed on the lower surface of the interposer wafer 200, so that the conductive bumps 700 are electrically connected to the singulated integrated circuit die 100b and electrically connected to the memory cube 300 via the interposer wafer 200. Then, a singulation process is performed to obtain a plurality of semiconductor structures SS. Fig.10 As described in FIG. 1 , after the singulation process is performed, the semiconductor structures SS each including the integrated circuit die 100 b and the interposer 200 ′ are fabricated.

[0048] In some embodiments, the insulating encapsulation body 500 is formed by performing a molding process (e.g., an overmolding process) followed by a grinding process (e.g., a mechanical grinding process and / or a chemical mechanical polishing process). The grinding process is used to partially grind the molding compound of the insulating encapsulation body 500 to expose the rear surface of the integrated circuit die 100b and some portions of the memory cube 300 so that the heat dissipation performance of the semiconductor structure SS can be enhanced.

[0049] like Fig.10 As described in , in this embodiment, since the thickness of the integrated circuit die 100b and the aspect ratio of the conductive bumps 170 and the conductive bumps 220 are high enough to match the relatively high thickness (e.g., about 900 microns) of the memory cube 300, the rear surface of the integrated circuit die 100b is not covered by the insulating encapsulation 500 and is accessible exposed from the insulating encapsulation 500. Therefore, Fig.10 The heat dissipation performance of the semiconductor structure SS described in the embodiment is enhanced.

[0050] refer to Fig.11 , the semiconductor structure SS is picked up and placed on a wiring substrate 600 (e.g., a printed circuit board) including a plurality of conductive terminals 650 (e.g., solder balls). In some embodiments, the semiconductor structure SS is mounted on the upper surface of the wiring substrate 600, and the conductive terminals 650 are disposed on the lower surface of the wiring substrate 600. In some embodiments, a filling primer material 750 is formed on the upper surface of the wiring substrate 600 to fill the gap between the interposer 200' and the wiring substrate 600. The filling primer material 750 encapsulates the conductive bumps 700 and enhances the bonding strength of the conductive bumps 700. Fig.11 The reliability of the packaging structure described in .

[0051] According to some embodiments of the present invention, a semiconductor structure including an integrated circuit die and a plurality of conductive bumps is provided. The integrated circuit die includes a plurality of bump pads. The plurality of conductive bumps are disposed on the plurality of bump pads. Each of the plurality of conductive bumps includes a first column portion disposed on one of the plurality of bump pads and a second column portion disposed on the first column portion. The second column portion is electrically connected to one of the plurality of bump pads via the first column portion, wherein the first width of the first column portion is greater than the second width of the second column portion. In an embodiment, a ratio of the height of the plurality of conductive bumps to the thickness of the integrated circuit die is in a range from about 0.05 to about 1. In an embodiment, the plurality of conductive bumps are arranged in an array, a first ratio of the first width to the arrangement pitch of the plurality of conductive bumps is in a range from about 0.7 to about 0.8, and a second ratio of the second width to the arrangement pitch of the plurality of conductive bumps is in a range from about 0.4 to about 0.6. In an embodiment, a ratio of the first height of the first column portion to the second height of the second column portion is in a range from about 1 to about 5. In an embodiment, a ratio of the second width to the first width is greater than about 0.5 and less than about 1. In an embodiment, a ratio of the height of the plurality of conductive bumps to the first width is in a range from about 2 to about 10. In an embodiment, the semiconductor structure further includes a dielectric layer partially encapsulating a plurality of sidewalls of the plurality of conductive bumps.

[0052] According to some embodiments of the present invention, a packaging structure including a circuit substrate, a semiconductor structure, a memory cube and an insulating encapsulation is provided. The semiconductor structure includes: an integrated circuit die including a plurality of bump pads; and a plurality of conductive bumps disposed on the plurality of bump pads. Each of the plurality of conductive bumps includes a first column portion disposed on one of the plurality of bump pads and a second column portion disposed on the first column portion. The second column portion is electrically connected to one of the plurality of bump pads via the first column portion. The first width of the first column portion is greater than the second width of the second column portion. The integrated circuit die is disposed on the circuit substrate and electrically connected to the circuit substrate via the plurality of conductive bumps. The memory cube is disposed on the circuit substrate and electrically connected to the circuit substrate. The insulating encapsulation laterally encapsulates the integrated circuit die and the memory cube, and a rear surface of the integrated circuit is tangibly exposed from the insulating encapsulation. In an embodiment, a ratio of the height of the plurality of conductive bumps to the thickness of the integrated circuit die is in a range from about 0.05 to about 1. In an embodiment, the plurality of conductive bumps are arranged in an array, a first ratio of the first width to an arrangement pitch of the plurality of conductive bumps is in a range from about 0.7 to about 0.8, and a second ratio of the second width to the arrangement pitch of the plurality of conductive bumps is in a range from about 0.4 to about 0.6. In an embodiment, a ratio of a first height of the first column portion to a second height of the second column portion is in a range from about 1 to about 5. In an embodiment, a ratio of the second width to the first width is greater than about 0.5 and less than about 1. In an embodiment, a ratio of the height of the plurality of conductive bumps to the first width is in a range from about 2 to about 10. In an embodiment, the package structure further comprises a dielectric layer partially encapsulating a plurality of sidewalls of the plurality of conductive bumps.

[0053] According to some embodiments of the present invention, a method for forming a semiconductor structure is provided, comprising: forming a seed layer on an integrated circuit die including a plurality of bump pads; forming a first patterned photoresist layer on the seed layer, a plurality of first openings of the first patterned photoresist layer exposing the plurality of bump pads of the integrated circuit die; forming a plurality of first column portions on a plurality of portions of the seed layer exposed by the plurality of first openings of the first patterned photoresist layer; forming a second patterned photoresist layer on the first patterned photoresist layer, a plurality of second openings of the second patterned photoresist layer exposing the plurality of first column portions; and forming a plurality of second column portions on a plurality of portions of the plurality of first column portions exposed by the plurality of second openings of the second patterned photoresist layer, wherein a first width of the plurality of first column portions is greater than a second width of the plurality of second column portions. In an embodiment, the seed layer is sputtered on the integrated circuit die to cover the plurality of bump pads. In an embodiment, the first patterned photoresist layer formed on the seed layer is thicker than the second patterned photoresist layer. In an embodiment, the second patterned photoresist layer is formed to cover the first patterned photoresist layer and to cover portions of the top surfaces of the first pillar portions. In an embodiment, the method further comprises: forming a dielectric layer, the dielectric layer covering the integrated circuit die and partially encapsulating the sidewalls of the first pillar portions. In an embodiment, the dielectric layer is formed by performing a dispensing process followed by a curing process.

[0054] According to some embodiments of the present invention, there is provided a packaging structure including an interposer substrate, a semiconductor structure, a memory cube, and an insulating encapsulation. The interposer substrate includes a plurality of first conductive bumps. The semiconductor structure includes: an integrated circuit die including a plurality of bump pads; and a plurality of second conductive bumps disposed on the plurality of bump pads. Each of the plurality of second conductive bumps includes a first column portion disposed on one of the plurality of bump pads and a second column portion disposed on the first column portion. The second column portion is located between the first column portion and one of the plurality of first conductive bumps. The first width of the first column portion is greater than the second width of the second column portion. The integrated circuit die is disposed on the interposer substrate and is electrically connected to the interposer substrate via the plurality of first conductive bumps and the plurality of second conductive bumps. The memory cube is disposed on the interposer substrate and is electrically connected to the interposer substrate. The insulating encapsulation laterally encapsulates the integrated circuit die and the memory cube, and a rear surface of the integrated circuit die is accessible and exposed from the insulating encapsulation.

[0055] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, wherein: include: A circuit substrate, comprising a plurality of first bump pads and a plurality of first conductive bumps disposed on the plurality of first bump pads; A semiconductor structure, comprising an integrated circuit die, the integrated circuit die comprising a plurality of second bump pads and a plurality of second conductive bumps disposed on the plurality of second bump pads, each of the plurality of second conductive bumps respectively comprising a first column portion disposed on one of the plurality of second bump pads and a second column portion disposed on the first column portion, the second column portion being aligned with the first column portion and one of the plurality of first bump pads, a first width of the first column portion being greater than a second width of the second column portion, and the integrated circuit die being disposed on the circuit substrate and electrically connected to the circuit substrate via the plurality of second conductive bumps; a memory cube disposed on and electrically connected to the circuit substrate, wherein a first distance between the integrated circuit die and the circuit substrate is greater than a second distance between the memory cube and the circuit substrate; as well as An insulating encapsulation laterally encapsulates the integrated circuit die and the memory cube. 2 . The package structure according to claim 1 , wherein a third width of the plurality of first conductive bumps is greater than the second width of the second column portion, and the third width of the plurality of first conductive bumps is equal to the first width of the first column portion. 3 . The package structure according to claim 1 , wherein a third width of the plurality of first conductive bumps is greater than the second width of the second column portion, and the third width of the plurality of first conductive bumps is not equal to the first width of the first column portion. 4 . The package structure according to claim 1 , wherein a ratio of a first height of the first pillar portion to a second height of the second pillar portion is in a range from 1 to 5. 5 . The package structure according to claim 1 , wherein a ratio of the second width to the first width is greater than 0.5 and less than 1. 6 . 6 . The package structure according to claim 1 , wherein a ratio of heights of the plurality of second conductive bumps to the first width is in a range from 2 to 10. 7 . 7 . The package structure of claim 1 , further comprising a dielectric layer partially encapsulating sidewalls of the plurality of second conductive bumps, wherein the dielectric layer is spaced apart from the second pillar portions of the plurality of second conductive bumps.

8. A packaging structure, wherein: include: Circuit substrate; A semiconductor structure, comprising an integrated circuit die, the integrated circuit die comprising a plurality of first conductive bumps disposed thereon, at least one of the plurality of first conductive bumps comprising a first pillar portion and a second pillar portion disposed on the first pillar portion, the second pillar portion being electrically connected to the integrated circuit die via the first pillar portion, a first width of the first pillar portion being greater than a second width of the second pillar portion, and the integrated circuit die being disposed on the circuit substrate and electrically connected to the circuit substrate via the plurality of first conductive bumps; a memory cube disposed on the circuit substrate and electrically connected to the circuit substrate, the memory cube comprising a plurality of second conductive bumps, the memory cube being electrically connected to the circuit substrate via the second conductive bumps, wherein the first conductive bumps are higher than the second conductive bumps relative to the circuit substrate, and a back surface of the circuit substrate is flush with a top surface of the memory cube; as well as An insulating encapsulation laterally encapsulates the integrated circuit die and the memory cube. 9 . The package structure of claim 8 , wherein a back surface of the circuit substrate and a top surface of the memory cube are flush with a surface of the insulating encapsulation body. 10 . The package structure according to claim 8 , wherein the circuit substrate comprises a plurality of third conductive bumps, the third conductive bumps contacting with and electrically connected to the first conductive bumps. 11 . The package structure according to claim 10 , wherein a third width of the plurality of third conductive bumps is greater than the second width of the second pillar portion. 12 . The package structure according to claim 10 , wherein a third width of the plurality of third conductive bumps is equal to the first width of the first pillar portion.

13. The package structure according to claim 8, further comprising: a dielectric layer encapsulating a plurality of first sidewall portions of the plurality of first conductive bumps; as well as The underfill is filled to encapsulate the dielectric layer and the second sidewall portions of the first conductive bumps, wherein the dielectric layer portion is in contact with the second column portions of the first conductive bumps. 14 . The package structure according to claim 13 , wherein the underfill is in contact with the second pillar portions of the plurality of first conductive bumps, and the underfill is spaced apart from the plurality of first sidewall portions of the plurality of first conductive bumps.

15. A method for forming a package structure, comprising: Disposing an integrated circuit die having a plurality of first conductive bumps on a circuit substrate, each of the plurality of first conductive bumps comprising a first pillar portion and a second pillar portion disposed on the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion, and the integrated circuit die is electrically connected to the circuit substrate via the plurality of first conductive bumps; disposing at least one memory cube having a plurality of second conductive bumps on the circuit substrate, wherein a first gap between the integrated circuit die and the circuit substrate is greater than a second gap between the memory cube and the circuit substrate; as well as The integrated circuit die and the at least one memory cube are laterally encapsulated with an insulating encapsulation.

16. The method according to claim 15, wherein forming the plurality of first conductive bumps comprises: forming a seed layer on the integrated circuit die including a plurality of bump pads; forming a first patterned photoresist layer on the seed layer, wherein a plurality of first openings of the first patterned photoresist layer expose the plurality of bump pads of the integrated circuit die; forming a plurality of first pillar portions on a plurality of portions of the seed layer exposed by the plurality of first openings of the first patterned photoresist layer; forming a second patterned photoresist layer on the first patterned photoresist layer, wherein a plurality of second openings of the second patterned photoresist layer expose the plurality of first pillar portions; as well as A plurality of second pillar portions are formed on the plurality of portions of the plurality of first pillar portions exposed by the plurality of second openings of the second patterned photoresist layer. 17 . The method of claim 16 , wherein the first patterned photoresist layer formed over the seed layer is thicker than the second patterned photoresist layer. 18 . The method of claim 16 , wherein the second patterned photoresist layer is formed to cover the first patterned photoresist layer and to cover portions of the plurality of top surfaces of the plurality of first pillar portions.

19. The method according to claim 16, further comprising: forming a dielectric layer to cover the integrated circuit die and partially encapsulate a plurality of sidewalls of the plurality of first pillar portions; as well as The first gap and the second gap are filled with a filling primer.

20. The method of claim 19, wherein the dielectric layer is formed by performing a dispensing process followed by a curing process.

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