Semiconductor storage device

Abstract

An embodiment of the present invention provides a high-quality semiconductor memory device. The semiconductor memory device of the embodiment comprises: a first cell region including a plurality of memory cells; a second cell region including a plurality of memory cells; a connection region sandwiched between the first cell region and the second cell region; and a row decoder that transmits a voltage to word lines of the first and second cell regions via the connection region.

Description

[0001] [Related applications]

[0002] This application claims priority based on Japanese Patent Application No. 2019-171693 (filing date: September 20, 2019). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor memory device. Background Art

[0004] There is known a NAND (Not AND) type flash memory capable of storing data in a nonvolatile manner. Summary of the invention

[0005] Embodiments provide a high-quality semiconductor memory device.

[0006] A semiconductor memory device according to an embodiment includes a first cell region, a second cell region, and a first connection region. The first cell region includes a plurality of first conductor layers stacked at intervals along a first direction, and a first semiconductor layer extending in the first direction within the plurality of first conductor layers, and the intersections of the plurality of first conductor layers and the first semiconductor layer each constitute a memory cell. The second cell region includes a plurality of second conductor layers stacked at intervals along a first direction, and a second semiconductor layer extending in the first direction within the plurality of second conductor layers, and the intersections of the plurality of second conductor layers and the second semiconductor layer each constitute a memory cell. The first connection region is arranged between the first unit region and the second unit region in a second direction intersecting the first direction, and has a first bridge region and a first step region, wherein in the first bridge region, a plurality of third conductor layers stacked at intervals along the first direction respectively electrically connect one of the plurality of first conductor layers and one of the plurality of second conductor layers, and in the first step region, the plurality of third conductor layers respectively have steps for setting a first contact plug.

[0007] The first stepped region may be connected to the first bridge region in a third direction intersecting the first direction and the second direction.

[0008] The first connection region may further include a first sub-channel region adjacent to the first bridge region and the first step region in the second direction and provided with a second contact plug extending in the first direction within the plurality of third conductive layers.

[0009] In the first sub-channel region, each of the plurality of third conductive layers may be electrically connected to one of the plurality of first conductive layers and one of the plurality of second conductive layers.

[0010] The semiconductor memory device may further include a first slit, a third unit region, a fourth unit region, and a second connection region including a second sub-channel region. The first slit is adjacent to the first unit region, the first connection region, and the second unit region in the third direction. The third unit region is adjacent to the first unit region in the third direction with the first slit interposed therebetween, and includes a plurality of fourth conductor layers stacked with intervals along the first direction, and a third semiconductor layer extending in the first direction within the plurality of fourth conductor layers, wherein the intersections of the plurality of fourth conductor layers and the third semiconductor layer constitute memory cells, respectively. The fourth unit region is adjacent to the second unit region in the third direction with the first slit interposed therebetween, and includes a plurality of fifth conductor layers stacked with intervals along the first direction, and a fourth semiconductor layer extending in the first direction within the plurality of fifth conductor layers, wherein the intersections of the plurality of fifth conductor layers and the fourth semiconductor layer constitute memory cells, respectively. The second sub-channel region is arranged between the third unit region and the fourth unit region in the second direction, and is provided with a second bridge region, a second step region and a fourth contact plug. In the second bridge region, a plurality of sixth conductor layers stacked at intervals along the first direction are respectively electrically connected to one of the plurality of fourth conductor layers and one of the plurality of fifth conductor layers. In the second step region, the plurality of sixth conductor layers respectively have steps for setting the third contact plug and are connected to the second bridge region in the third direction. The fourth contact plug is adjacent to the second bridge region and the second step region in the second direction and extends in the first direction within the plurality of sixth conductor layers.

[0011] The first bridge region and the first step region may be adjacent to the second sub channel region via the first slit in the third direction, and the second bridge region and the second step region may be adjacent to the first sub channel region via the first slit in the third direction.

[0012] A first row decoder associated with the first unit region and the second unit region may be disposed below the first bridge region, the first step region, and the second sub-channel region in the first direction, and the first unit region and the second unit region may be connected to the first row decoder via the fourth contact plug, the first contact plug, the first step region, and the first bridge region; a second row decoder associated with the third unit region and the fourth unit region may be disposed below the second bridge region, the second step region, and the first sub-channel region in the first direction, and the third unit region and the fourth unit region may be connected to the second row decoder via the third contact plug, the second contact plug, the second step region, and the second bridge region.

[0013] The semiconductor memory device may further include: a first wiring connecting the fourth contact plug and the first contact plug; and a second wiring connecting the third contact plug and the second contact plug.

[0014] The first to third conductor layers may be the same conductor layer.

[0015] The first to third conductive layers may also be word lines or selection gate lines.

[0016] The fourth to sixth conductive layers may be the same conductive layer.

[0017] The fourth to sixth conductive layers may also be word lines or selection gate lines.

[0018] The semiconductor memory device may further include a third step region, a third connection region, a fourth step region, and a fourth connection region. The third step region is separated from the first connection region by the first unit region in the second direction, and each of the plurality of seventh conductive layers stacked at intervals from each other along the first direction includes a step for providing a fifth contact plug. The third connection region includes a first contact region adjacent to the third step region in the second direction and provided with a sixth contact plug extending in the first direction within the plurality of seventh conductive layers. The fourth step region is separated from the second connection region by the third unit region in the second direction, and each of the plurality of eighth conductive layers stacked at intervals from each other along the first direction includes a step for providing a seventh contact plug. The fourth connection region includes a second contact region adjacent to the fourth step region in the second direction and provided with an eighth contact plug extending in the first direction within the plurality of eighth conductive layers.

[0019] The third step region may be adjacent to the second contact region via the first slit in the third direction, and the fourth step region may be adjacent to the first contact region via the first slit in the third direction.

[0020] A third row decoder associated with the first unit region is disposed below the third step region and the second contact region in the first direction, and the first unit region is connected to the third row decoder via the fifth contact plug, the eighth contact plug, and the third step region. A fourth row decoder associated with the third unit region is disposed below the fourth step region and the first contact region in the first direction, and the third unit region is connected to the fourth row decoder via the sixth contact plug, the seventh contact plug, and the fourth step region.

[0021] The semiconductor memory device may further include: a third wiring connecting the fifth contact plug and the eighth contact plug; and a fourth wiring connecting the sixth contact plug and the seventh contact plug.

[0022] The first to third and seventh conductive layers may be the same conductive layer.

[0023] The first to third and seventh conductive layers may also be word lines or selection gate lines.

[0024] The fourth to sixth and eighth conductive layers may be the same conductive layer.

[0025] A semiconductor memory device according to another embodiment includes a first cell region, a second cell region, a connection region, and a row decoder. The first cell region includes a plurality of first conductor layers stacked in a first direction, and a plurality of memory cells, wherein the plurality of memory cells extend in the first direction within the plurality of first conductor layers, include a first semiconductor layer, and each of the intersections of the plurality of first conductor layers and the first semiconductor layer constitutes a memory cell. The second cell region is a region arranged in a second direction intersecting the first direction of the first cell region, and includes a plurality of second conductor layers stacked in the first direction, and a plurality of memory cells, wherein the plurality of memory cells extend in the first direction within the plurality of second conductor layers, include a second semiconductor layer, and each of the intersections of the plurality of first conductor layers and the second semiconductor layer constitutes a memory cell. The connection region is a region disposed between the first cell region and the second cell region, and is sandwiched between a plurality of third conductive layers stacked in the first direction and electrically connecting one of the plurality of first conductive layers to one of the plurality of second conductive layers, and a first contact plug electrically insulated from the plurality of third conductive layers and extending in the first direction. The row decoder is disposed below the connection region, and transmits a voltage to the word lines of the first and second cell regions via the connection region electrically connected to the first contact plug of the connection region.

[0026] According to the embodiment, a high-quality semiconductor memory device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram showing a configuration example of a semiconductor memory device according to the first embodiment.

[0028] Figure 2 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0029] Figure 3 This is a bird's-eye view simply shown to facilitate understanding of the layout of the semiconductor memory device in the Z direction.

[0030] Figure 4 A diagram showing an example of a planar layout of a memory cell array.

[0031] Figure 5 A diagram showing a layout example related to the lower layer of a memory cell array.

[0032] Figure 6 A diagram showing a layout example related to an upper layer of a memory cell array.

[0033] Figure 7 It is a diagram showing the relationship between the lower layer and the upper layer.

[0034] Figure 8 It is a diagram showing a layout example of a connection region (lower) and a cell region (lower) sandwiching the connection region (lower).

[0035] Fig. 9 It is a diagram showing a layout example of the connection area (lower) in the first lower layer.

[0036] Fig.10 This is a diagram showing a layout example of the connection area (lower) in the second lower layer.

[0037] Fig.11 It is a diagram showing a layout example of a connection region (upper) and a cell region (upper) sandwiching the connection region (upper).

[0038] Fig.12 It is a diagram showing a layout example of the connection area (upper) in the first upper layer.

[0039] Fig.13 This is a diagram showing a layout example of the connection area (upper) in the second upper layer.

[0040] Fig.14 This is a block diagram showing the connection of each component in the first lower layer.

[0041] Fig.15 This is a block diagram showing the connection of each component in the second lower layer.

[0042] Fig.16 This is a block diagram showing the connection of each component in the first upper layer.

[0043] Fig.17 This is a block diagram showing the connection of each component in the second upper layer.

[0044] Fig.18 It is a diagram showing the relationship between the connected area (lower) and the connected area (upper).

[0045] Fig.19 It is a diagram showing an example of a planar layout of a circuit region.

[0046] Fig. 20 FIG. 1 is a diagram showing a layout example of a part of a row decoder module and a part of a sense amplifier module.

[0047] Fig.21 This is a diagram showing the relationship between a row decoder module in a circuit area and a connection area in a memory cell array.

[0048] Fig. 22 It is a diagram showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0049] Fig.23 This is a diagram showing an example of a detailed planar layout of a memory cell array in a cell region of the semiconductor memory device according to the first embodiment.

[0050] Fig.24 It is along Fig.23 1 is a cross-sectional view taken along line CC of , and is a diagram showing an example of a cross-sectional structure in a cell region of a memory cell array included in the semiconductor memory device according to the first embodiment.

[0051] Fig.25 It is along Fig.24 DD line, and is a diagram showing an example of a cross-sectional structure of a storage pillar in the semiconductor storage device according to the first embodiment.

[0052] Fig.26 is an example of a detailed planar layout of the connection region of the semiconductor memory device according to the first embodiment, and is a method of extracting two connection regions ( Fig. 22 B) is a diagram representing the same.

[0053] Fig. 27 It is along Fig.26 It is a cross-sectional view taken along line EE of , and is a diagram showing an example of the cross-sectional structure of the sub-channel connection region and the step region.

[0054] Fig.28 It is along Fig.26 It is a cross-sectional view taken along line FF of FIG. 1 , and is a diagram showing an example of the cross-sectional structure of the sub-channel connection region and the step region.

[0055] Fig.29 It is along Fig.26 It is a cross-sectional view taken along the GG line of FIG. , and is a diagram showing an example of the cross-sectional structure of the sub-channel connection region and the step region.

[0056] Fig.30 It is along Fig.26 : is a cross-sectional view taken along the HH line of , and is a diagram showing an example of the cross-sectional structure of the lower bridge region and the lower sub-channel connection region.

[0057] Fig.31 It is along Fig.26 It is a cross-sectional view taken along the JJ line of the embodiment of the present invention, and is a diagram showing an example of the cross-sectional structure of the first lower connectable region.

[0058] Fig.32 It is along Fig.26 The present invention is a cross-sectional view taken along the KK line of the present invention, and is a diagram showing an example of the cross-sectional structure of the lower bridging region and the lower sub-channel connecting region.

[0059] Fig.33 It is along Fig.26It is a cross-sectional view taken along line LL, and is a diagram showing an example of the cross-sectional structure of the first upper connectable region.

[0060] Fig.34 It is along Fig.26 It is a cross-sectional view taken along line MM of FIG. 1 , and is a diagram showing an example of a cross-sectional structure of a sub-channel connection region.

[0061] Fig.35 It is a diagram showing the direction in which a voltage is transmitted to a cell region in a comparative example.

[0062] Fig.36 It is a diagram showing the direction in which a voltage is transmitted to a cell region in a comparative example.

[0063] Fig.37 It is a diagram showing the direction in which a voltage is transmitted to a cell region in a comparative example.

[0064] Fig.38 It is a diagram showing the direction in which a voltage is transmitted to a cell region according to the embodiment.

[0065] Fig.39 It is a diagram showing the direction in which a voltage is transmitted to a cell region according to the embodiment.

[0066] Fig.40 It is a diagram showing a layout example of a connection region and a cell region sandwiching the connection region.

[0067] Fig.41 It is a diagram showing the layout of the circuit region and memory cell array of the semiconductor memory device according to the first embodiment.

[0068] Fig.42 1 is a diagram showing a layout of a circuit area CTA and a memory cell array 10 of a semiconductor memory device 1 according to a second modification of the first embodiment.

[0069] Fig.43 1 is a diagram showing a layout of a circuit area CTA and a memory cell array 10 of a semiconductor memory device 1 according to a second modification of the first embodiment.

[0070] Fig.44 It is a diagram showing an example of a planar layout of a circuit region.

[0071] Fig.45 A diagram showing an example of a planar layout of a memory cell array.

[0072] Fig.46 It is a diagram showing the direction in which a voltage is transmitted to a cell region according to the second embodiment.

[0073] Fig.47 It is a diagram showing the direction in which a voltage is transmitted to a cell region according to the second embodiment.

[0074] Fig.48 It is a diagram showing an example of a planar layout of a circuit region.

[0075] Fig.49 A diagram showing an example of a planar layout of a memory cell array.

[0076] Fig.50 FIG. 1 is a diagram showing a layout example of a connection region and a cell region adjacent to the connection region.

[0077] Fig.51 FIG. 1 is a diagram showing a layout example of a connection region and a cell region adjacent to the connection region.

[0078] Fig.52 It is a diagram showing the layout of a circuit region and a memory cell array of a semiconductor memory device according to a third embodiment.

[0079] Fig.53 It is a diagram showing the layout of a circuit region and a memory cell array of a semiconductor memory device according to a third embodiment.

[0080] Fig.54 It is a diagram showing the layout of a circuit region and a memory cell array of a semiconductor memory device according to a third embodiment.

[0081] Fig.55 It is a diagram showing the layout of a circuit region and a memory cell array of a semiconductor memory device according to a third embodiment.

[0082] Fig.56 It is a diagram showing an overview of the step region.

[0083] Fig.57 It is a diagram showing an overview of the step region.

[0084] Fig.58 This is an example of a detailed planar layout of a step region of the semiconductor memory device according to the fourth embodiment, and is a diagram showing two step regions adjacent to each other in the Y direction.

[0085] Fig.59 It is along Fig.58 It is a cross-sectional view taken along the NN line of FIG. , and is a diagram showing an example of the cross-sectional structure of the step region. DETAILED DESCRIPTION

[0086] The following describes the embodiments with reference to the accompanying drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual, and the dimensions and ratios of the drawings may not be the same as the actual situation. The technical idea of ​​the present invention is not specified by the shape, structure, configuration, etc. of the constituent elements.

[0087] In addition, in the following description, the same symbols are used to mark the components having substantially the same function and structure. The numbers after the characters constituting the reference symbols are referenced by the reference symbols containing the same characters, and are used to distinguish the components having the same structure from each other. In the case where it is not necessary to distinguish the components represented by the reference symbols containing the same characters from each other, these components are respectively referenced by the reference symbols containing only the characters.

[0088] <1> First Embodiment

[0089] Hereinafter, a semiconductor memory device 1 according to a first embodiment will be described.

[0090] <1-1> Overall Configuration of Semiconductor Memory Device 1

[0091] <1-1-1> Configuration example

[0092] Figure 1 The semiconductor memory device 1 of the first embodiment is a configuration example. The semiconductor memory device 1 is a NAND flash memory capable of storing data in a nonvolatile manner, and is controlled by an external memory controller 2. The communication between the semiconductor memory device 1 and the memory controller 2 supports, for example, the NAND interface standard.

[0093] like Figure 1 As shown, the semiconductor memory device 1 includes, for example, a memory cell array 10 , a command register 11 , an address register 12 , a sequencer 13 , a driver module 14 , a row decoder module 15 , and a sense amplifier module 16 .

[0094] The memory cell array 10 includes a plurality of blocks BLK(0) to BLK(n) (n is an integer greater than or equal to 1). The block BLK is a collection of a plurality of memory cells capable of storing data in a non-volatile manner, and is used, for example, as a unit for deleting data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 will be described below.

[0095] The command register 11 stores a command CMD received by the semiconductor storage device 1 from the memory controller 2. The command CMD includes, for example, a command for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, or the like.

[0096] The address register 12 stores the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAdd, a page address PAdd, and a column address CAdd. For example, the block address BA, the page address PAdd, and the column address CAdd are used to select the block BLK, the word line, and the bit line, respectively.

[0097] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD stored in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 to perform read, write, and erase operations.

[0098] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. The driver module 14 applies the generated voltages to signal lines corresponding to word lines selected based on the page address PAdd stored in the address register 12, for example.

[0099] The row decoder module 15 includes a plurality of row decoders RD. The row decoder RD selects one block BLK in the corresponding memory cell array 10 based on the block address BAdd stored in the address register 12. The row decoder RD transmits, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0100] In a write operation, the sense amplifier module 16 applies a required voltage to each bit line according to the write data DAT received from the memory controller 2. In addition, in a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and then reads the determination result and transmits it to the memory controller 2 in the form of data DAT.

[0101] The semiconductor storage device 1 and the memory controller 2 described above may be combined to form a semiconductor device. TM Card memory card, or SSD (solid state drive), etc.

[0102] <1-1-2> Circuit structure of memory cell array

[0103] Figure 2 An example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment is shown, and one block BLK is selected from among the plurality of blocks BLK included in the memory cell array 10. Figure 2 As shown, the block BLK includes a plurality of string components SU(0) to SU(k) (k is an integer greater than 1).

[0104] Each string component SU includes a plurality of NAND strings NS associated with bit lines BL(0) to BL(m) (m is an integer greater than 1). Each NAND string NS includes, for example, memory cell transistors MT(0) to MT(15), and selection transistors ST(1) and ST(2). The memory cell transistor MT includes a control gate and a charge accumulation layer to store data in a non-volatile manner. The selection transistors ST(1) and ST(2) are used to select the string component SU during various operations.

[0105] In each NAND string NS, the memory cell transistors MT(0) to MT(15) are connected in series. The drain of the selection transistor ST(1) is connected to the bit line BL associated therewith, and the source of the selection transistor ST(1) is connected to one end of the memory cell transistors MT(0) to MT(15) connected in series. The drain of the selection transistor ST(2) is connected to the other end of the memory cell transistors MT(0) to MT(15) connected in series. The source of the selection transistor ST(2) is connected to the source line SL.

[0106] In the same block BLK, the control gates of the memory cell transistors MT(0) to MT(15) are connected to the word lines WL(0) to WL(7). The gates of the select transistors ST(1) in the string components SU(0) to SU(k) are connected to the select gate lines SGD(0) to SGD(k). The gates of the select transistors ST(2) are connected to the select gate line SGS.

[0107] In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by the NAND strings NS assigned the same column address in each string unit SU. The source line SL is shared by, for example, a plurality of blocks BLK.

[0108] A collection of a plurality of memory cell transistors MT connected to a common word line WL in a string unit SU is called a unit unit CU, for example. For example, the storage capacity of a unit unit CU including memory cell transistors MT each storing 1 bit of data is defined as "1 page of data". The unit unit CU may have a storage capacity of more than 2 pages of data depending on the number of bits of data stored in the memory cell transistor MT.

[0109] In addition, the memory cell array 10 of the semiconductor memory device 1 of the first embodiment is not limited to the circuit configuration described above. For example, the number of memory cell transistors MT and selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to be any number. The number of string components SU included in each block BLK can be designed to be any number.

[0110] <1-2> Layout of semiconductor memory devices

[0111] Next, the layout of semiconductor memory device 1 will be described.

[0112] In the drawings referred to below, the Y direction corresponds to the extending direction of the bit lines BL, the X direction corresponds to the extending direction of the word lines WL, and the Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate 20 forming the semiconductor memory device 1. In the plan view, hatching is appropriately added for easy viewing of the drawings. The hatching added to the plan view is not necessarily related to the material or characteristics of the components to which the hatching is added.

[0113] <1-2-1> Overview of Layout of Semiconductor Memory Device

[0114] use Figure 3 , an overview of the layout of the semiconductor memory device 1 is described. Figure 3 This is a bird's-eye view simply shown to facilitate understanding of the layout of the semiconductor memory device 1 in the Z direction.

[0115] like Figure 3 As shown, the semiconductor memory device 1 includes a circuit area CTA having a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16, and a memory cell array 10 arranged on the circuit area CTA in the Z direction. The memory cell array 10 includes a lower layer LL, and an upper layer UL arranged on the lower layer LL in the Z direction. In addition, the lower layer LL includes a first lower layer LL1, and a second lower layer LL2 arranged on the first lower layer LL1 in the Z direction. Similarly, the upper layer UL includes a first upper layer UL1, and a second upper layer UL2 arranged on the first upper layer UL1 in the Z direction. Details of the first lower layer LL1, the second lower layer LL2, the first upper layer UL1, and the second upper layer UL2 will be described below.

[0116] <1-2-2> Layout of memory cell array

[0117] <1-2-2-1>Overview

[0118] Next, the layout of the memory cell array 10 in a plane including the X direction and the Y direction will be described with attention paid to it.

[0119] Figure 4 FIG. 2 shows an example of a planar layout of the memory cell array 10. Figure 4 , for simplicity, a schematic layout including a first lower layer LL1 , a second lower layer LL2 , a first upper layer UL1 , and a second upper layer UL2 is shown.

[0120] like Figure 4As shown, the memory cell array 10 generally includes a plurality of cell regions 100 and a plurality of connection regions 101. The cell region 100 is a region having the plurality of blocks BLK. The connection region 101 connects the blocks BLK of the cell region 100 across the connection region 101, or transmits a voltage from the row decoder module 15 to a selection gate line or a word line of the block BLK.

[0121] like Figure 4 As shown, there are a plurality of unit regions 100, which are roughly divided into Figure 4 The paper is located on the left and right sides. Moreover, the connection region 101 is located between the cell region 100 on the left and the cell region 100 on the right. This means that the connection region 101 is located in the center of the memory cell array 10 in the X direction. Figure 4 The cell region 100 on the left, the cell region 100 on the right, and the connection region 101 therebetween are collectively referred to as a “layer.” For example, the semiconductor memory device 1 may include a plurality of layers, and each layer may be controlled independently or in parallel.

[0122] Hereinafter, a layout example of the cell region 100 and the connection region 101 will be described.

[0123] Specifically, in Figure 4 On the paper, the unit area 100 is located in four positions, namely, the upper left, the upper right, the lower left, and the lower right. The upper left, the upper right, the lower left, and the lower right are represented by Figure 4 The performance is based on the paper.

[0124] For the sake of convenience, the cell regions 100 located at the upper left, upper right, lower left, and lower right in the memory cell array 10 are respectively recorded as cell region (upper left) 100-FP, cell region (upper right) 100-GP, cell region (lower left) 100-FD, and cell region (lower right) 100-GD. In addition, when the four cell regions are not distinguished, they are simply recorded as cell regions 100.

[0125] The cell region (upper left) 100-FP and the cell region (lower left) 100-FD may also share the bit line BL. Similarly, the cell region (upper right) 100-GP and the cell region (lower right) 100-GD may also share the bit line BL.

[0126] In addition, if Figure 4As shown, there are two connection regions 101. The first connection region 101 is set between the unit region (upper left) 100-FP and the unit region (upper right) 100-GP to connect (short-circuit) the unit regions. The second connection region 101 is set between the unit region (lower left) 100-FD and the unit region (lower right) 100-GD to connect (short-circuit) the unit regions.

[0127] For the sake of convenience, the connection region 101 provided between the unit region (upper left) 100-FP and the unit region (upper right) 100-GP is described as the connection region (upper) 101-P. In addition, the connection region 101 provided between the unit region (lower left) 100-FD and the unit region (lower right) 100-GD is described as the connection region (lower) 101-D. In addition, when the two connection regions are not distinguished, they are simply described as the connection region 101.

[0128] <1-2-2-2> Overview of layout related to lower layer LL

[0129] Next, use Figure 5 , an overview of the layout related to the lower layer LL of the memory cell array 10 is described. Figure 5 A layout example related to the lower layer LL of the memory cell array 10 is shown.

[0130] like Figure 5 As shown, the lower layer LL generally includes a cell region 100 and a connection region 101. Hereinafter, when the cell region 100 in the lower layer LL is indicated, it is sometimes described as a cell region (lower). In addition, when the connection region 101 in the lower layer LL is indicated, it is sometimes described as a connection region (lower) 101.

[0131] Specifically, in Figure 5 On the paper, the unit area (lower) 100 is located at four positions, namely, the upper left, the upper right, the lower left, and the lower right. The upper left, the upper right, the lower left, and the lower right in the case of representing the unit area (lower) 100 are represented by Figure 5 The performance is based on the paper.

[0132] For convenience, the unit area (lower) 100 located at the upper left, upper right, lower left, and lower right in the lower layer LL is respectively recorded as unit area (lower & upper left) 100-LFP, unit area (lower & upper right) 100-LGP, unit area (lower & lower left) 100-LFD, and unit area (lower & lower right) 100-LGD.

[0133] In addition, if Figure 5As shown, there are two connection regions (lower) 101. The first connection region (lower) 101 is set between the unit region (lower & upper left) 100-LFP and the unit region (lower & upper right) 100-LGP to connect (short-circuit) the unit regions. The second connection region (lower) 101 is set between the unit region (lower & lower left) 100-LFD and the unit region (lower & lower right) 100-LGD to connect (short-circuit) the unit regions.

[0134] For the sake of convenience, the connection region (lower) 101 disposed between the unit region (lower & upper left) 100-LFP and the unit region (lower & upper right) 100-LGP is recorded as a connection region (lower & upper) 101-LP. In addition, the connection region (lower) 101 disposed between the unit region (lower & lower left) 100-LFD and the unit region (lower & lower right) 100-LGD is recorded as a connection region (lower & lower) 101-LD.

[0135] <1-2-2-3> Overview of layout related to upper layer UL

[0136] Next, use Figure 6 , an overview of the layout related to the upper layer UL of the memory cell array 10 is described. Figure 6 A layout example related to the upper layer UL of the memory cell array 10 is shown.

[0137] like Figure 6 As shown, the upper layer UL generally includes a cell region 100 and a connection region (upper) 101. Hereinafter, when the cell region 100 in the upper layer UL is indicated, it is sometimes described as a cell region (upper). In addition, when the connection region 101 in the upper layer UL is indicated, it is sometimes described as a connection region (upper) 101.

[0138] Specifically, in Figure 6 On the paper, the unit area (upper) 100 is located at four positions, namely, the upper left, upper right, lower left, and lower right. The upper left, upper right, lower left, and lower right expressions when representing the unit area (upper) 100 are based on Figure 6 The performance is based on the paper.

[0139] For convenience, the unit area (upper) 100 located at the upper left, upper right, lower left, and lower right in the upper layer UL are respectively recorded as unit area (upper & upper left) 100-UFP, unit area (upper & upper right) 100-UGP, unit area (upper & lower left) 100-UFD, and unit area (upper & lower right) 100-UGD.

[0140] The cell region (upper & upper left) 100-UFP and the cell region (upper & lower left) 100-UFD may also share the bit line BL. Similarly, the cell region (upper & upper right) 100-UGP and the cell region (upper & lower right) 100-UGD may also share the bit line BL.

[0141] In addition, if Figure 6 As shown, there are two connection areas (upper) 101. The first connection area (upper) 101 is set between the unit area (upper & upper left) 100-UFP and the unit area (upper & upper right) 100-UGP, so that the unit areas are connected (short-circuited). The second connection area (upper) 101 is set between the unit area (upper & lower left) 100-UFD and the unit area (upper & lower right) 100-UGD, so that the unit areas are connected (short-circuited).

[0142] For the sake of convenience, the connection region (upper) 101 provided between the unit region (upper & upper left) 100-UFP and the unit region (upper & upper right) 100-UGP is recorded as the connection region (upper & upper) 101-UP. In addition, the connection region (upper) 101 provided between the unit region (upper & lower left) 100-UFD and the unit region (upper & lower right) 100-UGD is recorded as the connection region (upper & lower) 101-LD.

[0143] <1-2-2-4> Relationship between the lower layer LL and the upper layer UL

[0144] Here, if Figure 7 As shown, the relationship between the lower layer LL and the upper layer UL is described. Figure 7 The relationship between the lower layer LL and the upper layer UL is shown.

[0145] like Figure 7 As shown, in the Z direction, the unit area (upper & lower left) 100-UFD is set above the unit area (lower & lower left) 100-LFD, and the unit areas are connected. The unit area (lower & lower left) 100-LFD and the unit area (upper & lower left) 100-UFD become the unit area (lower left) 100-FD.

[0146] In addition, in the Z direction, the unit area (upper & lower right) 100-UGD is provided above the unit area (lower & lower right) 100-LGD, and the unit areas are connected. The unit area (lower & lower right) 100-LGD and the unit area (upper & lower right) 100-UGD become the unit area (lower right) 100-GD.

[0147] In addition, in the Z direction, the connection region (upper & lower) 101-UD is located above the connection region (lower & lower) 101-LD. The connection region (lower & lower) 101-LD and the connection region (upper & lower) 101-UD become the connection region (lower) 101-D.

[0148] Furthermore, in the Z direction, a unit area (upper & upper left) 100-UFP is provided above the unit area (lower & upper left) 100-LFP, and the unit areas are connected. The unit area (lower & upper left) 100-LFP and the unit area (upper & upper left) 100-UFP become the unit area (upper left) 100-FP.

[0149] In addition, in the Z direction, the unit area (upper & upper right) 100-UGP is provided above the unit area (lower & upper right) 100-LGP, and the unit areas are connected. The unit area (lower & upper right) 100-LGP and the unit area (upper & upper right) 100-UGP become the unit area (upper right) 100-GP.

[0150] In addition, in the Z direction, the connection area (upper & upper) 101-UP is located above the connection area (lower & upper) 101-LP. The connection area (lower & upper) 101-LP and the connection area (upper & upper) 101-UP become the connection area (upper) 101-P.

[0151] As described above, the connection region (upper) 101 is located above the connection region (lower) 101. This means that the connection region 101 is located at the center of the memory cell array 10 in the X direction.

[0152] <1-2-2-5> Overview of the unit area (lower) and the connection area (lower)

[0153] Second, use Figure 8 , a general layout of the connection region (lower) 101 and the unit region (lower) 100 sandwiching the connection region (lower) 101 is described. Figure 8 An example of the layout of the connection region (lower) 101 and the cell region (lower) 100 sandwiching the connection region (lower) 101 is shown.

[0154] exist Figure 8 , specifically showing a portion of the unit region (lower & upper left) 100-LFP, the unit region (lower & upper right) 100-LGP, and the lower connection region (lower & upper) 101-LP.

[0155] like Figure 8As shown, the unit region (lower & upper left) 100-LFP and the unit region (lower & upper right) 100-LGP each include a plurality of blocks BLK. In addition, in the Y direction, the plurality of blocks BLK are respectively divided by slits SLT extending in the X direction.

[0156] For the sake of convenience, the block BLK (v: any integer) belonging to the unit area (lower & upper left) 100-LFP is recorded as block (lower & upper left) BLK (v) -LFP. In addition, the block BLK (v) belonging to the unit area (lower & upper right) 100-LGP is recorded as block (lower & upper right) BLK (v) -LGP.

[0157] In addition, if Figure 8 As shown, the connection area (lower & upper) 101-LP includes a set of a step area (lower) SSA-L and a sub-channel area (lower) SBA-L for each block.

[0158] In the step region (lower) SSA-L, the ends of the selection gate line SGS and the word lines WL(0) to WL(7) are arranged to be stepped so as to form step differences in the X direction in sequence. In other words, in the step region (lower) SSA-L, the selection gate line SGS and the word lines WL(0) to WL(7) each have a stepped portion (also described as a step, a step portion, a lead portion, a step, or a step portion) at the end that does not overlap with the wiring layer (conductor layer) of the lower layer. A contact plug CC (not shown) is formed on each step portion. This step region can also be described as a lead region.

[0159] The sub-channel area (below) SBA-L is roughly divided into two functions.

[0160] The first one is a function of connecting the step region (lower) SSA-L to the row decoder module 15. Specifically, in the sub-channel region (lower) SBA-L, a contact plug C4 (not shown) is formed for connecting the row decoder module 15 formed below the connection region (lower) 101 in the Z direction to the contact plug CC. However, the contact plug C4 penetrates the sub-channel region (upper) SBA-U provided on the sub-channel region (lower) SBA-L in the Z direction and is exposed on the sub-channel region (upper) SBA-U. Therefore, in order to connect the contact plug C4 to the contact plug CC, the contact plug CC must be connected to the contact plug C4 exposed on the sub-channel region (upper) SBA-U provided on the sub-channel region (lower) SBA-L. The contact plugs CC and C4 include a conductive material, for example, a metal material such as tungsten (W) or titanium nitride (TiN) may also be used.

[0161] The second is a function of connecting adjacent blocks BLK in the X direction. Specifically, the block (lower & upper left) BLK(n-1)-LFP of the unit area (lower & upper left) 100-LFP and the block (lower & upper right) BLK(n-1)-LGP of the unit area (lower & upper right) 100-LGP are connected by the step area (lower) SSA-L and the sub-channel area (lower) SBA-L provided between the unit areas. Thus, the block (lower & upper left) BLK(n-1)-LFP of the unit area (lower & upper left) 100-LFP and the block (lower & upper right) BLK(n-1)-LGP of the unit area (lower & upper right) 100-LGP can be controlled simultaneously.

[0162] exist Figure 8 In the figure, the unit area (lower & upper left) 100-LFP, the unit area (lower & upper right) 100-LGP, and the connection area (lower & upper) 101-LP are explained in detail, and the same applies to the unit area (lower & lower left) 100-LFD, the unit area (lower & lower right) 100-LGD, and the connection area (lower & lower) 101-LD.

[0163] <1-2-2-6> Connection area in the lower layer

[0164] Next, use Fig. 9 ,and Fig.10 , the connection area (lower) 101 in the lower layer LL is described. Fig. 9 ,and Fig.10 In the figure, blocks (lower & upper left) BLK(n)-LFP, blocks (lower & upper right) BLK(n)-LGP, and step areas (lower) SSA-L and sub-channel areas (lower) SBA-L associated with blocks (lower & upper left) BLK(n)-LFP and blocks (lower & upper right) BLK(n)-LGP are shown.

[0165] For convenience, the step region (lower) SSA-L in the first lower layer LL1 is described as the step region (first lower) SSA-L1. Similarly, the sub-channel region (lower) SBA-L in the first lower layer LL1 is described as the sub-channel region (first lower) SBA-L1.

[0166] In addition, for the sake of convenience, the step region (lower) SSA-L in the second lower layer LL2 is recorded as the step region (second lower) SSA-L2. Similarly, the sub-channel region (lower) SBA-L in the second lower layer LL2 is recorded as the sub-channel region (second lower) SBA-L2.

[0167] like Fig. 9As shown, in the first lower layer LL1, the step region (first lower) SSA-L1 includes a lower bridge region LBBA and a lower sub channel connection region LBCA.

[0168] The lower bridge area LBBA is provided with wiring that connects (or also recorded as short-circuit) the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP.

[0169] The sub-channel area (1st lower) SBA-L1 connects the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP via the lower bridge area LBBA.

[0170] The lower sub-channel connection area LBCA includes, for example, terrace portions associated with the select gate line SGS and the word lines WL(0) to WL(4), and a contact plug CC (not shown) is provided in each terrace portion.

[0171] like Fig.10 As shown, the second lower layer LL2 does not include the lower bridging area LBBA.

[0172] In the second lower layer LL2, the step area (second lower) SSA-L2 includes a first lower connectable area LCA1 and a second lower connectable area LCA2.

[0173] The first lower connectable area LCA1 includes, for example, terrace portions associated with word lines WL(5) to WL(7) of the block (lower & upper left) BLK(n)-LFP, and contact plugs CC (not shown) are provided in each terrace portion.

[0174] The second lower connectable area LCA2, for example, includes a terrace portion associated with the word lines WL(5) to WL(7) of the block (lower & upper right) BLK(n)-LGP. Furthermore, contact plugs CB are provided in the terrace portion of the first lower connectable area LCA1 and the terrace portion of the second lower connectable area LCA2, respectively. Furthermore, wiring lines LCL are provided on the contact plugs CB to connect the word lines WL(5) to WL(7) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP, respectively.

[0175] <1-2-2-7> Overview of the unit area (top) and the connection area (top)

[0176] Next, a schematic layout of the connection region (upper) 101 and the cell region (upper) 100 sandwiching the connection region (upper) 101 will be described.

[0177] exist Fig.11 , a portion of the unit area (upper & upper left) 100-UFP, the unit area (upper & upper right) 100-UGP, and the connection area (upper & upper) 101-UP are specifically shown.

[0178] like Fig.11 As shown, the unit region (upper & upper left) 100-UFP and the unit region (upper & upper right) 100-UGP each include a plurality of blocks BLK. In addition, in the Y direction, the plurality of blocks BLK are respectively divided by slits SLT extending in the X direction.

[0179] In addition, for the sake of convenience, the block BLK(v) belonging to the unit area (upper & upper left) 100-UFP is recorded as block (upper & upper left) BLK(v)-UFP. The block BLK(v) belonging to the unit area (upper & upper right) 100-UGP is recorded as block (upper & upper right) BLK(v)-UGP.

[0180] In addition, if Fig.11 As shown, the connection area (upper & upper) 101-UP includes a group of a step area (upper) SSA-U and a sub-channel area (upper) SBA-U for each block.

[0181] In the step region (upper) SSA-U, the word lines WL(8) to WL(15) and the select gate line SGD are arranged at their respective ends in a step shape with steps formed in the X direction. In other words, in the step region (upper) SSA-U, the word lines WL(8) to WL(15) and the select gate line SGD have stepped portions at their respective ends that do not overlap with the wiring layer (conductor layer) below. A contact plug CC (not shown) is formed on each stepped portion.

[0182] The sub-channel area (upper) SBA-U is roughly divided into two functions. The first is the function of connecting the step area (upper) SSA-U to the row decoder module 15. Specifically, in the sub-channel area (upper) SBA-U, a contact plug C4 (not shown) is formed to connect the row decoder module 15 formed below the connection area (lower) 101 in the Z direction to the contact plug CC. The contact plug CC is connected to the upper end of the contact plug C4 through a wiring layer. The contact plugs CC and C4 contain conductive materials, for example, metal materials such as tungsten (W) or titanium nitride (TiN) can also be used. The second is the function of connecting the adjacent blocks BLK in the X direction.

[0183] Specifically, the block BLK(n-1)-UFP of the unit area (upper & upper left) 100-UFP and the block BLK(n-1)-UGP of the unit area (upper & upper right) 100-UGP are connected by the step area (upper) SSA-U and the sub-channel area (upper) SBA-U provided between the unit areas. Thus, the block BLK(n-1)-UFP of the unit area (upper & upper left) 100-UFP and the block BLK(n-1)-UGP of the unit area (upper & upper right) 100-UGP can be controlled simultaneously.

[0184] in addition, Figure 8 and Fig.11 The blocks BLK shown are located at the same coordinates in a plane including the X direction and the Y direction. That is, Fig.11 The block BLK(n-1) shown is located at Figure 8 The block BLK(n-1) shown is located above the Z direction. The same applies to the other blocks BLK.

[0185] also, Figure 8 The step area shown (bottom) SSA-L and Fig.11 The step area (upper) SSA-U shown is located at the same coordinate in the plane including the X direction and the Y direction. In other words, Fig.11 The step area shown (above) SSA-U is located at Figure 8 The step region (lower) SSA-L shown is above the Z direction. The same is true for the other step regions (lower) SSA-L and the step region (upper) SSA-U. Sometimes, for simplicity, the step region (lower) SSA-L and the step region (upper) SSA-U are combined and recorded as the step region SSA.

[0186] also, Figure 8 The side channel region (lower) of SBA-L is shown with Fig.11 The subchannel area (upper) SBA-U shown is located at the same coordinate in the plane including the X direction and the Y direction. In other words, Fig.11 The side channel area (top) shown is located at SBA-U Figure 8 The sub-channel area (lower) SBA-L shown in the figure is above the Z direction. The same is true for other sub-channel areas (lower) SBA-L and sub-channel areas (upper) SBA-U. Sometimes, for the sake of simplicity, the sub-channel area (lower) SBA-L and the sub-channel area (upper) SBA-U are combined and recorded as the sub-channel area SBA.

[0187] exist Fig.11In the figure, the unit area (upper & upper left) 100-UFP, the unit area (upper & upper right) 100-UGP, and the connection area (upper & upper) 101-UP are explained in detail, and the same applies to the unit area (upper & lower left) 100-UFD, the unit area (upper & lower right) 100-UGD, and the connection area (upper & lower) 101-UD.

[0188] <1-2-2-8> Connection area in the upper layer

[0189] Next, use Fig.12 and Fig.13 , the connection area (upper) 101 is described. Fig.12 and Fig.13 In the figure, the block (upper & upper left) BLK(n)-UFP, the block (upper & upper right) BLK(n)-UGP, the step area (upper) SSA-U related to the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP, and the sub-channel area (upper) SBA-U are shown.

[0190] For convenience, the step region (upper) SSA-U in the first upper layer UL1 is referred to as step region (first upper) SSA-U1. Similarly, the sub channel region (upper) SBA-U in the first upper layer UL1 is referred to as sub channel region (first upper) SBA-U1.

[0191] In addition, for convenience, the step area (upper) SSA-U in the second upper layer UL2 is recorded as the step area (second upper) SSA-U2. Similarly, the sub-channel area (upper) SBA-U in the second upper layer UL2 is recorded as the sub-channel area (second upper) SBA-U2.

[0192] like Fig.12 As shown, in the first upper layer UL1, the step region (first upper) SSA-U1 includes an upper bridging region UBBA and an upper sub channel connecting region UBCA.

[0193] The upper bridge area UBBA is provided with wiring that connects the word lines WL(8) to WL(12) in the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP.

[0194] The sub-channel area (1st upper) SBA-U1 connects the word lines WL(8) to WL(12) in the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP via the upper bridge area UBBA.

[0195] The upper sub-channel connection area UBCA includes, for example, terrace portions associated with word lines WL(8) to WL(12), and a contact plug CC (not shown) is provided in each terrace portion.

[0196] like Fig.13 As shown, the second upper layer UL2 does not include the upper bridging area UBBA.

[0197] In the second upper layer UL2, the step area (second upper) SSA-U2 includes a first upper connectable area UCA1 and a second upper connectable area UCA2.

[0198] The first upper connectable area UCA1, for example, includes a step portion associated with the word lines WL(13) to WL(15) of the block (upper & upper left) BLK(n)-UFP and the selection gate line SGD, and a contact plug CC (not shown) is provided in each step portion.

[0199] The second upper connectable area UCA2, for example, includes a step portion associated with the word lines WL(13) to WL(15) of the block (upper & upper right) BLK(n)-UGP and the selection gate line SGD. Furthermore, contact plugs CB are provided in the step portion of the first upper connectable area UCA1 and the step portion of the second upper connectable area UCA2, respectively. Furthermore, wiring lines UCL are provided on the contact plugs CB, which respectively connect the word lines WL(13) to WL(15) of the block (upper & upper left) BLK(n)-UFP and the selection gate line SGD of the block (upper & upper right) BLK(n)-UGP.

[0200] <1-2-2-9> Connection relationship in the lower layer

[0201] As described above, in the first lower layer LL1 and the second lower layer LL2, the connection method of the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP are different. Therefore, the connection method of the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP in the first lower layer LL1 and the second lower layer LL2, the connection method of the block (lower & upper left) BLK(n)-LFP and the row decoder RD of the row decoder module 15, and the connection method of the block (lower & upper right) BLK(n)-LGP and the row decoder RD of the row decoder module 15 are schematically described.

[0202] Fig.14 1 is a block diagram showing the connection of each component in the first lower layer LL1. Fig.14As shown, in the first lower layer LL1, the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP are connected via the lower bridge area LBBA and the sub-channel area (lower) SBA-L.

[0203] In addition, the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper left) BLK(n)-LFP are connected to the row decoder RD related to the block BLK(n) via the lower sub-channel connection area LBCA, the first contact wiring CL1 connecting the lower sub-channel connection area LBCA and the contact plug C4, and the contact plug C4. Hereinafter, the row decoder RD related to the block BLK(v) is recorded as RD(BLK(v)).

[0204] In addition, the selection gate line SGS and word lines WL(0) to WL(4) in the block (lower & upper right) BLK(n)-LGP are connected to the row decoder RD(BLK(n)) associated with the block BLK(n) via the sub-channel area (lower) SBA-L, the lower bridge area LBBA, the lower sub-channel connection area LBCA, the first contact wiring CL1, and the contact plug C4.

[0205] Fig.15 1 is a block diagram showing the connection of each component in the second lower layer LL2. Fig.15 As shown, in the second lower layer LL2, the word lines WL(5) to WL(7) in the block (lower & upper left) BLK(n)-LFP and the block (lower & upper right) BLK(n)-LGP are connected via the first lower connectable area LCA1, the lower connecting wiring LCL connecting the first lower connectable area LCA1 and the second lower connectable area LCA2, and the second lower connectable area LCA2.

[0206] In addition, the word lines WL(5) to WL(7) in the block (lower & upper left) BLK(n)-LFP are connected to the row decoder RD(BLK(n)) associated with the block BLK(n) via the first lower connectable area LCA1, the second contact wiring CL2 connecting the first lower connectable area LCA1 and the contact plug C4, and the contact plug C4.

[0207] In addition, the word lines WL(5) to WL(7) in the block (lower & upper right) BLK(n)-LGP are connected to the row decoder RD(BLK(n)) associated with the block BLK(n) via the sub-channel area (lower) SBA-L, the second lower connectable area LCA2, the lower connection wiring LCL, the first lower connectable area LCA1, the second contact wiring CL2, and the contact plug C4.

[0208] <1-2-2-10> Connection relationship in the upper layer

[0209] As described above, in the first upper layer UL1 and the second upper layer UL2, the connection method of the block (upper & upper left) BLK(n)-UFP is different from that of the block (upper & upper right) BLK(n)-UGP. Therefore, the connection of each structure in the first upper layer UL1 and the second upper layer UL2 is schematically described.

[0210] Fig.16 1 is a block diagram showing the connection of each component in the first upper layer UL1. Fig.16 As shown, in the first upper layer UL1, the word lines WL(8) to WL(12) in the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP are connected via the upper bridge area UBBA and the sub-channel area (upper) SBA-U.

[0211] In addition, the word lines WL(8) to WL(12) in the block (upper & upper left) BLK(n)-UFP are connected to the row decoder RD(BLK(n)) related to the block BLK(n) via the upper sub-channel connection area UBCA, the third contact wiring CL3 connecting the upper sub-channel connection area UBCA and the contact plug C4, and the contact plug C4.

[0212] In addition, the word lines WL(8) to WL(12) in the block (upper & upper right) BLK(n)-UGP are connected to the row decoder RD(BLK(n)) associated with the block BLK(n) via the sub-channel area (upper) SBA-U, the upper bridge area UBBA, the upper sub-channel connection area UBCA, the third contact wiring CL3, and the contact plug C4.

[0213] Fig.17 2 is a block diagram showing the connection of each component in the second upper layer UL2. Fig.17 As shown, in the second upper layer UL2, the word lines WL(13) to WL(15) in the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP, and the selection gate line SGD are connected via the first upper connectable area UCA1, the upper connecting wiring UCL connecting the first upper connectable area UCA1 and the second upper connectable area UCA2, and the second upper connectable area UCA2.

[0214] In addition, the word lines WL(13) to WL(15) and the selection gate line SGD in the block (upper & upper left) BLK(n)-UFP are connected to the row decoder RD(BLK(n)) associated with the block BLK(n) via the first upper connectable area UCA1, the fourth contact wiring CL4 connecting the first upper connectable area UCA1 and the contact plug C4, and the contact plug C4.

[0215] In addition, the word lines WL(13)~WL(15) and the selection gate line SGD in the block (upper & upper right) BLK(n)-UGP are connected to the row decoder RD(BLK(n)) associated with the block BLK(n) via the sub-channel area (upper) SBA-U, the second upper connectable area UCA2, the upper connection wiring UCL, the first upper connectable area UCA1, the fourth contact wiring CL4, and the contact plug C4.

[0216] In addition, when the first contact wiring CL1 , the second contact wiring CL2 , the third contact wiring CL3 , and the fourth contact wiring CL4 are not distinguished from each other, they are simply described as contact wirings CL.

[0217] <1-2-2-11> Relationship between the connection area (lower) and the connection area (upper)

[0218] Here, use Fig.18 , the relationship between the connection area (lower) 101 and the connection area (upper) 101 is described. Fig.18 In the figure, the block (lower & upper left) BLK(n)-UFP, the block (lower & upper right) BLK(n)-UGP, the step area (lower) SSA-L and the sub-channel area (lower) SBA-L related to the block (lower & upper left) BLK(n)-UFP and the block (lower & upper right) BLK(n)-UGP, as well as the block (upper & upper left) BLK(n)-UFP, the block (upper & upper right) BLK(n)-UGP, the step area (upper) SSA-U and the sub-channel area (upper) SBA-U related to the block (upper & upper left) BLK(n)-UFP and the block (upper & upper right) BLK(n)-UGP.

[0219] like Fig.18 As shown, the lower subchannel connection region LBCA of the first lower layer LL1 includes regions LBCA1 and LBCA2. Region LBCA1 is covered by the first lower connectable region LCA1 in the Z direction. On the other hand, region LBCA2 is not covered by the first lower connectable region LCA1 in the Z direction. Therefore, a step for setting a contact plug CC (not shown) is formed in region LBCA2.

[0220] The first lower connectable area LCA1 of the second lower layer LL2 includes areas LCA11 and LCA12. Area LCA11 is covered by the upper sub-channel connection area UBCA in the Z direction. On the other hand, area LCA12 is not covered by the upper sub-channel connection area UBCA in the Z direction. Therefore, a step for setting the contact plug CC is formed in area LCA12.

[0221] The second lower connectable area LCA2 of the second lower layer LL2 includes areas LCA21 and LCA22. Area LCA21 is covered by the second upper connectable area UCA2 in the Z direction. On the other hand, area LCA22 is not covered by the second upper connectable area UCA2 in the Z direction. Therefore, a step for providing a contact plug CC is formed in area LCA22.

[0222] In addition, the upper sub-channel connection area UBCA of the first upper layer UL1 includes areas UBCA1 and UBCA2. Area UBCA1 is covered by the first upper connectable area UCA1 in the Z direction. On the other hand, area UBCA2 is not covered by the first upper connectable area UCA1 in the Z direction. Therefore, a step for providing a contact plug CC is formed in area UBCA2.

[0223] Thus, the first upper connectable area UCA1 is provided above a portion of the upper sub channel connection area UBCA in the Z direction, and the first upper connectable area UCA1 is not provided above the other portion. Therefore, wiring can be connected from the upper sub channel connection area UBCA to the sub channel area.

[0224] Furthermore, an upper sub-channel connection area UBCA is provided above a portion of the first lower connectable area LCA1 in the Z direction, and no upper sub-channel connection area UBCA is provided above the other portion. Therefore, wiring can be connected from the first lower connectable area LCA1 to the sub-channel area.

[0225] Furthermore, the first lower connectable area LCA1 is provided above a portion of the lower sub-channel connection area LBCA in the Z direction, and the first lower connectable area LCA1 is not provided above the other portion. Therefore, wiring can be connected from the lower sub-channel connection area LBCA to the sub-channel area.

[0226] Furthermore, the second upper connectable area UCA2 is provided above a portion of the second lower connectable area LCA2 in the Z direction, and the second upper connectable area UCA2 is not provided above the other portion. Therefore, wiring can be connected from the second lower connectable area LCA2 to the sub-channel area.

[0227] <1-2-3> Layout of circuit area

[0228] <1-2-3-1>Overview

[0229] use Fig.19 , the layout of the plane including the X direction and the Y direction of the circuit area CTA will be described.

[0230] like Fig.19 As shown, in the circuit area CTA, the sense amplifier module 16 is divided into four.

[0231] Specifically, in Fig.19 On the paper, the sense amplifier module 16 is located in four locations, namely, the upper left, the upper right, the lower left, and the lower right. The upper left, the upper right, the lower left, and the lower right are represented by Fig.19 The performance is based on the paper.

[0232] For the sake of convenience, the sense amplifier modules 16 located at the upper left, upper right, lower left, and lower right in the circuit area CTA are respectively described as sense amplifier module (upper left) 16-FP, sense amplifier module (upper right) 16-GP, sense amplifier module (lower left) 16-FD, and sense amplifier module (lower right) 16-GD. In addition, when the four sense amplifier modules are not distinguished, they are simply described as sense amplifier modules 16.

[0233] In addition, if Fig.19 As shown, in the Z direction, the sense amplifier module (upper left) 16-FP is disposed below the cell region (upper & upper left) 100-UFP and the cell region (lower & upper left) 100-LFP. Furthermore, the sense amplifier module (upper left) 16-FP is connected to the bit line BL associated with the cell region (upper & upper left) 100-UFP and the cell region (lower & upper left) 100-LFP via the second peripheral circuit (upper left) 18-FP disposed on one side of the sense amplifier module (upper left) 16-FP.

[0234] In addition, if Fig.19 As shown, in the Z direction, the sense amplifier module (upper right) 16-GP is disposed below the cell region (upper & upper right) 100-UGP and the cell region (lower & upper right) 100-LGP. Furthermore, the sense amplifier module (upper right) 16-GP is connected to the bit line BL associated with the cell region (upper & upper right) 100-UGP and the cell region (lower & upper right) 100-LGP via the second peripheral circuit (upper right) 18-GP disposed on one side of the sense amplifier module (upper right) 16-GP.

[0235] In addition, if Fig.19As shown, in the Z direction, the sense amplifier module (lower left) 16-FD is disposed below the cell region (upper & lower left) 100-UFD and the cell region (lower & lower left) 100-LFD. Furthermore, the sense amplifier module (lower left) 16-FD is connected to the bit line BL associated with the cell region (upper & lower left) 100-UFD and the cell region (lower & lower left) 100-LFD via the second peripheral circuit (lower left) 18-FD disposed on one side of the sense amplifier module (lower left) 16-FD.

[0236] In addition, if Fig.19 As shown, in the Z direction, the sense amplifier module (lower right) 16-GD is disposed below the cell region (upper & lower right) 100-UGD and the cell region (lower & lower right) 100-LGD. Furthermore, the sense amplifier module (lower right) 16-GD is connected to the bit line BL associated with the cell region (upper & lower right) 10-UGD and the cell region (lower & lower right) 100-LGD via the second peripheral circuit (upper right) 18-GD disposed on one side of the sense amplifier module (lower right) 16-GD.

[0237] like Fig.19 As shown, the row decoder module (upper) 15-P is sandwiched between the sense amplifier module (upper left) 16-FP and the sense amplifier module (upper right) 16-GP in the X direction. In addition, the row decoder module (lower) 15-D is sandwiched between the sense amplifier module (lower left) 16-FD and the sense amplifier module (lower right) 16-GD in the X direction.

[0238] In addition, if Fig.19 As shown, the first peripheral circuit 17 is provided on one side of the circuit area CTA.

[0239] The first peripheral circuit 17 and the second peripheral circuit 18 include a command register 11 , an address register 12 , a sequencer 13 , and a driver module 14 as appropriate.

[0240] <1-2-3-2> Relationship between row decoder and block

[0241] Second, use Fig. 20 , the relationship between the row decoder and the block is explained.

[0242] exist Fig. 20 , a portion of the row decoder module 15 and a portion of the sense amplifier module 16 of the circuit area CTA are shown. Fig. 20 , a portion of a sense amplifier module (upper left) 16-FP, a sense amplifier module (upper right) 16-GP, and a row decoder module (upper) 15-P are shown.

[0243] like Fig. 20As shown, the row decoder module 15 includes a row decoder RD for each block BLK. Fig. 20 As shown, two row decoders RD are arranged along the X direction, and a plurality of row decoders RD are arranged along the Y direction.

[0244] <1-2-3-3> Relationship between row decoder module and connection area in memory cell array

[0245] Next, use Fig.21 , the relationship between the row decoder module 15 in the circuit area CTA and the connection area 101 in the memory cell array 10 is described.

[0246] exist Fig.21 In the circuit area CTA diagram and Fig. 20 The same content. In addition, Fig.21 In the figure, for the sake of simplicity, the memory cell array 10 is illustrated without distinguishing between the lower layer LL and the upper layer UL.

[0247] like Fig.21 As shown, the connection region 101 is provided above the row decoder module 15 in the Z direction. More specifically, a step region and a sub-channel region related to the block BLK(n-1) are provided above the row decoder RD(BLK(n-1)) related to the block BLK(n-1) in the Z direction. The row decoder RD(BLK(n-1)) related to the block BLK(n-1) is connected to the block BLK(n-1) of the memory cell array 10 via the step region and the sub-channel region related to the block BLK(n-1).

[0248] Other row decoder modules 15 , as well as step regions and sub-channel regions, are also provided corresponding to the blocks BLK of the memory cell array 10 .

[0249] <1-2-4> Detailed structure of memory cell array

[0250] <1-2-4-1> Memory cell array layout

[0251] use Fig. 22 , an example of a planar layout of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment will be described.

[0252] Fig. 22 This is an example of a planar layout of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment, and regions corresponding to two blocks BLK (that is, string units SU0 to SU3) are extracted and shown.

[0253] like Fig. 22As shown, in the planar layout of the memory cell array 10, for example, two cell regions 100 are connected via a connection region 101 in the X direction. In addition, the memory cell array 10 includes a plurality of slits SLT ( Fig. 22 SLT0 to SLT2), and a plurality of slits SHE (SHE0 and SHE1).

[0254] The plurality of slits SLT are provided to extend in the X direction and are arranged in the Y direction. The slits SLT cross the cell region 100 and the connection region 101 in the X direction.

[0255] For example, one slit SHE is located between each of the adjacent slits SLT. The slit SHE is provided to extend along the X direction and cross the cell region 100 in the X direction.

[0256] Specifically, the slit SLT divides a plurality of wiring layers corresponding to the word lines WL(0) to WL(15), the selection gate line SGD, and the selection gate line SGS, for example, and the slit SHE divides the wiring layer corresponding to the selection gate line SGD.

[0257] The slit SLT and the slit SHE each have a structure in which an insulating member is buried inside a groove.

[0258] In the above-described planar layout of the memory cell array 10, each region partitioned by the slits SLT and SHE in the cell region 100 corresponds to one string unit SU. That is, in this example, string units SU0 to SU3 extending in the X direction are arranged in the Y direction.

[0259] Specifically, a plurality of NAND strings NS disposed in the region between the slit SLT0 and the slit SHE0 in the Y direction are set as a string component SU0. In addition, a plurality of NAND strings NS disposed in the region between the slit SHE0 and the slit SLT1 in the Y direction are set as a string component SU1. Moreover, the string components SU0 and SU1 disposed in the region between the slit SLT0 and the slit SLT1 are recorded as, for example, a block BLK. Similarly, a plurality of NAND strings NS disposed in the region between the slit SLT1 and the slit SHE1 in the Y direction are set as a string component SU2. In addition, a plurality of NAND strings NS disposed in the region between the slit SHE1 and the slit SLT2 in the Y direction are set as a string component SU3. Moreover, the string components SU2 and SU3 disposed in the region between the slit SLT1 and the slit SLT2 are recorded as a block BLK.

[0260] In the above-described planar layout of the memory cell array 10, the number of slits SHE between adjacent slits SLT can be designed to be any number. The number of string assemblies SU between two adjacent slits SLT varies based on the number of slits SHE between two adjacent slits SLT.

[0261] <1-2-4-2> Structure of Memory Cell Array 10 in Cell Area CA

[0262] Next, a detailed planar layout of the memory cell array 10 in the cell region 100 of the semiconductor memory device 1 according to the first embodiment will be described.

[0263] Fig.23 This is an example of a detailed planar layout of the memory cell array 10 in the cell region 100 of the semiconductor memory device 1 according to the first embodiment, and the regions corresponding to the string units SU0 and SU1 are selected ( Fig. 22 A) is used to represent.

[0264] like Fig.23 As shown, in the cell region 100 , the memory cell array 10 further includes a plurality of memory pillars MP, a plurality of contact plugs CP, and a plurality of bit lines BL.

[0265] Each memory column MP functions as, for example, one NAND string NS.

[0266] The plurality of memory pillars MP are arranged along a plurality of “columns” and “rows”.

[0267] A “column” in which a plurality of memory pillars MP are arranged extends in the Y direction, and generally includes even-numbered columns Ce and odd-numbered columns Co. The even-numbered columns Ce and the odd-numbered columns Co are alternately arranged in the X direction.

[0268] For example, Fig.23 As shown, between the slits SLT in the string units SU0 and SU1, four memory pillars MP are provided in the even-numbered columns Ce, and five memory pillars MP are provided in the odd-numbered columns Co. The number of the memory pillars MP is not limited thereto.

[0269] A “row” in which a plurality of memory pillars MP are arranged extends in the X direction, and a plurality of rows (eg, 9 rows in this example) are provided in the Y direction between the slits SLT.

[0270] In each row, a memory pillar MP is provided corresponding to any one of the even-numbered columns Ce and the odd-numbered columns Co.

[0271] In addition, the plurality of memory pillars MP provided in the adjacent even-numbered columns Ce and odd-numbered columns Co may be described as being arranged to be offset in the Y direction.

[0272] In addition, the memory pillar MP located at a position overlapping with the slit SHE does not function as a NAND string NS, but is treated as a dummy NAND string NS.

[0273] A plurality of bit lines BL extend in the Y direction, respectively, and are arranged in the X direction. Each bit line BL is arranged so as to overlap with at least one storage column MP in each string component SU. In this example, two bit lines BL are arranged so as to overlap with each storage column MP. A contact plug CP is arranged between one bit line BL among the plurality of bit lines BL overlapping with the storage column MP and the storage column MP. Each storage column MP is electrically connected to the corresponding bit line BL via the contact plug CP.

[0274] In addition, as described above, the memory column MP overlapping the slit SHE is dummy. Therefore, the contact plug CP between the memory column MP overlapping the slit SHE and the bit line BL is omitted. The number and layout of the memory column MP or the slit SHE between adjacent slits SLT are not limited to the number and layout of the memory column MP or the slit SHE. Fig.23 The structure of the description can be changed appropriately.

[0275] <1-2-4-3> Cross-sectional structure in the cell region of the memory cell array

[0276] Second, use Fig.24 , an example of a cross-sectional structure in a cell region 100 of a memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment will be described.

[0277] Fig.24 It is along Fig.23 The cross-sectional view taken along the line CC of FIG. 1 shows an example of the cross-sectional structure in the cell region 100 of the memory cell array 10 included in the semiconductor memory device 1 according to the first embodiment. Fig.24 As shown, the memory cell array 10 further includes conductive layers 21 - 25 . The conductive layers 21 - 25 are disposed above the semiconductor substrate 20 .

[0278] Specifically, a conductive layer 21 is provided above the semiconductor substrate 20 via an insulator layer 40. A circuit corresponding to, for example, a row decoder module 15 or a sense amplifier module 16 may be provided in the insulator layer 40 between the semiconductor substrate 20 and the conductive layer 21. The conductive layer 21 is formed, for example, in a plate shape extending along the XY plane and is used as a source line SL. The conductive layer 21 includes, for example, silicon (Si).

[0279] The conductor layer 22 is provided above the conductor layer 21 via the insulating layer 41. The conductor layer 22 is formed in a plate shape extending along the XY plane, for example, and is used as a selection gate line SGS. The conductor layer 22 includes silicon, for example.

[0280] The insulating layer 42 and the conductive layer 23 are alternately stacked on the conductive layer 22. The conductive layer 23 is formed, for example, in a plate shape extending along the XY plane. For example, the stacked plurality of conductive layers 23 correspond to the word lines WL(0) to WL(15) in order from the semiconductor substrate 20 side. The conductive layer 23 contains, for example, tungsten (W).

[0281] A conductor layer 24 is stacked on the uppermost conductor layer 23 via an insulating layer 42. The conductor layer 24 is formed in a plate shape extending along the XY plane, for example. The conductor layer 24 corresponds to the selection gate line SGD, for example. The conductor layer 24 contains tungsten, for example.

[0282] A conductor layer 25 is provided above the uppermost conductor layer 24 via an insulating layer 43. The conductor layer 25 is formed in a linear shape extending in the Y direction, for example, and is used as a bit line BL. The conductor layer 25 includes copper (Cu), for example.

[0283] In addition, the plurality of conductive layers 23 may be described as a laminate.

[0284] The memory pillars MP are respectively provided to extend along the Z direction and penetrate the conductive layers 22 to 24. The memory pillars MP are respectively formed inside the memory holes MH.

[0285] The memory hole MH penetrates the conductive layers 22 to 24 , and the bottom thereof is in contact with the conductive layer 21 .

[0286] In addition, each of the memory pillars MP includes, for example, a core member 30 , a semiconductor layer 31 , and a stacked film 32 .

[0287] Specifically, the core member 30 is arranged to extend along the Z direction. For example, the upper end of the core member 30 is included in a layer higher than the uppermost conductor layer 24, and the lower end of the core member 30 is included in a layer in which the conductor layer 21 is provided. The semiconductor layer 31, for example, has a portion covering the side and bottom surfaces of the core member 30, and a columnar portion extending in the Z direction at the bottom of the core member 30. For example, the bottom of the columnar portion of the semiconductor layer 31 is included in the layer in which the conductor layer 21 is provided. The laminated film 32 covers the side and bottom surfaces of the semiconductor layer 31 except for the portion in which the columnar portion of the semiconductor layer 31 is provided. For example, the bottom of the columnar portion of the laminated film 32 is included in the layer in which the conductor layer 21 is provided. The core member 30, for example, includes silicon oxide (SiO 2 ) or other insulators. The semiconductor layer 31 includes, for example, silicon.

[0288] A columnar contact plug CP is provided on the upper surface of the semiconductor layer 31 in the storage column MP. In the illustrated area, contact plugs CP corresponding to two storage columns MP among the five storage columns MP are displayed. For the storage columns MP in the area that do not overlap with the slit SHE and are not connected to the contact plug CP, the contact plug CP is connected in an area not illustrated.

[0289] One conductive layer 25 , that is, one bit line BL contacts the upper surface of the contact plug CP. One contact plug CP is connected to one conductive layer 25 in each space (string element) partitioned by the slits SLT and SHE and the memory pillar MP contacting the slit SHE.

[0290] The slit SLT is formed in a plate shape extending along the XZ plane, for example, and divides the conductor layers 22 to 24. The upper end of the slit SLT is included in the layer between the uppermost conductor layer 24 and the conductor layer 25. The lower end of the slit SLT is included in the layer where the conductor layer 21 is provided. The slit SLT is made of an insulator such as silicon oxide, for example.

[0291] The slit SHE is, for example, formed in a plate shape extending along the XZ plane, dividing the stacked conductor layer 24. The upper end of the slit SHE is included in the layer between the conductor layer 24 and the conductor layer 25. The lower end of the slit SHE is, for example, included in the layer between the top conductor layer 23 and the conductor layer 24. The slit SHE includes, for example, an insulator such as silicon oxide. For example, the upper end of the slit SHE is aligned with the upper end of the storage column MP. This is not limited to this, and the upper end of the storage column MP may also be misaligned with the upper ends of the slit SLT and SHE.

[0292] In this embodiment, the portion from the source line SL to the word line WL(7) is defined as the lower layer LL. Also, the portion from the word line WL(8) to the select gate line SGD is defined as the upper layer UL.

[0293] <1-2-4-4> Cross-sectional Structure of Memory Pillar MP of Memory Cell Array 10

[0294] Fig.25 It is along Fig.24 The cross-sectional view taken along the line DD of FIG. 1 shows an example of the cross-sectional structure of the memory pillar MP in the semiconductor memory device 1 according to the first embodiment. More specifically, Fig.25 The cross-sectional structure of the memory pillar MP in a layer parallel to the surface of the semiconductor substrate 20 and including the conductor layer 23 is shown.

[0295] like Fig.21As shown, in the layer including the conductor layer 23, the core member 30 is provided, for example, at the center of the memory pillar MP. The semiconductor layer 31 surrounds the side of the core member 30. The laminated film 32 surrounds the side of the semiconductor layer 31. The laminated film 32 includes, for example, a tunnel insulating film 33, an insulating film 34, and a blocking insulating film 35.

[0296] The tunnel insulating film 33 surrounds the side surface of the semiconductor layer 31. The insulating film 34 surrounds the side surface of the tunnel insulating film 33. The blocking insulating film 35 surrounds the side surface of the insulating film 34. The conductive layer 23 surrounds the side surface of the blocking insulating film 35. The tunnel insulating film 33 and the blocking insulating film 35 each include, for example, silicon oxide. The insulating film 34 includes, for example, silicon nitride (SiN).

[0297] In the structure of the memory column MP described above, the portion where the memory column MP intersects the conductive layer 22 functions as the selection transistor ST2. The portion where the memory column MP intersects the conductive layer 23 functions as the memory cell transistor MT. The portion where the memory column MP intersects the conductive layer 24 functions as the selection transistor ST1.

[0298] That is, the semiconductor layer 31 is used as a channel for each of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 34 is used as a charge accumulation layer for the memory cell transistor MT. Thus, each memory column MP functions as one NAND string NS.

[0299] <1-2-4-5> Structure of the connection area

[0300] Next, the structure of the connection region 101 of the semiconductor memory device 1 according to the first embodiment will be described.

[0301] Fig.26 This is an example of a detailed planar layout of the connection regions 101 of the semiconductor memory device 1 according to the first embodiment. Two connection regions 101 ( Fig. 22 More specifically, Fig.26 Shown in the settings Figure 8 or Fig.11 The step area and the sub-channel area between the block BLK(n) and the block BLK(n-1) represented in FIG.

[0302] Fig. 27 It is along Fig.26 The cross-sectional view along the EE line of FIG. 1 shows an example of the cross-sectional structure of the secondary channel connection region and the step region. More specifically, Fig. 27 Contact plugs CC disposed in the step region are shown.

[0303] Fig.28 It is along Fig.26The cross-sectional view along the FF line of FIG. 1 shows an example of the cross-sectional structure of the secondary channel connection region and the step region. More specifically, Fig.28 The contact plug CB provided in the step region is shown.

[0304] Fig.29 It is along Fig.26 The cross-sectional view along the GG line of FIG. 1 shows an example of the cross-sectional structure of the secondary channel connection region and the step region. More specifically, Fig.29 A lower bridging area LBBA, an upper bridging area UBBA, and a sub-channel area are shown.

[0305] Fig.30 It is along Fig.26 The cross-sectional view taken along the HH line of FIG. 1 shows an example of the cross-sectional structure of the lower bridge area LBBA and the lower sub-channel connection area LBCA. More specifically, Fig.30 An example of the cross-sectional structure of the terrace portion related to the selection gate line SGS of the block BLK(n) and the block BLK(n-1) and the lower bridge area LBBA related to the selection gate line SGS is shown.

[0306] Fig.31 It is along Fig.26 The cross-sectional view taken along the JJ line of FIG. 1 shows an example of the cross-sectional structure of the first lower connectable area LCA1. More specifically, Fig.31 The diagram shows a terrace portion related to the word line WL(5) of the block BLK(n) and the block BLK(n-1), and contact plugs CC and CB provided in the terrace portion.

[0307] Fig.32 It is along Fig.26 The cross-sectional view taken along the KK line of FIG. 1 shows an example of the cross-sectional structure of the lower bridge area LBBA and the lower sub-channel connection area LBCA. More specifically, Fig.32 An example of the cross-sectional structure of the terrace portion related to the word line WL( 8 ) of the block BLK(n) and the block BLK(n−1) and the upper bridge area UBBA related to the word line WL( 8 ) is shown.

[0308] Fig.33 It is along Fig.26 The cross-sectional view taken along line LL of FIG. 1 shows an example of the cross-sectional structure of the first upper connectable area UCA1. More specifically, Fig.33 The diagram shows a terrace portion related to the word line WL(14) of the block BLK(n) and the block BLK(n-1), and contact plugs CC and CB provided in the terrace portion.

[0309] Fig.34 It is along Fig.26 The cross-sectional view along the MM line of FIG. 1 shows an example of the cross-sectional structure of the secondary channel connection region. More specifically, Fig.34 A contact plug C4 disposed in the sub-channel connection region is shown.

[0310] like Fig.26 , Fig. 27 ,and Fig.34 As shown, the contact plugs CC are located on the same straight line in the X direction, for example. In addition, the contact plug C4 penetrates the sub-channel region (lower) SBA-L and the sub-channel region (upper) SBA-U and is connected to the row decoder RD.

[0311] Likewise, if Fig.26 and Fig.28 As shown in FIG. 1 , the contact plugs CB are located on the same straight line in the X direction, for example. Fig.28 As shown, the positions of the first lower connectable area LCA1 and the second lower connectable area LCA2 in the Z direction (the height from the semiconductor substrate (not shown)) are respectively the same.

[0312] like Fig.29 As shown, the selection gate line SGS and word lines WL(0) to WL(4) are connected to the lower sub-channel connection area LBCA via the lower bridge area LBBA. Similarly, word lines WL(8) to WL(13) are connected to the upper sub-channel connection area UBCA via the upper bridge area UBBA. On the other hand, word lines WL(5) to WL(7) are not provided with the lower bridge area LBBA. In addition, word lines WL(14), WL(15), and the selection gate line SGD are not provided with the upper bridge area UBBA.

[0313] like Fig.30 As shown, the selection gate line SGS is connected to the lower bridge area LBBA via the lower sub-channel connection area LBCA. The above situation is also the same in the word line WL(0) to the word line WL(4). As a result, the selection gate line SGS and the word line WL(0) to the word line WL(4) of the two blocks BLK(n) separated by the connection area 101 are connected to each other. Similarly, the selection gate line SGS and the word line WL(0) to the word line WL(4) of the two blocks BLK(n-1) separated by the connection area 101 are connected to each other.

[0314] like Fig.31 As shown, the word line WL(5) is not provided with a lower bridge area LBBA. Therefore, a contact plug CB is provided in the terrace portion of the first lower connectable area LCA1 and is connected to the contact plug CB of the second lower connectable area LCA2 via a lower connection line LCL (not shown) (see Fig.26). Thus, the word lines WL(5) to WL(7) of the two blocks BLK(n) sandwiching the connection region 101 are connected to each other. Similarly, the word lines WL(5) to WL(7) of the two blocks BLK(n-1) sandwiching the connection region 101 are connected to each other.

[0315] like Fig.32 As shown, word line WL(8) is connected to upper bridge area UBBA via upper sub-channel connection area UBCA. The same is true for word line WL(9) to word line WL(13). Thus, word line WL(8) to word line WL(13) of two blocks BLK(n) separated by connection area 101 are connected to each other. Similarly, word line WL(8) to word line WL(13) of two blocks BLK(n-1) separated by connection area 101 are connected to each other.

[0316] like Fig.33 As shown, the word line WL (14) is not provided with an upper bridge area UBBA. Therefore, a contact plug CB is provided in the step portion of the first upper connectable area UCA1, and is connected to the contact plug CB of the second upper connectable area UCA2 via an upper connection line UCL (not shown) (see Fig.26 ). Thus, the word line WL(14), the word line WL(15), and the selection gate line SGD of the two blocks BLK(n) across the connection region 101 are connected to each other. Similarly, the word line WL(14), the word line WL(15), and the selection gate line SGD of the two blocks BLK(n-1) across the connection region 101 are connected to each other.

[0317] <1-3>Effect

[0318] According to the above embodiment, a lead-out region for applying voltage to the select gate line and the word line is provided in the center of the memory cell array 10. Moreover, the lead-out region short-circuits the select gate line and the word line of two cell regions sandwiched by the lead-out region. Therefore, the select gate line and the word line of two cell regions sandwiched by the lead-out region are transmitted with voltage via the lead-out region.

[0319] In order to illustrate the effect of this embodiment, a comparative example is described. Fig.35 , a cell region in a comparative example and a portion of a lead-out region for applying a voltage to a selection gate line and a word line are shown.

[0320] For example, in the comparative example, lead-out regions are provided at both ends of the unit region in the X direction. Fig.35 The lead-out area set on the left side of the paper is recorded as the lead-out area (left), and the lead-out area set on the right side is recorded as the lead-out area (right).

[0321] In the comparative example, for example, even-numbered blocks BLK (BLK(n), BLK(n+2)...) are connected to the lead-out region (left), and odd-numbered blocks BLK (BLK(n-1), BLK(n+1)...) are connected to the lead-out region (right). In other words, the selection gate line and word line of each block BLK are supplied with voltage from the lead-out region on one side (see arrows in the figure).

[0322] In recent years, memory cell transistors have been miniaturized and increased in capacity, and memory cell transistors are required to have improved writing and reading performances. In particular, as the wiring widths of select gate lines and word lines are reduced, wiring resistance may increase.

[0323] In the case of the comparative example, the voltage is applied from one side of the selection gate line and the word line. Therefore, the voltage transmission speed may be slowed down due to the wiring resistance. As a result, the writing performance and reading performance of the memory cell transistor may be reduced.

[0324] For this purpose, it is considered to set a lead-out area in the center of the cell area. Fig.36 As shown, the unit area is divided into Fig.36 The left and right parts of the paper. In addition, a lead-out area is provided between the left unit area (left) and the right unit area (right). The lead-out area includes a lead-out area (center & left) related to the left unit area (left) and a lead-out area (center & right) related to the right unit area (right). In this case, it is necessary to Fig.37 As shown, a row decoder module (center & left) related to the unit area (left) and a row decoder module (center & right) related to the unit area (right) are prepared.

[0325] On the other hand, Fig.38 As shown in FIG. 1 , in this embodiment, a connection region 101 is provided between two cell regions 100. The connection region 101 connects the two cell regions 100, so that the same voltage can be provided to the two cell regions 100 at the same time. Fig.39 As shown, the row decoder module is shared by the two cell regions 100. Therefore, the wiring length of the selection gate line and the word line can be halved while suppressing the area of ​​the row decoder module as described in the comparative example. As a result, the increase in the resistance in the selection gate line and the word line can be suppressed while suppressing the increase in the area of ​​the row decoder module. Therefore, the voltage transmission speed becomes faster than that in the comparative example. As a result, in the semiconductor memory device of this embodiment, the writing performance and reading performance of the memory cell transistor can be improved.

[0326] <1-4> Variation 1

[0327] A modification example 1 of the first embodiment is described. As a modification example 1 of the first embodiment, Fig.40 , the connection between the sub-channel area SBA and the step area SSA is explained.

[0328] exist Fig.40 , the directions of the first contact wiring CL1, the second contact wiring CL2, the third contact wiring CL3, and the fourth contact wiring CL4 (hereinafter referred to as contact wiring CL) that connect the contact plug CC provided in the step region SSA to the contact plug C4 provided in the sub-channel region, and the position of the row decoder RD provided below the connection region in the Z direction (see the dotted line). Fig.40 , a unit region (upper left) 100-FP, a unit region (upper right) 100-GP, and a portion of a connection region (upper) 101-P are specifically shown.

[0329] In addition, the contact wiring CL related to the block BLK(v) is recorded as CL(BLK(v)). In addition, the block BLK(v) belonging to the unit area 100-FP is recorded as BLK(v)-FP. Furthermore, the block BLK(v) belonging to the unit area 100-GP is recorded as BLK(v)-GP. In addition, the contact plug C4 related to the block BLK(v) is recorded as C4(BLK(v)). In addition, the contact plug CC related to the block BLK(v) is recorded as CC(BLK(v)). In addition, the step area SSA related to the block BLK(v) is recorded as SSA(BLK(v)). In addition, the sub-channel area SBA related to the block BLK(v) is recorded as SBA(BLK(v)).

[0330] like Fig.40 As shown, the row decoder RD(BLK(n-1)) associated with the block BLK(n-1) is disposed below the step area SSA associated with the block BLK(n-1) and the sub-channel area SBA associated with the block BLK(n) in the Z direction.

[0331] As described above, the step region SSA is provided with a contact plug CC (not shown). In addition, the sub channel region SSA is provided with a contact plug C4 (not shown) that penetrates the sub channel region SSA and connects to the row decoder RD provided below the sub channel region SSA in the Z direction.

[0332] As described above, the sub-channel region SSA has two functions, namely, connecting the blocks BLK adjacent in the X direction and connecting the selection gate line SGS, word lines WL0 to WL15, and selection gate line SGD of the block BLK to the row decoder RD provided below the sub-channel region SSA.

[0333] In this variation, the sub-channel region SSA (BLK (v)) sandwiched between two blocks BLK (v) in the X direction connects two blocks BLK (v) adjacent to each other in the X direction. Furthermore, the sub-channel region SSA (BLK (v)) includes a contact plug C4 (BLK (v±1)) for connecting the selection gate line SGS, word lines WL0 to WL15, and selection gate line SGD of the block BLK (v±1) adjacent to the block BLK (v) in the Y direction to the row decoder RD (BLK (v±1)) associated with the block BLK (v±1)). The contact plug C4 (BLK (v±1)) is connected to the contact plug CC (BLK (v±1)) provided in the step region SSA (BLK (v±1)) associated with the block BLK (v±1) via the wiring CL (BLK (v±1)) extending in the Y direction. As a result, the sub-channel area SSA(BLK(v)) can connect the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of the block BLK(v±1) to the row decoder RD(BLK(v±1)) related to the block BLK(v±1).

[0334] Specifically, the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of block BLK(n-1) are connected to the row decoder RD(BLK(n-1)) related to block BLK(n-1) via the step area SSA(BLK(n-1)), the contact plug CC(BLK(n-1) set in the step area SSA(BLK(n-1)), the contact plug C4(BLK(n-1)) related to block BLK(n) that penetrates the sub-channel area SBA(BLK(n)) related to block BLK(n), and the wiring CL(BLK(n-1)) connecting the contact plug CC(BLK(n-1)) and the contact plug C4(BLK(n-1)).

[0335] In addition, the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of block BLK(n) are connected to the row decoder RD(BLK(n)) related to block BLK(n) via the step area SSA(BLK(n)), the contact plug CC(BLK(n)) arranged in the step area SSA(BLK(n)), the contact plug C4(BLK(n)) related to block BLK(n) that penetrates the sub-channel area SBA(BLK(n-1)) related to block BLK(n-1), and the wiring CL(BLK(n)) connecting the contact plug CC(BLK(n)) and the contact plug C4(BLK(n)).

[0336] Similarly, the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of block BLK(n+1) are connected to the row decoder RD(BLK(n+1)) associated with block BLK(n+1) via the step area SSA(BLK(n+1)), the contact plug CC(BLK(n+1)) arranged in the step area SSA(BLK(n+1)), the contact plug C4(BLK(n+1)) associated with block BLK(n+1) that penetrates the sub-channel area SBA(BLK(n+2)) associated with block BLK(n+2), and the wiring CL(BLK(n+1)) connecting the contact plug CC(BLK(n+1)) and the contact plug C4(BLK(n+1)).

[0337] In addition, the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of block BLK(n+2) are connected to the row decoder RD(BLK(n+2)) related to block BLK(n+2) via the step area SSA(BLK(n+2)), the contact plug CC(BLK(n+2)) set in the step area SSA(BLK(n+2)), the contact plug C4(BLK(n+2)) related to block BLK(n+2) that penetrates the sub-channel area SBA(BLK(n+1)) related to block BLK(n+1), and the wiring CL(BLK(n+2)) connecting the contact plug CC(BLK(n+2)) and the contact plug C4(BLK(n+2)).

[0338] Similarly, the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of block BLK(n+3) are connected to the row decoder RD(BLK(n+3)) associated with block BLK(n+3) via the step area SSA(BLK(n+3)), the contact plug CC(BLK(n+3)) arranged in the step area SSA(BLK(n+3)), the contact plug C4(BLK(n+3)) associated with block BLK(n+3) that penetrates the sub-channel area SBA(BLK(n+4)) associated with block BLK(n+4), and the wiring CL(BLK(n+3)) connecting the contact plug CC(BLK(n+3)) and the contact plug C4(BLK(n+3)).

[0339] In addition, the selection gate line SGS, word lines WL0~WL15, and selection gate line SGD of block BLK(n+4) are connected to the row decoder RD(BLK(n+4)) related to block BLK(n+4) via the step area SSA(BLK(n+4)), the contact plug CC(BLK(n+4)) set in the step area SSA(BLK(n+4)), the contact plug C4(BLK(n+4)) related to block BLK(n+4) that penetrates the sub-channel area SBA(BLK(n+3)) related to block BLK(n+3), and the wiring CL(BLK(n+4)) connecting the contact plug CC(BLK(n+4)) and the contact plug C4(BLK(n+4)).

[0340] <1-5> Variation 2

[0341] A second modification of the first embodiment will be described. In the second modification of the first embodiment, a different example of the connection region will be described. Fig.41 The layout of the circuit area CTA and the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment is shown. Fig.42 The layout of the circuit area CTA and the memory cell array 10 of the semiconductor memory device 1 according to the second modification of the first embodiment is shown. Fig.43 The layout of the circuit area CTA and the memory cell array 10 of the semiconductor memory device 1 according to the second modification of the first embodiment is shown.

[0342] like Fig.41 As shown, in the first embodiment, the connection region (lower & upper) 101-LP in the first lower layer LL1 includes a step region (first lower) SSA-L1 and a sub-channel region (first lower) SBA-L1. In addition, the connection region (lower & upper) 101-LP in the second lower layer LL2 includes a step region (second lower) SSA-L2 and a sub-channel region (second lower) SBA-L2.

[0343] However, it is also possible to Fig.42 As shown, the connection area (lower & upper) 101-LP in the 2nd lower layer LL2 does not include the step area (2nd lower) SSA-L2 but includes a step area with the same structure as the step area (1st lower) SSA-L1 (for convenience, recorded as SSA-L1 in the accompanying drawings).

[0344] In addition, if Fig.41As shown, in the first embodiment, the connection region (upper & upper) 101-UP in the first upper layer UL1 includes a step region (first upper) SSA-U1 and a sub-channel region (first upper) SBA-U1. In addition, the connection region (upper & upper) 101-UP in the second upper layer UL2 includes a step region (second upper) SSA-U2 and a sub-channel region (second upper) SBA-U2.

[0345] However, it is also possible to Fig.43 As shown, the connection area (upper & upper) 101-UP in the second upper layer UL2 does not include the step area (second upper) SSA-U2 but includes a step area having the same structure as the step area (first upper) SSA-U1 (for convenience, recorded as SSA-U1 in the drawings).

[0346] In addition, you can also Fig.42 The layout described in Fig.43 The layout combination described in .

[0347] <2> Second Embodiment

[0348] A second embodiment will be described. In the second embodiment, a case where the row decoder associated with the selection gate line SGD is arranged at a position different from the row decoders associated with the selection gate line SGS and the word lines WL0 to WL15 will be described.

[0349] <2-1> Layout of circuit area

[0350] The following describes the layout of the plane including the X direction and the Y direction, focusing on the circuit area CTA.

[0351] like Fig.44 As shown, Fig.19 Compared with the circuit area CTA described in the above, a row decoder module related to the selection gate line SGD is further provided at the end of the sense amplifier module 16. Hereinafter, the row decoder module 15 related to the selection gate line SGD is described as a row decoder module (SGD) 15 or the like.

[0352] Specifically, the row decoder module associated with the select gate line SGD is located at Fig.44 The left side of the sense amplifier module (upper left) 16-FP on the paper. The row decoder module is described as a row decoder module (SGD & upper left) 15-LU. In this way, the sense amplifier module (upper left) 16-FP is sandwiched between the row decoder module (upper) 15-P and the row decoder module (SGD & upper left) 15-LU in the X direction. In addition, the row decoder module (upper) 15-P includes a row decoder related to the selection gate line SGD as in the first embodiment.

[0353] In addition, the row decoder module associated with the select gate line SGD is located at Fig.44 The sense amplifier module (upper right) 16-GP is on the right side of the paper. The row decoder module is described as the row decoder module (SGD & upper right) 15-RU. In this way, the sense amplifier module (upper right) 16-GP is sandwiched between the row decoder module (upper) 15-P and the row decoder module (SGD & upper right) 15-RU in the X direction.

[0354] In addition, the row decoder module associated with the select gate line SGD is located at Fig.44 The left side of the sense amplifier module (lower left) 16-FD on the paper. The row decoder module is recorded as a row decoder module (SGD & lower left) 15-LD. In this way, the sense amplifier module (lower left) 16-FD is sandwiched between the row decoder module (lower) 15-D and the row decoder module (SGD & lower left) 15-LD in the X direction. In addition, the row decoder module (lower) 15-D includes a row decoder related to the selection gate line SGD as in the first embodiment.

[0355] In addition, the row decoder module associated with the select gate line SGD is located at Fig.44 The sense amplifier module (lower right) 16-GD is located on the right side of the paper. The row decoder module is described as the row decoder module (SGD & lower right) 15-RD. In this way, the sense amplifier module (lower right) 16-GD is sandwiched between the row decoder module (lower) 15-D and the row decoder module (SGD & lower right) 15-RD in the X direction.

[0356] In addition, the area for setting the row decoder module (SGD & upper left) 15-LU and the row decoder module (SGD & lower left) 15-LD is also recorded as the "left end". In addition, the area for setting the row decoder module (SGD & upper right) 15-RU and the row decoder module (SGD & lower right) 15-RD is also recorded as the "right end".

[0357] <2-2> Layout of memory cell array

[0358] Next, the layout of the memory cell array 10 in a plane including the X direction and the Y direction will be described with attention paid to it.

[0359] Fig.45 FIG. 2 shows an example of a planar layout of the memory cell array 10. Fig.45 For simplicity, a rough layout including a first lower layer LL1, a second lower layer LL2, a first upper layer UL1, and a second upper layer UL2 is shown.

[0360] like Fig.45 As shown, Figure 4Compared with the memory cell array 10 described in , a connection region 101 for connecting the selection gate line SGD to the row decoder module (SGD) 15 is further provided at the end of the cell region 100. Hereinafter, the connection region 101 related to the selection gate line SGD is described as the connection region (SGD) 101 or the like.

[0361] Specifically, the connection area associated with the select gate line SGD is located at Fig.45 The connection region is recorded as the connection region (SGD & upper left) 101-LU. In this way, the unit region (upper left) 100-FP is sandwiched between the connection region (upper) 101-P and the connection region (SGD & upper left) 101-LU in the X direction. In addition, the connection region (upper) 101-P includes a connection region related to the selection gate line SGD as in the first embodiment.

[0362] In addition, the connection area associated with the selection gate line SGD is located at Fig.45 The unit region (upper right) 100-GP is on the right side of the paper. The connection region is recorded as the connection region (SGD & upper right) 101-RU. In this way, the unit region (upper right) 100-GP is sandwiched between the connection region (upper) 101-P and the connection region (SGD & upper right) 101-RU in the X direction.

[0363] In addition, the connection area associated with the selection gate line SGD is located at Fig.45 The unit region (lower left) 100-FD on the paper is on the left side. The connection region is recorded as the connection region (SGD & lower left) 101-LD. In this way, the unit region (lower left) 100-FD is sandwiched between the connection region (lower) 101-D and the connection region (SGD & lower left) 101-LD in the X direction. In addition, the connection region (lower) 101-D includes a connection region related to the selection gate line SGD as in the first embodiment.

[0364] In addition, the connection area associated with the selection gate line SGD is located at Fig.45 The unit region (lower right) 100-GD is on the right side of the paper. The connection region is recorded as the connection region (SGD & lower right) 101-RD. In this way, the unit region (lower right) 100-GD is sandwiched between the connection region (lower) 101-D and the connection region (SGD & lower right) 101-RD in the X direction.

[0365] In addition, the area for setting the connection area (SGD & upper left) 101-LU and the connection area (SGD & lower left) 101-LD is also recorded as the "left end". In addition, the area for setting the connection area (SGD & upper right) 101-RU and the connection area (SGD & lower right) 101-RD is also recorded as the "right end".

[0366] The row decoder module (SGD & upper left) 15-LU is located below the connection area (SGD & upper left) 101-LU in the Z direction. The row decoder module (SGD & upper right) 15-RU is located below the connection area (SGD & upper right) 101-RU in the Z direction. The row decoder module (SGD & lower left) 15-LD is located below the connection area (SGD & lower left) 101-LD in the Z direction. The row decoder module (SGD & lower right) 15-RD is located below the connection area (SGD & lower right) 101-RD in the Z direction.

[0367] <2-3>Effect

[0368] According to the above embodiment, compared with the configuration of the first embodiment, the voltage is transmitted to the selection gate line SGD not only from the center of the memory cell array 10 but also from both ends (the left end and the right end).

[0369] Since the selection gate line SGD is divided by the slit SHE or the like, the width of the wiring may be narrowed. In this case, the resistance value of the wiring of the selection gate line SGD may be increased. Therefore, for the selection gate line SGD, if Fig.46 and Fig.47 As shown, the voltage is transmitted not only from the center but also from both ends of the memory cell array 10. Therefore, even when the resistance value of the wiring of the selection gate line SGD is increased, the effect described in the first embodiment can be obtained.

[0370] In addition, in the second embodiment, the second modification of the first embodiment can also be applied.

[0371] <3> Third Embodiment

[0372] In the third embodiment, a case is described in which the row decoder module 15 related to the lower layer LL is arranged at the center in the X direction, and the row decoder module 15 related to the upper layer UL is arranged at the left and right ends in the X direction.

[0373] <3-1> Layout of circuit area

[0374] The following describes the layout of the circuit area CTA with attention paid to a plane including the X direction and the Y direction.

[0375] like Fig.48 As shown, Fig.19 Compared with the circuit area CTA described in the above, the row decoder modules 15-P and 15-D are row decoder modules related to the lower layer LL. In addition, a row decoder module (upper) related to the upper layer UL is further provided at the end of the sense amplifier module 16.

[0376] like Fig.48 As shown, Fig.19 The row decoder module (upper) 15-P, and the row decoder module (lower) 15-D are respectively recorded as the row decoder module (lower & upper) 15-LP, and the row decoder module (lower & lower) 15-LD.

[0377] The row decoder module related to the upper layer UL is located in Fig.48 The sense amplifier module (upper left) 16-FP is on the left side of the paper. The row decoder module is described as the row decoder module (upper & upper left) 15-UFP. In this way, the sense amplifier module (upper left) 16-FP is sandwiched between the row decoder module (lower & upper) 15-LP and the row decoder module (upper & upper left) 15-UFP in the X direction.

[0378] In addition, the row decoder module related to the upper layer UL is located in Fig.48 The sense amplifier module (upper right) 16-GP is located on the right side of the paper. The row decoder module is described as the row decoder module (upper & upper right) 15-UGP. In this way, the sense amplifier module (upper right) 16-GP is sandwiched between the row decoder module (lower & upper) 15-LP and the row decoder module (upper & upper right) 15-UGP in the X direction.

[0379] In addition, the row decoder module related to the upper layer UL is located in Fig.48 The left side of the sense amplifier module (lower left) 16-FD on the paper. The row decoder module is described as the row decoder module (upper & lower left) 15-UFD. In this way, the sense amplifier module (lower left) 16-FD is sandwiched between the row decoder module (lower & lower) 15-LD and the row decoder module (upper & lower left) 15-UFD in the X direction.

[0380] In addition, the row decoder module related to the upper layer UL is located in Fig.48 The sense amplifier module (lower right) 16-GD is located on the right side of the paper. The row decoder module is described as the row decoder module (upper & lower right) 15-UGD. In this way, the sense amplifier module (lower right) 16-GD is sandwiched between the row decoder module (lower & lower) 15-LD and the row decoder module (upper & lower right) 15-UGD in the X direction.

[0381] In addition, the area where the row decoder module (upper & upper left) 15-UFP and the row decoder module (upper & lower left) 15-UFD are installed is also described as the "left end". In addition, the area where the row decoder module (upper & upper right) 15-UGP and the row decoder module (upper & lower right) 15-UGD are installed is also described as the "right end".

[0382] <3-2> Layout of memory cell array

[0383] Next, the layout of the memory cell array 10 in a plane including the X direction and the Y direction will be described with attention paid to it.

[0384] Fig.49 FIG. 2 shows an example of a planar layout of the memory cell array 10. Fig.49 , for simplicity, a schematic layout including a first lower layer LL1 , a second lower layer LL2 , a first upper layer UL1 , and a second upper layer UL2 is shown.

[0385] like Fig.49 As shown, Figure 4 Compared to the memory cell array 10 described in the above, a connection region (upper) 101 for connecting the upper layer UL and the row decoder module (upper) 15 is further provided at the end of the cell region 100 .

[0386] like Fig.49 As shown, Fig.19 The connection region (upper) 101-P and the connection region (lower) 101-D in the embodiment are recorded as the connection region (lower & upper) 101-LP and the connection region (lower & lower) 101-LD, respectively. In the present embodiment, the connection region (upper) 101-P and the connection region (lower) 101-D do not include the connection region (upper) 101.

[0387] The connection area (upper) 101 is located at Fig.49 The unit region (upper left) 100-FP on the paper is on the left side. The connection region (upper) 101 is recorded as the connection region (upper & upper left) 101-UFP. In this way, the unit region (upper left) 100-FP is sandwiched between the connection region (lower & upper) 101-LP and the connection region (upper & upper left) 101-UFP in the X direction.

[0388] In addition, the connection area (upper) 101 is located Fig.49 The unit region (upper right) 100-GP on the paper is on the right side. The connection region (upper) 101 is recorded as the connection region (upper & upper right) 101-UGP. In this way, the unit region (upper right) 100-GP is sandwiched between the connection region (lower & upper) 101-LP and the connection region (upper & upper right) 101-UGP in the X direction.

[0389] In addition, the connection area (upper) 101 is located Fig.49 The unit region (lower left) 100-FD on the paper is on the left side. The connection region (upper) 101 is recorded as the connection region (upper & lower left) 101-UFD. In this way, the unit region (lower left) 100-FD is sandwiched between the connection region (lower & lower) 101-LD and the connection region (upper & lower left) 101-UFD in the X direction.

[0390] In addition, the connection area (upper) 101 is located Fig.49 The unit region (lower right) 100-GD on the paper is on the right side. The connection region (upper) 101 is recorded as the connection region (upper & lower right) 101-UGD. In this way, the unit region (lower right) 100-GD is sandwiched between the connection region (lower & lower) 101-LD and the connection region (upper & lower right) 101-UGD in the X direction.

[0391] In addition, the area for setting the connection area (upper & upper left) 101-UFP and the connection area (upper & lower left) 101-UFD is also recorded as the "left end". In addition, the area for setting the connection area (upper & upper right) 101-UGP and the connection area (upper & lower right) 101-UGD is also recorded as the "right end".

[0392] The row decoder module (upper & upper left) 15-UFP is located below the connection area (upper & upper left) 101-UFP in the Z direction. The row decoder module (upper & upper right) 15-UGP is located below the connection area (upper & upper right) 101-UGP in the Z direction. The row decoder module (upper & lower left) 15-UFD is located below the connection area (upper & lower left) 101-UFD in the Z direction. The row decoder module (upper & lower right) 15-UGD is located below the connection area (upper & lower right) 101-UGD in the Z direction.

[0393] Here, the connection region (upper) 101 will be described.

[0394] use Fig.50 , the relationship between the connection area (upper) 101 and the XY plane of the row decoder module (upper) 15 is described. Fig.50 , a portion of the unit area (upper & upper left) 100-UFP, the connection area (upper & upper left) 101-UFP, and the row decoder module (upper & upper left) 15-UFP are specifically shown. Fig.50 In the figure, the row decoder RD included in the row decoder module (top & upper left) 15-UFP is represented by a dotted line.

[0395] For the sake of convenience, the row decoder RD associated with the block (upper & upper left) BLK(v)-UFP is recorded as RD(BLK(v)-UFP). In addition, the second contact wiring CL2 associated with the block (upper & upper left) BLK(v)-UFP is recorded as CL2(BLK(v)-UFP). The contact plug area CPA associated with the block (upper & upper left) BLK(v)-UFP is recorded as CPA(BLK(v)-UFP).

[0396] like Fig.50 As shown, the connection region (upper & upper left) 101-UFP has a group of a step region (upper) SSA-U and a contact plug region CPA for each block. Since the step region (upper) SSA-U is the same as the step region (upper) SSA-U described in the first embodiment, the description is omitted. The contact plug region CPA is a region for connecting the step region (upper) SSA-U to the row decoder RD. Specifically, in the contact plug region CPA, a contact plug C4 (not shown) is formed for connecting the row decoder DC formed below the connection region (upper & upper left) 101-UFP in the Z direction to the contact plug CC. The upper ends of the contact plug CC and the contact plug C4 are connected by the second contact wiring CL2. The second contact wiring CL2 extends in the Y direction.

[0397] In the present embodiment, the contact plug area CPA (BLK (v)) includes a contact plug C4 (BLK (v±1)-UFP) which is used to connect the word lines WL8 to WL15 of the block BLK (v±1)-UFP adjacent to the block BLK (v)-UFP in the Y direction and the selection gate line SGD to the row decoder RD (BLK (v±1)-UFP) associated with the block BLK (v±1)-UFP. The contact plug C4 (BLK (v±1)-UFP) is connected to the contact plug CC (BLK (v±1)-UFP) provided in the step area SSA (BLK (v±1)-UFP) associated with the block BLK (v±1)-UFP via the second contact wiring CL2 (BLK (v±1)-UFP) extending in the Y direction. As a result, the sub-channel area SSA(BLK(v)-UFP) can connect the word lines WL8~WL15 and the selection gate line SGD of the block BLK(v±1)-UFP to the row decoder RD(BLK(v±1)-UFP) related to the block BLK(v±1)-UFP.

[0398] Specifically, the word lines WL8~WL15 and the selection gate line SGD of the block BLK(n-1)-UFP are connected to the row decoder RD(BLK(n-1)-UFP) related to the block BLK(n-1)-UFP via the step area SSA(BLK(n-1)-UFP), the contact plug CC(BLK(n-1)-UFP) arranged in the step area SSA(BLK(n-1)-UFP), the contact plug C4(BLK(n-1)-UFP) related to the block BLK(n)-UFP that penetrates the sub-channel area SBA(BLK(n)-UFP) related to the block BLK(n)-UFP, and the second contact wiring CL2(BLK(n-1)-UFP) connecting the contact plug CC(BLK(n-1)-UFP) and the contact plug C4(BLK(n-1)-UFP).

[0399] In addition, the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(n)-UFP are connected to the row decoder RD(BLK(n)-UFP) associated with the block BLK(n)-UFP via the step area SSA(BLK(n)-UFP), the contact plug CC(BLK(n)-UFP) provided in the step area SSA(BLK(n)-UFP), the contact plug C4(BLK(n)-UFP) associated with the block BLK(n)-UFP which penetrates the sub-channel area SBA(BLK(n-1)-UFP) associated with the block BLK(n-1)-UFP, and the second contact wiring CL2(BLK(n)-UFP) connecting the contact plug CC(BLK(n)-UFP) and the contact plug C4(BLK(n)-UFP).

[0400] Similarly, the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(n+1)-UFP are connected to the row decoder RD(BLK(n+1)-UFP) associated with the block BLK(n+1)-UFP via the step area SSA(BLK(n+1)-UFP), the contact plug CC(BLK(n+1)-UFP) arranged in the step area SSA(BLK(n+1)-UFP), the contact plug C4(BLK(n+1)-UFP) associated with the block BLK(n+1)-UFP which penetrates the sub-channel area SBA(BLK(n+2)-UFP) associated with the block BLK(n+2)-UFP, and the wiring CL(BLK(n+1)-UFP) connecting the contact plug CC(BLK(n+1)-UFP) and the contact plug C4(BLK(n+1)-UFP).

[0401] In addition, the word lines WL8~WL15 and the selection gate line SGD of the block BLK(n+2)-UFP are connected to the row decoder RD(BLK(n+2)-UFP) related to the block BLK(n+2)-UFP via the step area SSA(BLK(n+2)-UFP), the contact plug CC(BLK(n+2)-UFP) arranged in the step area SSA(BLK(n+2)-UFP), the contact plug C4(BLK(n+2)-UFP) related to the block BLK(n+1)-UFP that penetrates the sub-channel area SBA(BLK(n+1)-UFP) related to the block BLK(n+1)-UFP, and the second contact wiring CL2(BLK(n+2)-UFP) connecting the contact plug CC(BLK(n+2)-UFP) and the contact plug C4(BLK(n+2)-UFP).

[0402] Similarly, the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(n+3)-UFP are connected to the row decoder RD(BLK(n+3)-UFP) associated with the block BLK(n+3)-UFP via the step area SSA(BLK(n+3)-UFP), the contact plug CC(BLK(n+3)-UFP) arranged in the step area SSA(BLK(n+3)-UFP), the contact plug C4(BLK(n+3)-UFP) associated with the block BLK(n+3)-UFP which penetrates the sub-channel area SBA(BLK(n+4)-UFP) associated with the block BLK(n+4)-UFP, and the second contact wiring CL2(BLK(n+3)-UFP) connecting the contact plug CC(BLK(n+3)-UFP) and the contact plug C4(BLK(n+3)-UFP).

[0403] In addition, the word lines WL8 to WL15 of the block BLK(n+4)-UFP and the selection gate line SGD are connected to the row decoder RD(BLK(n+4)-UFP) associated with the block BLK(n+4)-UFP via the step area SSA(BLK(n+4)-UFP), the contact plug CC(BLK(n+4)-UFP) provided in the step area SSA(BLK(n+4)-UFP), the contact plug C4(BLK(n+4)-UFP) associated with the block BLK(n+4)-UFP which penetrates the sub-channel area SBA(BLK(n+3)-UFP) associated with the block BLK(n+3)-UFP, and the second contact wiring CL2(BLK(n+4)-UFP) connecting the contact plug CC(BLK(n+4)-UFP) and the contact plug C4(BLK(n+4)-UFP). In addition, the use Fig.51, the relationship between the connection area (upper) 101 and the XY plane of the row decoder module (upper) 15 is described. Fig.51 , a portion of the unit region (upper & upper right) 100-UGP, the connection region (upper & upper right) 101-UGP, and the row decoder module (upper & upper right) 15-UGP are specifically shown. Fig.51 In the figure, the row decoder RD included in the row decoder module (top & top right) 15-UGP is represented by a dotted line.

[0404] For the sake of convenience, the row decoder RD associated with the block (upper & upper right) BLK(v)-UGP is recorded as RD(BLK(v)-UGP). In addition, the second contact wiring CL2 associated with the block (upper & upper right) BLK(v)-UGP is recorded as CL2(BLK(v)-UGP). The contact plug area CPA associated with the block (upper & upper right) BLK(v)-UGP is recorded as CPA(BLK(v)-UGP).

[0405] like Fig.51 As shown, the connection area (upper & upper right) 101-UGP has a group of a step area (upper) SSA-U and a contact plug area CPA for each block. Since the step area (upper) SSA-U is the same as the step area (upper) SSA-U described in the first embodiment, the description is omitted. The contact plug area CPA is an area for connecting the step area (upper) SSA-U to the row decoder RD. Specifically, in the contact plug area CPA, a contact plug C4 (not shown) is formed for connecting the row decoder DC formed below the connection area (upper & upper right) 101-UGP in the Z direction to the contact plug CC. The upper ends of the contact plug CC and the contact plug C4 are connected by the second contact wiring CL2. The second contact wiring CL2 extends in the Y direction.

[0406] In the present embodiment, the contact plug area CPA(BLK(v)) includes a contact plug C4(BLK(v±1)-UGP) which is used to connect the word lines WL8 to WL15 of the block BLK(v±1)-UGP adjacent to the block BLK(v)-UGP in the Y direction and the selection gate line SGD to the row decoder RD(BLK(v±1)-UGP) associated with the block BLK(v±1)-UGP. The contact plug C4(BLK(v±1)-UGP) is connected to the contact plug CC(BLK(v±1)-UGP) provided in the step area SSA(BLK(v±1)-UGP) associated with the block BLK(v±1)-UGP via the second contact wiring CL2(BLK(v±1)-UGP) extending in the Y direction. As a result, the sub-channel area SSA (BLK (v) -UGP) can connect the word lines WL8~WL15 and the selection gate line SGD of the block BLK (v±1) -UGP to the row decoder RD (BLK (v±1) -UGP) related to the block BLK (v±1) -UGP.

[0407] Specifically, the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(n-1)-UGP are connected to the row decoder RD(BLK(n-1)-UGP) associated with the block BLK(n-1)-UGP via the step area SSA(BLK(n-1)-UGP), the contact plug CC(BLK(n-1)-UGP) provided in the step area SSA(BLK(n-1)-UGP), the contact plug C4(BLK(n-1)-UGP) associated with the block BLK(n-1)-UGP which penetrates the sub-channel area SBA(BLK(n)-UGP) associated with the block BLK(n)-UGP, and the second contact wiring CL2(BLK(n-1)-UGP) connecting the contact plug CC(BLK(n-1)-UGP) and the contact plug C4(BLK(n-1)-UGP).

[0408] In addition, the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(n)-UGP are connected to the row decoder RD(BLK(n)-UGP) associated with the block BLK(n)-UGP via the step area SSA(BLK(n)-UGP), the contact plug CC(BLK(n)-UGP) provided in the step area SSA(BLK(n)-UGP), the contact plug C4(BLK(n)-UGP) associated with the block BLK(n)-UGP which penetrates the sub-channel area SBA(BLK(n-1)-UGP) associated with the block BLK(n-1)-UGP, and the second contact wiring CL2(BLK(n)-UGP) connecting the contact plug CC(BLK(n)-UGP) and the contact plug C4(BLK(n)-UGP).

[0409] Similarly, the word lines WL8 to WL15 and the selection gate line SGD of the block BLK(n+1)-UGP are connected to the row decoder RD(BLK(n+1)-UGP) associated with the block BLK(n+1)-UGP via the step area SSA(BLK(n+1)-UGP), the contact plug CC(BLK(n+1)-UGP) arranged in the step area SSA(BLK(n+1)-UGP), the contact plug C4(BLK(n+1)-UGP) associated with the block BLK(n+1)-UGP which penetrates the sub-channel area SBA(BLK(n+2)-UGP) associated with the block BLK(n+2)-UGP, and the wiring CL(BLK(n+1)-UGP) connecting the contact plug CC(BLK(n+1)-UGP) and the contact plug C4(BLK(n+1)-UGP).

[0410] In addition, the word lines WL8~WL15 and the selection gate line SGD of the block BLK(n+2)-UGP are connected to the row decoder RD(BLK(n+2)-UGP) related to the block BLK(n+2)-UGP via the step area SSA(BLK(n+2)-UGP), the contact plug CC(BLK(n+2)-UGP) arranged in the step area SSA(BLK(n+2)-UGP), the contact plug C4(BLK(n+2)-UGP) related to the block BLK(n+1)-UGP that penetrates the sub-channel area SBA(BLK(n+1)-UGP) related to the block BLK(n+1)-UGP, and the second contact wiring CL2(BLK(n+2)-UGP) connecting the contact plug CC(BLK(n+2)-UGP) and the contact plug C4(BLK(n+2)-UGP).

[0411] Similarly, the word lines WL8~WL15 and the selection gate line SGD of the block BLK(n+3)-UGP are connected to the row decoder RD(BLK(n+3)-UGP) associated with the block BLK(n+3)-UGP via the step area SSA(BLK(n+3)-UGP), the contact plug CC(BLK(n+3)-UGP) arranged in the step area SSA(BLK(n+3)-UGP), the contact plug C4(BLK(n+3)-UGP) associated with the block BLK(n+3)-UGP which penetrates the sub-channel area SBA(BLK(n+4)-UGP) associated with the block BLK(n+4)-UGP, and the second contact wiring CL2(BLK(n+3)-UGP) connecting the contact plug CC(BLK(n+3)-UGP) and the contact plug C4(BLK(n+3)-UGP).

[0412] In addition, the word lines WL8~WL15 and the selection gate line SGD of the block BLK(n+4)-UGP are connected to the row decoder RD(BLK(n+4)-UGP) related to the block BLK(n+4)-UGP via the step area SSA(BLK(n+4)-UGP), the contact plug CC(BLK(n+4)-UGP) arranged in the step area SSA(BLK(n+4)-UGP), the contact plug C4(BLK(n+4)-UGP) related to the block BLK(n+4)-UGP that penetrates the sub-channel area SBA(BLK(n+3)-UGP) related to the block BLK(n+3)-UGP, and the second contact wiring CL2(BLK(n+4)-UGP) connecting the contact plug CC(BLK(n+4)-UGP) and the contact plug C4(BLK(n+4)-UGP).

[0413] <3-3> Circuit area and memory cell array layout

[0414] Next, use Fig.52 , the layout of the semiconductor memory device 1 observed from a cross section parallel to the XZ plane will be described.

[0415] exist Fig.52 , a cross-sectional view of the circuit area CTA and the memory cell array 10 is shown. Fig.52 , a row decoder module (upper & upper left) 15-UFP, a row decoder module (upper & upper right) 15-UGP, a row decoder module (lower & upper) 15-LP, a sense amplifier module (upper left) 16-FP, and a sense amplifier module (upper right) 16-GP are shown as a circuit area CTA. In addition, Fig.52, a cell region (lower & upper left) 100-LFP, a cell region (lower & upper right) 100-LGP, and a connection region (lower & upper) 101-LP are shown as the lower layer LL of the memory cell array 10. Fig.52 , a unit region (upper & upper left) 100-UFP, a unit region (upper & upper right) 100-UGP, a connection region (upper & upper left) 101-UFP, and a connection region (upper & upper right) 101-UGP are shown as the upper layer UL of the memory cell array 10.

[0416] like Fig.52 As shown, a unit region (lower & upper left) 100-LFP and a unit region (upper & upper left) 100-UFP are provided above the sense amplifier module (upper left) 16-FP in the Z direction. The sense amplifier module (upper left) 16-FP is connected to the unit region (lower & upper left) 100-LFP and the unit region (upper & upper left) 100-UFP by wiring not shown.

[0417] Furthermore, a connection region (lower & upper) 101-LP is provided above the row decoder module (lower & upper) 15-LP in the Z direction. The row decoder module (lower & upper) 15-LP and the connection region (lower & upper) 101-LP are connected by wiring (not shown).

[0418] Furthermore, a connection region (upper & upper left) 101-UFP is provided above the row decoder module (upper & upper left) 15-UFP in the Z direction. The row decoder module (upper & upper left) 15-UFP and the connection region (upper & upper left) 101-UFP are connected by wiring (not shown).

[0419] Furthermore, a connection area (upper & upper right) 101-UGP is provided above the row decoder module (upper & upper right) 15-UGP in the Z direction. The row decoder module (upper & upper right) 15-UGP and the connection area (upper & upper right) 101-UGP are connected by wiring (not shown).

[0420] That is to say, Fig.52 As shown, the cell region (lower & upper left) 100-LFP and the cell region (lower & upper right) 100-LGP receive voltages from the row decoder module (lower & upper) 15-LP via the connection region (lower & upper) 101-LP.

[0421] In addition, the unit region (upper & upper left) 100 -UFP receives a voltage from the row decoder module (upper & upper left) 15 -UFP via the connection region (upper & upper left) 101 -UFP.

[0422] In addition, the unit region (upper & upper right) 100 -UGP receives a voltage from the row decoder module (upper & upper right) 15 -UGP via the connection region (upper & upper right) 101 -UGP.

[0423] In addition, if Fig.53 As shown, in the third embodiment, the connection region (lower & upper) 101-LP in the first lower layer LL1 includes a step region (first lower) SSA-L1 and a sub-channel region (first lower) SBA-L1. In addition, the connection region (lower & upper) 101-LP in the second lower layer LL2 includes a step region (second lower) SSA-L2 and a sub-channel region (second lower) SBA-L2.

[0424] However, it is also possible to Fig.54 As shown, the connection area (lower & upper) 101-LP in the 2nd lower layer LL2 does not include the step area (2nd lower) SSA-L2 but includes a step area with the same structure as the step area (1st lower) SSA-L1 (for convenience, recorded as SSA-L1 in the accompanying drawings).

[0425] In addition, you can Fig.55 As shown, the connection area (lower & upper) 101-LP in the 1st lower layer LL1 does not include the step area (1st lower) SSA-L1 but includes a step area with the same structure as the step area (2nd lower) SSA-L2 (for convenience, recorded as SSA-L2 in the accompanying drawings).

[0426] <4> Fourth embodiment

[0427] A fourth embodiment will be described. In the fourth embodiment, another structure of the step region will be described.

[0428] <4-1>Overview

[0429] In the above embodiments, Fig.56 As shown in FIG. 1 , the step region SSA is provided with steps (descending steps) descending in the Z direction toward the selection gate line SGD, the word lines WL15 to WL0, and the selection gate line SGS. However, in the above-mentioned embodiments, Fig.57 As shown, in the step area SSA, there are provided steps (descending steps) that descend in the Z direction toward the selection gate line SGD, the word lines WL15 to WL0, and the selection gate line SGS, and steps (ascending steps) that rise upward in the Z direction. The ascending steps may be dummy steps without contact plugs, or may be provided with contact plugs.

[0430] Here, the so-called descending step refers to a step in the direction from the cell region 100 to the direction where the sub-channel region SBA is provided, toward the direction where the semiconductor substrate is provided. In addition, the so-called ascending step refers to a step in the direction from the cell region 100 to the direction where the sub-channel region SBA is provided, toward the direction opposite to the direction where the semiconductor substrate is provided.

[0431] <4-2>Concrete examples

[0432] Hereinafter, a specific example of the step area SSA according to the present embodiment will be described.

[0433] Fig.58 1 is an example of a detailed planar layout of the step region SSA of the semiconductor memory device 1 according to the fourth embodiment, and two step regions SSA adjacent to each other in the Y direction are selected and shown. More specifically, Fig.58 Shown in the Figure 8 or Fig.11 The step area between the block BLK(n) and the block BLK(n-1) represented in FIG.

[0434] Fig.59 It is along Fig.58 The cross-sectional view taken along the line NN shows an example of the cross-sectional structure of the step region.

[0435] like Fig.58 ,and Fig.59 As shown, the step region (lower) SSA-L and the step region (upper) SSA-U are descending steps. Moreover, a dummy step region DBCA is provided between the step region (lower) SSA-L and the step region (upper) SSA-U. The dummy step region DBCA is an ascending step.

[0436] The dummy step area DBCA is disposed between the step area (lower) SSA-L and the step area (upper) SSA-U, but may be disposed at any position. For example, the dummy step area DBCA is included in the step area (lower) SSA-L or the step area (upper) SSA-U. In addition, the dummy step area DBCA may be connected to the lower bridge area LBBA or the upper bridge area UBBA adjacent in the Y direction. In this case, the dummy step area DBCA may be connected to each block via the lower bridge area LBBA or the upper bridge area UBBA. Therefore, a contact plug may also be disposed in the dummy step area DBCA.

[0437] In addition, the number of steps of the dummy step area DBCA can be changed as appropriate. In addition, the number of the dummy step areas DBCA can be changed as appropriate.

[0438] <5>Other changes, etc.

[0439] In the above embodiment, the case where the structure between two adjacent slits SLT corresponds to one string assembly SU is exemplified, but the present invention is not limited thereto. For example, a plurality of string assemblies SU may be formed between two adjacent slits SLT by providing a slit that divides the selection gate line SGD between the two adjacent slits SLT. The number of string assemblies SU between the adjacent slits SLT varies based on the number of slits that divide the selection gate line SGD.

[0440] In the above-mentioned embodiments, the storage column MP, and the contact plugs CP, CV, V0, V1, and V2 may have a conical shape or an inverted conical shape, or may have a shape with a convex middle portion. Similarly, the slit SLT may have a conical shape or an inverted conical shape, or may have a shape with a convex middle portion. In addition, although the case where the cross-sectional structure of the storage column MP or the transistor TR is circular is illustrated, their cross-sectional structures may also be elliptical and may be designed into any shape.

[0441] In the above embodiment, the case where the stacked wiring such as the word line WL forms a step structure with a step difference in the X direction in the connection area is exemplified, but the present invention is not limited to this. For example, the ends of the stacked word line WL and the selection gate lines SGD and SGS may also form a step difference in the Y direction. The ends of the stacked word line WL and the selection gate lines SGD and SGS in the connection area may be designed to have a step shape with any number of columns. The formed step structure may also be different between the selection gate line SGS, the word line WL, and the selection gate line SGD.

[0442] In this specification, "connection" means electrical connection, and does not exclude the case where other elements are interposed therebetween. "Electrical connection" may be interposed with an insulator as long as it can operate in the same manner as electrical connection. "Columnar" means a structure disposed in a hole formed in the manufacturing step of the semiconductor memory device 1.

[0443] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and the scope of their equivalents.

[0444] [Explanation of Symbols]

[0445] 1 Semiconductor storage device

[0446] 2 Memory Controller

[0447] 10 Memory Cell Array

[0448] 10-UGD (lower right)

[0449] 11 Command Register

[0450] 12 Address register

[0451] 13 Sequencer

[0452] 14 Driver module

[0453] 15-line decoder module

[0454] 16 Sense Amplifier Module

[0455] 17 Peripheral Circuit

[0456] 18 Peripheral Circuit

[0457] 20 Semiconductor substrate

[0458] 21~25 Conductor layer

[0459] 30 core components

[0460] 31 Semiconductor layer

[0461] 32 Laminated Film

[0462] 33 Tunnel insulation film

[0463] 34 Insulation film

[0464] 35 Barrier insulation film

[0465] 40~43 Insulation layer

[0466] 100 unit area

[0467] 101 Connection Area

Claims

1. A semiconductor storage device comprising: The first cell region comprises a plurality of first conductive layers stacked at intervals along a first direction, and a first semiconductor layer extending in the first direction within the plurality of first conductive layers, wherein intersections of the plurality of first conductive layers and the first semiconductor layer constitute memory cells respectively; a second cell region including a plurality of second conductive layers stacked at intervals along the first direction and a second semiconductor layer extending in the first direction within the plurality of second conductive layers, wherein intersections of the plurality of second conductive layers and the second semiconductor layer constitute memory cells; and The first connection region is arranged between the first unit region and the second unit region in a second direction intersecting the first direction, and has a first bridge region and a first step region, wherein in the first bridge region, a plurality of third conductor layers stacked at intervals along the first direction respectively electrically connect one of the plurality of first conductor layers and one of the plurality of second conductor layers, and in the first step region, the plurality of third conductor layers respectively have steps for setting a first contact plug.

2. The semiconductor memory device according to claim 1, wherein The first stepped region is connected to the first bridge region in a third direction intersecting the first direction and the second direction.

3. The semiconductor memory device according to claim 2, wherein The first connection region further includes a first sub-channel region adjacent to the first bridge region and the first step region in the second direction, and provided with a second contact plug extending in the first direction within the plurality of third conductive layers.

4. The semiconductor memory device according to claim 3, wherein In the first sub-channel region, each of the plurality of third conductive layers electrically connects one of the plurality of first conductive layers and one of the plurality of second conductive layers.

5. The semiconductor memory device according to claim 4, comprising: The first slit is adjacent to the first unit region, the first connection region, and the second unit region in the third direction; a third unit region, adjacent to the first unit region in the third direction with the first slit interposed therebetween, and comprising a plurality of fourth conductive layers stacked at intervals along the first direction, and a third semiconductor layer extending in the first direction within the plurality of fourth conductive layers, wherein intersections of the plurality of fourth conductive layers and the third semiconductor layer constitute memory cells; a fourth unit region adjacent to the second unit region in the third direction with the first slit interposed therebetween, and comprising a plurality of fifth conductive layers stacked at intervals along the first direction, and a fourth semiconductor layer extending in the first direction within the plurality of fifth conductive layers, wherein intersections of the plurality of fifth conductive layers and the fourth semiconductor layer constitute memory cells; and The second connection region is arranged between the third unit region and the fourth unit region in the second direction, and comprises a second bridge region, a second step region and a second sub-channel region, wherein in the second bridge region, a plurality of sixth conductor layers stacked at intervals along the first direction respectively electrically connect one of the plurality of fourth conductor layers and one of the plurality of fifth conductor layers, and in the second step region, the plurality of sixth conductor layers respectively comprise steps for setting a third contact plug, and the second step region is connected to the second bridge region in the third direction, and the second sub-channel region is adjacent to the second bridge region and the second step region in the second direction, and a fourth contact plug extending in the first direction is set in the plurality of sixth conductor layers.

6. The semiconductor memory device according to claim 5, wherein The first bridge region and the first step region are adjacent to the second sub-channel region via the first slit in the third direction, and The second bridge region and the second step region are adjacent to the first sub-channel region via the first slit in the third direction.

7. The semiconductor memory device according to claim 6, wherein A first row decoder associated with the first unit area and the second unit area is provided below the first bridge area, the first step area, and the second sub-channel area in the first direction. The first cell region and the second cell region are connected to the first row decoder via the fourth contact plug, the first contact plug, the first step region, and the first bridge region. A second row decoder associated with the third unit area and the fourth unit area is provided below the second bridge area, the second step area, and the first sub-channel area in the first direction, and The third cell region and the fourth cell region are connected to the second row decoder via the third contact plug, the second contact plug, the second step region, and the second bridge region.

8. The semiconductor memory device according to claim 7, further comprising: a first wiring connecting the fourth contact plug and the first contact plug; and The second wiring connects the third contact plug and the second contact plug.

9. The semiconductor memory device according to any one of claims 1 to 8, wherein The first to third conductor layers are the same conductor layer.

10. The semiconductor memory device according to any one of claims 1 to 8, wherein The first to third conductive layers are word lines or selection gate lines.

11. The semiconductor memory device according to any one of claims 5 to 8, wherein The fourth to sixth conductive layers are the same conductive layer.

12. The semiconductor memory device according to any one of claims 5 to 8, wherein The fourth to sixth conductive layers are word lines or selection gate lines.

13. The semiconductor memory device according to any one of claims 5 to 8, further comprising: a third step region, in which the first cell region is sandwiched from the first connection region in the second direction and each of the plurality of seventh conductive layers stacked at intervals from each other along the first direction has a step for providing a fifth contact plug; a third connection region including a first contact region adjacent to the third step region in the second direction and provided with a sixth contact plug extending in the first direction within the plurality of seventh conductive layers; a fourth step region, wherein each of the plurality of eighth conductive layers stacked at intervals from the second connection region in the second direction across the third cell region and along the first direction comprises a step for providing a seventh contact plug; and The fourth connection region includes a second contact region adjacent to the fourth step region in the second direction and provided with an eighth contact plug extending in the first direction within the plurality of eighth conductive layers.

14. The semiconductor memory device according to claim 13, wherein the third step region is adjacent to the second contact region in the third direction with the first slit interposed therebetween, and The fourth stepped region is adjacent to the first contact region in the third direction with the first slit interposed therebetween.

15. The semiconductor memory device according to claim 14, wherein A third row decoder associated with the first cell region is provided below the third step region and the second contact region in the first direction. The first cell region is connected to the third row decoder via the fifth contact plug, the eighth contact plug, and the third step region. A fourth row decoder associated with the third cell region is disposed below the fourth step region and the first contact region in the first direction, and The third cell region is connected to the fourth row decoder via the sixth contact plug, the seventh contact plug, and the fourth stepped region.

16. The semiconductor memory device according to claim 15, further comprising: a third wiring connecting the fifth contact plug and the eighth contact plug; and The fourth wiring connects the sixth contact plug and the seventh contact plug.

17. The semiconductor memory device according to claim 13, wherein The first to third and seventh conductive layers are the same conductive layer.

18. The semiconductor memory device according to claim 13, wherein The first to third and seventh conductive layers are word lines or selection gate lines.

19. The semiconductor memory device according to claim 13, wherein The fourth to sixth and eighth conductive layers are the same conductive layer.

20. A semiconductor storage device comprising: A first cell region includes a plurality of first conductive layers stacked in a first direction, and a plurality of memory cells, wherein the plurality of memory cells extend in the first direction within the plurality of first conductive layers and include a first semiconductor layer, and intersections of the plurality of first conductive layers and the first semiconductor layer constitute memory cells respectively; a second cell region, which is a region arranged in a second direction intersecting the first direction of the first cell region, and includes a plurality of second conductive layers stacked in the first direction, and a plurality of memory cells, the plurality of memory cells extending in the first direction within the plurality of second conductive layers, including a second semiconductor layer, and intersections of the plurality of first conductive layers and the second semiconductor layer respectively constituting memory cells; a connection region disposed between the first unit region and the second unit region and sandwiched between a plurality of third conductive layers stacked in the first direction and electrically connecting one of the plurality of first conductive layers to one of the plurality of second conductive layers, and a first contact plug electrically insulated from the plurality of third conductive layers and extending in the first direction; as well as The row decoder is disposed below the connection region and transmits a voltage to the word lines of the first and second cell regions via the connection region electrically connected to the first contact plug of the connection region.

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