Power mode transition management for cascaded power supplies

Abstract

The present disclosure relates to power mode transition management for cascaded power supplies. A cascaded power system is disclosed, including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled, and otherwise discharges the core voltage. The comparator circuitry monitors voltage levels of the supply voltage and the core voltage, and the control circuitry performs a handshake with the slave circuitry based in part on the voltages to ensure a smooth transition between the normal mode and the low power mode. The control circuitry asserts a low power good signal when the supply voltage and the core voltage are discharged, and de-asserts the low power good signal when the supply voltage and the core voltage are fully charged. A processor can rely on the low power mode signal for transitioning between power modes.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to power mode management, and more specifically to a system and method of ensuring that power mode transitions occur in a robust, safe, and reliable manner to reduce the likelihood of cascading power supply failures. BACKGROUND

[0002] For certain applications, such as automotive applications or industrial applications, among others, safety is a concern. Semiconductor devices or integrated circuits (ICs) configured for such applications can be implemented with a large amount of computing capability. Processing systems, including microprocessors, microcontrollers, system-on-chips, or any other processing configuration, for example, can be used to process any type of data or information to control certain parameters, functions, or operations associated with a particular application. Automotive applications can include, for example, gateways (e.g., in-vehicle networking and telematics), adaptive driver assistance systems (ADAS), infotainment (audio and / or video entertainment, information, navigation, hands-free control, etc.), clusters (digital instrument clusters, head-up displays, etc.), vehicle-to-everything (V2X) (e.g., vehicle-to-vehicle and external entity communication, traffic sign recognition, etc.), radar, vision (e.g., cameras, proximity sensors, collision avoidance, blind spot monitoring, etc.). Industrial applications can include, for example, industrial tablets or laptops, among others, Internet protocol television (IPTV), industrial control, medical monitoring, home automation and / or alarm systems, etc.

[0003] Processing systems can consume a large amount of power or can require a large number of different supply voltages, such that a single power management IC (PMIC) can not be sufficient to supply the necessary power levels or the necessary amount of different supply voltages to processing devices, memory devices, communication devices, etc. Cascaded power supply schemes can be used to meet the necessary power requirements, which can include a master PMIC and one or more slave PMICs. Processing systems can have a low power mode (e.g., reduced power mode, sleep mode, standby mode, etc.) to minimize power consumption during periods of low activity or inactivity in which all but a minimal amount of circuitry or logic is powered down. Cascaded PMIC schemes can be used to provide supply voltages and core voltages to processing systems and can further be used to control power modes, including transitioning between normal mode and low power mode. In such configurations, any erroneous communication between the master PMIC and the slave PMIC can cause power to be removed at an incorrect time, resulting in the unintended power down of the main processing device and any corresponding peripherals. For applications in which safety is a concern, including safety-critical applications, the consequences of unintended power down can be inconvenient, and even dangerous in situations where the system is unable to transition to a safe state. SUMMARY

[0004] Aspects of the disclosure are defined in the appended claims.

[0005] In a first aspect, a cascaded power supply is provided, including master power management circuitry and slave power management circuitry. The master power management circuitry includes a master power regulator that provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode, comparator circuitry that monitors voltage levels of the supply voltage and a core voltage and provides at least one state signal indicative of the voltage levels, and control circuitry that deactivates a slave enable signal and commands the master power regulator to discharge the supply voltage when a low power mode signal is activated for transitioning from the normal mode to the low power mode, and activates a low power good signal when the at least one state signal indicates that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold. The slave power management circuitry provides the core voltage when the slave enable signal is activated for the normal mode, and discharges the core voltage when the slave enable signal is deactivated for the low power mode.

[0006] In one or more embodiments, the control circuitry can command the master power regulator to charge the supply voltage when the low power mode signal is deactivated, can activate the slave enable signal when the supply voltage is at least a first high threshold, and can deactivate the low power good signal to enter the normal mode when the slave enable signal is activated and the synchronization signal is activated; and the slave power management circuitry can activate the synchronization signal when the core voltage reaches a regulated level.

[0007] In one or more embodiments, the control circuitry can deactivate the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0008] In one or more embodiments, the control circuitry can command the master power regulator to charge the supply voltage when the low power mode signal is deactivated, can activate the slave enable signal when the supply voltage is at least a first high threshold, and can deactivate the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0009] In one or more embodiments, the master power management circuitry can be implemented on a first semiconductor device, and the slave power management circuitry can be implemented on a second semiconductor device.

[0010] In one or more embodiments, the cascaded power supply can further include a processor that provides the low power mode signal and receives the low power good signal.

[0011] In one or more embodiments, the processor transitions from the normal mode to the low power mode only when the low power good signal is asserted and transitions from the low power mode to the normal mode only when the low power good signal is de-asserted.

[0012] In one or more embodiments, the master power management circuitry can be implemented on a first semiconductor device, the slave power management circuitry can be implemented on a second semiconductor device, and the processor can be implemented on a third semiconductor device.

[0013] In a second aspect, a method is provided, comprising: providing master power management circuitry and providing slave power management circuitry. Providing the master power management circuitry includes providing a supply voltage during a normal mode and discharging the supply voltage during a low power mode, monitoring voltage levels of the supply voltage and a core voltage and providing at least one status signal indicative of the voltage levels, and de-asserting a slave enable signal and commanding the master power regulator to discharge the supply voltage when a low power mode signal is asserted for transitioning from the normal mode to the low power mode, and asserting a low power good signal when the at least one status signal indicates that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold. Providing the slave power management circuitry includes providing the core voltage when the slave enable signal is asserted for the normal mode, and otherwise discharging the core voltage for the low power mode.

[0014] In one or more embodiments, the method can further include commanding the master power regulator to charge the supply voltage when the low power mode signal is de-asserted, asserting the slave enable signal when the supply voltage is at least a first high threshold, asserting a synchronization signal when the core voltage reaches a regulated level, and de-asserting the low power good signal to enter the normal mode when the synchronization signal is asserted after the slave enable signal is asserted.

[0015] In one or more embodiments, the method can further include de-asserting the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0016] In one or more embodiments, the method can further include commanding the master power regulator to charge the supply voltage when the low power mode signal is de-asserted, asserting the slave enable signal when the supply voltage is at least a first high threshold, and de-asserting the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0017] In one or more embodiments, providing the master power management circuitry can include providing the master power management circuitry on a first semiconductor device, and providing the slave power management circuitry can include providing the slave power management circuitry on a second semiconductor device.

[0018] In one or more embodiments, the method can further include providing a processor that provides the low-power mode signal and receives the low-power good signal.

[0019] In one or more embodiments, the method can further include transitioning by the processor from the normal mode to the low-power mode only when the low-power good signal is asserted and from the low-power mode to the normal mode only when the low-power good signal is de-asserted.

[0020] In one or more embodiments, providing the master power management circuitry can include providing the master power management circuitry on a first semiconductor device, providing the slave power management circuitry can include providing the slave power management circuitry on a second semiconductor device, and providing the processor can include providing the processor on a third semiconductor device.

[0021] In a third aspect, a processing system is provided, including: a cascaded power management system and a processor. The cascaded power management system includes: master power management circuitry and slave power management circuitry. The master power management circuitry includes: a master power regulator that provides a supply voltage during a normal mode and discharges the supply voltage during a low-power mode; comparator circuitry that monitors voltage levels of the supply voltage and a core voltage and provides at least one state signal indicative of the voltage levels; and control circuitry that de-asserts a slave enable signal and commands the master power regulator to discharge the supply voltage when a low-power mode signal is asserted for transitioning from the normal mode to the low-power mode, and asserts a low-power good signal when the at least one state signal indicates that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold. The slave power management circuitry provides the core voltage when the slave enable signal is asserted for the normal mode, and discharges the core voltage when the slave enable signal is de-asserted for the low-power mode. The processor includes: power supply circuitry that receives the supply voltage and the core voltage; and low-power domain circuitry that provides the low-power mode signal and receives the low-power good signal, wherein the processor transitions from the normal mode to the low-power mode only when the low-power good signal is asserted, and transitions from the low-power mode to the normal mode only when the low-power good signal is de-asserted.

[0022] In one or more embodiments, the control circuitry can command the master power regulator to charge the supply voltage when deasserting the low power mode signal, can assert the slave enable signal when the supply voltage is at least a first high threshold, and can deassert the low power good signal to enter the normal mode when asserting the synchronization signal after asserting the slave enable signal; and the slave power management circuitry can assert the synchronization signal when the core voltage reaches the regulation level.

[0023] In one or more embodiments, the control circuitry can deassert the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0024] In one or more embodiments, the control circuitry can command the master power regulator to charge the supply voltage when deasserting the low power mode signal, can assert the slave enable signal when the supply voltage is at least a first high threshold, and can deassert the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold. BRIEF DESCRIPTION OF DRAWINGS

[0025] Embodiments of the application are illustrated by way of example, and not by way of limitation, in the figures of the drawing. Like reference numbers in different figures can indicate like elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0026] Figure 1 is a simplified block diagram of a processing system implemented in accordance with one embodiment of the present disclosure.

[0027] Figure 2 is a simplified block diagram of a processing system implemented in accordance with one embodiment of the present disclosure. Figure 1 is a more detailed block diagram of a cascaded PMIC system for processor interfacing to control power mode transitions of

[0028] Figure 3 is a state diagram illustrating operation of a cascaded PMIC system of Figure 1 including a master PMIC and a slave PMIC in accordance with one embodiment of the present disclosure. Figure 2 DETAILED DESCRIPTION

[0029] ​The inventors have recognized that it is advantageous to provide a robust and safe method to transition between a normal mode of operation and one or more low power modes of operation between two or more power management ICs (PMICs). The normal mode means that the system is fully powered to perform the functions and operations for which the system is designed. The one or more low power modes include any reduced power mode (e.g., reduced power mode, sleep mode, standby mode, etc.) that reduces quiescent current in order to reduce overall power consumption. The system and method of power mode management as described herein provides dedicated interaction between a master PMIC and at least one slave PMIC to ensure that low power mode transitions occur in a safe and robust manner. This eliminates the possibility of a serious malfunction.

[0030] Figure 1 is a simplified block diagram of a processing system 102 implemented in accordance with one embodiment of the present disclosure. The processing system 102 can be implemented in discrete fashion or can be integrated onto a single module such as a system on a chip (SoC) or the like. The processing system 102 includes a cascaded power management IC (PMIC) system 104 that provides power to a processor (PROC) 106, a peripheral system 108, and a memory and storage system 110. The cascaded PMIC system 104 cooperates with the processor 106 to ensure that power mode transitions of the processing system 102, including transitions of the processor 106 and any other devices, occur in a robust and safe manner to reduce the likelihood of a malfunction, as further described herein. The processor 106 can include any type of processing device or the like, such as a programmable integrated circuit, microprocessor, microcontroller or MCU, central processing unit (CPU), application processor, or the like, and can include multiple processing devices. The memory and storage system 110 can include one or more or any combination of any type of memory or storage device, including, for example, random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), low power double data rate (DDR) (LPDDR4), non-volatile memory such as serial peripheral interface (SPI) flash memory 190, NVRAM, flash memory, solid state drive (SSD), hard disk drive, optical drive, or any other suitable form of internal or external storage. The memory and storage can be consolidated on the processing system 102, or, alternatively, the memory and storage system 110 can be configured as an interface to interface with external memory or drives or the like.

[0031] The processing system 102 can be used to implement or be part of automotive applications or industrial applications, etc., where security and robustness are of concern. The peripheral system 108 can be used to interface sensors, communication devices, detectors, display devices, keyboards, controllers, mice, etc., to enable the processor 106 to process any type of data or information to control certain parameters, functions, or operations associated with a particular application. In many such applications, the processing system 102 includes a low power mode to reduce power consumption, where only a minimal amount of logic and circuitry is kept supplied with power sufficient to reawaken the processing system 102 to resume normal operation. The cascaded PMIC system 104 converts a source voltage (Vsrc) to one or more supply voltages (Vsup) provided to the processor 106, the peripheral system 108, the memory and storage system 110 (and any other devices or peripherals), and further facilitates transitioning the processing system 102 and the processor 106 between its normal mode and low power mode, as described further herein. The Vsrc can be sourced from an external power source (not shown), such as an external battery (e.g., a car battery) or an AC source, etc., or can be provided by a power converter (not shown) of the processing system 102. The cascaded PMIC system 104 also has a low power mode that it maintains at an extremely low, but sufficient, level of operation to detect a request to reawaken the system. The request to reawaken the system can come from any of a number of sources, such as the processor 106 or the peripheral system 108.

[0032] Figure 2 is a more detailed block diagram of the cascaded PMIC system 104 interfacing with the processor 106 for controlling power mode transitions according to one embodiment of the present disclosure. Although not specifically shown or described herein, the cascaded PMIC system 104 can also control power mode transitions of the peripheral system 108 as well as the memory and storage system 110. The cascaded PMIC system 104 includes a master PMIC 202 and a slave PMIC 204. Although only one slave PMIC 204 is shown, additional slave PMICs (not shown) can be included (e.g., for any additional processors or high power circuitry, etc.). The master PMIC 202 includes power regulator circuitry 206 that converts the Vsrc voltage to one or more supply voltages, generally shown as Vsup. Depending on the configuration of the slave PMIC 204 and the processor 106, the Vsup can be a single supply voltage or can include multiple voltages.

[0033] VSUP includes at least one switchable supply voltage, shown as VSUP S, having a voltage level that depends on a command signal VSON, as further described herein. VSUP can also include a non-switchable supply voltage VSUP NS. VSUP S is provided to a voltage supply (VS) input of slave PMIC 204 and to an input of processor supply circuitry 208 of processor 106. VSUP NS is provided to an input of low power domain 216 of processor 106 and possibly to other peripherals that can remain powered in low power mode. When VSON is deasserted to low (e.g., VSON = 0), power regulator circuitry 206 discharges VSUP S while VSUP NS remains charged so that low power domain 216 remains powered during low power mode. It is noted that VSUP can include one or more switchable supply voltages and one or more non-switchable supply voltages. In addition, whether a supply voltage is switched can be configured based on register settings, etc. Slave PMIC 204 includes core supply circuitry 210 that converts VSUP to a core voltage VCOR that is provided to a CORE voltage input of processor supply 208. VCOR is also provided to a voltage monitor (VMON) input of master PMIC 202. In an alternative embodiment, slave PMIC 204 can receive VSRC separately and convert VSRC to VCOR.

[0034] Master PMIC 202 includes comparator circuitry 212 that monitors voltage levels of VSUP S and VCOR (via VMON), and control circuitry 214 that manages transitions between normal and low power modes of operation, as further described herein. Master PMIC 202 has a slave enable output S EN that is provided to an enable input EN of slave PMIC 204. Slave PMIC 204 has a power good output PGOOD that is provided to a power synchronization input PSYNC of master PMIC 202. Processor 106 includes a low power domain 216 that remains powered during low power mode. Low power domain 216 provides a low power mode signal LPM to an LPM input of master PMIC 202, and master PMIC 202 has a low power good output LPGOOD that provides an LPGOOD signal to an input of low power domain 216 of processor 106.

[0035] Comparator circuitry 212 compares VSUP S to configurable values S LO and S HI and provides supply voltage status signals SS to control circuitry 214, and further compares VCOR to configurable values C LO and C HI and provides core voltage status signals CS to control circuitry 214. S LO represents a discharge voltage level for VSUP S, and S HI represents a nominal operating voltage level for VSUP S. SS can include multiple signals indicating the relative status of VSUP S with respect to S LO and S HI. For example, SS can indicate when VSUP S < S HI, when VSUP S > S HI, when VSUP S > S LO, or when VSUP S < S LO. Similarly, C LO represents a discharge voltage level for VCOR, and C HI represents a nominal operating voltage level for VCOR. CS can include multiple signals indicating the relative status of VCOR with respect to C LO and C HI. For example, CS can indicate when VCOR < C HI, when VCOR > C HI, when VCOR > C LO, or when VCOR < C LO. Comparator circuitry 212 can be implemented in the digital domain, where VSUP S and VCOR are converted to digital values, and where S LO, S HI, C LO, and C HI can be stored as digital values.

[0036] Control circuitry 214 receives CS, SS, PSYNC, and LPM and provides LPGOOD, VSON, and S EN. In alternative embodiments, comparator circuitry 212 can be simplified by not comparing VCOR to C HI, such that C HI can be ignored. Instead, control circuitry 214 relies on PSYNC for determining when VCOR is at or above its nominal regulated voltage level.

[0037] Figure 3is a state diagram illustrating the operation of a cascaded PMIC system 104 including a master PMIC 202 and a slave PMIC 204 according to one embodiment of the present disclosure. For both master PMICs 202, operation begins in an OFF state, shown as a MASTER OFF state 301 for the master PMIC 202 and a SLAVE OFF state 302 for the slave PMIC 202. The OFF state can mean that the processing system 102 is off or held in a reset state. When a power-on indication, shown as ON, is received, the master PMIC 202 transitions to a MASTER POWER UP state 303. In the MASTER POWER UP state 303, the control circuitry 214 of the master PMIC 202 deasserts the S_EN signal to low (e.g., S_EN = 0) to keep the slave PMIC 204 in its OFF state 202, and asserts the LPGOOD signal to low (e.g., LPGOOD = 0) to keep the processor 106 in its reset state. At this time, the low power domain 216 of the processor 106 can be powered up, but until the LPGOOD signal is deasserted high, the low power domain 216 does not attempt to power up the rest of the processor 106.

[0038] Upon transitioning to the MASTER POWER UP state 303, the regulator within the power regulator circuitry 214 begins converting the source voltage VSRC to the supply voltage VSUP. In the MASTER POWER UP state 303, the control circuitry 214 asserts VSON high (e.g., VSON = 1) to command the power regulator 206 to charge the supply voltage VSUP S for providing power to the slave PMIC 204 and the processor 106. The comparator circuitry 212 monitors the voltage level of VSUP S, and the control circuitry 214 keeps the master PMIC 204 in the MASTER POWER UP state 303 while VSUP S is below a configurable voltage level S HI (e.g., VSUP S < S HI). If VSUP S represents multiple voltages, each voltage can have a corresponding threshold voltage level, where S HI represents multiple voltage level thresholds. When the voltage level of VSUP S reaches or otherwise exceeds S HI (e.g., when VSUP S > S HI), then the master PMIC 202 transitions to the WAIT state 305, and the control circuitry 214 asserts the S EN signal high to enable the slave PMIC 204. The control circuitry 214 keeps VSON high and also keeps LPGOOD asserted low to keep the processor 106 in its reset state. When S EN = 1, the slave PMIC 204 transitions to the SLAVE POWER UP state 304, where the core supply circuitry 210 begins charging the core voltage VCOR (e.g., based on converting VSUP or VSRC, etc.).

[0039] At the same time, in the WAIT state 305, the control circuitry 214 of the master PMIC 202 monitors the PSYNC input. The comparison circuitry 212 can also monitor the voltage level of VCOR via the VMON input. The master PMIC 202 remains in the WAIT state 305 while the PSYNC is deasserted low (e.g., PSYNC = 0) and at the same time VCOR remains below C HI. The slave PMIC 204 remains in the SLAVE POWER UP state 304 until VCOR is regulated, as indicated by its output PGOOD. When the core supply circuitry 210 achieves regulation of VCOR, PGOOD is asserted high (e.g., PGOOD = 1) and the slave PMIC 204 transitions to the SLAVE NORMAL state 306. When PGOOD = 1, the PSYNC input of the master PMIC 202 is asserted high (e.g., PSYNC = 1) and the control circuitry 214 assumes, in the first embodiment, that VCOR is at its regulated level, or otherwise monitors CS to ensure that the voltage level of VCOR is greater than or equal to C HI. When PSYNC = 1 (and VCOR > C HI), the master PMIC 202 transitions to the MASTER NORMAL state 307 for normal mode of operation.

[0040] While in the MASTER NORMAL state 307, the control circuitry 214 releases LPGOOD high (e.g., LPGOOD = 1) to allow the processor 106 to power up and operate in its normal mode. In this manner, the processor 106 is prevented from starting up until sufficient power is available via VSUP S and VCOR. An early start up without sufficient power can cause the processing system 102 to trigger and unwanted resets. The processor 106 keeps its LPM output low (e.g., LPM = 0), which indicates that it is in its normal mode of operation, and also keeps VSON and S EN asserted high. In the normal mode of operation, the master PMIC 202 remains in its MASTER NORMAL state 307 and the slave PMIC 204 remains in its SLAVE NORMAL state 306. It should be noted that S EN can also be provided to one or more of the regulators of the power regulator 206 to manage a defined start-up sequence between the regulators.

[0041] When processor 106 determines to enter or re-enter its low power mode, processor 106 asserts its LPM output high (or LPM = 1). Control circuitry 214 detects the LPM being asserted high and transitions master PMIC 202 to a MASTER POWER DOWN state 309. In the MASTER POWER DOWN state 309, control circuitry 214 de-asserts S_EN low (e.g., S_EN = 0) to power down slave PMIC 204. In response, slave PMIC 204 transitions back to its SLAVE OFF state 302 and begins to return VCOR to discharge low. In the MASTER POWER DOWN state 309, control circuitry 214 also de-asserts VSON low (e.g., VSON = 0) to command power regulator circuitry 206 of master PMIC 202 to begin discharging VSUP S to power down PMIC slave 204 and processor 106. Master PMIC 202 remains in the MASTER POWER DOWN state 309 while VSUP S remains greater than a configurable low threshold S LO (e.g., VSUP S > S LO) and while VCOR remains greater than a configurable low threshold C LO (e.g., VCOR > C LO). In the MASTER POWER DOWN state 309, control circuitry 214 also remains de-asserting LPGOOD high so that processor 106 does not prematurely begin to transition to its low power state. Prematurely transitioning to low power can cause residual internal biasing of processor 106, which is disadvantageous upon restart.

[0042] The comparator circuitry 212 and control circuitry 214 monitor VSUP S and VCOR in the MASTER POWER DOWN state 309. When VSUP S is less than or equal to S LO (e.g., VSUP S < S LO) and when VCOR is less than or equal to C LO (e.g., VCOR < C LO), then the master PMIC 202 transitions to the LOW POWER state 311. S LO and C LO can be selected to be low enough values to prevent residual internal bias, and can represent values equal to or very close to 0 volts (V) each. In the LOW POWER state 311, the control circuitry 214 of the master PMIC 202 keeps S EN inactive low to keep the slave PMIC 204 in the SLAVE OFF state 302, and keeps VSON low to keep VSUP S discharging. In the LOW POWER state 311, the control circuitry 214 asserts the LPGOOD signal low (e.g., LPGOOD = 0) so that the processor 106 can transition to its low power state. The LPGOOD is asserted to prevent unpredictable behavior due to low power entry sequence exceptions ending or interrupting. The master PMIC 202 remains in the LOW POWER state 311 while the LPM remains asserted high by the processor 106.

[0043] When the processor 106 determines to re-enter its normal operating mode, the processor 106 deactivates its LPM output low (or LPM = 0). The control circuitry 214 detects the LPM being deactivated low and transitions the master PMIC 202 back to the MASTER POWER UP state 303. As previously described, when in the MASTER POWER UP state 303, the control circuitry 214 deactivates the S EN signal low (e.g., S EN = 0) to keep the slave PMIC 204 in its OFF state 202, and asserts the LPGOOD signal low (e.g., LPGOOD = 0) to keep the processor 106 in its low power state. In addition, the control circuitry 214 reasserts VSON high to command the power regulator circuitry 206 to begin recharging the switched supply voltage VSUP S for providing power to the slave PMIC 204 and the processor 106, as previously described, and the operation transitions to the WAIT state 305 and subsequently to the MASTER NORMAL state 307 in response to the same conditions previously described. When in the WAIT state 305, the S EN signal is asserted high to power up the slave PMIC 204 in a similar manner as previously described for providing VCOR to the processor 106.

[0044] It should be appreciated that the processor 106 only communicates with the master PMIC 202 and not the slave PMIC 204. In fact, the circuitry of the processor 106 can not even be aware of the existence of the slave PMIC 204 except for receiving the core voltage VCOR. It should be noted that the processor 106 communicates the desire to transition between the low power mode of operation and the normal mode of operation using a single signal LPM. Although not shown, additional communication or additional signals can be included for signaling the transition between different modes of operation. For example, a separate LPM_EXIT signal (not shown) can be incorporated for exiting the low power mode, in which case the LPM is only used for entering the low power mode.

[0045] A cascaded power supply according to one embodiment includes master power management circuitry and slave power management circuitry. The master power management circuitry includes a master power regulator, comparator circuitry, and control circuitry. The master power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The comparator circuitry monitors voltage levels of the supply voltage and a core voltage and provides at least one state signal indicative of the voltage levels. The control circuitry deactivates a slave enable signal and disables the master power regulator when activating a low power signal for transitioning from the normal mode to the low power mode, and activates a low power good signal when the at least one state signal indicates that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold. The slave power management circuitry provides the core voltage when the slave enable signal is activated for the normal mode, and discharges the core voltage when the slave enable signal is deactivated for the low power mode.

[0046] The control circuitry can command the master power regulator to charge the supply voltage when deactivating the low power mode signal, can activate the slave enable signal when the supply voltage is at least a first high threshold, and can deactivate the low power good signal to enter the normal mode when activating the synchronization signal after activating the slave enable signal. The slave power management circuitry can activate the synchronization signal when the core voltage reaches a regulated level. Additionally, the control circuitry can deactivate the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0047] The control circuitry can command the master power regulator to charge the supply voltage when deactivating the low power mode signal, can activate the slave enable signal when the supply voltage is at least a first high threshold, and can deactivate the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0048] The master power management circuitry can be implemented on a first semiconductor device, and the slave power management circuitry can be implemented on a second semiconductor device.

[0049] The cascaded power supply can further include a processor that provides the low power mode signal and receives the low power good signal. The processor can be configured to transition from the normal mode to the low power mode only when the low power good signal is asserted and to transition from the low power mode to the normal mode only when the low power good signal is de-asserted. The master power management circuitry can be implemented on a first semiconductor device, the slave power management circuitry can be implemented on a second semiconductor device, and the processor can be implemented on a third semiconductor device.

[0050] A method according to one embodiment includes providing master power management circuitry and providing slave power management circuitry. Providing the master power management circuitry can include providing a supply voltage during a normal mode and discharging the supply voltage during a low power mode, monitoring voltage levels of the supply voltage and a core voltage and providing at least one status signal indicative of the voltage levels, de-asserting a slave enable signal and disabling a master power regulator when a low power mode signal is asserted for transitioning from the normal mode to the low power mode, and asserting a low power good signal when the at least one status signal indicates that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold. Providing the slave power management circuitry can include providing the core voltage when the slave enable signal is asserted for the normal mode and discharging the core voltage for the low power mode.

[0051] The method can further include commanding the master power regulator to charge the supply voltage when the low power mode signal is de-asserted, asserting the slave enable signal when the supply voltage is at least a first high threshold, asserting a synchronization signal when the core voltage reaches a regulated level, and de-asserting the low power good signal to enter the normal mode when the slave enable signal is asserted after the synchronization signal is asserted. The method can include de-asserting the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0052] The method can include commanding the master power regulator to charge the supply voltage when the low power mode signal is de-asserted, asserting the slave enable signal when the supply voltage is at least a first high threshold, and de-asserting the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

[0053] The method can include providing a processor that provides the low power mode signal and receives the low power good signal. The method can include transitioning from the normal mode to the low power mode by the processor only when the low power good signal is asserted and transitioning from the low power mode to the normal mode by the processor only when the low power good signal is de-asserted.

[0054] A processing system according to one embodiment includes a cascaded power management system and a processor. The cascaded power management system can include master power management circuitry and slave power management circuitry. The master power management circuitry can include a master power regulator that provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode, comparator circuitry that monitors voltage levels of the supply voltage and a core voltage and provides at least one state signal indicative of the voltage levels, and control circuitry that deactivates a slave enable signal and disables the master power regulator when a low power mode signal is asserted for transitioning from the normal mode to the low power mode, and asserts a low power good signal when the at least one state signal indicates that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold. The slave power management circuitry can provide the core voltage when the slave enable signal is asserted for the normal mode, and can discharge the core voltage when the slave enable signal is de-asserted for the low power mode. The processor can include power supply circuitry that receives the supply voltage and the core voltage, and low power domain circuitry that provides the low power mode signal and receives the low power good signal. The processor can be configured to transition from the normal mode to the low power mode only when the low power good signal is asserted, and to transition from the low power mode to the normal mode only when the low power good signal is de-asserted.

[0055] A cascaded power system can include master power management circuitry and slave power management circuitry. The master circuitry can include a master power regulator, comparator circuitry, and control circuitry. The power regulator can provide a supply voltage during a normal mode and can discharge the supply voltage during a low power mode. The slave circuitry can provide a core voltage when enabled, and otherwise discharge the core voltage. The comparator circuitry can monitor voltage levels of the supply voltage and the core voltage, and the control circuitry can perform a handshake with the slave circuitry based in part on the voltages to ensure a smooth transition between the normal mode and the low power mode. The control circuitry can assert a low power good signal when the supply voltage and the core voltage are discharged, and can de-assert the low power good signal when the supply voltage and the core voltage are fully charged. A processor can rely on a low power mode signal for transitioning between power modes.

[0056] Although the application has been described in connection with several embodiments, it is not intended to be limited to the particular form set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the scope of the application as defined by the appended claims. For example, changes in logic or order of logic can be made to various embodiments of the application without departing from the scope of the application. For example, signals can be active low and inactive high, but can also be active high and inactive low, depending on whether the pin or signal is implemented in positive logic or negative logic, etc. In some cases, the particular logic state can be programmable, where the logic state can be inverted for a given logic function.

[0057] As used herein, the term "a" is defined as one or more. Additionally, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introducing phrase can be limited to only one of the particular claim elements recited therein. Further, the use of certain terms in various places in the specification is merely for the purpose of reference, and thus are not intended to limit the application. For example, the terms "first," "second," and "third" can be used interchangeably throughout the specification, and are merely intended to differentiate between various regions or elements. Similarly, when relative terms are used, such as "top," "bottom," "upper," "lower," "up," "down," "vertical," "horizontal," "front," "back," "rear," "side," "end," "side," "out," "in," "upward," "downward," "upwards," "downwards," "forward," "backward," "forwardly," "backwardly," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly," "front," "back," "frontward," "rearward," "frontwards," "rearwards," "frontwardly," "rearwardly

Claims

1. A cascaded power supply, characterized by, comprising: master power management circuitry, comprising: a master power regulator, the master power regulator providing a supply voltage during a normal mode and discharging the supply voltage during a low power mode; comparator circuitry, the comparator circuitry monitoring voltage levels of the supply voltage and a core voltage and providing at least one status signal indicative of the voltage levels; and control circuitry, the control circuitry deactivating a slave enable signal and commanding the master power regulator to discharge the supply voltage upon asserting a low power mode signal for transitioning from the normal mode to the low power mode, and asserting a low power good signal upon the at least one status signal indicating that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold; and slave power management circuitry, the slave power management circuitry providing the core voltage upon asserting the slave enable signal for the normal mode, and discharging the core voltage upon deactivating the slave enable signal for the low power mode.

2. The cascaded power supply of claim 1, wherein: the control circuitry deactivates the low power mode signal, commands the master power regulator to charge the supply voltage, asserts the slave enable signal upon the supply voltage being at least a first high threshold, and deactivates the low power good signal upon asserting the slave enable signal and asserting a synchronization signal to enter the normal mode; and wherein the slave power management circuitry asserts the synchronization signal upon the core voltage reaching a regulated level.

3. A cascaded power supply according to claim 2, characterised in that, the control circuitry deactivates the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

4. The cascaded power supply of any of claims 1-3, wherein, the control circuitry deactivates the low power mode signal, commands the master power regulator to charge the supply voltage, asserts the slave enable signal upon the supply voltage being at least a first high threshold, and deactivates the low power good signal to enter the normal mode only after the core voltage is at least a second high threshold.

5. The cascaded power supply of any one of claims 1-3, wherein, the master power management circuitry is implemented on a first semiconductor device, and wherein the slave power management circuitry is implemented on a second semiconductor device.

6. The cascaded power supply of any one of claims 1-3, wherein, further comprising a processor, the processor providing the low power mode signal and receiving the low power good signal.

7. The cascaded power supply of claim 6, wherein, the processor transitions from the normal mode to the low power mode only upon asserting the low power good signal, and transitions from the low power mode to the normal mode only upon deactivating the low power good signal.

8. The cascaded power supply of claim 6, wherein, the master power management circuitry is implemented on a first semiconductor device, wherein the slave power management circuitry is implemented on a second semiconductor device, and wherein the processor is implemented on a third semiconductor device.

9. A method of power mode management, the method comprising: comprising: providing master power management circuitry, comprising: providing a supply voltage during a normal mode and discharging the supply voltage during a low power mode; monitoring voltage levels of the supply voltage and a core voltage and providing at least one status signal indicative of the voltage levels; and de-asserting the slave enable signal and commanding the master power regulator to discharge the supply voltage upon asserting the low power mode signal for transitioning from the normal mode to the low power mode, and asserting the low power good signal upon at least one state signal indicating that the supply voltage is discharged below a first low threshold and the core voltage is discharged below a second low threshold; and providing slave power management circuitry to provide the core voltage when the slave enable signal is asserted for the normal mode, and otherwise to discharge the core voltage for the low power mode.

10. A processing system, characterized by comprising: a cascaded power supply according to any one of claims 1 to 8; and a processor comprising: power supply circuitry to receive a supply voltage and a core voltage; and low power domain circuitry to provide a low power mode signal and to receive a low power good signal, wherein the processor is to transition from the normal mode to the low power mode only upon asserting the low power good signal, and to transition from the low power mode to the normal mode only upon de-asserting the low power good signal.

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