Gate driver circuit and method of driving a transistor

Abstract

Gate driver circuits and methods of driving a transistor are disclosed. A gate driver circuit includes a first supply rail providing a first fixed supply voltage, a second supply rail providing a second fixed supply voltage, a transistor including a gate terminal having a gate voltage, and a gate driver integrated circuit (IC) provided with the first fixed supply voltage and the second fixed supply voltage, the gate driver IC including an output terminal, the gate driver IC configured to provide a gate drive voltage at the output terminal to drive the transistor between switching states. The gate driver IC includes a first voltage converter configured to modulate a magnitude of the first fixed supply voltage to generate a first modulated supply voltage, and a first switch configured to selectively couple the first fixed supply voltage and the first modulated supply voltage to the output terminal of the gate driver IC to regulate the gate drive voltage.

Description

Technical Field

[0001] This disclosure relates generally to power transistors, and more specifically, to controlling the gate drive voltage of power transistors. Background Technology

[0002] In automotive, consumer, and industrial applications, many functions of modern equipment, such as converting electrical energy and driving electric motors, rely on power semiconductor devices. For example, to name just a few, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes have been used in a wide range of applications, including but not limited to switches in power supplies and power converters.

[0003] Power semiconductor devices typically include semiconductor components configured to conduct load current along a load current path between two load terminal components of the device. Furthermore, the load current path can be controlled by means of a control electrode (sometimes called a gate electrode). For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of an on state or a blocking state. The control signal can be a voltage signal or a current signal with a controlled value.

[0004] A power transistor is a power semiconductor device that can be used to drive load current. There are conduction and turn-off processes for turning a power transistor on and off. During the conduction process, a gate driver integrated circuit (IC) is used to supply gate current to the gate of the power transistor to charge the gate. Conversely, during the turn-off process, the gate driver IC is used to draw gate current from the gate of the power transistor to discharge the gate. The gate driver circuit can be an integrated circuit (IC).

[0005] The gate driver IC is supplied with a fixed positive voltage V by the positive power rail. pos And a fixed negative voltage V is provided by the negative power rail. neg These voltages cannot be changed during operation. The gate resistor Rg connects the output terminal (OUT) of the gate driver IC to the gate terminal of the power transistor. Therefore, the driven gate current I... g It is also fixed and follows Ohm's law (I g =(V pos –V neg This means that the switching characteristics of the power transistor are also fixed for any operation that varies with temperature or transistor current.

[0006] Figure 1 The left side shows the dV / dt characteristics of the power switch, and the right side shows a schematic representation of IGBT 1. Figure 1The left side shows V during a switching event. CE (i.e., dV / dt) and I c Transient graph of (i.e., di / dt). V CE The voltage transient (called dV / dt) is initially very steep and fast, and then when the gate-collector capacitance C... GC When the charge at a point increases, it becomes shallowly sloped to end with a slow tailing at the last few volts.

[0007] During the conduction switch event, as C GC Being charged, V GE Increase. Once V GE Equal to threshold voltage Vth, current I c It begins to flow. Figure 1 A further schematic diagram of power transistor 1 is shown on the right, illustrating the gate-collector (parasitic) capacitance C. GC Collector-emitter voltage V CE Collector current I c and gate-emitter voltage V GE .

[0008] In standard planar technology, there is a fast dV / dt transient, but due to the gate-collector capacitance C... GC The Miller effect is mitigated by the rapid dV / dt transient. In fact, the gate driver output current I used to raise (i.e., charge) the gate voltage of the power transistor during the turn-on transient is reduced. g During the period when dV / dt and gate voltage present a flat or constant voltage that forms the "Miller plateau", C flows completely. GC The phase during which the gate voltage exhibits a flat transition is called the Miller phase. After the Miller phase, the gate-emitter voltage V0... GE Charge to positive voltage V pos .

[0009] All power transistors exhibit a constant gate voltage during the transition between collector-emitter voltage (or drain-source voltage) and collector current (or drain current). This gate voltage is called the Miller voltage. The level of the Miller voltage is a function of the collector current or drain current of the power transistor. As the collector / drain current increases, the Miller voltage (gate-emitter voltage V) increases. GE As the voltage across the gate resistor Rg increases, and since the voltage at the output terminal of the gate driver IC is fixed, the voltage difference across Rg decreases. Therefore, the effective gate drive voltage across Rg (which drives the collector / drain current during the turn-on transient) decreases with increasing collector / drain current. This results in greater turn-on energy (i.e., higher switching losses) at lower switching speeds.

[0010] Therefore, an improved device may be needed where the supply voltage is no longer fixed but adjustable to increase or decrease the gate current during the Miller phase of operation. The switching characteristics of the power transistor can then be varied according to the operating conditions of the power transistor to compensate for the Miller effect. Summary of the Invention

[0011] This document provides systems, apparatus, and methods for adaptively controlling the gate current of a power transistor based on its input capacitance.

[0012] According to one or more embodiments, a gate driver circuit is provided. The gate driver circuit includes: a first power rail configured to provide a first fixed power supply voltage; a second power rail configured to provide a second fixed power supply voltage; a transistor including a gate terminal having a gate voltage; a gate driver integrated circuit (IC) provided with the first fixed power supply voltage and the second fixed power supply voltage, the gate driver IC including an output terminal coupled to the gate terminal of the transistor and configured to provide a gate drive voltage at the output terminal to drive the transistor between switching states; and a gate resistor coupled between the output terminal of the gate driver IC and the gate terminal of the transistor, wherein the gate resistor defines a gate current based on the gate drive voltage and the gate voltage. The gate driver IC further includes: a first voltage converter configured to receive the first fixed power supply voltage and modulate the amplitude of the first fixed power supply voltage to generate a first modulated power supply voltage; and a first switch configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC to regulate the gate drive voltage.

[0013] According to one or more embodiments, a method is provided for driving a transistor between switching states in a power supply circuit. The method includes: providing a gate drive voltage at an output terminal of a gate driver IC to drive the transistor between switching states; providing a first fixed power supply voltage and a second fixed power supply voltage to the gate driver IC; converting the first fixed power supply voltage into a first modulated power supply voltage by the gate driver IC; and selectively coupling the first fixed power supply voltage and the first modulated power supply voltage to an output terminal of the gate driver IC via a first switch to regulate the gate drive voltage.

[0014] According to one or more embodiments, a gate driver includes: a first terminal configured to receive a first fixed power supply voltage; a second terminal configured to receive a second fixed power supply voltage; an output terminal configured to provide a gate drive voltage to drive a transistor between switching states; a first voltage converter configured to receive the first fixed power supply voltage and adjust the amplitude of the first fixed power supply voltage to generate a first modulated power supply voltage; and a first switch configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal to adjust the gate drive voltage. Attached Figure Description

[0015] The embodiments are described in the text with reference to the accompanying drawings.

[0016] Figure 1 A voltage circuit diagram showing the dV / dt characteristics of a power switch is shown on the left, and a schematic representation of a power switch according to one or more embodiments is shown on the right.

[0017] Figure 2 A schematic block diagram illustrating a gate voltage control circuit configured to control a power transistor according to one or more embodiments is shown.

[0018] Figure 3A It is a timing diagram of switches S1 and S2 based on PWM control signals according to one or more implementations;

[0019] Figure 3B It is a signal diagram of the gate drive voltage for a boost-buck converter according to one or more embodiments;

[0020] Figure 4 A schematic block diagram of the control logic of a gate driver IC according to one or more embodiments is shown;

[0021] Figure 5 A schematic block diagram of the control logic of a gate driver IC according to one or more embodiments is shown; and

[0022] Figure 6 and Figure 7 A schematic block diagram of a gate voltage control circuit with self-adjusting feedback correction according to one or more embodiments is shown. Detailed Implementation

[0023] In the following sections, details are set forth to provide a more thorough description of exemplary embodiments. However, it will be apparent to those skilled in the art that embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagrams or schematic diagrams rather than in detail to avoid obscuring the embodiments. Furthermore, unless explicitly stated otherwise, features of the different embodiments described below can be combined with each other.

[0024] Furthermore, in the following description, equivalent or similar elements, or elements having equivalent or similar functions, are indicated using equivalent or similar reference numerals. Since identical or functionally equivalent elements in the drawings are given the same reference numerals, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals can be used interchangeably.

[0025] In this regard, directional terms such as "top," "bottom," "below," "above," "front," "back," "rear," "front part," and "tail" may be used with reference to the orientation of the accompanying drawings. Because components of the embodiments can be positioned in many different orientations, directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description should not be construed as limiting.

[0026] What will be understood is that when an element is described as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other terms used to describe relationships between elements (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.) should be understood in a similar manner.

[0027] In the embodiments described herein or shown in the accompanying drawings, any direct electrical connection or coupling—that is, any connection or coupling without additional intermediate elements—can also be achieved through an indirect connection or coupling—that is, a connection or coupling with one or more additional intermediate elements, or vice versa, as long as the general purpose of the connection or coupling, such as transmitting a signal or transmitting information, is substantially maintained. Features from different embodiments can be combined to form other embodiments. For example, unless otherwise stated, variations or modifications described with respect to one embodiment may also apply to other embodiments.

[0028] Without departing from aspects of the embodiments described herein, the term "substantially" may be used herein to interpret small manufacturing tolerances (e.g., within 5%) that are considered industrially acceptable.

[0029] Signal processing circuitry and / or signal conditioning circuitry can receive one or more signals (i.e., measurement signals) in the form of raw measurement data from one or more components, and can derive further information from the measurement signals. As used herein, signal conditioning refers to manipulating an analog signal in a manner that makes the signal meet the requirements of the next stage of further processing. Signal conditioning may include analog-to-digital conversion (e.g., conversion via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0030] Therefore, signal processing circuitry may include an analog-to-digital converter (ADC) that converts analog signals from one or more components into digital signals. Signal processing circuitry may also include a digital signal processor (DSP) that performs some processing on the digital signals.

[0031] A power transistor (also called a power switch or transistor switch) is a power semiconductor device that can be used to drive load current. For example, an IGBT is turned on or off by activating and deactivating its gate terminal. Applying a positive input voltage signal across the gate and emitter terminals will keep the device in the "on" state, while making the input gate signal zero or slightly negative will turn the device "off". There are turn-on and turn-off processes for turning a power transistor on and off.

[0032] During the conduction process, a gate driver integrated circuit (IC) can be used to supply gate current (i.e., on-current) to the gate of the power transistor to charge the gate to a sufficient voltage to turn the device on. Specifically, the current Io+ is the output current I of the gate driver that flows from the gate driver IC to the gate of the power transistor during the turn-on transient for gate boosting (i.e., charging). g Therefore, the current Io+ is used to turn on the power transistor.

[0033] Conversely, during the turn-off process, the gate driver IC is used to draw (suck) gate current (i.e., turn-off current) from the gate of the power transistor to fully discharge the gate and turn off the device. The current Io- is the output current I of the gate driver that flows from the gate to the gate driver IC during the turn-off transient to discharge the gate of the power transistor. g Therefore, the current Io- is used to turn off the power transistor.

[0034] According to the pulse width modulation (PWM) scheme, a voltage pulse can be output from the gate driver IC as a control signal. Therefore, during the PWM cycle, the control signal can switch between the on-state voltage level and the off-state voltage level to control the power transistor. This allows the gate voltage to be charged and discharged sequentially to turn the power transistor on and off, respectively.

[0035] Specifically, the gate of the power transistor is a capacitive load, and the on-current (i.e., gate supply current) and off-current (i.e., gate sink current) are specified as initial currents when a switching event is initiated. During the off-event, the gate current decreases after a short period (smaller than the PWM cycle) and reaches zero when the gate reaches 0V. During the on-event, the gate current decreases after a short period (smaller than the PWM cycle) and reaches zero when the gate reaches 15V.

[0036] Transistors may include insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) (e.g., Si MOSFETs or SiC MOSFETs). Although IGBTs may be used as examples in the embodiments described below, it should be understood that MOSFETs can be used instead of IGBTs, and vice versa. In this case, in any of the examples described herein, when a MOSFET is used instead of an IGBT, the drain of the MOSFET can replace the collector of the IGBT, the source of the MOSFET can replace the emitter of the IGBT, and the drain-source voltage V of the MOSFET... DS It can replace the collector-emitter voltage V of an IGBT CE Therefore, any IGBT module can be replaced by a MOSFET module, and vice versa.

[0037] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used within a power converter or power supply. Therefore, in these embodiments, the power semiconductor device can be configured to carry load current to be supplied to a load and / or load current supplied by a power supply, respectively. For example, the semiconductor device may include one or more power semiconductor units, such as monolithic integrated diode units and / or monolithic integrated transistor units. Such diode units and / or such transistor units may be integrated within a power semiconductor module.

[0038] In the field of power electronics, power semiconductor devices that include transistors appropriately connected to form a half-bridge are commonly used. For example, a half-bridge can be used to drive an electric motor or a switch-mode power supply.

[0039] For example, a three-phase inverter includes three inverter legs, each for each of the three phases, and each inverter leg is connected in parallel to a direct current (DC) voltage source. Each inverter leg includes a pair of power transistors, arranged, for example, in a half-bridge configuration, for converting DC to AC. In other words, each inverter leg includes two complementary transistors connected in series (i.e., a high-side transistor and a low-side transistor), which complementaryly turn on and off to drive the phase load. However, multiphase inverters are not limited to three-phase and may include two or more phases, where each phase has an inverter leg.

[0040] Figure 2 A schematic block diagram is shown illustrating a gate voltage control circuit 100 configured to control a power transistor M1 according to one or more embodiments. The gate voltage control circuit 100 is a device in which the power supply voltage coupled to current sources Q1 and Q2 (i.e., the supply voltage to FET Q1 and the sink voltage to FET Q2) is no longer fixed but adjustable, so as to increase or decrease the gate current I during the Miller phase of operation. g As a result, the switching characteristics of the power transistor M1 can be changed according to the operating conditions of the power transistor M1, and the Miller effect can be compensated.

[0041] For example, if more gate current I is applied during the Miller stage g This can reduce the switching energy under high collector current / drain current conditions. Conversely, if a smaller gate current I is applied under low collector current / drain current conditions, the switching energy can be reduced. g This allows for a more suitable electromagnetic interference (EMI) spectrum. The gate voltage control circuit 100 introduces an additional, independent, and adjustable supply voltage used only during gate voltage transients (e.g., during the Miller phase). The gate voltage control circuit 100 provides an effective gate drive voltage V across the gate resistor Rg. g Active adaptive adjustment to adapt to gate current I during operation g Different gate current levels can be obtained. As a result, the gate current I is adjusted by regulating the voltage at the output terminal OUT of the gate driver IC 10. g It is adaptively adjustable and can be regulated to a constant during switching events (i.e., the gate current I0). g (Constant throughout the transient). Alternatively or alternatively, the gate current I... g It is adaptively adjusted and can be kept constant independent of the Miller voltage during each Miller phase. Therefore, the gate current I can be adjusted. gTo maintain a constant effective gate drive voltage V during the Miller phase g .

[0042] As described above, the current Io+ is the gate current I flowing from the output terminal OUT of the gate driver IC to the gate during the turn-on transient and used to boost (i.e. charge) the gate of the power transistor M1. g The alternative symbol. Additionally, the current Io- is the gate current I flowing from the gate to the output terminal OUT of the gate driver IC during the turn-off transient and used to discharge the gate of the power transistor M1. g The alternative symbol is given. Therefore, the current Io+ can be set and / or regulated during the turn-on switching event of the power transistor M1 by adjusting the supply voltage provided to the supply FET Q1. Similarly, the current Io- can be set and / or regulated during the turn-off switching event of the power transistor M1 by adjusting the supply voltage provided to the sink FET Q2. Note that the supply FET Q1 and sink FET Q2 operate complementaryly to each other.

[0043] The gate voltage control circuit 100 includes a gate driver IC 10 configured to drive a power transistor M1. The gate driver IC 10 provides a gate drive voltage at its output terminal OUT, which is coupled to the gate terminal of the power transistor M1 via a gate resistor Rg. The voltage across the gate resistor is called the effective gate drive voltage because it directly affects the gate-collector capacitance C of the power transistor. GC Gate current I during charging or discharging g The voltage. As described above, as the power transistor is fully turned on (i.e., during the turn-on transient) or fully turned off (i.e., during the turn-off transient), the gate voltage V... GE It may change, and the gate current I g The voltage may decrease during one of these transients, which will result in longer switching times and higher power losses. The gate driver IC 10 is configured to prevent or mitigate this phenomenon.

[0044] The gate voltage control circuit 100 is a bipolar gate drive circuit coupled to bipolar power supplies 11p and 11n, which are connected by a positive voltage power rail V. pos The provided 15V positive gate bias and the negative voltage power rail V neg A negative gate bias of -5V is provided. However, these voltages are configurable. Capacitor C pos and C neg This is used to stabilize the rail voltage supplied to terminals VCC2 and VEE2 of gate driver IC 10. Gate driver IC 10 also includes a ground terminal GND coupled to ground.

[0045] Alternatively, the gate voltage control circuit 100 may be a unipolar gate drive circuit coupled to a unipolar power supply (e.g., a negative voltage power rail coupled to ground). Even with a unipolar power supply, the gate voltage control circuit 100 may be configured to drive in a bipolar manner.

[0046] The supply FET Q1 is configured to be turned on to supply power from the power rail V. pos A positive gate bias is provided to the gate of power transistor M1, or an adjusted positive gate bias is provided to the gate of power transistor M1 from positive voltage converter 12 via switch S1. Similarly, FET Q2 is configured to be turned on to draw power from the power rail V. neg A negative gate bias is provided to the gate of the power transistor M1, or an adjusted negative gate bias is provided to the gate of the power transistor M1 from the negative voltage converter 13 via the switch S2.

[0047] Gate driver IC 10 is supplied from power rail V. pos and V neg A fixed positive voltage and a fixed negative voltage are applied. The gate resistor Rg connects the output terminal OUT of the gate driver IC 10 to the gate terminal of the transistor M1. Therefore, the gate current I is generated based on the gate resistor Rg, the on / off states of the supply FET Q1 and the draw FET Q2, and the gate drive voltage coupled to the load path terminals of the corresponding FET Q1 or FET Q2. g More specifically, the gate current I g The voltage at the output terminal OUT and the instantaneous voltage V of the power transistor M1 GE The difference between them is used to define the limit.

[0048] For example, when the gate voltage is from V neg To V pos During transient-limited turn-on events, the gate current I can be adjusted by changing the positive gate bias (i.e., the positive gate drive voltage) coupled to and subsequently provided by the output terminal OUT of the gate driver IC 10. g More specifically, the gate current I can be adjusted during the Miller phase of the turn-on event. g Adjusting the positive gate drive voltage effectively regulates the effective gate drive voltage Vg across the gate resistor Rg, thereby regulating the gate current I. g .

[0049] Similarly, for example, when the gate voltage is from V pos To V negDuring transient-limited turn-off events, the gate current Ig can be adjusted by changing the negative gate bias (i.e., the negative gate drive voltage) coupled to and subsequently provided by the output terminal OUT of the gate driver IC 10. More specifically, the gate current Ig... g This can be used in the Miller phase of a turn-off switching event. Adjusting the negative gate drive voltage effectively regulates the effective gate drive voltage Vg across the gate resistor Rg, thereby regulating the gate current I. g .

[0050] The gate driver IC 10 includes a positive voltage converter 12 configured to modulate the positive rail voltage supplied to the output terminal OUT to provide a constant gate current I through the gate resistor Rg, at least during the Miller phase of a turn-on event. g The gate driver IC 10 includes a sensing terminal, Sense-V. ge The sensing terminal Sense-Vge is electrically coupled to the output of the gate resistor Rg to measure the sensing node N. sense Gate-emitter voltage V at the location GE As mentioned above, with the collector current I... c Increase, Miller voltage (gate-emitter voltage V) GE This increases. Therefore, for some reason, the voltage at the output of the gate resistor Rg can be measured.

[0051] First, the sensing node N can be measured (i.e., monitored) via control logic 14. sense Gate-emitter voltage V at the location GE This is used to detect the Miller phase, and more specifically, to detect when the Miller phase ends. When the gate-emitter voltage V... GE The event can be detected when an increase begins after a constant period (e.g., an increase is detected after the Miller plateau). Once the Miller phase ends, clamping to V can be enabled. pos or V neg As described below. Before this, clamping can be disabled. Alternatively, the Miller voltage can be recorded and used as feedback information to adaptively adjust V for the next pulse (i.e., for the next switching event). gdp and / or V gdn .

[0052] Secondly, the sensing node N can be measured (i.e., monitored) through control logic 14. sense Gate-emitter voltage V at the point GE This is to precisely determine when the clamp to V should be activated (i.e., implemented) via switches S1 and S2. pos Or clamp to V neg .

[0053] The gate driver IC 10 also includes a negative voltage converter 13 configured to modulate the negative rail voltage supplied to the output terminal OUT to provide a constant gate current, at least during the Miller phase of a turn-off switching event. The gate driver IC 10 includes a sensing terminal Sense-V. ge It is electrically connected to the output of the gate resistor Rg to sense the sensing node N. sense Gate-emitter voltage V at the point GE As mentioned above, with the collector current I... c Decrease, Miller voltage (gate-emitter voltage V) GE The value decreases. Therefore, it can be used for the same reasons as described above (e.g., to detect when the Miller phase ends, to record the Miller voltage as an adjustment V). gdp and / or V gdn The feedback information, and the voltage at the output of the gate resistor Rg, are used to determine when to activate clamping.

[0054] Depending on the configuration, converter 12 or 13 can be a boost-buck converter, a boost converter, or a buck converter. It will also be appreciated that, depending on the application, only one of converter 12 or 13 may be implemented in the gate voltage control circuit 100.

[0055] Gate voltage control circuit 100 includes a blocking capacitor C coupled to the output of the corresponding converter 12 or converter 13. gdp and C gdn Blocking capacitor C gdp and C gdn It is configured to stabilize the output of its corresponding converter 12 or 13 and provide a sufficient storage pool for supplying the converter voltage to the gate of transistor M1.

[0056] Dashed line Sense-V gdp and Sense-V gdn These indicate optional electrical connections. Specifically, they might be sensing lines for each of converters 12 and 13 to measure each blocking capacitor C. gdp and C gdn The voltage across the two ends (i.e., to measure the voltage V respectively) gdp and voltage V gdn Then, converter 12 may include a sensor based on the Sense-V sensor line. gdp The measured voltage V gdp A feedback control loop is used to ensure voltage V gdpIt is positioned at a desired level indicated by the SRC-On control signal, and its output voltage is adjusted accordingly if there is a deviation from this level. Similarly, converter 13 may include a voltage based on the Sense-V signal from the sensing line. gdn The measured voltage V gdn A feedback control loop is used to ensure voltage V gdn It is at the desired level indicated by the SRC-Off control signal, and if the voltage V gdn If there is a deviation from the desired level, its output voltage is adjusted accordingly. (In the absence of a sensing line, Sense-V...) gdp and Sense-V gdn In this case, converters 12 and 13 can perform open-loop control on their output voltage.

[0057] The gate driver IC 10 includes a switch S1 coupled to a load path terminal supplying FET Q1 and configured to switchably couple FET Q1 to one of two positive rail voltage sources based on switch position 1a or switch position 1b. The positive rail voltage source includes a positive power rail V that provides a fixed positive rail voltage. pos and provides a modulated positive rail voltage V generated based on a fixed positive rail voltage. gdp Positive voltage converter 12.

[0058] Positive voltage converter 12 is configured to draw voltage from positive power rail V pos It receives a fixed positive rail voltage and converts the fixed positive rail voltage to a higher or lower voltage based on a slew rate control (SRC) turn-on control signal. The SRC turn-on control signal can be provided by an external controller (not shown) and can include setting the voltage output value V of the positive voltage converter 12. gdp Information such as voltage amplitude level. If faster switching of transistor M1 is desired, positive voltage converter 12 can be configured to convert a fixed positive rail voltage to a higher voltage (larger voltage). On the other hand, if slower switching of transistor M1 is desired, positive voltage converter 12 can be configured to convert a fixed positive rail voltage to a lower voltage (smaller positive voltage).

[0059] The gate driver IC 10 also includes a switch S2, which is coupled to the load path terminal of the pull-up FET Q2 and configured to switchably couple the pull-up FET Q2 to one of two negative rail voltage sources based on switch position 2a or switch position 2b. The negative rail voltage source includes a negative power rail V that provides a fixed negative rail voltage. neg and provides a modulated negative rail voltage V generated based on a fixed negative rail voltage. gdn The negative voltage converter 13.

[0060] The negative voltage converter 13 is configured to draw voltage from the negative power rail V. neg It receives a fixed negative rail voltage and converts it to a higher or lower voltage based on an SRC shutdown control signal. The SRC shutdown control signal can be provided by an external controller (not shown) and can include setting the voltage output value V of the negative voltage converter 13. gdn Information such as voltage amplitude level. If faster switching of transistor M1 is desired, negative voltage converter 13 can be configured to convert the fixed negative rail voltage to a lower voltage (a negative voltage with a larger absolute value). On the other hand, if slower switching of transistor M1 is desired, negative voltage converter 13 can be configured to convert the fixed negative rail voltage to a higher voltage (a negative voltage with a smaller absolute value).

[0061] The external controller is also configured to provide one or more PWM control signals to the control logic 14, which includes control circuitry, of the gate driver IC. The control logic 14 includes receiving the PWM control signals and, based on the PWM control signals, controlling the on / off states of the supply FET Q1 and the sink FET Q2 to generate the gate current I. g (i.e., the circuitry for gate current Io+ or gate current Io-). Control logic 14 also transmits control logic via control line S1. ctrl and S2 ctrl Control signals are provided to switches S1 and S2 to be based on the sensing terminal Sense-V. ge The sensed voltage is received and the clamping control circuit controls their respective switching states / positions.

[0062] Voltage converters 12 and 13 can be configured to perform V0 operation respectively before the Miller phase (e.g., upon triggering an on or off switching event). gdp and V gdn The pre-regulation, and maintains the regulated voltage V throughout the Miller event, and even for most of the switching event. gdp V gdn Constant. Additionally, voltage converters 12 and 13 can change V pulse-by-pulse (i.e., for each PWM pulse) and thus for each discrete switching event. gdp and V gdn .

[0063] Even during switching events (i.e., turn-on transients or turn-off transients), the gate drive voltage may be higher or lower than the supply voltage of the gate driver IC during the transient interval of the gate voltage. However, the voltage level during static turn-on or static turn-off states (i.e., during the clamping interval) can still be the supply voltage level V. pos and V negThe static on-state is defined by the interval between the gate voltage turn-on transient and the transistor being fully on. In the static on-state, the gate voltage is clamped to V by coupling switch S1 to position 1a. pos Similarly, the static turn-off state is defined by the interval during which the transistor is fully turned off after a gate voltage turn-off transient. In the static turn-off state, the gate voltage is clamped to V by coupling switch S2 to position 2a. neg .

[0064] Figure 3A This is a timing diagram of switches S1 and S2 based on PWM control signals according to one or more embodiments. When the switch is in position 1b, the control pulse for switch S1 is high. The length of this control pulse can be based on the desired V. GE The rise time is adjusted. Similarly, when the switch is in position 2b, the control pulse for switch S2 is high. The length of this control pulse can be based on V. GE The descent time is adjusted. The length T of the switch control pulse... S1 and T S2 It is possible to use a comparator at the Sense-V sensing terminal. ge Gate voltage V measured at [location] GE Or it can be adjusted based on a pre-configured time period using a timer.

[0065] Figure 3B It is a signal diagram of the gate drive voltage for a boost-buck converter according to one or more embodiments, wherein V gdp1 Vgdp2 and V are different positive gate drive voltages, and V gdn1 and V gdn2 These are different negative gate drive voltages.

[0066] Figure 4 A schematic block diagram of control logic 14 for a gate driver IC 10 according to one or more embodiments is shown. Control logic 14 includes logic circuitry 41 that receives PWM control signals and, based on control signal Q1, etc. ctrl and Q2 ctrl To control the supply of FET Q1 and the absorption of FET Q2.

[0067] Control logic 14 also includes clamping control circuitry, which includes logic circuitry 41 and two comparators 42 and 43. The clamping control circuitry is configured to... sense Receiver gate-emitter voltage V GE To determine the control decisions used for switches S1 and S2.

[0068] For example, the clamping control circuit may include a first comparator 42, which receives a sensed voltage V at its non-inverting terminal. GE And receives a positive reference voltage V at its inverting terminal. pos -X, where X is a predetermined voltage amount. Therefore, the positive reference voltage is set to be greater than the positive power rail V. pos The fixed voltage is small by a factor of X. When the sensed voltage V... GE When the voltage is greater than the positive reference voltage, the logic is configured to switch S1 from switch position 1b to switch position 1a, so that the gate of transistor M1 is not overcharged (i.e., to prevent the gate from being charged beyond the positive power rail V). pos ). Here, that is to say, once the sensed voltage V GE If the voltage is greater than the positive reference voltage, the gate drive voltage will be clamped to the supply voltage V. pos Otherwise, switch S1 is set to switch position 1b. Therefore, the gate voltage V during the switch-on event... GE During the transient interval, including before and after the Miller phase, switch S1 is set to switch position 1b until V GE It is equal to or substantially equal to the positive reference voltage, where substantially equal is protected by the positive reference voltage. That is, after switch S1 changes position from 1b to 1a, the gate can still be protected by the positive reference voltage V. pos -X slowly charges to a fixed supply voltage V pos Until it reaches the fixed power supply voltage V pos If X = 0, then the gate voltage V at the turn-on event... GE During the entire transient interval, switch S1 is set to position 1b. On the other hand, if X is greater than zero, although after the Miller phase, during the transient interval (i.e., before the static state), switch S1 changes position from 1b to 1a. Therefore, switch S1 can be set to position 1b close to V. GE At the end of the transient interval (i.e., at V) pos (At some voltage point between the Miller platform and the voltage source) it is coupled to a fixed supply voltage V. pos .

[0069] The positive reference voltage can be set to represent the level at which the gate transient is complete and the transistor is fully turned on. Furthermore, overcharging the gate may increase the risk of a short circuit. Therefore, once the transistor is fully turned on, the gate of transistor M1 is clamped to the positive power rail V. pos This reduces the risk of short circuits.

[0070] The clamping control circuit may further include a second comparator 43, which receives the sensed voltage V at its inverting terminal. GE And receives a negative reference voltage V at its non-inverting terminal. neg+X, where X is a predetermined voltage amount. Therefore, the negative reference voltage is set to be greater than the negative power rail V. neg The fixed voltage is a large amount of X (a negative voltage with a small absolute value). When the sensed voltage V GE When the voltage is smaller than the negative reference voltage (a negative voltage with a larger absolute value), the logic is configured to switch S2 from switch position 2b to switch position 2a, so that the gate of transistor M1 is not overcharged (i.e., to prevent the gate from being charged to a value greater than the negative power rail V). neg Smaller (larger absolute negative voltage)). That is to say, once the sensed voltage V... GE If the voltage is smaller than the negative reference voltage (a negative voltage with a larger absolute value), the gate drive voltage will be clamped to the supply voltage V. neg Otherwise, switch S2 is set to switch position 2b. Therefore, the gate voltage V used for the switch-off event... GE During the transient interval, including before and after the Miller phase, switch S2 is set to switch position 2b until V GE It is equal to or substantially equal to the negative reference voltage, where substantially equal is protected by the negative reference voltage. That is, after switch S2 changes position from 2b to 2a, the gate can still be protected from the negative reference voltage V. neg +X slowly discharges to a fixed supply voltage V. neg Until it reaches the fixed power supply voltage V neg If X = 0, then the gate voltage V at the turn-off event... GE During the entire transient interval, switch S2 is set to position 2b. On the other hand, if X is greater than zero, although after the Miller phase, switch S2 changes its position from 2b to 2a during the transient interval (i.e., before the static state). Therefore, switch S2 can be close to V. GE At the end of the transient interval (i.e., at V) neg (At some voltage point between the Miller platform and the voltage source) it is coupled to a fixed supply voltage V. neg .

[0071] The negative reference voltage can be set to represent the level at which the gate transient is complete and the transistor is fully turned off. Therefore, once the transistor is fully turned off, the gate of transistor M1 is clamped to the negative power rail V. neg This reduces the risk of overcharging transistor M1.

[0072] Figure 5 A schematic block diagram of control logic 14 for a gate driver IC 10 according to one or more embodiments is shown. Control logic 14 includes logic circuitry 41 that receives PWM control signals and uses control signal Q1 based on them respectively. ctrl and Q2 ctrl To control the supply of FET Q1 and the absorption of FET Q2.

[0073] Control logic 14 also includes clamping control circuitry, which comprises logic circuitry 41 and two timers 52 and 53. Therefore, gate driver IC 10 can use timers 52 and 53 to control switches S1 and S2. As a result, as described above, timers 52 and 53 are used to switchably couple the supply FET Q1 and the pull FET Q2 to either the corresponding modulation rail voltage or the corresponding fixed rail voltage.

[0074] Specifically, timers 52 and 53, combined with edge-triggered (rising and / or falling edge) pulses based on the PWM control signal, can be used by control logic 14 to control the switching positions of switches S1 and S2. Control circuit 41 is configured to trigger the start of timers 52 and 53 based on edge-triggered PWM control signals, and timers 52 and 53 are configured to generate the switch control signal S1 based on a predetermined time interval. ctrl or S2 ctrl .

[0075] For example, when control logic 14 detects the rising edge of the PWM control signal, it couples switch S1 to position 1b (i.e., to the modulated positive rail voltage V). gdp The timer 52 switches switch S1 from position 1b to position 1a after a first predetermined time period tracked by timer 52. Logic circuit 41 can trigger the start of timer 52 upon detecting the rising edge of the PWM signal. In response to the trigger signal, timer 52 starts counting and also uses the switch control signal S1. ctrl Ensure switch S1 is in position 1b until a first predetermined time period has elapsed. Then, after the first predetermined time period has elapsed, timer 52 changes the switch control signal S1. ctrl This causes switch S1 to change from position 1b to position 1a.

[0076] Similarly, when the falling edge of the PWM control signal is detected, control logic 14 couples switch S2 to position 2b (i.e., coupled to the modulated negative rail voltage V). gdn The switch S2 is switched from position 2b to position 2a after a second predetermined time period tracked by timer 53. Logic circuit 41 can trigger the start of timer 53 upon detecting a falling edge of the PWM signal. In response to the trigger signal, timer 53 starts counting and also uses the switch control signal S2. ctrl Ensure switch S2 is in position 2b until a second predetermined time period has elapsed. Then, after the second predetermined time period has elapsed, timer 53 changes the switch control signal S2. ctrl This causes switch S2 to change from position 2b to position 2a.

[0077] For each switch S1 and S2, the first predetermined time period and the second predetermined time period can be independently configurable, and therefore the time periods of each switch can be different from each other.

[0078] Instead of a single PWM control signal, there can be a first dedicated control signal for turning on power transistor M1 (i.e., turning on supply FET Q1) and a second dedicated control signal for turning off power transistor M1 (i.e., turning on sucker FET Q2). In this case, control logic 14 couples switch S1 to position 1b (i.e., coupled to the modulated positive rail voltage V) when it detects the rising edge of the first dedicated control signal. gdp The switch S1 is switched from position 1b to position 1a after a first predetermined time period tracked by timer 52. Timer 52 is started when the rising edge of the first dedicated control signal is detected.

[0079] Additionally, when the rising edge of the second dedicated control signal is detected, control logic 14 couples switch S2 to position 2b (i.e., coupled to the modulated negative rail voltage V). gdn The switch S2 is switched from position 2b to position 2a after a second predetermined time period has elapsed. The second predetermined time period may be the same as or different from the first predetermined time period tracked by timer 53. Timer 53 is started when the rising edge of the second dedicated control signal is detected.

[0080] Figure 6 and Figure 7 A schematic block diagram of a gate voltage control circuit with self-adjusting feedback correction according to one or more embodiments is shown. Besides Figure 6 and Figure 7 In addition to the self-adjusting feedback correction function using sensor 60, Figure 6 The gate voltage control circuit 600 shown and Figure 7 The gate voltage control circuit 700 shown is... Figure 1 The gate voltage control circuit 100 shown is similar.

[0081] The self-adjusting feedback correction function is a control function that automatically updates the SRC on and SRC off states of two input control signals, and can, for example... Figure 6 and Figure 7 The implementation is shown. The input signal for the control function can be temperature, such as heat sink temperature, power transistor temperature, or load information, such as shunt voltage level or other load current sensor information. Therefore, sensor 60 can include one or more temperature sensors, current sensors, or voltage sensors configured to measure the corresponding physical characteristics and provide sensor information to the converter control circuit. Figure 6The external controller 61 shown, or as... Figure 7 Converters 12 and 13 are shown.

[0082] For example, self-regulating feedback correction can be based on the operating temperature of the power transistor. Typically, hotter transistors switch more slowly, and colder transistors switch more quickly. Therefore, the temperature can be measured, and the gate drive voltage can be adjusted by regulating the corresponding rail voltage.

[0083] exist Figure 6 In this configuration, the external controller 61 can directly modulate the SRC turn-on control signal using the received sensor information. In this case, the external controller can receive temperature or load information from the sensor 60 and directly adjust the voltage level (amplitude) information of the SRC turn-on control signal to set the output of the converter 12.

[0084] Similarly, the external controller 61 can directly adjust the SRC shutdown control signal using the received sensor information. In this case, the external controller can receive temperature or load information from the sensor 60 and directly adjust the voltage level (amplitude) information of the SRC shutdown control signal to set the output of the converter 13.

[0085] Alternative locations, such as Figure 7 As shown, each converter 12 and 13 can adjust its output based on temperature or load information received from sensor 60 and voltage level (amplitude) information received in the corresponding SRC control signal. In this way, each converter 12 and 13 calculates a correction for the voltage level (amplitude) of the converter output based on the sensor information and the voltage level (amplitude) information provided in the SRC control signal to achieve the desired switching speed for the power transistor M1. This can be accomplished by converters 12 and 13, for example, using a lookup table or implementing a control algorithm.

[0086] Based on the above, the input PWM pulse triggers switch S1 to convert the positive gate drive voltage V gdp Connect to Q1. Switch S1 remains in this position until the switching transient of power transistor M1 is complete. Then, switch S1 connects the gate of power transistor M1 to the power supply voltage V. pos And clamp it. This ensures two advantages: reduced Qg losses; and ensures sufficient on-state gate voltage and short-circuit capability of the power transistor.

[0087] This also applies to the turn-off sequence using switch S2. The input PWM turn-off signal triggers switch S2 to switch the source of FET Q2 to the negative gate drive voltage V. gdn Connection. When the gate voltage level reaches a level below the gate-source threshold voltage, S2 is connected to the negative power supply voltage V.neg This also reduces Qg losses and provides sufficient gate voltage in the off-state.

[0088] The adjustment of the effective gate drive voltage by means of two active converters results in a change in the gate current amplitude. This is in Figure 3B Gate current signal I in g The timing is indicated in the diagram. The steeper the rise / fall of the gate voltage, the faster the power transistor switches. The decision to change S1 or S2 can be derived from the comparator or timer, or both.

[0089] The following additional implementation methods are provided:

[0090] 1. A gate driver circuit, comprising: a first power rail configured to provide a first fixed power supply voltage; a second power rail configured to provide a second fixed power supply voltage; a transistor including a gate terminal having a gate voltage; a gate driver integrated circuit (IC) provided with the first fixed power supply voltage and the second fixed power supply voltage, the gate driver IC including an output terminal coupled to the gate terminal of the transistor and configured to provide a gate drive voltage at the output terminal to drive the transistor between switching states; and a gate resistor coupled between the output terminal of the gate driver IC and the gate terminal of the transistor, wherein the gate resistor defines a gate current based on the gate drive voltage and the gate voltage, wherein the gate driver IC further comprises: a first voltage converter configured to receive the first fixed power supply voltage and modulate the amplitude of the first fixed power supply voltage to generate a first modulated power supply voltage; and a first switch configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC to regulate the gate drive voltage.

[0091] 2. The gate driver circuit according to embodiment 1, wherein the first switch is configured to selectively couple a first fixed power supply voltage and a first modulated power supply voltage to the output terminal of the gate driver IC to adjust the gate current.

[0092] 3. The gate driver circuit according to embodiment 1, wherein the gate driver IC further includes: a controller configured to control a first switch such that during a transient interval of the gate voltage during a first switching event of the transistor, the first switch is coupled to a first modulated power supply voltage, and to control the first switch such that during a first static state of the gate voltage, the first static state is coupled to a first fixed power supply voltage adjacent to the transient interval.

[0093] 4. The gate driver circuit according to embodiment 3, wherein the controller is configured to control the first switch such that the first switch is coupled to the first modulation power supply voltage during the Miller phase of the transient interval of the gate voltage during the first switching event.

[0094] 5. The gate driver circuit according to embodiment 3, wherein: the controller is configured to receive a PWM control signal and drive a transistor between switching states based on the PWM control signal, and the controller is configured to detect the pulse edge of the PWM control signal and control a first switch such that the first switch is coupled to a first modulation power supply voltage in response to detecting the pulse edge.

[0095] 6. The gate driver circuit according to embodiment 5, wherein: the controller includes a timer, and the controller is configured to start the timer and control the first switch in response to detecting a pulse edge, such that the first switch is coupled to a first fixed power supply voltage in response to the timer elapsed through a predetermined time interval.

[0096] 7. The gate driver circuit according to embodiment 5, wherein: the controller is coupled to the gate terminal of the transistor and configured to monitor the gate voltage and compare the monitored gate voltage with a threshold voltage value, and the controller is configured to control a first switch such that the first switch is coupled to a first fixed power supply voltage in response to the monitored gate voltage exceeding the threshold voltage value.

[0097] 8. The gate driver circuit according to embodiment 7, wherein the threshold voltage value is a first fixed power supply voltage.

[0098] 9. The gate driver circuit according to embodiment 7, wherein the amplitude of the threshold voltage value is less than the amplitude of the first fixed power supply voltage.

[0099] 10. The gate driver circuit according to embodiment 1, wherein: the first fixed power supply voltage is a positive fixed power supply voltage, and the first modulated power supply voltage is a modulated positive power supply voltage, and the first switching event is a transistor turn-on switching event.

[0100] 11. The gate driver circuit according to embodiment 1, wherein: the first fixed power supply voltage is a negative fixed power supply voltage, and the first modulated power supply voltage is a modulated negative power supply voltage, and the first switching event is a transistor turn-off switching event.

[0101] 12. The gate driver circuit according to embodiment 1, wherein the first voltage converter is configured to receive a slew rate control (SRC) control signal from an external controller and generate a first modulated power supply voltage based on the voltage amplitude information provided by the SRC control signal.

[0102] 13. The gate driver circuit according to embodiment 12 further includes: a sensor configured to measure the physical characteristics of the gate driver circuit and generate a measurement signal, wherein the first voltage converter is configured to receive the measurement signal from the sensor and generate a first modulated power supply voltage based on the measurement signal and voltage amplitude information provided by the SRC control signal.

[0103] 14. The gate driver circuit according to embodiment 13, wherein the sensor is one of: a temperature sensor configured to measure the temperature associated with the transistor; a voltage sensor configured to measure the load voltage corresponding to the load coupled to the transistor; or a current sensor configured to measure the load current corresponding to the load.

[0104] 15. The gate driver circuit according to embodiment 12 further includes: a sensor configured to measure the physical characteristics of the gate driver circuit and generate a measurement signal; and an external controller configured to receive the measurement signal from the sensor, generate voltage amplitude information based on the measurement signal, and send an SRC control signal including the voltage amplitude information to a first voltage converter.

[0105] 16. The gate driver circuit according to embodiment 1, wherein the gate driver IC further includes: a second voltage converter configured to receive a second fixed power supply voltage and modulate the amplitude of the second fixed power supply voltage to generate a second modulated power supply voltage; and a second switch configured to selectively couple the second fixed power supply voltage and the second modulated power supply voltage to the output terminal of the gate driver IC to adjust the gate drive voltage.

[0106] 17. The gate driver circuit according to embodiment 16, wherein the gate driver IC further includes: a controller configured to: control a first switch such that during a first transient interval of the gate voltage during a first switching event of the transistor, the first switch is coupled to a first modulated power supply voltage, and during a first static state of the gate voltage, the first static state is adjacent to the first transient interval; and control a second switch such that during a second transient interval of the gate voltage during a second switching event of the transistor, the second switch is coupled to a second modulated power supply voltage, and during a second static state of the gate voltage, the second switch is coupled to a second fixed power supply voltage, the second static state is adjacent to the second transient interval.

[0107] 18. The gate driver circuit according to embodiment 17, wherein the controller is configured to: control a first switch such that the first switch is coupled to a first modulation power supply voltage during a first Miller phase of a first transient interval of the gate voltage during a first switching event, and control a second switch such that the second switch is coupled to a second modulation power supply voltage during a second Miller phase of a second transient interval of the gate voltage during a second switching event.

[0108] 19. A method for driving a transistor between switching states in a power circuit, the method comprising: providing a gate drive voltage at an output terminal of a gate driver integrated circuit (IC) to drive the transistor between switching states; providing a first fixed supply voltage and a second fixed supply voltage to the gate driver IC; converting the first fixed supply voltage into a first modulated supply voltage by the gate driver IC; and selectively coupling the first fixed supply voltage and the first modulated supply voltage to the output terminal of the gate driver IC via a first switch to regulate the gate drive voltage.

[0109] 20. The method according to embodiment 19 further includes: controlling a first switch such that during a transient interval of the gate voltage during a first switching event of the transistor, the first switch is coupled to a first modulated power supply voltage; and controlling the first switch such that during a first static state of the gate voltage, the first static state is adjacent to the transient interval.

[0110] 21. The method according to embodiment 20 further includes: controlling the first switch such that the first switch is coupled to the first modulation power supply voltage during the Miller phase of the transient interval of the gate voltage during the first switching event.

[0111] 22. The method according to embodiment 21 further includes: receiving a PWM control signal by a gate driver IC; driving a transistor between switching states by the gate driver IC based on the PWM control signal; detecting a pulse edge of the PWM control signal by the gate driver IC; and controlling a first switch by the gate driver IC such that the first switch is coupled to a first modulation power supply voltage in response to detecting a pulse edge.

[0112] 23. The method according to embodiment 19 further includes: converting a second fixed power supply voltage into a second modulated power supply voltage by a gate driver IC; and selectively coupling the second fixed power supply voltage and the second modulated power supply voltage to the output terminal of the gate driver IC via a second switch to adjust the gate drive voltage.

[0113] 24. The method according to embodiment 23 further includes: controlling a first switch such that during a first transient interval of the gate voltage during a first switching event of the transistor, the first switch is coupled to a first modulated power supply voltage; controlling the first switch such that during a first static state of the gate voltage, the first static state is adjacent to the first transient interval; controlling a second switch such that during a second transient interval of the gate voltage during a second switching event of the transistor, the second switch is coupled to a second modulated power supply voltage; and controlling the second switch such that during a second static state of the gate voltage, the second switch is coupled to a second fixed power supply voltage, the second static state is adjacent to the second transient interval.

[0114] 25. The method according to embodiment 24 further includes: controlling a first switch such that the first switch is coupled to a first modulation power supply voltage during a first Miller phase of a first transient interval of the gate voltage during a first switching event; and controlling a second switch such that the second switch is coupled to a second modulation power supply voltage during a second Miller phase of a second transient interval of the gate voltage during a second switching event.

[0115] 26. A gate driver comprising: a first terminal configured to receive a first fixed power supply voltage; a second terminal configured to receive a second fixed power supply voltage; an output terminal configured to provide a gate drive voltage to drive a transistor between switching states; a first voltage converter configured to receive the first fixed power supply voltage and modulate the amplitude of the first fixed power supply voltage to generate a first modulated power supply voltage; and a first switch configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal to regulate the gate drive voltage.

[0116] 27. The gate driver according to embodiment 26 further includes: a controller configured to control a first switch such that during a transient interval of the gate voltage of the transistor during a first switching event of the transistor, the first switch is coupled to a first modulated power supply voltage; and to control the first switch such that during a first static state of the gate voltage, the first static state is coupled to a first fixed power supply voltage adjacent to the transient interval.

[0117] 28. The gate driver according to embodiment 27, wherein the controller is configured to control the first switch such that the first switch is coupled to the first modulation power supply voltage during the Miller phase of the transient interval of the gate voltage during the first switching event.

[0118] 29. The gate driver according to embodiment 27, wherein: the controller is configured to receive a PWM control signal and drive a transistor between switching states based on the PWM control signal, and the controller is configured to detect a pulse edge of the PWM control signal and control a first switch such that the first switch is coupled to a first modulation power supply voltage in response to the detection of a pulse edge.

[0119] 30. The gate driver according to embodiment 29, wherein: the controller includes a timer, and the controller is configured to start the timer and control a first switch in response to detecting a pulse edge, such that the first switch is coupled to a first fixed power supply voltage in response to the timer elapsed through a predetermined time interval.

[0120] 31. The gate driver according to embodiment 29, wherein: the controller is configured to monitor the gate voltage and compare the monitored gate voltage with a threshold voltage value, and the controller is configured to control a first switch such that the first switch is coupled to a first fixed power supply voltage in response to the monitored gate voltage exceeding the threshold voltage value.

[0121] 32. The gate driver according to embodiment 26 further includes: a second voltage converter configured to receive a second fixed power supply voltage and modulate the amplitude of the second fixed power supply voltage to generate a second modulated power supply voltage; and a second switch configured to selectively couple the second fixed power supply voltage and the second modulated power supply voltage to the output terminal of the gate driver IC to adjust the gate drive voltage.

[0122] 33. The gate driver according to embodiment 32 further includes: a controller configured to: control a first switch such that during a first transient interval of the gate voltage of the transistor during a first switching event of the transistor, the first switch is coupled to a first modulated power supply voltage, and during a first static state of the gate voltage, the first static state is adjacent to the first transient interval; and control a second switch such that during a second transient interval of the gate voltage during a second switching event of the transistor, the second switch is coupled to a second modulated power supply voltage, and during a second static state of the gate voltage, the second switch is coupled to a second fixed power supply voltage, the second static state is adjacent to the second transient interval.

[0123] 34. The gate driver according to embodiment 33, wherein the controller is configured to: control a first switch such that the first switch is coupled to a first modulation power supply voltage during a first Miller phase of a first transient interval of the gate voltage during a first switching event, and control a second switch such that the second switch is coupled to a second modulation power supply voltage during a second Miller phase of a second transient interval of the gate voltage during a second switching event.

[0124] Although various implementations have been described, it will be apparent to those skilled in the art that many more implementations and methods are possible within the scope of this disclosure. For example, other methods may exist to determine V. GE The slope. Therefore, the invention is not limited except as provided in the appended claims and their equivalents. Regarding the various functions performed by the aforementioned components or structures (components, devices, circuits, systems, etc.), unless otherwise stated, the terminology used to describe such components (including references to “device”) is intended to correspond to any component or element that performs the specified function of the described component (i.e., is functionally equivalent), even if it is not structurally equivalent to the disclosed component that performs that function in the exemplary implementation of the invention shown herein.

[0125] Furthermore, the appended claims are hereby incorporated into the detailed description, wherein each claim may stand alone as an independent illustrative embodiment. While each claim may stand alone as a separate illustrative embodiment, it should be noted that although dependent claims may refer in the claim to a specific combination of one or more other claims, other illustrative embodiments may also include combinations of dependent claims with the subject matter of each of the other dependent or independent claims. Such combinations are presented herein unless otherwise indicated. Furthermore, it is intended that the features of the claims be included in any other independent claim, even if that claim is not directly incorporated into the independent claim.

[0126] It should also be noted that the methods disclosed in the specification or claims can be implemented by a device having means for performing the various actions of these methods.

[0127] Furthermore, it should be understood that the disclosure of multiple actions or functions in the specification or claims is not to be construed as being in a particular order. Therefore, the disclosure of multiple actions or functions will not limit them to a specific order unless these actions or functions are not interchangeable for technical reasons. Additionally, in some embodiments, a single action may include or may be divided into multiple sub-actions. Unless expressly excluded, such sub-actions may be included within and are part of the disclosure of the single action.

[0128] The techniques described in this disclosure can be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, aspects of the described techniques can be implemented within one or more processors, including one or more microprocessors, central processing units (CPUs), analog-to-digital converters, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or any other equivalent integrated or discrete logic circuits, and any combination of such components.

[0129] The terms "processor" and "processing circuit" are used interchangeably and can generally refer to any of the aforementioned logic circuits, alone or in combination with other logic circuits, or any other equivalent circuit suitable for implementing the techniques described herein. Additionally, two or more of the aforementioned processing units (e.g., correction factor units, gate control units, and comparator circuits) can be combined into fewer processing units and incorporated into a single processor. However, each processing unit may have its own corresponding sub-processor or processing circuit.

[0130] The control unit, including hardware, may also execute one or more of the techniques described in this disclosure, and may further include a processor or suitable processing circuitry. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described in this disclosure.

[0131] Although various exemplary embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made to achieve some of the advantages of the concepts disclosed herein without departing from the spirit and scope of the invention. It will also be apparent to those skilled in the art that other components performing the same function can be suitably replaced. It should be understood that other embodiments can be utilized, and structural or logical changes can be made, without departing from the scope of the invention. It should be mentioned that features described with reference to specific drawings may be combined with features of other drawings, even if not explicitly mentioned. Such modifications to the general inventive concept are intended to be covered by the appended claims and their legal equivalents.

Claims

1. A gate driver circuit, comprising: A first power rail is configured to provide a first fixed power supply voltage; The second power rail is configured to provide a second fixed power supply voltage; A transistor, which includes a gate terminal having a gate voltage; A gate driver integrated circuit (IC) is provided with a first fixed power supply voltage and a second fixed power supply voltage. The gate driver IC includes an output terminal coupled to the gate terminal of the transistor and is configured to provide a gate drive voltage at the output terminal to drive the transistor between switching states. as well as A gate resistor is coupled between the output terminal of the gate driver IC and the gate terminal of the transistor, wherein the gate resistor defines the gate current based on the gate drive voltage and the gate voltage; The gate driver IC further includes: A first voltage converter is configured to receive the first fixed power supply voltage and modulate the amplitude of the first fixed power supply voltage to generate a first modulated power supply voltage; and A first switch is configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC to adjust the gate drive voltage. Wherein, the first switch is configured to couple the first modulated power supply voltage to the gate terminal of the transistor during a first switching event of the transistor, the transistor transitioning from a first state to a second state during the first switching event, and wherein, the first switch is configured to couple the first fixed power supply voltage to the gate terminal of the transistor during the second state of the transistor.

2. The gate driver circuit according to claim 1, wherein, The first switch is configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC to regulate the gate current.

3. The gate driver circuit according to claim 1, wherein, The gate driver IC also includes: A controller is configured to control the first switch such that during a transient interval of the gate voltage during the first switching event of the transistor, the first switch is coupled to the first modulated power supply voltage, and to control the first switch such that during a first static state of the gate voltage, the first static state is adjacent to the transient interval.

4. The gate driver circuit according to claim 3, wherein, The controller is configured to control the first switch such that during the Miller phase of the transient interval of the gate voltage during the first switching event, the first switch is coupled to the first modulated power supply voltage.

5. The gate driver circuit according to claim 3, wherein: The controller is configured to receive a PWM control signal and drive the transistor between the switching states based on the PWM control signal. The controller is configured to detect the pulse edge of the PWM control signal and control the first switch such that, in response to detecting the pulse edge, the first switch is coupled to the first modulated power supply voltage.

6. The gate driver circuit according to claim 5, wherein: The controller includes a timer, and The controller is configured to start the timer and control the first switch in response to detecting the pulse edge, such that the first switch is coupled to the first fixed power supply voltage in response to the timer elapsed a predetermined time interval.

7. The gate driver circuit according to claim 5, wherein: The controller is coupled to the gate terminal of the transistor and configured to monitor the gate voltage and compare the monitored gate voltage with a threshold voltage value. The controller is configured to control the first switch such that, in response to a monitored gate voltage exceeding the threshold voltage value, the first switch is coupled to the first fixed power supply voltage.

8. The gate driver circuit according to claim 7, wherein, The threshold voltage value is the first fixed power supply voltage.

9. The gate driver circuit according to claim 7, wherein, The amplitude of the threshold voltage value is less than the amplitude of the first fixed power supply voltage.

10. The gate driver circuit according to claim 3, wherein: The first fixed power supply voltage is a positive fixed power supply voltage, and the first modulated power supply voltage is a modulated positive power supply voltage; and The first switching event is the transistor's on / off switching event.

11. The gate driver circuit according to claim 1, wherein: The first fixed power supply voltage is a negative fixed power supply voltage, and the first modulated power supply voltage is a modulated negative power supply voltage. The first switching event is the transistor's turn-off switching event.

12. The gate driver circuit according to claim 1, wherein, The first voltage converter is configured to receive a slew rate control (SRC) signal from an external controller and generate the first modulated power supply voltage based on the voltage amplitude information provided by the SRC control signal.

13. The gate driver circuit according to claim 12, further comprising: A sensor configured to measure the physical characteristics of the gate driver circuit and generate a measurement signal; The first voltage converter is configured to receive the measurement signal from the sensor and generate the first modulated power supply voltage based on the measurement signal and the voltage amplitude information provided by the SRC control signal.

14. The gate driver circuit according to claim 13, wherein, The sensor is one of the following: a temperature sensor configured to measure the temperature associated with the transistor; a voltage sensor configured to measure a load voltage corresponding to a load coupled to the transistor; or a current sensor configured to measure a load current corresponding to the load.

15. The gate driver circuit according to claim 12, further comprising: A sensor configured to measure the physical characteristics of the gate driver circuit and generate a measurement signal; as well as An external controller is configured to receive the measurement signal from the sensor, generate the voltage amplitude information based on the measurement signal, and send the SRC control signal including the voltage amplitude information to the first voltage converter.

16. A gate driver circuit, comprising: A first power rail is configured to provide a first fixed power supply voltage; The second power rail is configured to provide a second fixed power supply voltage; A transistor, which includes a gate terminal having a gate voltage; A gate driver integrated circuit (IC) is provided with a first fixed power supply voltage and a second fixed power supply voltage. The gate driver IC includes an output terminal coupled to the gate terminal of the transistor and is configured to provide a gate drive voltage at the output terminal to drive the transistor between switching states. as well as A gate resistor is coupled between the output terminal of the gate driver IC and the gate terminal of the transistor, wherein the gate resistor defines the gate current based on the gate drive voltage and the gate voltage; The gate driver IC further includes: A first voltage converter is configured to receive the first fixed power supply voltage and modulate the amplitude of the first fixed power supply voltage to generate a first modulated power supply voltage. A first switch is configured to selectively couple the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC to adjust the gate drive voltage; A second voltage converter is configured to receive the second fixed power supply voltage and modulate the amplitude of the second fixed power supply voltage to generate a second modulated power supply voltage; and A second switch is configured to selectively couple the second fixed power supply voltage and the second modulated power supply voltage to the output terminal of the gate driver IC to regulate the gate drive voltage.

17. The gate driver circuit according to claim 16, wherein, The gate driver IC also includes: The controller is configured to: The first switch is controlled such that during a first transient interval of the gate voltage during a first switching event of the transistor, the first switch is coupled to the first modulated power supply voltage, and during a first static state of the gate voltage, the first static state is coupled to the first transient interval. The second switch is controlled such that during a second transient interval of the gate voltage during a second switching event of the transistor, the second switch is coupled to the second modulated power supply voltage, and during a second static state of the gate voltage, the second static state is coupled to the second transient interval.

18. The gate driver circuit according to claim 17, wherein, The controller is configured to: Control the first switch such that during the first Miller phase of the first transient interval of the gate voltage during the first switching event, the first switch is coupled to the first modulated power supply voltage, and The second switch is controlled such that during the second Miller phase of the second transient interval of the gate voltage during the second switching event, the second switch is coupled to the second modulated power supply voltage.

19. A method for driving a transistor between switching states in a power circuit, the method comprising: A gate drive voltage is provided at the output terminal of the gate driver integrated circuit IC to drive the transistor between switching states; A first fixed power supply voltage and a second fixed power supply voltage are provided to the gate driver IC; The gate driver IC converts the first fixed power supply voltage into a first modulated power supply voltage. as well as The gate driver IC selectively couples the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC via a first switch to adjust the gate drive voltage. Specifically, during a first switching event of the transistor, the first modulated power supply voltage is coupled to the gate terminal of the transistor, the transistor transitions from a first state to a second state during the first switching event, and during the second state of the transistor, the first fixed power supply voltage is coupled to the gate terminal of the transistor.

20. The method of claim 19, further comprising: The first switch is controlled such that during the transient interval of the gate voltage during the first switching event of the transistor, the first switch is coupled to the first modulated power supply voltage. as well as The first switch is controlled such that during a first static state of the gate voltage, the first switch is coupled to the first fixed power supply voltage, the first static state being adjacent to the transient interval.

21. The method of claim 20, further comprising: The first switch is controlled such that during the Miller phase of the transient interval of the gate voltage during the first switching event, the first switch is coupled to the first modulated power supply voltage.

22. The method of claim 21, further comprising: The gate driver IC receives the PWM control signal; The gate driver IC drives the transistor between the switching states based on the PWM control signal; The pulse edge of the PWM control signal is detected by the gate driver IC; as well as The first switch is controlled by the gate driver IC such that it is coupled to the first modulated power supply voltage in response to the detection of the pulse edge.

23. A method for driving a transistor between switching states in a power circuit, the method comprising: A gate drive voltage is provided at the output terminal of the gate driver integrated circuit IC to drive the transistor between switching states; A first fixed power supply voltage and a second fixed power supply voltage are provided to the gate driver IC; The gate driver IC converts the first fixed power supply voltage into a first modulated power supply voltage. The gate driver IC selectively couples the first fixed power supply voltage and the first modulated power supply voltage to the output terminal of the gate driver IC via a first switch to adjust the gate drive voltage; The gate driver IC converts the second fixed power supply voltage into a second modulated power supply voltage; as well as The gate driver IC selectively couples the second fixed power supply voltage and the second modulated power supply voltage to the output terminal of the gate driver IC via a second switch to adjust the gate drive voltage.

24. The method of claim 23, further comprising: Control the first switch such that during a first transient interval of the gate voltage during a first switching event of the transistor, the first switch is coupled to the first modulated power supply voltage. The first switch is controlled such that during a first static state of the gate voltage, the first switch is coupled to the first fixed power supply voltage, the first static state being adjacent to the first transient interval. Control the second switch such that during the second transient interval of the gate voltage during the second switching event of the transistor, the second switch is coupled to the second modulated power supply voltage; as well as The second switch is controlled such that during the second static state of the gate voltage, the second switch is coupled to the second fixed power supply voltage, the second static state being adjacent to the second transient interval.

25. The method of claim 24, further comprising: The first switch is controlled such that during the first Miller phase of the first transient interval of the gate voltage during the first switching event, the first switch is coupled to the first modulated power supply voltage. as well as The second switch is controlled such that during the second Miller phase of the second transient interval of the gate voltage during the second switching event, the second switch is coupled to the second modulated power supply voltage.

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