An adaptive phase correction and data automatic alignment system for uncooled infrared movement

Abstract

The present invention discloses a non-cooled infrared movement adaptive phase correction and data automatic alignment system, including a detector, a driving module, an FPGA, and a power module. The FPGA sends configuration and correction signals to the detector, thereby providing the correct timing for the normal operation of the detector; the FPGA also performs adaptive clock phase correction and data alignment on the image signal transmitted by the detector, and then performs image processing, which is displayed by a display device. Compared with the prior art, the present invention is automatically executed after the system is turned on, and no human participation is required, thereby improving development efficiency. Since the system has good adaptability to extreme temperature environments, it will greatly improve the environmental adaptability and stability of non-cooled infrared equipment. At the same time, the present invention is also of reference significance to other high-speed AD acquisition scenarios.

Description

Technical Field

[0001] The invention belongs to the technical field of infrared imaging, and in particular relates to a non-cooling infrared core adaptive phase correction and data automatic alignment system. Background Art

[0002] The uncooled infrared core is the core device of infrared imaging. The analog signal output by the infrared core needs to be converted into a digital signal through AD conversion, and then input into the FPGA. After the FPGA performs relevant image algorithm processing, an image that can be discerned by the human eye can be formed.

[0003] According to the number of data storage bits, high-speed AD is divided into multiple resolutions; the more storage bits, the higher the resolution and the larger the data transmission volume. The signal output by AD includes a high-speed data clock DCLK, a low-speed clock FCLK and several data signals DATAn output according to different configurations. In order to ensure the sampling effect, the rising edge of DCLK is aligned with the center of the data, and FCLK is aligned with the edge of the data. Under high-speed and extreme environmental conditions, phase drift is prone to occur due to the fast data transmission rate and high data clock frequency; at the same time, due to the differences in the number of data output channels and lines, the format and order of the output data are not the same. It is necessary to manually test the arrangement of the output data and calibrate and correct it. The process is cumbersome and easily interfered.

[0004] With the development of optoelectronic component technology, the resolution of mainstream infrared cameras has increased from 320x240 to 640x480. The increase in resolution has led to an exponential increase in data transmission rate. Since the clock signal and the data signal are routed differently inside the FPGA, the delays experienced by the clock signal and the data signal will be different. The increase in data transmission rate and the change in external temperature will cause the data sampling clock to deviate from the data center after being input into the FPGA, ultimately leading to sampling errors.

[0005] In response to the drift of the clock phase, the traditional method is to manually set the delay parameters of the FPGA and observe online whether the image output is correct. However, the above method is based on the premise that the byte order of the AD acquisition results has been determined in advance and is only applicable to the current environment. When the environment changes drastically, such as the high and low temperature tests that optoelectronic equipment usually undergoes, the byte order of the AD acquisition results needs to be re-determined and the delay of the data clock needs to be adjusted again.

[0006] Due to differences in data output channels and the number of output lines, the formats of AD output data are not exactly the same, and the order and arrangement of the output data need to be tested, which is a cumbersome process and is easily susceptible to interference.

[0007] The traditional method uses AD test mode to determine the data alignment order. By configuring the AD test mode parameters, each data channel outputs a certain value, and then by comparing the difference between the actual output of each channel and the target output, the arrangement of the output bytes is determined. This is an offline operation method that is only applicable to a specified environment and needs to be re-determined every time the environment changes.

[0008] Whether it is the online adjustment of the clock phase or the offline calibration of the data output byte order, both require human participation throughout the process, are only applicable to the current environment, are inefficient, and have no repeatability in application scenarios. Therefore, there is an urgent need for an uncooled infrared movement adaptive phase correction and data automatic alignment system that can adapt to different temperature environments and perform adaptive operations in different environments, so as to ensure the environmental adaptability of uncooled infrared equipment. Summary of the invention

[0009] In order to solve the defects in the prior art, the present invention provides a non-cooled infrared movement adaptive phase correction and data automatic alignment system.

[0010] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0011] The present invention provides a non-refrigerated infrared movement adaptive phase correction and data automatic alignment system, comprising a detector, a driving module, an FPGA, and a power module. The power module is electrically connected to the driving module and the FPGA respectively to supply power to the driving module and the FPGA. The FPGA is bidirectionally electrically connected to the driving module, and the driving module is also bidirectionally electrically connected to the detector. The FPGA sends configuration and correction signals to the detector, thereby providing correct timing for the normal operation of the detector. The FPGA also performs adaptive clock phase correction and data alignment on an image signal transmitted from the detector, and then performs image processing, which is displayed by a display device.

[0012] As a preferred technical solution of the present invention, the power supply module includes various groups of power supply modules, a video DA conversion module, and a motor power amplifier module; the drive module includes a filter amplifier, an AD converter, and a detector configuration and correction data module; the FPGA includes a controller, a detector configuration data acquisition module, a phase adaptive correction and data alignment module, a video processing module, a focusing motor and a baffle motor control module; the controller is bidirectionally electrically connected to the detector configuration data acquisition module, the output end of the controller is also electrically connected to the input end of the video processing module, the focusing motor and the baffle motor control module, the output end of the detector configuration data acquisition module is electrically connected to the input end of the detector configuration and correction data module, and the output end of the detector configuration and correction data module is electrically connected to the input end of the detector;

[0013] The output end of the detector is electrically connected to the input end of the filter amplifier, the output end of the filter amplifier is electrically connected to the input end of the AD converter, the output end of the AD converter is electrically connected to the input end of the phase adaptive correction and data alignment module, and the output end of the phase adaptive correction and data alignment module is electrically connected to the input end of the detector configuration data acquisition module;

[0014] Each group of power supply modules is electrically connected to the power supply modules of the FPGA and the driving module; the video processing module is electrically connected to the input end of the video DA conversion module, and the output end of the video DA conversion module is electrically connected to the display device; the output end of the focus motor and the baffle motor control module is electrically connected to the motor power amplifier module, and the output end of the motor power amplifier module is electrically connected to the input end of the focus motor and the baffle motor.

[0015] As a preferred technical solution of the present invention, the detector adopts a domestically produced 25µm vanadium oxide detector.

[0016] As a preferred technical solution of the present invention, the configuration and correction signals include a working clock, an integration time, a TEC parameter, and an OCC parameter.

[0017] As a preferred technical solution of the present invention, the phase adaptive correction and data alignment module includes a delay module, a phase sampling module, and a phase adaptive correction state machine. DCLK is electrically connected to the input end of the delay module and the D of the phase sampling module through a buffer IBUFDS. The delay module is used to adjust the delay amount of the input DCLK. The output end of the delay module is electrically connected to the CLK of the phase sampling module through a buffer BUFFIO, and is electrically connected to the CLKDIV of the phase sampling module through a buffer BUFFR. The 8 output ends of the phase sampling module are electrically connected to the input end of the phase adaptive correction state machine, and the 8 output ends are Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8. The output end of the phase adaptive correction state machine is electrically connected to the C, CE, INC, and RST of the delay module, respectively.

[0018] The beneficial effects of the present invention are as follows: compared with the prior art, the present invention is automatically executed after the system is turned on, and no human intervention is required, thereby improving development efficiency. Since the present system has good adaptability to extreme temperature environments, it will greatly improve the environmental adaptability and stability of non-cooled infrared equipment. At the same time, the present invention is also of reference significance to other high-speed AD acquisition scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the overall structure of a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0020] Figure 2It is a structural schematic diagram of a phase adaptive correction and data alignment module in a non-refrigerated infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0021] Figure 3 It is a schematic diagram of crossover area sampling in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0022] Figure 4 It is a schematic diagram of stable area sampling in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0023] Figure 5 The invention discloses a working flow chart of a phase adaptive correction state machine in a non-refrigerated infrared core adaptive phase correction and data automatic alignment system.

[0024] Figure 6 It is a schematic diagram of FCLK sampling results in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0025] Figure 7a It is a schematic diagram of the corresponding combination results of 1100 and 0110 in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0026] Figure 7b It is a schematic diagram of the corresponding combination results of 1100 and 1100 in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0027] Figure 8 It is a schematic diagram of two-wire acquisition results in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0028] Fig. 9 It is a schematic diagram of the phase correction effect in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention.

[0029] Fig.10 It is a schematic diagram of single-wire acquisition results in a non-cooled infrared movement adaptive phase correction and data automatic alignment system of the present invention. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0031] In order to achieve the purpose of the present invention, Figure 1As shown, in one embodiment of the present invention, a non-cooled infrared movement adaptive phase correction and data automatic alignment system is provided, including a detector, a driving module, an FPGA, and a power module. The power module is electrically connected to the driving module and the FPGA respectively to supply power to the driving module and the FPGA. The FPGA is bidirectionally electrically connected to the driving module, and the driving module is also bidirectionally electrically connected to the detector. The FPGA sends configuration and correction signals to the detector, thereby providing the correct timing for the normal operation of the detector; wherein the configuration and correction signals include a working clock, an integration time, TEC parameters, and OCC parameters; while ensuring that the detector can work normally, the FPGA also performs adaptive clock phase correction and data alignment on the image signal transmitted by the detector, and then performs image processing, which is displayed by a display device. AD data acquisition is performed in the driving module, and the sampling result is output in a 16-bit two-wire system.

[0032] Specifically, the detector adopts a domestically produced 25µm vanadium oxide detector, the power module includes various power supply modules, a video DA conversion module, and a motor power amplifier module; the drive module includes a filter amplifier, an AD converter, and a detector configuration and correction data module; the FPGA includes a controller, a detector configuration data acquisition module, a phase adaptive correction and data alignment module, a video processing module, a focusing motor and a baffle motor control module; the controller is bidirectionally electrically connected to the detector configuration data acquisition module, the output end of the controller is also electrically connected to the input end of the video processing module, the focusing motor and the baffle motor control module, the output end of the detector configuration data acquisition module is electrically connected to the input end of the detector configuration and correction data module, and the output end of the detector configuration and correction data module is electrically connected to the input end of the detector;

[0033] The output end of the detector is electrically connected to the input end of the filter amplifier, the output end of the filter amplifier is electrically connected to the input end of the AD converter, the output end of the AD converter is electrically connected to the input end of the phase adaptive correction and data alignment module, and the output end of the phase adaptive correction and data alignment module is electrically connected to the input end of the detector configuration data acquisition module;

[0034] Each group of power supply modules is electrically connected to the power supply modules of the FPGA and the driving module; the video processing module is electrically connected to the input end of the video DA conversion module, and the output end of the video DA conversion module is electrically connected to the display device; the output end of the focus motor and the baffle motor control module is electrically connected to the motor power amplifier module, and the output end of the motor power amplifier module is electrically connected to the input end of the focus motor and the baffle motor.

[0035] like Figure 2As shown, the phase adaptive correction and data alignment module includes a delay module, a phase sampling module, and a phase adaptive correction state machine. DCLK is electrically connected to the input end of the delay module and D of the phase sampling module through a buffer IBUFDS. The delay module is used to adjust the delay amount of the input DCLK. The output end of the delay module is electrically connected to the CLK of the phase sampling module through a buffer BUFFIO, and is electrically connected to the CLKDIV of the phase sampling module through a buffer BUFFR. The 8 output ends of the phase sampling module are electrically connected to the input end of the phase adaptive correction state machine, and the 8 output ends are Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8. The output end of the phase adaptive correction state machine is electrically connected to C, CE, INC, and RST of the delay module, respectively.

[0036] The delay module controls the increase or decrease of the delay through the INC port. The phase sampling module uses DCLK after the buffer BUFFIO - BitClk to sample BitClk_MonClkOut, and the sampling result is output through Q1-Q8; BitClk is DCLK after the buffer IBUFDS. Since all differential signals need to pass through the same IBUFDS, as long as the DCLK is still aligned with the original clock after passing through a series of units, the accuracy of sampling can be guaranteed. The phase adaptive correction state machine is used to determine whether the delayed DCLK is aligned with the BitClk phase, and adopt corresponding strategies to control the delay amount according to different states. The basis for judging whether it is aligned is the result Q1-Q8 of BitClk_MonClkOut sampling BitClk 8 times in a row.

[0037] (1) The working process of the phase adaptive correction state machine is further explained. The working process of the entire phase adaptive correction state machine is as follows: Figure 5 shown.

[0038] Specifically, the sampling results of BitClk to BitClk_MonClkOut have obvious characteristics at different phase differences and can be divided into two categories: stable area sampling and crossover area sampling, such as Figure 3 , Figure 4 shown.

[0039] Crossover area sampling, due to the uncertainty of edge sampling, the output results of Q1-Q8 are different each time. If the value of the sampling result jumps, it can be proved that the phase of BitClk_MonClkOut and BitClk is aligned.

[0040] In the stable region, the values ​​of Q1-Q8 are the same. If the high level is sampled 8 times, Q1-Q8 are all 1; if the low level is sampled 8 times, Q1-Q8 are all 0. In this case, the delay amount needs to be adjusted to find the crossover region so that the BitClk_MonClkOut and BitClk phases are aligned.

[0041] When designing the phase adaptive correction state machine, the DCLK period of 5ns is used as the limit, and the initial delay value is set to 16, which can be divided into the following situations.

[0042] State1: DCLK cycle is less than 5ns, and the delay is reduced by 3 steps. If the initial sampling is in the crossover area, the rising edge or falling edge is determined by the state after reducing the delay by 3 steps, and marked with EDGE, the same below.

[0043] Rising edge: EDGE = 1, initial Q1-Q8 jumps, and after reducing the delay, Q1-Q8 are all 0.

[0044] Falling edge: EDGE = 0, initial Q1-Q8 jumps, and after reducing the delay, Q1-Q8 are all 1.

[0045] State2: DCLK period is less than 5ns. Initially, sampling is in the stable area. Initially, Q1-Q8 are all 1. After the delay is reduced, they are all 0 or sampled in the crossover area to maintain alignment. Initially, Q1-Q8 are all 0. After the delay is reduced, they are all 1 or sampled in the crossover area to maintain alignment.

[0046] State3: The DCLK period is less than 5ns, the initial sampling is in the stable region, the delay is reduced by 3 steps, and the Q1-Q8 values ​​do not change. Then the delay is increased sequentially from 16 (up to 32 times) until the sampling reaches the crossover region or the Q1-Q8 output is reversed to maintain alignment.

[0047] State4: DCLK period is greater than 5ns, initial sampling is in the stable area, delay is reduced by 3 steps, Q1-Q8 values ​​do not change, then delay is increased from 16 (up to 32 times) until the sampling reaches the crossover area or Q1-Q8 output reverses, and alignment is maintained. If no edge is found after 32 adjustments, it means that the DCLK period is much greater than 5ns, and the phase does not need to be adjusted. Set the delay value to the default value of 0.

[0048] (2) The work of automatic data alignment is further explained below.

[0049] The phase requirements of the DCLK edge and the data center are guaranteed by the phase adaptive correction and data alignment module. Using BitClk_MonClkOut to sample data can ensure the accuracy of sampling. Next, the output order of the data needs to be judged and adjusted.

[0050] The present invention changes the byte output sequence test method using the ADC test mode in the past, and determines the position of the sampled data in the data stream by the phase relationship between BitClk_MonClkOut and FCLK. Since FCLK has a good edge alignment relationship with the data when the ADC inputs to the FPGA, Figure 6 As shown, therefore, if FCLK is also regarded as a data input, the order of the output data can be determined by sampling it.

[0051] When sampling, refer to Figure 6 , according to the different data bits sampled on the rising edge, the sampling result of FCLK has four possible values: 1100, 1001, 0011, 0110. Since the phase difference between two adjacent rising edges and falling edges is always 180°, taking the rising edge sampling result of FCLK 1100 as an example, the falling edge sampling result may be 1100 or 0110. Due to the different combination order of the rising edge and the falling edge, there are three combination results, as shown in Figure 7 (a) and Figure 7 (b). For the three cases of 1001, 0011, and 0110 on the rising edge, the same results as Figure 7 (a) and Figure 7 (b) can be obtained by shifting the data, which can be regarded as the same situation.

[0052] The infrared movement used in this experimental platform has a resolution of 640x512, a total number of pixels transmitted in a single frame image of 680x523, a frame rate of 50Hz, and an FCLK clock frequency output to AD of 17.75M; the AD conversion result adopts a four-wire output mode.

[0053] The non-cooled infrared movement adaptive phase correction and data automatic alignment system designed by the present invention makes it possible to transmit AD at a higher rate. After testing, the power consumption and resource occupancy of the entire system in the two-wire and single-wire output modes are shown in Table 1. Compared with the two-wire system, the four-wire system is used to output the data of each channel. The power consumption is 8.7% higher and the IO occupancy is 50% higher; compared with the single-wire output, the power consumption is 16% higher and the IO occupancy is 100% higher. It can be seen that the design of the present invention can reduce the IO resource occupancy and power consumption of the system.

[0054] Table 1 shows the FPGA resource consumption under different output lines

[0055] Output / Line IO occupancy / unit Power consumption / W 1 12 2.1 2 16 2.3 4 24 2.5

[0056] The test of the automatic data alignment effect is as follows: Figure 8 , Fig.10 As shown, the two-wire 16-bit and single-wire 12-bit acquisition results are shown.

[0057] In order to reflect the advantages of the uncooled infrared movement adaptive phase correction and data automatic alignment system proposed by the present invention, during the test, a method similar to the AD test mode is adopted to determine the byte order, and a fixed data input is generated to test whether its output meets expectations. The generated DATA data is shown in Table 2, and it is easy to know that the two-wire input is adopted.

[0058] Table 2 Test data format

[0059] D0P 1 0 1 0 1 0 1 0 D1P 0 1 1 1 1 1 0 1 D2P 0 0 0 1 1 1 0 0 D3P 1 1 1 1 1 0 0 0

[0060] To verify the effectiveness of the scheme, the adaptive phase correction and data alignment modules are called twice respectively, and the test data is divided into two groups. D0P and D1P represent the first group of differential data input; D2P and D3P represent the second group of differential data input. It is easy to know that the input of the first group of differential data is 7DAA, 7 is the upper four bits of D1P, D is the lower four bits of D1P, and A is the upper four bits and lower four bits of D0P; the input of the second group of differential data is F81C, and the meaning of each bit is similar to the first group.

[0061] It is easy to see that the two sets of differential data output results DatIn[15:0]_1 and DatIn[15:0]_2 are 7DAA and F81C respectively, which is in line with expectations. Figure 8 By zooming in locally, it is found that if Bitclk is not adjusted by the adaptive phase correction module, its edge has been misaligned with the data, and the sampling is located near the crossover area. Fig. 9 . Prove the effectiveness of the automatic data alignment system proposed in this invention.

[0062] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An uncooled infrared movement adaptive phase correction and data automatic alignment system, comprising a detector, a drive module, an FPGA and a power module, characterized in that: The power supply module is electrically connected to the driving module and the FPGA respectively, and is used to supply power to the driving module and the FPGA. The FPGA is electrically connected to the driving module in a bidirectional manner, and the driving module is also electrically connected to the detector in a bidirectional manner. The FPGA sends configuration and correction signals to the detector, thereby providing the correct timing for the normal operation of the detector. The FPGA also performs adaptive clock phase correction and data alignment on the image signal transmitted by the detector, and then performs image processing, which is displayed by the display device. The power supply module includes various groups of power supply modules, a video DA conversion module and a motor power amplifier module; the drive module includes a filter amplifier, an AD converter and a detector configuration and correction data module; the FPGA includes a controller, a detector configuration data acquisition module, a phase adaptive correction and data alignment module, a video processing module and a focusing motor and baffle motor control module; the controller is bidirectionally electrically connected to the detector configuration data acquisition module, the output end of the controller is also electrically connected to the input end of the video processing module and the focusing motor and baffle motor control module respectively, the output end of the detector configuration data acquisition module is electrically connected to the input end of the detector configuration and correction data module, and the output end of the detector configuration and correction data module is electrically connected to the input end of the detector; The output end of the detector is electrically connected to the input end of the filter amplifier, the output end of the filter amplifier is electrically connected to the input end of the AD converter, the output end of the AD converter is electrically connected to the input end of the phase adaptive correction and data alignment module, and the output end of the phase adaptive correction and data alignment module is electrically connected to the input end of the detector configuration data acquisition module; The power supply modules of each group are electrically connected to the power supply module of the FPGA and the power supply module of the driving module respectively; the video processing module is electrically connected to the input end of the video DA conversion module, and the output end of the video DA conversion module is electrically connected to the display device; the output end of the focus motor and the shutter motor control module is electrically connected to the motor power amplifier module, and the output end of the motor power amplifier module is electrically connected to the input end of the focus motor and the shutter motor respectively; The phase adaptive correction and data alignment module includes a delay module, a phase sampling module and a phase adaptive correction state machine. DCLK is electrically connected to the input end of the delay module and the D end of the phase sampling module respectively through a buffer IBUFDS. The signal of DCLK input to the D end of the phase sampling module after passing through the buffer IBUFDS is BitClk. The delay module is used to adjust the delay amount of the input DCLK. The output end of the delay module is electrically connected to the CLK end of the phase sampling module through a buffer BUFFIO, and is electrically connected to the CLKDIV end of the phase sampling module through a buffer BUFFR. The signal of the output end of the delay module input to the CLK end of the phase sampling module after passing through the buffer BUFFIO is BitClk_MonClkOut. The 8 output ends of the phase sampling module are electrically connected to the input end of the phase adaptive correction state machine. The 8 output ends are Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8. The output end of the phase adaptive correction state machine is electrically connected to the C end, CE end, INC end and RST end of the delay module respectively. The delay module controls the increase or decrease of the delay through the INC port; the phase sampling module uses BitClk to sample BitClk_MonClkOut, and the sampling result is output through Q1-Q8; the phase adaptive correction state machine is used to determine whether the delayed DCLK is aligned with the BitClk phase, and adopt corresponding strategies to control the delay amount according to different states. The basis for determining whether it is aligned is the result Q1-Q8 of BitClk sampling BitClk_MonClkOut 8 times in a row; The sampling results of BitClk to BitClk_MonClkOut have obvious characteristics at different phase differences and can be divided into two categories: Crossover area sampling: Due to the uncertainty of edge sampling, the output results of Q1-Q8 are different each time. If the value of the sampling result jumps, it proves that the phase of BitClk_MonClkOut and BitClk has been aligned; Stable area sampling: the values ​​of Q1-Q8 are the same; if the high level is sampled 8 times, Q1-Q8 are all 1; if the low level is sampled 8 times, Q1-Q8 are all 0; in this case, the delay amount needs to be adjusted to find the crossover area so that the BitClk_MonClkOut and BitClk phases are aligned; When designing the phase adaptive correction state machine, the DCLK cycle is 5ns as the limit, and the initial delay value is set to 16, which is divided into the following situations: State1: DCLK cycle is less than 5ns, and the delay is reduced by 3 steps. That is, the initial sampling is in the crossover area. Then the rising edge or falling edge is determined by the state after reducing the delay by 3 steps, and marked with EDGE; Rising edge: EDGE = 1, initial Q1-Q8 jumps, and after reducing the delay, Q1-Q8 are all 0; Falling edge: EDGE = 0, initial Q1-Q8 jumps, and after reducing the delay, Q1-Q8 are all 1; State2: DCLK cycle is less than 5ns, the initial sampling is in the stable area, Q1-Q8 are all 1 initially, and after the delay is reduced, they are all 0 or sampled in the crossover area, and the alignment is maintained; Q1-Q8 are all 0 initially, and after the delay is reduced, they are all 1 or sampled in the crossover area, and the alignment is maintained; State3: DCLK period is less than 5ns, initial sampling is in the stable region, delay is reduced by 3 steps, Q1-Q8 values ​​do not change, then delay is increased sequentially from 16, up to 32 times, until sampling reaches the crossover region or Q1-Q8 output is reversed, and alignment is maintained; State4: If the DCLK period is greater than 5ns, the initial sampling is in the stable area, the delay is reduced by 3 steps, and the Q1-Q8 values ​​do not change, the delay is increased from 16 to a maximum of 32 times until the sampling reaches the crossover area or the Q1-Q8 output is reversed to maintain alignment; if no edge is found after 32 adjustments, it means that the DCLK period is greater than 5ns, and the phase does not need to be adjusted. The delay value is set to the default value of 0.

2. The uncooled infrared movement adaptive phase correction and data automatic alignment system according to claim 1 is characterized in that: The detector uses a domestically produced 25μm vanadium oxide detector.

3. The uncooled infrared movement adaptive phase correction and data automatic alignment system according to claim 1, characterized in that: Configuration and correction signals include working clock, integration time, TEC parameters and OCC parameters.

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