ISAR multi-pulse cumulative cross-correlation distance and phase correction system based on FPGA

Abstract

The invention discloses an ISAR (Inverse Synthetic Aperture Radar) multi-pulse accumulation cross-correlation distance and phase correction system based on an FPGA (Field Programmable Gate Array). The ISAR multi-pulse accumulation cross-correlation distance and phase correction system comprises an upper computer and the FPGA, the upper computer is used for controlling the inverse synthetic aperture radar system to transmit a signal and receiving an echo signal; performing de-line frequency modulation on the echo signal to obtain an echo signal after pulse compression, and preprocessing the echo signal to obtain a to-be-processed echo signal; quantizing the echo signal to be processed, acquiring a quantized echo signal, transmitting the quantized echo signal to the FPGA, and receiving the distance returned by the FPGA and the echo signal after phase correction; and the FPGA is used for executing a multi-pulse cumulative cross-correlation envelope alignment algorithm to perform alignment processing on the quantized echo signal, obtaining a corrected echo signal and returning the corrected echo signal. The register transfer stage circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm is designed based on the FPGA, high-parallelization acceleration based on the multi-pulse cumulative cross-correlation envelope alignment algorithm module is achieved, and the processing speed and efficiency of the algorithm are remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of radar, and particularly relates to an ISAR multi-pulse accumulation cross-correlation distance and phase correction system based on FPGA. Background Art

[0002] ISAR (Inverse Synthetic Aperture Radar) achieves high range resolution by transmitting large time-bandwidth product signals and high azimuth resolution through coherent accumulation of radar echoes. The core of ISAR lies in decomposing the complex motion of the target into translational and rotational components, and using the Doppler frequency differences generated by equivalent rotation to construct the cross-range resolution, thereby obtaining high-resolution imaging results of targets such as satellites and airplanes. During the ISAR imaging process, the motion of the target relative to the radar can be decomposed into translational and rotational components. The translational motion of the target will cause range migration of the echo signal, resulting in a decrease in the alignment accuracy of each pulse echo in the range dimension, and thus affecting the imaging quality. Therefore, translational compensation becomes a key step in ISAR imaging. Envelope alignment is the core link in translational compensation. Its main task is to accurately estimate the time delay or range offset between echo signals, ensure that all pulses are aligned in the range dimension, and lay a foundation for subsequent phase compensation and high-resolution imaging.

[0003] Existing envelope alignment algorithms are usually based on CPUs (Central Processing Unit / Processor), GPUs (Graphics Processing Unit), and DSPs (Digital Signal Processor). However, these algorithms have their own limitations when facing large-scale echo data, high real-time requirements, and low-cost, low-power application scenarios:

[0004] Envelope alignment algorithms based on CPUs: CPUs adopt a serial processing architecture, with limited core numbers and mainly optimized for general computing tasks. When processing high-resolution, large-scale ISAR data, the parallel computing ability of CPUs is severely insufficient, resulting in low computational efficiency of the envelope alignment algorithm. This makes it difficult for envelope alignment algorithms based on CPUs to meet the high real-time application requirements. In addition, the scalability of CPU systems is poor, and it is difficult to linearly improve the processing ability by increasing the number of CPUs. This limits the application potential of envelope alignment algorithms based on CPUs when processing larger amounts of data or higher-resolution data. Therefore, in practical engineering applications, envelope alignment algorithms based on CPUs often cannot quickly respond to real-time envelope alignment requirements due to long computational time, resulting in an increase in system delay and affecting the overall performance.

[0005] GPU-based Envelope Alignment Algorithm: Although GPUs, based on parallel programming frameworks such as CUDA, can efficiently handle large-scale parallel computing tasks and significantly improve the computational speed of the envelope alignment algorithm. However, the data transfer bandwidth between the GPU and the CPU has become a key bottleneck restricting the overall system performance. The frequent transfer of large-scale ISAR data between the CPU and the GPU will cause significant delays and reduce the effectiveness of the GPU's parallel computing advantages. Especially in real-time processing scenarios, the limitations of data transfer and access speeds will seriously affect the overall real-time processing ability of the system. In addition, while providing powerful computing capabilities, GPUs usually come with high power consumption and heat dissipation requirements. This poses a severe challenge in power-sensitive application scenarios (such as spaceborne and airborne platforms). High power consumption not only limits the device's endurance but also increases the complexity and cost of the system's heat dissipation design.

[0006] DSP-based Envelope Alignment Algorithm: Although DSPs are optimized for signal processing tasks, their computing capabilities and storage resources are usually relatively limited and difficult to meet the complex computational requirements of high-resolution ISAR data envelope alignment algorithms. Especially when dealing with large-scale data or using complex algorithms, the computing power of DSPs may become a bottleneck and cannot withstand excessive parallel computing loads, resulting in a decrease in processing speed. In addition, DSPs are usually optimized for specific applications, and their hardware structures and instruction sets are relatively fixed. This makes DSPs less flexible when adapting to algorithm updates, function expansions, or processing different types of data.

[0007] In summary, the existing envelope alignment algorithms generally have problems such as performance bottlenecks, data transfer limitations, high power consumption, insufficient computing power, and limited flexibility when processing high-resolution and large-scale data. Summary of the Invention

[0008] The purpose of the embodiments of the present invention is to provide an ISAR multi-pulse cumulative cross-correlation distance and phase correction method based on FPGA to solve the problems of performance bottlenecks, data transfer limitations, high power consumption, insufficient computing power, and limited flexibility existing in the prior art when processing high-resolution and large-scale data. The specific technical solutions are as follows:

[0009] To achieve the above objective, in the first aspect, the embodiments of the present invention provide an ISAR multi-pulse cumulative cross-correlation distance and phase correction method based on FPGA, and the method includes:

[0010] Controlling an inverse synthetic aperture radar system to transmit a signal to a target and receiving the echo signal generated by the reflection of the transmitted signal by the target; wherein, the transmitted signal is a chirp signal;

[0011] Dechirping the echo signal to obtain the echo signal after pulse compression;

[0012] Preprocess the echo signal after pulse compression to obtain the echo signal to be processed;

[0013] Perform quantization processing on the echo signal to be processed to obtain a quantized echo signal, and transmit the quantized echo signal to a preset field-programmable gate array (FPGA) development board, so that when the FPGA development board receives the quantized echo signal, it executes a preset multi-pulse accumulation cross-correlation envelope alignment algorithm to perform alignment processing on the quantized echo signal, and obtain and return the echo signal after range and phase correction;

[0014] Receive the echo signal after range and phase correction returned by the FPGA development board.

[0015] Optionally, the step of performing de-chirping on the echo signal to obtain the echo signal after pulse compression includes:

[0016] Perform difference frequency processing on the echo signal and a reference signal to obtain a difference frequency signal; wherein, the reference signal is a linear frequency modulation signal having the same frequency and the same frequency modulation slope as the transmitted signal;

[0017] Perform fast Fourier transform on the difference frequency signal along the range direction to obtain the echo signal after pulse compression.

[0018] Optionally, the step of preprocessing the echo signal after pulse compression to obtain the echo signal to be processed includes:

[0019] Multiply the echo signal after pulse compression by a phase compensation function to remove the video residual phase term and the envelope skew term in the echo signal after pulse compression, and obtain the echo signal to be processed.

[0020] Optionally, before the step of transmitting the quantized echo signal to a preset FPGA development board, it further includes:

[0021] Design a register transfer level circuit based on the multi-pulse accumulation cross-correlation envelope alignment algorithm according to the algorithm model of the multi-pulse accumulation cross-correlation envelope alignment algorithm, and implement it on the FPGA development board.

[0022] Optionally, the algorithm model of the multi-pulse accumulation cross-correlation envelope alignment algorithm is:

[0023] Use the initial echo signal of the quantized echo signal as the reference echo signal, and use the next echo signal adjacent to the initial echo signal as the echo signal to be aligned;

[0024] Calculate the integral of the product of the echo signal to be aligned and the reference echo signal under time translation, obtain the cross-correlation function between the echo signal to be aligned and the reference echo signal, and determine the offset corresponding to the peak value of the envelope cross-correlation coefficient between the echo signal to be aligned and the reference echo signal according to the cross-correlation function;

[0025] Take the offset corresponding to the peak value of the envelope cross-correlation coefficient between the echo signal to be aligned and the reference echo signal as the relative movement amount between the two echo signals;

[0026] Construct a phase compensation term based on the relative movement amount, and multiply the echo signal to be aligned by the phase compensation term to obtain the echo signal after range alignment;

[0027] Take the echo signal obtained by accumulating the echo signal after range alignment and the reference echo signal as the new reference echo signal, take the next echo signal adjacent to the second echo signal as the new echo signal to be aligned, and return to the step of calculating the integral of the product of the echo signal to be aligned and the reference echo signal under time translation to continue execution until the echo signals at all azimuth time moments are aligned.

[0028] Optionally, when the field programmable gate array development board receives the quantized echo signal, the steps of performing alignment processing on the quantized echo signal by executing a preset multi-pulse cumulative cross-correlation envelope alignment algorithm include:

[0029] When the field programmable gate array development board receives the quantized echo signal, the field programmable gate array development board uses the reusable integrated circuit module integrated inside itself to perform a fast Fourier transform on the quantized echo signal along the range direction with Nr points to obtain frequency domain data, where Nr is the preset number of samples of the quantized echo signal in the range direction;

[0030] Pad zeros at both the beginning and the end of the frequency domain data to expand the data length of the frequency domain data to a preset multiple of the original length, and perform an inverse fast Fourier transform with a preset multiple × Nr points along the range direction to obtain the data after interpolation by a preset multiple, and determine whether the data after interpolation by a preset multiple is the primary echo data corresponding to the primary echo signal. If so, save the data after interpolation by a preset multiple to the sampling module, and perform modulus operation and square root operation on the data after interpolation by a preset multiple in sequence; if not, directly perform modulus operation and square root operation on the data after interpolation by a preset multiple in sequence;

[0031] Obtain the data after modulo square root extraction, and determine whether the data after modulo square root extraction is the initial echo data corresponding to the initial echo signal. If so, save the data after modulo square root extraction as the reference echo data to the reference module; if not, when the next echo data validity moment arrives, respectively obtain the reference echo data and the next echo data validity signal, and perform a fast Fourier transform of a preset number of times × Nr points on the reference echo data and the next echo data validity signal along the range direction simultaneously to respectively obtain the frequency domain signal to be aligned and the reference echo frequency domain signal;

[0032] Perform point-by-point complex conjugate multiplication on the frequency domain signal to be aligned and the reference echo frequency domain signal, obtain the multiplication result, and perform an inverse fast Fourier transform of a preset number of times × Nr points on the multiplication result along the range direction to obtain the transform result, and perform modulo and square root calculations on the transform result in sequence to obtain the cross-correlation coefficient between the echo to be aligned and the reference echo;

[0033] Iteratively update the cross-correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the cross-correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantization sine function value and cosine function value from the pre-saved index table according to the index, construct a phase compensation function according to the obtained function values, and use the phase compensation function to compensate the data after interpolation within a preset number of times corresponding to each echo to obtain the frequency domain phase-compensated data of the echo to be aligned corresponding to each echo;

[0034] For the frequency domain phase-compensated data of the echo to be aligned corresponding to each echo, perform an inverse fast Fourier transform of a preset number of times × Nr points along the range direction respectively, obtain the transform result, perform a fast Fourier transform cyclic shift operation on the transform result, obtain the shifted data, and save the shifted data to the sampling module;

[0035] Accumulate the shifted data and the saved reference echo data, and save the accumulation result as the new reference echo data to the reference module;

[0036] Obtain the data saved in the sampling module, and perform a preset number of times of decimation on the data to obtain the range-aligned echo data with the same range dimension as the initial input data, and return the echo data;

[0037] Judge whether envelope alignment has been completed for each echo data. If so, end; if not, return to the step of performing modulo and square root operations on the data after interpolation within a preset number of times in sequence and continue to execute.

[0038] Second aspect, an embodiment of the present invention provides an ISAR multi-pulse accumulation cross-correlation distance and phase correction system based on FPGA, and the system includes: a host computer and a field programmable gate array development board;

[0039] The host computer is used for:

[0040] Controlling the inverse synthetic aperture radar system to transmit a signal to the target and receiving the echo signal generated by the reflection of the transmitted signal by the target; wherein, the transmitted signal is a chirp signal;

[0041] Dechirping the echo signal to obtain the echo signal after pulse compression;

[0042] Preprocessing the echo signal after pulse compression to obtain the echo signal to be processed;

[0043] Performing quantization processing on the echo signal to be processed to obtain a quantized echo signal, transmitting the quantized echo signal to the field programmable gate array development board through a network, and receiving the echo signal after distance and phase correction returned by the field programmable gate array development board;

[0044] The field programmable gate array development board is used for:

[0045] Receiving the quantized echo signal sent by the host computer and performing alignment processing on the quantized echo signal by executing a preset multi-pulse accumulation cross-correlation envelope alignment algorithm to obtain the echo signal after distance and phase correction and returning it to the host computer.

[0046] Optionally, the field programmable gate array development board is specifically used for:

[0047] When receiving the quantized echo signal, using the reusable integrated circuit module integrated inside itself to perform a fast Fourier transform of Nr points on the quantized echo signal along the range direction to obtain frequency domain data, where Nr is the preset number of samples of the quantized echo signal in the range direction;

[0048] Padding zeros at both ends of the frequency domain data to expand the data length of the frequency domain data to a preset multiple of the original length, and performing an inverse fast Fourier transform of the preset multiple × Nr points along the range direction to obtain the data after interpolation of the preset multiple, and determining whether the data after interpolation of the preset multiple is the primary echo data corresponding to the primary echo signal. If so, saving the data after interpolation of the preset multiple to the sampling module and performing modulus and square root operations on the data after interpolation of the preset multiple in sequence; if not, directly performing modulus and square root operations on the data after interpolation of the preset multiple in sequence;

[0049] Obtain the data after modulo square root extraction, and determine whether the data after modulo square root extraction is the initial echo data corresponding to the initial echo signal. If so, save the data after modulo square root extraction as the reference echo data to the reference module; if not, when the next echo data validity time arrives, respectively obtain the reference echo data and the next echo data validity signal, and perform a fast Fourier transform of a preset number of times × Nr points simultaneously along the range direction on the reference echo data and the next echo data validity signal, respectively obtaining the frequency domain signal to be aligned and the reference echo frequency domain signal;

[0050] Perform point-by-point complex conjugate multiplication on the frequency domain signal to be aligned and the reference echo frequency domain signal, obtain the multiplication result, and perform an inverse fast Fourier transform of a preset number of times × Nr points along the range direction on the multiplication result to obtain the transform result, and perform modulo and square root calculations on the transform result in sequence to obtain the cross-correlation coefficient between the echo to be aligned and the reference echo;

[0051] Iteratively update the cross-correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the cross-correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantized sine function value and cosine function value from the pre-saved index table according to the index, construct a phase compensation function according to the obtained function values, and use the phase compensation function to compensate the data after interpolation within a preset number of times corresponding to each echo to obtain the frequency domain phase-compensated data of the echo to be aligned corresponding to each echo;

[0052] For the frequency domain phase-compensated data of the echo to be aligned corresponding to each echo, perform an inverse fast Fourier transform of a preset number of times × Nr points along the range direction respectively, obtain the transform result, perform a fast Fourier transform cyclic shift operation on the transform result, obtain the shifted data, and save the shifted data to the sampling module;

[0053] Accumulate the shifted data and the saved reference echo data, and save the accumulation result as the new reference echo data to the reference module;

[0054] Obtain the data saved in the sampling module, and perform extraction of a preset number of times on the data to obtain the range-aligned echo data with the same range dimension as the initial input data, and return the echo data to the host computer;

[0055] Judge whether envelope alignment has been completed for each echo data. If so, end; if not, return to the step of performing modulo and square root operations on the data after interpolation within a preset number of times in sequence and continue to execute.

[0056] In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete communication with each other through the communication bus;

[0057] The memory is used to store a computer program;

[0058] The processor is configured to implement the method steps of the ISAR multi-pulse accumulation cross-correlation distance and phase correction based on FPGA described in the first aspect above when executing the program stored on the memory.

[0059] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, it implements the method steps of the ISAR multi-pulse accumulation cross-correlation distance and phase correction based on FPGA described in the first aspect above.

[0060] In a fifth aspect, an embodiment of the present invention further provides a computer program product containing instructions, which when running on a computer, enables the computer to implement the method steps of the ISAR multi-pulse accumulation cross-correlation distance and phase correction based on FPGA described in the first aspect above when executed.

[0061] It can be seen that the method provided by the embodiment of the present invention introduces a range compression signal model including the target translational component into the multi-pulse accumulation cross-correlation algorithm with error suppression ability, constructs a multi-pulse accumulation cross-correlation envelope alignment algorithm, and is used to solve the problems of range and phase correction in ISAR imaging, which is beneficial to achieving precise alignment of echo signals at all azimuth moments, improving the accuracy and robustness of ISAR imaging. And in the embodiment of the present invention, according to the algorithm model of the preset multi-pulse accumulation cross-correlation envelope alignment algorithm, a register transfer level circuit based on the multi-pulse accumulation cross-correlation envelope alignment algorithm is designed and implemented on a field-programmable gate array development board (Field-Programmable Gate Array, FPGA), constructing a lightweight hardware-in-the-loop verification system for system-level verification of the designed register transfer level circuit based on the multi-pulse accumulation cross-correlation envelope alignment algorithm. The system takes the FPGA development board as the core and conducts two-way communication with the host computer through an Ethernet interface to form a test loop of "host computer - network - FPGA - network - host computer". Based on this system platform, comprehensive board-level debugging and performance testing are carried out, including but not limited to function correctness verification, timing constraint satisfaction analysis, resource utilization evaluation, and performance index testing under actual application scenarios. The experimental results verify the effectiveness and superiority of the method provided by the embodiment of the present invention. Description of the Drawings

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art.

[0063] Figure 1 It is a schematic flowchart of a method for ISAR multi-pulse accumulation cross-correlation distance and phase correction based on FPGA provided by an embodiment of the present invention;

[0064] Figure 2 It is a schematic flowchart of the multi-pulse accumulation cross-correlation envelope alignment algorithm executed by FPGA after receiving the quantized echo signal provided by an embodiment of the present invention;

[0065] Figure 3 It is a schematic diagram of the result of implementing the envelope alignment algorithm provided by an embodiment of the present invention on FPGA;

[0066] Figure 4 It is a schematic diagram of the result of the envelope alignment algorithm provided by an embodiment of the present invention in theory;

[0067] Figure 5 It is a schematic diagram for comparing the average one-dimensional range profile of the envelope alignment algorithm implemented on FPGA with that in theory provided by an embodiment of the present invention;

[0068] Figure 6 It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0069] Next, the technical solutions in the embodiments of the present invention will be described with reference to the drawings in the embodiments of the present invention. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0070] Figure 1 It is a schematic flowchart of a method for ISAR multi-pulse accumulation cross-correlation distance and phase correction based on FPGA provided by an embodiment of the present invention. As Figure 1 shown, the method includes:

[0071] S101: Control the inverse synthetic aperture radar system to transmit a signal to the target and receive the echo signal generated by the reflection of the transmitted signal by the target;

[0072] Among them, the transmitted signal is a chirp signal;

[0073] S102: De-chirp the echo signal to obtain the echo signal after pulse compression;

[0074] Chirp rate solution, also known as dechirp processing, is an important processing method for linear frequency modulation (LFM) signals in the field of signal processing. Chirp rate solution is to mix the received linear frequency modulation echo signal with a reference linear frequency modulation signal that is fixed in time and has the same frequency and chirp rate.

[0075] Specifically, the steps of performing chirp rate solution on the echo signal to obtain the echo signal after pulse compression may include:

[0076] Perform difference frequency processing on the echo signal and the reference signal to obtain a difference frequency signal; wherein, the reference signal is a linear frequency modulation signal having the same frequency and the same chirp slope as the transmitted signal;

[0077] Perform fast Fourier transform on the difference frequency signal along the range direction to obtain the echo signal after pulse compression.

[0078] S103: Preprocess the echo signal after pulse compression to obtain the echo signal to be processed;

[0079] Specifically, the steps of preprocessing the echo signal after pulse compression to obtain the echo signal to be processed may include:

[0080] Multiply the echo signal after pulse compression by a phase compensation function to remove the video residual phase term and the envelope skew term in the echo signal after pulse compression, and obtain the echo signal to be processed.

[0081] In practical applications, the chirp rate solution process will introduce a video residual phase term and an envelope skew term. The method of multiplying the echo signal after pulse compression by a phase compensation function can be used to remove the video residual phase term. The research object in the embodiments of the present invention is the pulse compression signal that has been preprocessed, that is, the above two phase errors have been eliminated.

[0082] S104: Quantize the echo signal to be processed to obtain a quantized echo signal, and transmit the quantized echo signal to a preset field programmable gate array development board, so that when the field programmable gate array development board receives the quantized echo signal, it executes a preset multi-pulse cumulative cross-correlation envelope alignment algorithm to perform alignment processing on the quantized echo signal, and obtain and return the echo signal after range and phase correction;

[0083] In a specific embodiment, before the step of transmitting the quantized echo signal to a preset field programmable gate array development board, it is also necessary to design a register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm according to the algorithm model of the preset multi-pulse cumulative cross-correlation envelope alignment algorithm, and implement it on the field programmable gate array development board.

[0084] In a specific embodiment, the multi-pulse cumulative cross-correlation envelope alignment algorithm can be a non-parametric envelope alignment algorithm, and the algorithm model of the multi-pulse cumulative cross-correlation envelope alignment algorithm can be as follows:

[0085] Use the primary echo signal of the quantized echo signal as the reference echo signal, and use the next echo signal adjacent to the primary echo signal as the echo signal to be aligned;

[0086] Calculate the integral of the product of the echo signal to be aligned and the reference echo signal under time translation, obtain the cross-correlation function between the echo signal to be aligned and the reference echo signal, and determine the offset corresponding to the peak of the envelope cross-correlation coefficient between the echo signal to be aligned and the reference echo signal according to the cross-correlation function;

[0087] Use the offset corresponding to the peak of the envelope cross-correlation coefficient between the echo signal to be aligned and the reference echo signal as the relative movement amount between the two echo signals;

[0088] Construct a phase compensation term based on the relative movement amount, and multiply the echo signal to be aligned by the phase compensation term to obtain the echo signal after range alignment;

[0089] Use the echo signal obtained by accumulating the echo signal after range alignment and the reference echo signal as the new reference echo signal, use the next echo signal adjacent to the second echo signal as the new echo signal to be aligned, and return to the step of calculating the integral of the product of the echo signal to be aligned and the reference echo signal under time translation to continue execution until the echo signals at all azimuth time instants are aligned.

[0090] Calculating the integral of the product of the echo signal to be aligned and the reference echo signal under time translation can obtain the cross-correlation function between the echo signal to be aligned and the reference echo signal. The cross-correlation function can be used to measure the similarity between two signals. In echo signal processing, by calculating the cross-correlation function, the time translation amount that maximizes the similarity between the two signals can be found, thereby realizing signal alignment.

[0091] When the field programmable gate array development board receives the quantized echo signal, the steps of performing the preset multi-pulse cumulative cross-correlation envelope alignment algorithm on the quantized echo signal can include:

[0092] When the field programmable gate array development board receives the quantized echo signal, the field programmable gate array development board uses the reusable integrated circuit module integrated in itself to perform a fast Fourier transform of the quantized echo signal along the range direction with Nr points to obtain frequency domain data, where Nr is the preset number of samples of the quantized echo signal in the range direction;

[0093] Pad zeros at both the beginning and the end of the frequency-domain data to extend the data length of the frequency-domain data to a preset multiple of the original length, and perform an inverse fast Fourier transform of the preset multiple × Nr points along the range direction to obtain the interpolated data after the preset multiple. Then, determine whether the interpolated data after the preset multiple is the initial echo data corresponding to the initial echo signal. If so, save the interpolated data after the preset multiple to the sampling module, and perform modulus and square root operations on the interpolated data after the preset multiple in sequence; if not, directly perform modulus and square root operations on the interpolated data after the preset multiple in sequence.

[0094] Obtain the data after modulus and square root operations, and determine whether the data after modulus and square root operations is the initial echo data corresponding to the initial echo signal. If so, save the data after modulus and square root operations as the reference echo data to the reference module; if not, when the next echo data validity time arrives, respectively obtain the reference echo data and the next echo data validity signal, and perform a fast Fourier transform of the preset multiple × Nr points along the range direction on the reference echo data and the next echo data validity signal simultaneously to obtain the frequency-domain signal to be aligned and the reference echo frequency-domain signal respectively.

[0095] Perform point-by-point complex conjugate multiplication on the frequency-domain signal to be aligned and the reference echo frequency-domain signal, obtain the multiplication result, and perform an inverse fast Fourier transform of the preset multiple × Nr points along the range direction on the multiplication result to obtain the transformation result. Then, perform modulus and square root calculations on the transformation result in sequence to obtain the cross-correlation coefficient between the echo to be aligned and the reference echo.

[0096] Iteratively update the cross-correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the cross-correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantized sine function value and cosine function value from the pre-saved index table according to the index, construct a phase compensation function based on the obtained function values, and use the phase compensation function to compensate the interpolated data after the preset multiple corresponding to each echo to obtain the frequency-domain phase-compensated data of the echo to be aligned corresponding to each echo.

[0097] For the frequency-domain phase-compensated data of the echo to be aligned corresponding to each echo, perform an inverse fast Fourier transform of the preset multiple × Nr points along the range direction respectively, obtain the transformation result, perform a fast Fourier transform cyclic shift operation on the transformation result, obtain the shifted data, and save the shifted data to the sampling module.

[0098] Accumulate the shifted data and the saved reference echo data, and save the accumulation result as the new reference echo data to the reference module.

[0099] Obtain the data saved in the sampling module, perform decimation by a preset number of times on the data, obtain the range-aligned echo data with the same range dimension as the initial input data, and return the echo data;

[0100] Determine whether envelope alignment has been completed for each echo data. If so, end; if not, return to the step of performing modulo operation and square root operation on the data after interpolation by a preset number of times in sequence and continue to execute.

[0101] S105: Receive the echo signal after range and phase correction returned by the field programmable gate array development board.

[0102] In the embodiment of the present invention, the modeling process of the ISAR echo signal can be:

[0103] Assume that the inverse synthetic aperture radar system is controlled to transmit a large bandwidth linear frequency modulation signal to the target:

[0104]

[0105] Among them, is the fast time, t m = mT is the slow time, m is an integer, T a is the pulse width, f c is the center frequency, γ is the frequency modulation slope, rect(x) is a rectangular window function, j is the imaginary unit, t is the total time, and T is the pulse repetition period.

[0106] Assume that the target is at a distance R i from the radar, and the round-trip time delay of the echo relative to the initial transmitted signal is denoted as Δt. Then the received echo signal is:

[0107]

[0108] At this time, use a linear frequency modulation signal with the same frequency and frequency modulation slope as the transmitted signal as the reference signal:

[0109]

[0110] Among them, in the formula R ref is the reference distance, T ref is the pulse width of the reference signal, and the value of T ref is slightly greater than T a .

[0111] Then perform difference frequency processing on the echo signal and the reference signal, and perform FFT (Fast Fourier Transform) transformation on the signal after difference frequency processing along the range direction to achieve pulse compression of the echo signal:

[0112]

[0113] Among them, in the formula, R Δ =R i -R ref =R ΔT (t)+xsinθ(t)+ycosθ(t)-R ref represents the differential distance between the target and the reference, f i is the Fourier transform frequency domain coordinate, and (x, y) is the distance coordinate of the target.

[0114] So far, the de-chirping operation of the radar echo signal is completed, and the echo signal after pulse compression is obtained. Multiply the echo signal after pulse compression by the phase compensation function to remove the video residual phase term and the envelope skew term to obtain the signal to be processed:

[0115]

[0116] In the above formula, R Δ The R contained in the variable ΔT (t) is the translational component in the ISAR imaging process. This component directly affects the envelope and phase of the echo signal, resulting in defocus distortion of the target image. Therefore, it is necessary to compensate for this translational component, and this process is usually called translational compensation. The first step of translational compensation is to align the envelopes of the echo signals.

[0117] In the modeling process of the non-parametric multi-pulse cumulative cross-correlation envelope alignment algorithm in the embodiment of the present invention, it can be:

[0118] For the signal to be processed:

[0119]

[0120] First, select the initial echo signal as the reference echo signal S ref =S if (f i ,t m ), where m = 1; calculate the integral of the product of the adjacent next echo signal S if (f i ,t m+1 ) and the reference echo signal S ref under the time shift τ:

[0121]

[0122] Since the cross-correlation coefficient reaches its maximum when the adjacent echo envelopes are aligned, the envelope offset corresponding to the peak of the cross-correlation coefficient between adjacent echo envelopes is approximately equal to the relative movement between echo signals. Therefore, a compensation term is constructed based on this offset and multiplied by the echo signal to be aligned to complete the envelope alignment of the current echo signal. After envelope alignment, the R ΔT (t) in the target envelope term (i.e., the sinc term) of the current echo signal is removed, and the aligned echo expression is:

[0123]

[0124] To avoid the influence of error accumulation, the echo signal S if ′(f i ,t m ) after range alignment is accumulated with the reference echo signal S ref used in this alignment to obtain a new reference echo signal S ref ′ for the alignment of the adjacent next echo signal. After the next echo alignment, the echo signal after this alignment is also accumulated with the reference echo signal used in this alignment to obtain a new reference echo signal for the alignment of the adjacent next echo signal. This process is repeated until the echo signals at all azimuthal times are aligned.

[0125] In the method provided by the embodiments of the present invention, to achieve a high degree of parallelization of the multi-pulse cumulative cross-correlation envelope alignment algorithm module and improve the processing speed and efficiency of the algorithm, a register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm is designed and implemented on an FPGA development board. Moreover, in view of the hardware architecture characteristics of the FPGA development board, the register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm is deeply customized and optimized, thereby constructing a lightweight hardware-in-the-loop verification system that can be used for system-level verification of the register transfer level circuit designed based on the multi-pulse cumulative cross-correlation envelope alignment algorithm of the present invention. This verification system takes the FPGA development board as the core and can communicate bidirectionally with the host computer through an Ethernet interface to form a test loop of "host computer - Ethernet - FPGA - Ethernet - host computer". Based on this verification system, comprehensive board-level debugging and performance testing can be carried out on the register transfer level circuit designed based on the multi-pulse cumulative cross-correlation envelope alignment algorithm of the present invention, and functional correctness verification, timing constraint satisfaction analysis, resource utilization evaluation, and performance index testing in actual application scenarios can also be carried out.

[0126] In a specific embodiment, the register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm can be implemented on a K7-325T FPGA development board, and the host computer can also perform data interaction with the FPGA through the UDP protocol. At the same time, to ensure the reliability of data transmission, a CRC (Cyclic Redundancy Check) verification module can also be implemented inside the FPGA to perform real-time verification on the received and sent data.

[0127] The verification system designed in the embodiment of the present invention has high flexibility and scalability, can be easily configured into different test modes, and in addition to being used for verifying the function of the multi-pulse cumulative cross-correlation envelope alignment algorithm in the present invention, can also be widely applied to the hardware acceleration and performance evaluation of other digital signal processing algorithms.

[0128] In summary, the method provided in the embodiment of the present invention introduces a range compression signal model including the target translational component into the multi-pulse cumulative cross-correlation algorithm with error suppression ability, constructs a multi-pulse cumulative cross-correlation envelope alignment algorithm to solve the problems of range and phase correction in ISAR imaging, which is beneficial to achieving precise alignment of echo signals at all azimuth moments, and improving the accuracy and robustness of ISAR imaging.

[0129] In addition, the method provided in the embodiment of the present invention also designs a deeply customized and optimized register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm according to the characteristics of the FPGA hardware architecture, realizes the highly parallel acceleration of the multi-pulse cumulative cross-correlation envelope alignment algorithm module, and significantly improves the processing speed and efficiency of the algorithm. Moreover, the method provided in the embodiment of the present invention also constructs a lightweight hardware-in-the-loop verification system, and based on this system platform, conducts system-level verification on the customized circuit designed in the present invention. The experimental results verify the effectiveness and superiority of the method provided in the embodiment of the present invention.

[0130] The following lists a specific embodiment to further elaborate on the steps of the method provided in the embodiment of the present invention in which the FPGA, when receiving the quantized echo signal, executes the preset multi-pulse cumulative cross-correlation envelope alignment algorithm to perform alignment processing on the quantized echo signal.

[0131] In this embodiment, Nr is the preset number of range samples of the quantized echo signal, and the preset number of times is 8 times. In practical applications, the quantized echo signal generated after quantizing the range-compressed echo signal is transmitted from the host computer to the FPGA development board in binary format through the Ethernet interface. See Figure 2 After the FPGA receives the quantized echo signal, the process of executing the preset multi-pulse cumulative cross-correlation envelope alignment algorithm is as follows:

[0132] S201: Use the reusable integrated circuit module integrated inside itself to perform a fast Fourier transform of Nr points along the range direction on the quantized echo signal to obtain frequency-domain data;

[0133] Specifically, after receiving the quantized echo signal, the FPGA development board first uses the FFT (Fast Fourier Transform) IP (Internet Protocol) core integrated inside itself to perform a fast Fourier transform of Nr points along the range direction on the quantized echo signal to obtain the corresponding frequency-domain data. The FFT IP core is a reusable integrated circuit module that implements the FFT algorithm and can be embedded in various chip designs without having to redesign the FFT circuit, saving design time and cost.

[0134] S202: Pad zeros at both the beginning and the end of the frequency-domain data to expand the data length of the frequency-domain data to 8 times the original length, and perform an inverse fast Fourier transform of 8×Nr points along the range direction to obtain the interpolated data of a preset number of times, and determine whether the interpolated data of the preset number of times is the initial echo data corresponding to the initial echo signal. If so, save the interpolated data of the preset number of times to the sampling module and execute step S203; if not, directly execute step S203;

[0135] Specifically, pad zeros at both the beginning and the end of the frequency-domain data to expand the frequency-domain data to 8 times the original length, and then perform an inverse fast Fourier transform (Inverse Fast Fourier Transform, IFFT) of 8×Nr points along the range direction on the expanded data to obtain the 8-fold interpolated data, and determine whether the 8-fold interpolated data is the initial echo data, that is, the first radar echo data. If so, divide the 8-fold interpolated data into two paths. One path of data is directly output to the sampling module for storage. The sampling module is a preset sampling module in the FPGA development board. Since the initial echo data does not need to be aligned, it is directly output to the sampling module; the other path of data enters step S203 for further processing. If not, it enters step S203.

[0136] S203: Perform modulus and square root operations on the interpolated data of the preset number of times in sequence to obtain the data after modulus and square root operations, and determine whether the data after modulus and square root operations is the initial echo data corresponding to the initial echo signal. If so, save the data after modulus and square root operations as the reference echo data to the reference module;

[0137] The data flowing into step S202 is successively subjected to modulo operation and square root operation. These operations can be implemented respectively through the parallel multiplier, adder and square root IP core inside the FPGA. The IP core is a macro module that has been repeatedly verified and has specific functions. It is independent of the chip manufacturing process and can be transplanted into different semiconductor processes. Open IP core means making such an IP core available to users in an open license manner, enabling them to freely obtain, use, modify and redistribute it, etc., to promote technology sharing and innovation.

[0138] Judge whether the data after modulo operation and square root operation is the initial echo data. If so, save it to the reference module, which is a preset reference module in the FPGA development board. The algorithm will use the first echo data as the starting reference echo data.

[0139] S204: When reaching the next echo data validity moment, respectively obtain the reference echo data and the next echo data validity signal, and perform a fast Fourier transform of 8×Nr points simultaneously along the range direction on the reference echo data and the next echo data validity signal, respectively obtaining the frequency domain signal to be aligned and the reference echo frequency domain signal;

[0140] In step S203, the next set of echo data validity signal and the reading of the reference echo data in the reference module are synchronously triggered. The two-way data simultaneously perform an 8×Nr point FFT operation along the range direction, and respectively obtain the smoothed frequency domain signal to be aligned and the reference echo frequency domain signal.

[0141] S205: Perform point-by-point complex conjugate multiplication on the frequency domain signal to be aligned and the reference echo frequency domain signal, obtain the multiplication result, perform an inverse fast Fourier transform of 8×Nr points along the range direction on the multiplication result, obtain the transformation result, and successively perform modulo operation and square root calculation on the transformation result to obtain the cross-correlation coefficient between the echo to be aligned and the reference echo;

[0142] S206: Iteratively update the cross-correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the cross-correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantized sine function value and cosine function value from the pre-saved index table according to the index, construct a phase compensation function based on the obtained function values, and use the phase compensation function to compensate the data interpolated by a preset number of times corresponding to each echo, obtaining the frequency domain phase-compensated data of the echo to be aligned corresponding to each echo;

[0143] Specifically, the cross-correlation coefficient between the echo to be aligned and the reference echo is iteratively updated to determine the index corresponding to the maximum value of the cross-correlation coefficient between the echo to be aligned and the reference echo. Using this index, the corresponding quantized sine function value and quantized cosine function value are respectively read from the quantized sine function table and cosine function table pre-stored in the ROM (Read-Only Memory), and a phase compensation function is constructed based on the quantized sine function value and quantized cosine function value. The phase compensation function is used to compensate the 8-fold interpolated data corresponding to the corresponding number of echo times in step S202, and the frequency-domain phase compensation of the echo to be aligned this time is completed.

[0144] S207: For the data after frequency-domain phase compensation of the echo to be aligned corresponding to each echo, perform an inverse fast Fourier transform of 8×Nr points along the range direction respectively, obtain the transformation result, perform a fast Fourier transform cyclic shift operation on the transformation result, obtain the shifted data, and save the shifted data to the sampling module;

[0145] Specifically, perform an 8×Nr point IFFT operation on the data compensated in step S206 along the range direction, and perform an FFT cyclic shift operation on the result. Subsequently, the data is output and split into 2 paths: 1 path is output to the sampling module; the other path is accumulated with the echo data cached in the reference module to update the reference echo.

[0146] S208: Accumulate the shifted data with the saved reference echo data, and save the accumulated result as the new reference echo data to the reference module;

[0147] S209: Obtain the data saved in the sampling module, and perform 8-fold decimation on the data to obtain the range-aligned echo data with the same range dimension as the initial input data, and return the echo data to the host computer;

[0148] Specifically, perform 8-fold decimation on the data input to the sampling module to obtain the range-aligned echo data with the same range dimension as the initial input data. And this data is output as the 1-time echo alignment result of the envelope alignment module to the host computer.

[0149] S210: Determine whether envelope alignment has been completed for each echo data. If so, end; if not, return to step S203 to continue execution.

[0150] Specifically, that is, determine whether envelope alignment has been completed for the echo signals at all azimuth moments. If so, end; if not, return to step S203 to continue execution until envelope alignment has been completed for the echo signals at all azimuth moments.

[0151] By Figures 3 - 5It can be seen that the results of the envelope alignment algorithm provided by the embodiments of the present invention implemented on the FPGA, the average one-dimensional range profile ( Figure 5 The blue line in Figure 5 represents the average one-dimensional range profile of the envelope alignment algorithm provided by the embodiments of the present invention implemented on the FPGA) and the theoretical results and average one-dimensional range profile (

[0152] The red line in represents the theoretical average one-dimensional range profile) are very similar, which also means that the algorithm function of the envelope alignment algorithm provided by the embodiments of the present invention can be well implemented on the FPGA.

[0153] In summary, the method provided by the embodiments of the present invention designs a deeply customized and optimized register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm based on the characteristics of the FPGA hardware architecture, realizes the highly parallel acceleration of the multi-pulse cumulative cross-correlation envelope alignment algorithm module, and significantly improves the processing speed and efficiency of the algorithm.

[0154] Corresponding to the Figure 1 illustrated embodiment, the embodiments of the present invention also provide an ISAR multi-pulse cumulative cross-correlation range and phase correction system based on the FPGA, and the system includes: a host computer, a field programmable gate array development board; wherein,

[0155] The host computer is used for:

[0156] Controlling the inverse synthetic aperture radar system to transmit a signal to the target and receiving the echo signal generated by the reflection of the transmitted signal by the target; wherein, the transmitted signal is a chirp signal;

[0157] Dechirping the echo signal to obtain the echo signal after pulse compression;

[0158] Preprocessing the echo signal after pulse compression to obtain the echo signal to be processed;

[0159] Performing quantization processing on the echo signal to be processed to obtain a quantized echo signal, transmitting the quantized echo signal to the field programmable gate array development board through a network, and receiving the range and phase corrected echo signal returned by the field programmable gate array development board;

[0160] The field programmable gate array development board is used for:

[0161] Receive the quantized echo signal sent by the host computer, and execute the preset multi-pulse accumulation cross-correlation envelope alignment algorithm to align the quantized echo signal, obtain the echo signal after distance and phase correction, and return it to the host computer.

[0162] Optionally, execute the field programmable gate array development board, specifically used for:

[0163] When receiving the quantized echo signal, use the reusable integrated circuit module integrated inside itself to perform a fast Fourier transform of Nr points along the range direction of the quantized echo signal to obtain frequency domain data, where Nr is the preset number of samples of the quantized echo signal in the range direction;

[0164] Pad zeros at both ends of the frequency domain data to expand the data length of the frequency domain data to a preset multiple of the original length, and perform an inverse fast Fourier transform of the preset multiple × Nr points along the range direction to obtain the data after interpolation by the preset multiple, and determine whether the data after interpolation by the preset multiple is the primary echo data corresponding to the primary echo signal. If so, save the data after interpolation by the preset multiple to the sampling module, and perform modulus and square root operations on the data after interpolation by the preset multiple in sequence; if not, directly perform modulus and square root operations on the data after interpolation by the preset multiple in sequence;

[0165] Obtain the data after modulus and square root calculation, and determine whether the data after modulus and square root calculation is the primary echo data corresponding to the primary echo signal. If so, save the data after modulus and square root calculation as the reference echo data to the reference module; if not, when reaching the next echo data validity moment, respectively obtain the reference echo data and the next echo data validity signal, and perform a fast Fourier transform of the preset multiple × Nr points along the range direction on the reference echo data and the next echo data validity signal respectively to obtain the frequency domain signal to be aligned and the reference echo frequency domain signal;

[0166] Perform point-by-point complex conjugate multiplication on the frequency domain signal to be aligned and the reference echo frequency domain signal, obtain the multiplication result, and perform an inverse fast Fourier transform of the preset multiple × Nr points along the range direction on the multiplication result to obtain the transformation result, and perform modulus and square root calculations on the transformation result in sequence to obtain the cross-correlation coefficient between the echo to be aligned and the reference echo;

[0167] Iteratively update the cross-correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the cross-correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantized sine function value and cosine function value from the pre-saved index table according to the index, construct a phase compensation function according to the obtained function values, and use the phase compensation function to compensate the data after interpolation by the preset multiple corresponding to each echo to obtain the frequency domain phase-compensated data of the echo to be aligned corresponding to each echo;

[0168] For the data after frequency-domain phase compensation of the echo to be aligned corresponding to each echo, perform an inverse fast Fourier transform of a preset number of times multiplied by the number of points Nr along the range direction respectively, obtain the transformation result, perform a cyclic shift operation of the fast Fourier transform on the transformation result, obtain the shifted data, and save the shifted data to the sampling module;

[0169] Accumulate the shifted data with the saved reference echo data, and save the accumulation result as the new reference echo data to the reference module;

[0170] Obtain the data saved in the sampling module, perform a preset number of times of decimation on the data, obtain the range-aligned echo data with the same range dimension as the initial input data, and return the echo data to the host computer;

[0171] Judge whether envelope alignment has been completed for each echo data. If so, end; if not, return to the step of performing modulus and square root operations on the interpolated data of a preset number of times in sequence and continue to execute.

[0172] For the system provided by the embodiments of the present invention, in order to achieve a high degree of parallelization of the multi-pulse cumulative cross-correlation envelope alignment algorithm module, and improve the processing speed and efficiency of the algorithm, a register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm is designed, implemented on an FPGA development board, and also deeply customized and optimized for the hardware architecture characteristics of the FPGA development board, thereby constructing a lightweight hardware-in-the-loop verification system, which can be used for system-level verification of the register transfer level circuit designed by the present invention based on the multi-pulse cumulative cross-correlation envelope alignment algorithm. This verification system takes the FPGA development board as the core, and can communicate bidirectionally with the host computer through an Ethernet interface, forming a test loop of "host computer - Ethernet - FPGA - Ethernet - host computer". Based on this verification system, comprehensive board-level debugging and performance testing can be carried out on the register transfer level circuit designed by the present invention based on the multi-pulse cumulative cross-correlation envelope alignment algorithm, and functional correctness verification, timing constraint satisfaction analysis, resource utilization evaluation, and performance index testing under actual application scenarios can also be carried out.

[0173] Corresponding to Figure 1 the embodiment shown, the embodiments of the present invention also provide an electronic device, see Figure 6 , including a processor 601, a communication interface 602, a memory 603, and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604;

[0174] The memory 603 is used to store a computer program;

[0175] The processor 601, when executing the program stored in the memory, implements the method steps of the FPGA-based ISAR multi-pulse cumulative cross-correlation distance and phase correction described in any of the above embodiments.

[0176] Applying the electronic device provided by the embodiment of the present invention to solve the problems of distance and phase correction in ISAR imaging is beneficial to achieving precise alignment of echo signals at all azimuth moments, and improving the accuracy and robustness of ISAR imaging.

[0177] And Figure 1 Corresponding to the embodiment shown, the embodiment of the present invention also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the method steps of the FPGA-based ISAR multi-pulse cumulative cross-correlation distance and phase correction described in any of the above embodiments.

[0178] Applying the storage medium provided by the embodiment of the present invention to solve the problems of distance and phase correction in ISAR imaging is beneficial to achieving precise alignment of echo signals at all azimuth moments, and improving the accuracy and robustness of ISAR imaging.

[0179] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can be in the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories and optical memories, etc.) containing computer-usable program codes.

[0180] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0181] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the functions specified in the process Figure 1 a process or processes and / or blocks Figure 1 specified in one block or more blocks.

[0182] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in the process Figure 1 a process or processes and / or blocks Figure 1 specified in one block or more blocks.

[0183] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. An ISAR multi-pulse cumulative cross-correlation distance and phase correction method based on FPGA, characterized in that: The method comprises: Controlling the inverse synthetic aperture radar system to transmit a signal to a target, and receiving an echo signal generated by the transmission signal being reflected by the target; wherein the transmission signal is a linear frequency modulation signal; Performing frequency modulation on the echo signal to obtain a pulse-compressed echo signal; Preprocessing the echo signal after the pulse compression to obtain an echo signal to be processed; Quantizing the echo signal to be processed to obtain a quantized echo signal, and transmitting the quantized echo signal to a preset field programmable gate array development board, so that when the field programmable gate array development board receives the quantized echo signal, it executes a preset multi-pulse cumulative cross-correlation envelope alignment algorithm to align the quantized echo signal, obtains the echo signal after distance and phase correction, and returns it; Receive the distance and phase corrected echo signal returned by the field programmable gate array development board.

2. The method according to claim 1, characterized in that The step of performing frequency modulation on the echo signal to obtain the echo signal after pulse compression includes: Performing difference frequency processing on the echo signal and the reference signal to obtain a difference frequency signal; wherein the reference signal is a linear frequency modulation signal having the same frequency and the same frequency modulation slope as the transmission signal; The difference frequency signal is subjected to fast Fourier transform along the distance direction to obtain an echo signal after pulse compression.

3. The method according to claim 1, characterized in that The step of preprocessing the echo signal after pulse compression to obtain the echo signal to be processed includes: The echo signal after pulse compression is multiplied by a phase compensation function, and the video residual phase term and the envelope tilt term in the echo signal after pulse compression are removed to obtain the echo signal to be processed.

4. The method according to claim 1, characterized in that: Before the step of transmitting the quantized echo signal to a preset field programmable gate array development board, the method further includes: According to the preset algorithm model of the multi-pulse cumulative cross-correlation envelope alignment algorithm, a register transfer level circuit based on the multi-pulse cumulative cross-correlation envelope alignment algorithm is designed and implemented on the field programmable gate array development board.

5. The method according to claim 4, characterized in that The algorithm model of the multi-pulse accumulation cross-correlation envelope alignment algorithm is: Taking the first echo signal of the quantized echo signal as a reference echo signal, and taking the next echo signal adjacent to the first echo signal as an echo signal to be aligned; Calculating the integral of the product of the echo signal to be aligned and the reference echo signal under time translation, obtaining a cross-correlation function between the echo signal to be aligned and the reference echo signal, and determining an offset corresponding to a peak value of an envelope cross-correlation coefficient between the echo signal to be aligned and the reference echo signal according to the cross-correlation function; Taking the offset corresponding to the peak value of the envelope mutual correlation coefficient between the echo signal to be aligned and the reference echo signal as the relative movement between the two echo signals; constructing a phase compensation term based on the relative movement amount, and multiplying the echo signal to be aligned by the phase compensation term to obtain an echo signal after distance alignment; The echo signal obtained by adding the echo signal after distance alignment and the reference echo signal is used as a new reference echo signal, the next echo signal adjacent to the second echo signal is used as a new echo signal to be aligned, and the step of calculating the integral of the product of the echo signal to be aligned and the reference echo signal under time shift is returned to continue execution until the echo signals at all azimuth moments are aligned.

6. The method according to claim 1, characterized in that When the field programmable gate array development board receives the quantized echo signal, the step of executing a preset multi-pulse cumulative cross-correlation envelope alignment algorithm to align the quantized echo signal includes: When the field programmable gate array development board receives the quantized echo signal, the field programmable gate array development board uses the reusable integrated circuit module integrated inside itself to perform a fast Fourier transform of Nr points along the distance direction on the quantized echo signal to obtain frequency domain data, wherein Nr is a preset number of sampling points of the quantized echo signal in the distance direction; Zeros are respectively padded at both ends of the frequency domain data to extend the data length of the frequency domain data to a preset number of times of the original length, and a fast Fourier inverse transform of a preset number of times × Nr points is performed along the distance direction to obtain a preset number of times of interpolated data, and it is determined whether the preset number of times of interpolated data is the primary echo data corresponding to the primary echo signal. If so, the preset number of times of interpolated data is saved in a sampling module, and the preset number of times of interpolated data is sequentially performed with modulus and square root operations; if not, the preset number of times of interpolated data is directly performed with modulus and square root operations in sequence; Obtain the data after square root extraction, and determine whether the data after square root extraction is the initial echo data corresponding to the initial echo signal. If so, save the data after square root extraction as reference echo data to the reference module; if not, when the validity moment of the next echo data is reached, respectively obtain the reference echo data and the validity signal of the next echo data, and perform fast Fourier transform of a preset number of times × Nr points on the reference echo data and the validity signal of the next echo data simultaneously along the distance direction, and respectively obtain the frequency domain signal to be aligned and the reference echo frequency domain signal; Perform point-by-point complex conjugate multiplication on the frequency domain signal to be aligned and the frequency domain signal of the reference echo, obtain the multiplication result, perform a fast Fourier inverse transform of a preset number of times × Nr points on the multiplication result along the distance direction, obtain the transformation result, and perform modulus calculation and square root calculation on the transformation result in turn to obtain the mutual correlation coefficient between the echo to be aligned and the reference echo; Iteratively update the mutual correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the mutual correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantized sine function value and cosine function value from a pre-saved index table according to the index, construct a phase compensation function according to the obtained function values, and use the phase compensation function to compensate the preset number of times interpolated data corresponding to each echo, and obtain the frequency domain phase compensated data of the echo to be aligned corresponding to each echo; For the frequency domain phase compensated data of the echo to be aligned corresponding to each echo, perform an inverse fast Fourier transform of a preset number of times × Nr points along the distance direction, obtain the transformation result, perform a fast Fourier transform cyclic shift operation on the transformation result, obtain the shifted data, and save the shifted data to the sampling module; Accumulating the shifted data and the saved reference echo data, and saving the accumulated result as new reference echo data to the reference module; Acquire the data saved in the sampling module, perform a preset number of extractions on the data, obtain the distance-aligned echo data whose distance dimension is consistent with the initial input data, and return the echo data; Determine whether the envelope alignment has been completed for each echo data, if so, end; if not, return to the step of performing modulus and square root operations on the preset number of times interpolated data in sequence and continue to execute.

7. An FPGA-based ISAR multi-pulse cumulative cross-correlation distance and phase correction system, characterized in that: The system comprises: a host computer and a field programmable gate array development board; The host computer is used for: Controlling the inverse synthetic aperture radar system to transmit a signal to a target, and receiving an echo signal generated by the transmission signal being reflected by the target; wherein the transmission signal is a linear frequency modulation signal; Performing frequency modulation on the echo signal to obtain a pulse-compressed echo signal; Preprocessing the echo signal after the pulse compression to obtain an echo signal to be processed; Quantizing the echo signal to be processed to obtain a quantized echo signal, transmitting the quantized echo signal to the field programmable gate array development board through a network, and receiving the distance and phase corrected echo signal returned by the field programmable gate array development board; The FPGA development board is used to: Receive the quantized echo signal sent by the host computer, and execute a preset multi-pulse cumulative cross-correlation envelope alignment algorithm to align the quantized echo signal, obtain the echo signal after distance and phase correction and return it to the host computer.

8. The system according to claim 7, characterized in that The field programmable gate array development board is specifically used for: When the quantized echo signal is received, the reusable integrated circuit module integrated inside the device is used to perform a fast Fourier transform of Nr points along the distance direction on the quantized echo signal to obtain frequency domain data, wherein Nr is a preset number of sampling points of the quantized echo signal along the distance direction; Zeros are respectively padded at both ends of the frequency domain data to extend the data length of the frequency domain data to a preset number of times of the original length, and a fast Fourier inverse transform of a preset number of times × Nr points is performed along the distance direction to obtain a preset number of times of interpolated data, and it is determined whether the preset number of times of interpolated data is the primary echo data corresponding to the primary echo signal. If so, the preset number of times of interpolated data is saved in a sampling module, and the preset number of times of interpolated data is sequentially performed with modulus and square root operations; if not, the preset number of times of interpolated data is directly performed with modulus and square root operations in sequence; Obtain the data after square root extraction, and determine whether the data after square root extraction is the initial echo data corresponding to the initial echo signal. If so, save the data after square root extraction as reference echo data to the reference module; if not, when the validity moment of the next echo data is reached, respectively obtain the reference echo data and the validity signal of the next echo data, and perform fast Fourier transform of a preset number of times × Nr points on the reference echo data and the validity signal of the next echo data simultaneously along the distance direction, and respectively obtain the frequency domain signal to be aligned and the reference echo frequency domain signal; Perform point-by-point complex conjugate multiplication on the frequency domain signal to be aligned and the frequency domain signal of the reference echo, obtain the multiplication result, perform a fast Fourier inverse transform of a preset number of times × Nr points on the multiplication result along the distance direction, obtain the transformation result, and perform modulus calculation and square root calculation on the transformation result in turn to obtain the mutual correlation coefficient between the echo to be aligned and the reference echo; Iteratively update the mutual correlation coefficient between the echo to be aligned and the reference echo, determine the index corresponding to the maximum value of the mutual correlation coefficient between the echo to be aligned and the reference echo, obtain the corresponding quantized sine function value and cosine function value from a pre-saved index table according to the index, construct a phase compensation function according to the obtained function values, and use the phase compensation function to compensate the preset number of times interpolated data corresponding to each echo, and obtain the frequency domain phase compensated data of the echo to be aligned corresponding to each echo; For the frequency domain phase compensation of the echo to be aligned corresponding to each echo, perform a fast Fourier inverse transform of a preset number of times × Nr points along the distance direction, obtain the transformation result, perform a fast Fourier transform cyclic shift operation on the transformation result, obtain the shifted data, and save the shifted data to the sampling module; Accumulating the shifted data and the saved reference echo data, and saving the accumulated result as new reference echo data to the reference module; Acquire the data saved in the sampling module, perform a preset number of extractions on the data, obtain the distance-aligned echo data whose distance dimension is consistent with the initial input data, and return the echo data to the host computer; Determine whether the envelope alignment has been completed for each echo data, if so, end; if not, return to the step of performing modulus and square root operations on the preset number of times interpolated data in sequence and continue to execute.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; The memory is used to store computer programs; The processor is used to implement the method steps described in any one of claims 1-6 when executing the program stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1 to 6 are implemented.

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