Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a peripheral area provided around the display area; a pad area provided near an edge of the substrate; and a plurality of pads provided in the pad area and arranged along the edge of the substrate. An end of a first pad, which is the outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is provided between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wiring.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0121680, filed with the Korean Intellectual Property Office on October 1, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to a display device. Background Art

[0003] A display device such as a liquid crystal display (LCD) device or an organic light emitting diode (OLED) display device includes a display panel, and the display panel includes a plurality of signal lines and a plurality of pixels for displaying an image. Each pixel may include a pixel electrode for receiving a data signal, and the pixel electrode may be connected to at least one transistor and may receive a data signal.

[0004] The display panel may include a display area in which an image is displayed and a peripheral area provided around the display area. A driving circuit for driving the display panel may be formed in the peripheral area, or a printed circuit film or a driving chip may be attached in the peripheral area. A pad area in which a plurality of pads (or referred to as "bond pads" or "landing pads") are formed may be provided at one edge of the peripheral area of the display panel. The printed circuit film or the driving chip may be attached to the pads in the pad area. Summary of the Invention

[0005] Exemplary embodiments of the present invention prevent static electricity from being provided into the display panel through the pads of the display panel.

[0006] According to an exemplary embodiment, a display device includes: a substrate including a display area and a peripheral area provided around the display area; a pad area provided near an edge of the substrate; and a plurality of pads provided in the pad area and arranged along the edge of the substrate. An end of a first pad, which is the outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is provided between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wiring.

[0007] In an exemplary embodiment, the display device further includes: a resistor pattern provided on the substrate; and an insulating layer provided on the resistor pattern and having an opening exposing the resistor pattern. The resistor includes the resistor pattern, and the first pad is provided on the insulating layer and is electrically connected to the resistor pattern through the opening.

[0008] In an exemplary embodiment, the resistor pattern includes a semiconductor material.

[0009] In an exemplary embodiment, the resistor pattern has a polygonal shape in a plan view.

[0010] In an exemplary embodiment, the display device further includes: a plurality of gate lines disposed in the display area; and a gate driver disposed in the peripheral area and electrically connected to the plurality of gate lines. The gate driver includes transistors, and wirings are electrically connected to the transistors.

[0011] In an exemplary embodiment, the display device further includes: a plurality of data lines disposed in the display area; and a circuit portion disposed in the peripheral area and electrically connected to the plurality of data lines. The circuit portion includes transistors, and wirings are electrically connected to the gate terminals of the transistors.

[0012] In an exemplary embodiment, the circuit portion is disposed between the pad area and the display area in a plan view.

[0013] In an exemplary embodiment, the display device further includes: a plurality of data lines disposed in the display area; and a connection controller disposed in the peripheral area and electrically connected to the plurality of data lines. The connection controller includes transistors, and wirings are electrically connected to the gate terminals of the transistors.

[0014] In an exemplary embodiment, the connection controller is disposed between the pad area and the display area in a plan view.

[0015] In an exemplary embodiment, the display device further includes a voltage line disposed in the peripheral area and transmitting a constant voltage. The plurality of pads further include a second pad electrically connected to the voltage line.

[0016] In an exemplary embodiment, the second pad is disposed at a position more outward than the first pad.

[0017] In an exemplary embodiment, the display device includes: a substrate including a display area and a peripheral area disposed around the display area; a pad area disposed near an edge of the substrate; and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. Ends of the pads included in the plurality of pads are connected to resistors, and the resistors are disposed between the ends of the pads and the edge of the substrate.

[0018] In an exemplary embodiment, the display device further includes: a resistor pattern disposed on the substrate; and an insulating layer disposed on the resistor pattern and having an opening exposing the resistor pattern. The resistor includes the resistor pattern, and the pad is disposed on the insulating layer and electrically connected to the resistor pattern through the opening.

[0019] In an exemplary embodiment, the resistor pattern includes a semiconductor material.

[0020] In an exemplary embodiment, the resistor pattern intersects with the edge of the substrate.

[0021] In an exemplary embodiment, the resistor pattern is bent in a zigzag form.

[0022] In an exemplary embodiment, the resistor pattern includes a first resistor pattern and a second resistor pattern. The first resistor pattern is disposed between the pad and the edge of the substrate, and the second resistor pattern is connected to the first resistor pattern and overlaps the pad in a plan view.

[0023] According to an exemplary embodiment, a display device includes: a substrate including a display area and a peripheral area disposed around the display area; a pad area disposed near an edge of the substrate; and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a pad included in the plurality of pads is electrically connected to a resistor pattern disposed on the substrate, and the resistor pattern includes a portion disposed between the pad and the edge of the substrate.

[0024] In an exemplary embodiment, the resistor pattern includes a semiconductor material and is bent in a zigzag form.

[0025] In an exemplary embodiment, the resistor pattern intersects the edge of the substrate.

[0026] According to an exemplary embodiment of the present invention, static electricity can be prevented from being provided into the display panel through the pads of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 A plan layout view of a display panel included in a display device according to an exemplary embodiment of the present invention is shown.

[0029] Figure 2 A plan layout view of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention is shown.

[0030] Figure 3 A plan layout view of an enlarged portion of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention is shown.

[0031] Figure 4 Shows Figure 3 A cross-sectional view of the display panel shown in taken with respect to line IVa-IVb.

[0032] Figure 5 , Figure 6 , Figure 7 and Figure 8 respectively show plan layout views of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention.

[0033] Figure 9A plan layout view showing an enlarged portion of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention.

[0034] Figure 10 Shows Figure 9 A cross-sectional view of the display device shown in

[0035] Figure 11 A plan layout view showing an enlarged portion of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention.

[0036] Figure 12 Shows Figure 11 A cross-sectional view of the display device shown in Detailed Description

[0037] Hereinafter, exemplary embodiments of the present invention will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0038] It will be understood that when a component such as a film, region, layer, or element is referred to as being "on", "connected to", "bonded to", or "adjacent to" another component, the component can be directly on, directly connected to, directly bonded to, or directly adjacent to the other component, or an intermediate component may be present. It will also be understood that when a component is referred to as being "between" two components, the component can be the only component between the two components, or one or more intermediate components may also be present. Other words used to describe the relationship between elements should be interpreted in a similar manner.

[0039] For ease of description, spatial relative terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "under", "below", or "beneath" another element or feature will then be positioned "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can cover both an upper and a lower orientation.

[0040] It should be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, a "first" element in an exemplary embodiment can be described as a "second" element in another exemplary embodiment.

[0041] It should be understood that the description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments, unless the context clearly indicates otherwise.

[0042] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0043] Unless expressly stated to the contrary, the word "comprising" and its variants will be understood to mean including the stated element but not excluding any other element.

[0044] Throughout the specification, a plan view represents a view for observing a plane parallel to two directions (e.g., a first direction DR1 and a second direction DR2) intersecting each other, and a cross-sectional view represents a view for observing a plane cut in a direction (e.g., a third direction DR3) perpendicular to the plane parallel to the first direction DR1 and the second direction DR2. In addition, when two constituent elements are stacked on each other, this means that the two constituent elements are stacked on each other in the third direction DR3 (e.g., in a direction perpendicular to the upper side of the substrate).

[0045] Now, reference will be made to Figures 1 to 4 a display device according to an exemplary embodiment of the present invention will be described.

[0046] Figure 1 A plan layout view of a display panel included in a display device according to an exemplary embodiment of the present invention is shown. Figure 2 A plan layout view of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention is shown. Figure 3 A plan layout view of an enlarged portion of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention is shown. Figure 4 Shown is Figure 3 a cross-sectional view of the display panel shown in

[0047] A display device according to an exemplary embodiment of the present invention includes a display panel 1000, and the display panel 1000 includes a display area DA and a peripheral area PA. The display panel 1000 includes a substrate 110.

[0048] The display area DA is an area in which a plurality of pixels PX are arranged to display an image. Each pixel PX may include a pixel circuit including at least one transistor (e.g., Tb, Tf) and a light emitter for displaying light.

[0049] A plurality of signal lines 151 and 171 may be provided in the display area DA. The signal lines 151 and 171 may include gate lines 151 for transmitting gate signals and data lines 171 for transmitting data signals. The gate line 151 may be electrically connected to a gate terminal Gb of one transistor Tb of the pixel circuit of the pixel PX. The data line 171 may be electrically connected to a source terminal Sf of one transistor Tf of the pixel circuit of the pixel PX. The transistor Tf may be different from the transistor Tb or may be an equivalent transistor depending on the structure of the pixel circuit.

[0050] Each gate line 151 may extend substantially along a first direction DR1, and each data line 171 may extend substantially along a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be substantially perpendicular to each other.

[0051] The peripheral area PA is an area in which no image is displayed and is provided near the display area DA. For example, the peripheral area PA may surround the display area DA. The peripheral area PA may correspond to a bezel of the display device. However, the present invention is not limited thereto. For example, in an exemplary embodiment, at least a part of the peripheral area PA may display an image.

[0052] The peripheral area PA may include gate drivers 400a and 400b, a connection controller 500, a circuit part 600, and a pad area PADA. According to an exemplary embodiment, each of the gate drivers 400a and 400b, the connection controller 500, and the circuit part 600 may be an electronic circuit.

[0053] The gate drivers 400a and 400b may be electrically connected to the plurality of gate lines 151 and may apply a plurality of gate signals to the plurality of gate lines 151. Figure 1 A case where the first gate driver 400a is provided on the left edge DE1 of the display area DA and the second gate driver 400b is provided on the right edge DE2 of the display area DA is illustrated. The gate drivers 400a and 400b may generate gate signals including a gate-on voltage and a gate-off voltage and may apply the gate signals to the plurality of gate lines 151 extending along the first direction DR1 and arranged along the second direction DR2.

[0054] The gate drivers 400a and 400b may include a plurality of stages ST1, ST2, ST3, …… that are connected dependently on each other and sequentially output gate signals. Each stage ST1, ST2, ST3, …… may include a transistor Ta. The transistor Ta may include a source terminal Sa for receiving a start signal indicating the start of the operation of the stages ST1, ST2, ST3, …… or a carry signal from a previous stage.

[0055] When forming the transistors Tb and Tf included in the pixel circuit forming the pixel PX, the plurality of transistors Ta may be integrated with the substrate 110 in the same process.

[0056] In an exemplary embodiment, one of the first gate driver 400a and the second gate driver 400b may be omitted.

[0057] The connection controller 500 and the circuit portion 600 may be disposed outside the lower edge DE3 of the display area DA and may be connected to the data line 171. In an exemplary embodiment, the connection controller 500 and the circuit portion 600 may be disposed between the pad area PADA and the display area DA. In an exemplary embodiment, the circuit portion 600 may be disposed in the peripheral area PA below the display area DA.

[0058] The connection controller 500 may include a demultiplexer for selecting one of the data lines 171 and applying a data signal input from the outside. The connection controller 500 may include a plurality of transistors Tc and Te electrically connected to a plurality of data lines 171. The transistor Tc and the transistor Te may be electrically connected to different data lines 171. For example, the transistor Tc may include a source terminal Sc connected to the data line 171. The gate terminal Gc of the transistor Tc and the gate terminal Ge of the transistor Te may be connected to different control lines to receive different control signals, thereby allowing control of the on / off of the transistors Te and Tc. According to the on / off control of the transistors Tc and Te, a data line 171 to which a data signal is to be applied is selected from among the plurality of data lines 171, thereby allowing application of a data signal from the data driving circuit.

[0059] The circuit portion 600 may be a test circuit portion. For example, the circuit portion 600 may be a light emission test circuit portion for testing defects in the display area DA. The circuit portion 600 may include a transistor Td electrically connected to one of the data lines 171. For example, the transistor Td may include a source terminal Sd connected to one of the data lines 171. A test signal may be applied to the data line 171 through the transistor Td in a stage for testing defects in the display area DA, and the display area DA may be tested to determine whether there are defects based on the light emission state of the pixel PX connected to the data line 171.

[0060] The pad region PADA may include a plurality of conductive pads PDa and PDf disposed near an edge EG of the substrate 110, and the edge EG of the substrate 110 is disposed near a lower edge DE3 of the display region DA. The pads PDa and PDf may be arranged substantially parallel to each other in a first direction DR1 along the edge EG of the substrate 110 and may be arranged to form at least one row.

[0061] The display device according to an exemplary embodiment of the present invention may further include a driving circuit 700 attached to and electrically connected to the pad PDf among the plurality of pads PDa and PDf. The driving circuit 700 may include at least one driving circuit chip (such as a data driving circuit as an example) and a circuit film or a circuit board. The at least one driving circuit chip may be mounted on the circuit film or the circuit board.

[0062] A conductive adhesive film such as an anisotropic conductive film is disposed on the plurality of pads PDf so that the pads PDf can be electrically connected to the driving circuit 700. The conductive adhesive film may include an adhesive material and conductive particles.

[0063] The peripheral region PA may further include a voltage line 173 extending along a peripheral portion of the display region DA. The voltage line 173 may receive a constant voltage from the driving circuit 700 through the pad PDf.

[0064] According to an exemplary embodiment of the present invention, the plurality of pads PDf are attached to and electrically connected to the driving circuit 700, and the plurality of pads PDa are not connected to the driving circuit 700 and are not covered by the driving circuit 700 and the conductive adhesive film. In this case, the pads PDf connected to or covered by the conductive adhesive film or the driving circuit 700 may be disposed at the center of the pad region PADA, and the plurality of pads PDa not connected to the driving circuit 700 may be disposed on the right or left side of the pads PDf. For example, as Figure 1 shown, the plurality of pads PDa may be disposed on the right and left sides of the pad region PADA, adjacent to the plurality of pads PDf disposed at the center of the pad region PADA.

[0065] The pads PDa not covered by the driving circuit 700 and the conductive adhesive film may include pads for contacting a test probe and inputting a test signal when testing the display panel 1000 to determine whether there are defects.

[0066] According to an exemplary embodiment of the present invention, different from Figure 1 the above, the pads PDa may be connected to the conductive adhesive film and the driving circuit 700 in the same manner as the pads PDf.

[0067] The edges of the substrate 110 may have a circular shape at the four corner portions. For example, the corner edge EG1 of the substrate 110 may have the circular shape as described above, and as the radius of curvature of the corner edge EG1 increases, the distance between the corner edge EG1 and the pad PDa decreases.

[0068] Referring Figure 2 , the plurality of pads PDa may sequentially include a first pad PDa1, a second pad PDa2, a third pad PDa3, a fourth pad PDa4, a fifth pad PDa5,... arranged in order from the pad set closest to the corner edge EG1 of the substrate 110. For example, as the sequence progresses from the first pad PDa1, the second pad PDa2, the third pad PDa3, the fourth pad PDa4, the fifth pad PDa5,..., the pad PDa may approach the plurality of pads PDr. The first pad PDa1, the second pad PDa2, the third pad PDa3, the fourth pad PDa4, the fifth pad PDa5,... may be arranged substantially along the first direction DR1.

[0069] Figure 2 The lower right corner portion of the display panel 1000 is shown. The lower left corner portion of the display panel 1000 may have a form and arrangement symmetric to the structure shown in Figure 2 .

[0070] The first pad PDa1 and the second pad PDa2 may be electrically connected to the voltage line 173 through the wiring 60 and may receive a constant voltage.

[0071] Except for the first pad PDa1 and the second pad PDa2 connected to the voltage line 173, the third pad PDa3 is the pad set outermost with respect to the corner edge EG1 among the plurality of pads PDa. For example, among the plurality of pads PDa, only the pads connected to the voltage line 173 (e.g., the first pad PDa1 and the second pad PDa2) may be set closer to the corner edge EG1 than the third pad PDa3.

[0072] The upper end of the third pad PDa3 is serially coupled to the resistor R1. For example, among the lower end of the third pad PDa3 disposed near the edge EG of the substrate 110 and the upper end of the third pad PDa3 disposed farther from the edge EG of the substrate 110, the upper end is connected to the resistor R1. Accordingly, the lower end of the resistor R1 may be connected to the upper end of the third pad PDa3, and the upper end of the resistor R1 may be connected to one end of the wiring 61. The other end of the wiring 61 may be connected to a different component of the display device as further described below. The resistor R1 may have a conductivity lower than the conductivity of the third pad PDa3 and the wiring 61 (e.g., a higher resistance).

[0073] The resistor R1 may include a material having a resistance greater than that of the third pad PDa3 and the wiring 61. For example, the resistor R1 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0074] Referring Figure 3 and Figure 4 , as a barrier layer 111 of the insulating layer, it may be disposed on the substrate 110, and a resistor pattern 132 included in the resistor R1 may be disposed on the barrier layer 111. The resistor pattern 132 may be disposed on the same layer as the active layer, and a channel region of transistors Ta, Tb, Tc, Td, Te, and Tf, gate drivers 400a and 400b, a connection controller 500, or a circuit portion 600 may be formed on the active layer. The resistor pattern 132 may include a semiconductor material having a carrier concentration similar to that of the channel region of the active layer or a carrier concentration similar to that of the conductive region of the active layer.

[0075] As Figure 3 shown, the resistor pattern 132 according to an exemplary embodiment may have a polygonal shape (such as a rectangle for example) in a plan view. However, the shape of the resistor pattern 132 is not limited thereto. The resistance of the resistor R1 can be adjusted in various ways by controlling the length and / or width of the resistor pattern 132 in the plan view. According to an exemplary embodiment, the resistor pattern 132 may be bent in a meandering form or a zigzag form in the plan view.

[0076] Insulating layers 140a and 140b may be disposed on the resistor pattern 132. The insulating layers 140a and 140b may have an opening 142 exposing a part of the resistor pattern 132. The insulating layer 140a may also have an opening 143 exposing another part of the resistor pattern 132.

[0077] The third pad PDa3 may be disposed on the insulating layers 140a and 140b. The third pad PDa3 may be electrically connected to the resistor pattern 132 through the opening 142.

[0078] The wiring 61 may be disposed between the insulating layer 140a and the insulating layer 140b in a cross-sectional view. The wiring 61 may be electrically connected to the resistor pattern 132 through the opening 143.

[0079] At least one of the third pad PDa3 and the wiring 61 may include at least one of metals including, for example, copper, aluminum, magnesium, silver, gold, platinum, palladium, nickel (Ni), neodymium, iridium, molybdenum, tungsten, titanium, chromium, tantalum, and alloys thereof.

[0080] Compared with the third pad PDa3, the upper ends of at least one pad (e.g., the fifth pad PDa5) among the plurality of pads PDa that is set to be close to the pad PDf can be serially coupled to the resistor R2. The resistor R2 can include a material having a higher resistance than the resistance of the pad PDa. For example, the resistor R2 can include a semiconductor material such as amorphous silicon, polysilicon, or an oxide semiconductor. The resistor R2 can have a similar configuration to the above-described resistor R1.

[0081] In an exemplary embodiment, the resistor R2 can be omitted.

[0082] In an exemplary embodiment, at least one of the first pad PDa1 and the second pad PDa2 can be omitted. In this case, when both the first pad PDa1 and the second pad PDa2 are omitted, the third pad PDa3 is the outermost - set pad among the plurality of pads PDa (e.g., with respect to the corner edge EG1 of the substrate 110). For example, among all of the plurality of pads PDa, the outermost third pad PDa3 can be set to be closest to the corner edge EG1 of the substrate 110. In this case, the first end of the outermost third pad PDa3 is connected to the first end of the resistor R1, the outermost third pad PDa3 is disposed between the resistor R1 and the edge EG of the substrate 110, and the second end of the resistor R1 is connected to the wiring 61.

[0083] Electrostatic electricity input from the display side of the display panel 1000 or from the outside of the display panel 1000 can be input into the pads PDa and PDf through the edge EG or the corner edge EG1 of the substrate 110, and the electrostatic electricity input into the pads PDa and PDf can be input into the display panel 1000, which may damage electrical components or wirings. For example, as the radius of curvature of the corner edge EG1 of the display panel 1000 increases, the distance between the corner edge EG1 and the pad PDa decreases. As a result, the third pad PDa3, which is the outermost pad among the plurality of pads PDa (excluding pads connected to the voltage line 173, such as pads PDa1 and PDa2), is more vulnerable to the input of electrostatic electricity (e.g., compared with other pads, the third pad PDa3 is more likely to allow the inflow of electrostatic electricity).

[0084] However, according to an exemplary embodiment of the present invention, the resistor R1 is connected to the upper ends of the third pad PDa3 disposed at the right - most outermost portion and the left - most outermost portion in the pad region PADA (excluding the first pad PDa1 and the second pad PDa2 that are electrically connected to the voltage line 173 for transmitting a constant voltage), thereby preventing electrostatic electricity from being input into the display panel 1000 through the third pad PDa3 that is set to be closest to the corner edge EG1 of the substrate 110.

[0085] When there are a first pad Pda1 and a second pad Pda2, the first pad Pda1 and the second pad Pda2 set closest to the corner edge EG1 of the substrate 110 are connected to a voltage line 173 for transmitting a constant voltage, thereby dispersing static electricity.

[0086] Unlike the pad Pdf, when a pad Pda among a plurality of pads Pda and Pdf is not connected to the conductive adhesive film or the driving circuit 700, the pad Pda is exposed to the outside. As a result, the pad Pda may be vulnerable to the inflow of static electricity (e.g., the pad Pda may be more likely to allow the inflow of static electricity compared to the pad Pdf). However, according to an exemplary embodiment of the present invention, it is possible to prevent static electricity from flowing into the display panel 1000 through a third pad Pda3 set closest to the corner edge EG1 of the substrate 110 (excluding pads connected to the voltage line 173, such as pads Pda1 and Pda2).

[0087] Now, reference will be made to Figures 5 to 7 a display device according to an exemplary embodiment of the present invention will be described together with the above - mentioned drawings.

[0088] Figures 5 to 7 A plan layout diagram of an edge portion of a display panel 1000 included in a display device according to an exemplary embodiment of the present invention is shown respectively.

[0089] Figures 5 to 7 A lower - right corner portion of a display panel 1000 according to an exemplary embodiment of the present invention is shown. The lower - left corner portion of the display panel 1000 may have a shape and arrangement symmetric to the structure described with reference to Figures 5 to 7 the description.

[0090] Reference is made to Figure 5 together with Figure 1 , in a display device according to an exemplary embodiment, a wiring 61 connected to the upper end of a resistor R1 connected to a third pad Pda3 may be electrically connected to the gate drivers 400a and 400b. For example, the wiring 61 may be electrically connected to a source terminal Sa of a transistor Ta included in a first stage ST1 among a plurality of stages ST1, ST2, ST3,... included in the gate drivers 400a and 400b.

[0091] When a start signal is input to the third pad PDa3 in a stage for testing the display panel 1000, the first stage ST1 of the gate drivers 400a and 400b may output a first scan signal to the gate line 151 in response to the start signal. The first scan signal or carry signal output in the first stage ST1 may be applied to the second stage ST2 as a start signal of the second stage ST2. In the above manner, a plurality of stages ST1, ST2, ST3, … included in the gate drivers 400a and 400b may be sequentially driven to sequentially apply scan signals to the plurality of gate lines 151.

[0092] Referring Figure 6 Together with Figure 1 , in the display device according to an exemplary embodiment, a wiring 61 connected to the upper end of a resistor R1 connected to the third pad PDa3 may be electrically connected to the circuit portion 600. For example, the wiring 61 may be electrically connected to gate terminals Gd of a plurality of transistors Td included in the circuit portion 600.

[0093] When a test gate signal is input to the third pad PDa3 in a stage for testing the display panel 1000, the transistor Td of the circuit portion 600 may be turned on in response to the test gate signal, and a test signal may be applied to the data line 171 connected to the transistor Td through the turned-on transistor Td. Then, a test may be performed to determine whether the display panel 1000 has a defect in view of the light-emitting state of the pixel PX connected to the data line 171.

[0094] Referring Figure 7 Together with Figure 1 , in the display device according to an exemplary embodiment, a wiring 61 connected to the upper end of a resistor R1 connected to the third pad PDa3 may be electrically connected to the connection controller 500. For example, the wiring 61 may be electrically connected to a gate terminal Gc of a transistor Tc or a gate terminal Ge of a transistor Te included in the connection controller 500.

[0095] When a control signal is input to the third pad PDa3 in a stage for testing the display panel 1000, the transistor Tc or the transistor Te to which the control signal is applied in the connection controller 500 is turned on, and a data signal may be applied to the data line 171 connected to the transistors Tc and Te through the turned-on transistors Tc and Te. Then, a test may be performed to determine whether the display panel 1000 has a defect in view of the light-emitting state of the pixel PX connected to the data line 171.

[0096] Compared with the signal applied to the fourth pad PDa4 to which the resistor among the multiple pads PDa is not connected, the signal applied to the third pad PDa3 disposed on the right outermost part and the left outermost part of the pad region PADA and not connected to the voltage line 173 can be a signal with less flowing current and for controlling whether to turn on / off a transistor or a driver. Therefore, when the resistor R1 is connected to the upper end of the third pad PDa3, the signal can be sufficiently applied through the third pad PDa3.

[0097] One of the various signals applied to the above-mentioned third pad PDa3 can be applied to the fifth pad PDa5 connected to the resistor R2.

[0098] Now, reference will be made to Figures 8 to 10 the display device according to an exemplary embodiment of the present invention together with the above-mentioned drawings.

[0099] Figure 8 A plan layout diagram showing an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention is shown. Figure 9 A plan layout diagram showing an enlarged portion of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention is shown. Figure 10 Shows Figure 9 a cross-sectional view of the display device shown in

[0100] Referring to Figure 8 , the display device according to an exemplary embodiment may include a display panel 1000a, and the display panel 1000a includes a pad region PADA disposed near one edge EG of a substrate 110.

[0101] The pad region PADA includes a plurality of conductive pads PD arranged along the edge EG of the substrate 110. The plurality of pads PD may or may not be connected to at least one driving circuit chip (taking, for example, a data driving circuit included in a display device according to an exemplary embodiment of the present invention), a circuit film, or a circuit board. For example, the plurality of pads PD may include pads PDa or pads PDf according to the above exemplary embodiment.

[0102] The lower end of at least one of the plurality of pads PD may be serially coupled to a resistor R3. For example, among the upper and lower ends of at least one pad PD whose lower end is disposed closer to the edge EG of the substrate 110 than the upper end among the plurality of pads PD, the lower end may be connected to the resistor R3. In an exemplary embodiment, each of the plurality of pads PD may be connected to the resistor R3, as shown in Figure 8 .

[0103] The wiring 14 may be connected between the pad PD and the resistor R3. In an exemplary embodiment, the wiring 14 may be omitted.

[0104] The resistor R3 may have a lower conductivity (e.g., a higher resistance) than the conductivity of the pad PD and the wiring 14. The resistor R3 may be formed up to the edge EG of the substrate 110.

[0105] The resistor R3 may include a material having a higher resistance than the resistance of the pad PD and the wiring 14. For example, the resistor R3 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0106] According to an exemplary embodiment of the present invention, the resistor R3 is connected to the lower end of the pad PD in the pad region PADA provided near the edge EG of the substrate 110. As a result, it is possible to prevent the inflow of static electricity provided from the display side of the display panel 1000a or the outside of the display panel 1000a from being provided to the pad PD through the edge EG of the substrate 110. Therefore, it is possible to prevent static electricity from flowing into the display panel 1000a through the pad PD, and it is possible to prevent the electrical components or wirings of the display panel 1000a from being damaged by static electricity.

[0107] Refer to Figure 8 , during the process for manufacturing the display device, the display panel 1000a may further include a wiring region RA provided on the mother substrate 1 before the edge EG of the substrate 110 is cut. The wiring region RA may be a region that is removed when the manufacturing process is completed.

[0108] The wiring region RA may include a plurality of wirings 12 electrically connected to the pad PD and a shorting bar 10. The shorting bar 10 may include a portion extending substantially along the first direction DR1. The shorting bar 10 may transmit a constant voltage such as a ground voltage for example. The wiring 12 may include the same material as the material of the resistor pattern 130 (see Figure 9 ), or may include a conductive material different from the material of the resistor pattern 130.

[0109] The plurality of wirings 12 may be arranged along the first direction DR1 and extend along a substantially second direction DR2.

[0110] Each of the wirings 12 may start from the edge EG of the substrate 110 and may extend up to the shorting bar 10. During the process for manufacturing the display panel 1000a, the wiring 12 may protect the pad PD from static electricity by transmitting a constant voltage such as a ground voltage for example from the shorting bar 10. The upper end of the wiring 12 may be electrically connected to the lower end of the resistor R3 near the edge EG of the substrate 110.

[0111] For the process for manufacturing the display panel 1000a, after removing the wiring region RA, it is possible to prevent static electricity from flowing into the pad PD through the resistor R3.

[0112] Multiple pad PDs may or may not have characteristics equivalent to those of the above-described pad PDa according to an exemplary embodiment.

[0113] Referring to Figure 9 and Figure 10 Referring to

[0114] Referring to Figure 9 and Figure 9 as shown in

[0115] A barrier layer 111 serving as an insulating layer may be disposed on a substrate 110, and a resistor pattern 130 included in a resistor R3 may be disposed on the barrier layer 111. The resistor pattern 130 may be disposed on the same layer as an active layer, and a channel region of transistors Ta, Tb, Tc, Td, Te, and Tf, gate drivers 400a and 400b, a connection controller 500, or a circuit portion 600 may be formed on the active layer. The resistor pattern 130 may include a semiconductor material having a carrier concentration similar to that of the channel region of the active layer or a carrier concentration similar to that of the conductive region of the active layer.

[0116] Referring to Figure 10 and

[0117] Insulating layers 140a and 140b may be disposed on the resistor pattern 130. The insulating layers 140a and 140b may have openings 145 exposing the resistor pattern 130.

[0118] A pad PD may be disposed on the insulating layers 140a and 140b. The pad PD may be electrically connected to the resistor pattern 130 through the opening 145.

[0119] An insulating layer 160 may be disposed on the pad PD. The insulating layer 160 may have an opening 165 exposing an upper portion of the pad PD.

[0120] It may be removed in a process for manufacturing a display device in Figure 8 and Figure 9The wiring area RA is provided outside the edge EG of the substrate 110 as shown. Accordingly, the wiring 12 connected to the resistor R3 can be removed. However, after the wiring area RA is removed, the resistor R3 is connected between the pad PD and the edge EG of the substrate 110. As a result, electrostatic charge input from the outside can be prevented from being transferred to the pad PD.

[0121] Now, a display device according to an exemplary embodiment of the present invention will be described with reference to Figure 11 and Figure 12 .

[0122] Figure 11 FIG. shows a plan layout view of an enlarged portion of an edge portion of a display panel included in a display device according to an exemplary embodiment of the present invention. Figure 12 FIG. shows Figure 11 a cross-sectional view of the display device shown in

[0123] with respect to the line XIIa-XIIb. Figure 11 , except that in Figure 11 the resistor R3 may include resistor patterns 130a and 130b, a display device according to an exemplary embodiment may be similar to the display device according to an exemplary embodiment described with reference to Figures 8 to 10 . The resistor patterns 130a and 130b may be disposed on the same layer as the active layer in the same manner as the resistor pattern 130.

[0124] The resistor pattern 130a may be disposed between the pad PD and the edge EG of the substrate 110 in a plan view, and the resistor pattern 130b may include a portion overlapping the pad PD in a plan view. The resistor pattern 130a is electrically connected to the resistor pattern 130b.

[0125] With reference to Figure 12 , insulating layers 140a and 140b may be disposed on the resistor patterns 130a and 130b. The insulating layers 140a and 140b may have an opening 145 exposing the resistor pattern 130b.

[0126] The pad PD may be disposed on the insulating layers 140a and 140b. The pad PD may be electrically connected to the resistor pattern 130b through the opening 145.

[0127] An insulating layer 160 may be disposed on the pad PD. The insulating layer 160 may have an opening 165 exposing an upper portion of the pad PD.

[0128] The resistance of the resistor R3 can be controlled in various ways by controlling the planar length and / or width of the resistor patterns 130a and 130b. As Figure 11As shown, the resistor patterns 130a and 130b may be bent in a meandering form or a zigzag form in a plan view. The resistance of the resistor R3 may be controlled in various ways by controlling the degree of bending and the number of bends of the resistor patterns 130a and 130b.

[0129] The wiring area provided outside the edge EG of the substrate 110 shown in Figure 11 may be removed during the process for manufacturing the display device. Accordingly, the wiring 12 connected to the resistor R3 may be removed. However, after the wiring area is removed, the resistor R3 is connected between the pad PD and the edge EG of the substrate 110. As a result, electrostatic electricity provided from the outside may be prevented from being transferred to the pad PD. In addition, the resistor pattern 130b may be formed to overlap the pad PD. As a result, the ability to control the resistance of the resistor R3 including the resistor patterns 130a and 130b may be increased.

[0130] Although the present invention has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention as defined by the claims.

Claims

1. A display device, the display device comprising: A substrate, including a display area and a peripheral area disposed around the display area; A pad area, disposed near an edge of the substrate; A plurality of pads, disposed in the pad area and arranged along the edge of the substrate, wherein the plurality of pads includes a first group of pads disposed at a center of the pad area and a second group of pads disposed at a side of the first group of pads; and A voltage line, disposed in the peripheral area and transmitting a constant voltage, wherein a second pad, which is an outermost pad among the second group of pads, receives the constant voltage through the voltage line, An end of a first pad, which is disposed between the first group of pads and the second pad among the second group of pads, is connected to a first end of a resistor, The first pad is disposed between the resistor and the edge of the substrate, and A second end of the resistor is connected to a wiring.

2. The display device according to claim 1, the display device further comprising: A resistor pattern, disposed on the substrate; And An insulating layer, disposed on the resistor pattern and having an opening exposing the resistor pattern, wherein the resistor includes the resistor pattern, and The first pad is disposed on the insulating layer and is electrically connected to the resistor pattern through the opening.

3. The display device according to claim 2, wherein, The resistor pattern includes a semiconductor material.

4. The display device according to claim 2, wherein, The resistor pattern has a polygonal shape in a plan view.

5. The display device according to claim 1, the display device further comprising: A plurality of gate lines, disposed in the display area; And A gate driver, disposed in the peripheral area and electrically connected to the plurality of gate lines, wherein the gate driver includes a transistor, and The wiring is electrically connected to the transistor.

6. The display device according to claim 1, the display device further comprising: A plurality of data lines, disposed in the display area; And A circuit portion, disposed in the peripheral area and electrically connected to the plurality of data lines, wherein the circuit portion includes a transistor, and The wiring is electrically connected to a gate terminal of the transistor.

7. The display device according to claim 6, wherein, The circuit portion is disposed between the pad area and the display area in a plan view.

8. The display device according to claim 1, the display device further comprising: A plurality of data lines, disposed in the display area; And A connection controller, disposed in the peripheral area and electrically connected to the plurality of data lines, wherein the connection controller includes a transistor, and The wiring is electrically connected to a gate terminal of the transistor.

9. The display device according to claim 8, wherein, The connection controller is disposed between the pad area and the display area in a plan view.

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