A task processing method and device

Abstract

The present invention discloses a task processing method and device of a processor, wherein the processor comprises at least two processing cores, and the method comprises: obtaining a scheduling parameter corresponding to a first task executed by each of the processing cores in a first cycle; determining a second core-time slot table corresponding to each of the processing cores in the second cycle according to a second task of each of the processing cores in the second cycle and the scheduling parameter; utilizing each of the processing cores to execute the second task based on the second core-time slot table in the second cycle; the second cycle is after the first cycle; obtaining the second core-time slot table by inferring the time consumption data of the first cycle, so that the task arrangement in the second core-time slot table is more compact and precise, and is very close to the actual execution situation; and improving the overall operation efficiency of the processor.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a task processing method and device. Background Art

[0002] In current servers or computers, processors generally include multiple cores. Multi-core collaborative task processing can significantly improve the work efficiency of the processor. The collaboration between multiple cores, as well as the scheduling and allocation of tasks, have a direct impact on the overall efficiency of the processor.

[0003] In the process of task scheduling, the prior art can formulate a two-dimensional table including time / core, called core-time slot table, to reflect the distribution of tasks. In reality, due to the influence of various factors, the time consumed by the core to execute a specific task is often unstable. Therefore, in the scheduling strategy, the core-time slot table can also be designed to be dynamic. That is, combined with the actual execution of the task, the scheduling is constantly re-performed, and the task allocation in the core-time slot table is frequently adjusted. In this way, each core can achieve full load in a dynamic manner, avoiding the waste of performance resources.

[0004] The drawback of the prior art is that frequent scheduling itself will also cause a certain waste of performance resources, resulting in the overall efficiency of the processor to be improved. Summary of the invention

[0005] The present invention provides a task processing method and device for a processor, so as to at least solve the above technical problems existing in the prior art.

[0006] In a first aspect, the present invention provides a task processing method of a processor, wherein the processor includes at least two processing cores, and the method includes:

[0007] Obtaining scheduling parameters corresponding to the first task executed by each of the processing cores in the first cycle;

[0008] Determine a second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter;

[0009] Utilizing each of the processing cores, executing the second task based on the second core-time slot table in the second cycle;

[0010] The second period is after the first period.

[0011] Preferably, obtaining the scheduling parameters corresponding to the execution of the first task by each of the processing cores in the first cycle includes:

[0012] Utilizing each of the processing cores, executing the first task based on a first core-time slot table in the first cycle;

[0013] The scheduling parameters are determined according to the time consumption data of each processing core executing the first task.

[0014] Preferably, determining the scheduling parameter according to the time consumption data of each processing core executing the first task includes:

[0015] The scheduling parameters are determined according to the time consumption data and the load data of each of the processing cores in the first cycle.

[0016] Preferably, determining the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter includes:

[0017] According to the second task and the scheduling parameters, a pre-defined scheduling table is queried to determine the second core-time slot table.

[0018] Preferably, determining the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter includes:

[0019] The second task and the scheduling parameters are input into a preset prediction model to predict the second core-time slot table.

[0020] Preferably, determining the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter includes:

[0021] Determining task chain data corresponding to the second task;

[0022] The second core-time slot table is determined according to the task chain data and the scheduling parameters.

[0023] Preferably, the second core-time slot table includes:

[0024] Each of the processing cores corresponds to a second task in each time slot of the second cycle.

[0025] In a second aspect, the present invention provides a task processing device of a processor, wherein the processor includes at least two processing cores, and the method includes:

[0026] Calling a parameter determination module to obtain a scheduling parameter corresponding to the execution of the first task by each of the processing cores in the first cycle;

[0027] A second core-time slot table determination module, configured to determine a second core-time slot table corresponding to each of the processing cores in the second cycle according to the second task of each of the processing cores in the second cycle and the scheduling parameter;

[0028] a second task execution module, configured to execute the second task based on the second core-time slot table in the second cycle by using each of the processing cores;

[0029] The second period is after the first period.

[0030] In a third aspect, the present invention provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program is used to execute the task processing method of the processor described in the present invention.

[0031] In a fourth aspect, the present invention provides an electronic device, comprising:

[0032] processor;

[0033] a memory for storing instructions executable by the processor;

[0034] The processor is used to read the executable instructions from the memory and execute the instructions to implement the task processing method of the processor described in the present invention.

[0035] Compared with the prior art, the present invention provides a task processing method and device, which obtains a second core-time slot table by inferring the time-consuming data of the first cycle, so that the task arrangement in the second core-time slot table is more compact and precise, and is very close to the actual execution situation, thereby avoiding task execution timeout or task completion in advance; there is no need to leave extra margin in the allocation of time slots during the scheduling process, and there is no need to reschedule along the execution process; the overall operating efficiency of the processor is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a core-time slot table in the prior art;

[0037] Figure 2 A flowchart of a task processing method of a processor provided by an embodiment of the present invention;

[0038] Figure 3 A flowchart of another task processing method of a processor provided by an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a first core-time slot table in another task processing method of a processor provided by an embodiment of the present invention;

[0040] Figure 5A schematic diagram of a second core-time slot table in another task processing method of a processor provided by an embodiment of the present invention;

[0041] Figure 6 A schematic diagram of the structure of a task processing device of a processor provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0043] The task scheduling and allocation method of multiple processing cores of a processor has a direct impact on the overall efficiency of the processor. In the process of task scheduling, the prior art can formulate a two-dimensional table including time / core, called a core-time slot table, to reflect the distribution of tasks. During the task execution process, each processing core only needs to know which time slot it is currently in, and can determine which specific task it should execute according to the core-time slot table.

[0044] Figure 1 Schematic diagram of the core-time slot table. Figure 1 In the example shown, the processor includes two processing cores, core 1 and core 2. The tasks to be executed include an upstream task chain and a downstream task chain. The upstream task chain includes task A, task B, task C, and task D, a total of 4 tasks. The downstream task chain includes task a and task b, a total of 2 tasks. Figure 1 The core-time slot table shown clearly shows which task is executed by which processing core in which time slot. For example, task A will be executed by core 1 in time slot 1. Thus, the scheduling and allocation of tasks are realized through the core-time slot table.

[0045] However, the processing core may be affected by various factors during operation, resulting in fluctuations in its performance. Therefore, the time taken by the processing core to execute a specific task is often unstable. In order to ensure that all tasks can be completed, a margin is usually left in the allocation of time slots. For example, Figure 1 In the example, core 2 executes task B in the time range of time slot 2 to time slot 3, and is idle in time slot 4. Considering that the execution of task B may time out, time slot 4 is reserved to ensure that task B is completed even if it times out.

[0046] But in fact, task B may be completed in timeout, or it may be completed normally or even in advance. Assuming that task B has been completed in time slot 2, core 2 is in the space from time slot 3 to time slot 4, which results in performance waste.

[0047] In this regard, the solution of the prior art is to adopt a dynamic scheduling method. That is, after finding that a similar processing core is idle, the subsequent unexecuted tasks are rescheduled. That is, by re-modifying the core-time slot table, some tasks are advanced to the idle time slots of the processing core. In this way, the task allocation in the core-time slot table is as compact as possible to improve the work efficiency of the processor.

[0048] However, the above dynamic scheduling method will constantly reschedule during the operation of the processor and frequently adjust the task allocation in the core-time slot table. However, frequent scheduling itself will also cause a certain waste of performance resources, and sometimes even require a processing core to be occupied for task scheduling. Therefore, the existing task scheduling method still has the technical problem of low efficiency to a certain extent.

[0049] Therefore, an embodiment of the present invention provides a task processing method of a processor to at least solve the above technical problems existing in the prior art. The processor involved in this embodiment also includes at least two processing cores. Figure 2 As shown, the method in this embodiment includes the following steps:

[0050] Step 201: Obtain scheduling parameters corresponding to the execution of a first task by each processing core in a first cycle.

[0051] The first cycle is the time period in which the task execution has been completed. There is also a corresponding core-time slot table in the first cycle, which can be referred to as the first core-time slot table in this embodiment. In the first cycle, each processing core can be used to perform tasks based on the first core-time slot table. The task executed in the first cycle can be referred to as the first task. For example, in the physical layer of a 5G base station, the first task may include uplink tasks and downlink tasks. Uplink tasks may include channel estimation, channel equalization, uplink demodulation, and uplink decoding. The above-mentioned uplink tasks constitute a task chain, which has a strict timing relationship between them and needs to be executed in sequence. Downlink tasks may include downlink coding, downlink modulation, and channel mapping. The above-mentioned downlink tasks also constitute a task chain, which also has a strict timing relationship between them and needs to be executed in sequence.

[0052] After the first task is completed according to the first core-time slot table in the first cycle, the time consumption data of each processing core executing the first task can be further determined. The time consumption data is the time consumed by each processing core to complete each specific task, that is, the actual time consumption of each task in the upstream task chain and the downstream task chain.

[0053] In this embodiment, it can be considered that the computing power required for each type of task in the upstream task chain and the downstream task chain in each cycle is basically the same, that is, the time consumption of executing the task mainly depends on the performance of the processing core. However, a core-time slot table only covers a very short time range in a macro sense, and the performance change of the processing core is continuous. Therefore, it can be inferred that on the same processing core, the time consumption data of a specific task in the previous cycle will be very close to its time consumption in the next cycle.

[0054] In this embodiment, based on this principle, the time consumption data in the first cycle is used as a reference to estimate the time required for the processing core to execute each task in the second cycle after the first cycle. The scheduling parameters are determined based on the estimated time. In other words, the scheduling data includes the time required to be reserved for each task in the second cycle, or how many time slots each task needs to occupy in the second core-time slot table corresponding to the second cycle.

[0055] It should also be noted that the load states of different processing cores of the processor may be different, resulting in differences in their performance. Therefore, when scheduling tasks of the same type to different processing cores, the actual performance states of the processing cores should also be considered to reflect the differences in the execution of tasks by different processing cores. Therefore, preferably, the scheduling parameters can be determined based on the time consumption data and the load data of each processing core in the first cycle.

[0056] Step 202: Determine a second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameters.

[0057] The second cycle is another cycle after the first cycle, and is also the time cycle that is about to begin. The tasks that need to be performed in the second cycle are the second tasks. The specific type, content and number of the second tasks will depend on the actual operation of the processor. For example, in the physical layer of the 5G base station, the second task is generally still the above-mentioned uplink task chain and downlink task chain.

[0058] The purpose of the method of this embodiment is to complete the scheduling of the second task in the second cycle and determine the second core-time slot table corresponding to the second cycle. In other words, the second core-time slot table includes the second tasks corresponding to each processing core in each time slot of the second cycle. Therefore, each processing core runs according to the second core-time slot table in the second cycle, and the second task can be completed.

[0059] In this embodiment, the second core-time slot table is determined based on the scheduling parameters. In other words, the duration required for the second task is estimated based on the time consumption data of the first task. Then, the second task is distributed in the core-time slot table according to the time required for the second task to obtain the second core-time slot table. It can be seen from the above that the time consumption data of a specific task in the previous cycle on the same processing core will be very close to its time consumption in the next cycle; and the scheduling parameters are determined based on the time consumption data and the load data of each processing core, which can also reflect the differences in the execution of tasks by different processing cores.

[0060] Therefore, it can be considered that the duration reserved for each task in the scheduling parameters is basically accurate, without obvious errors. In the process of determining the second core-time slot table, there is no need to leave extra margin in the allocation of time slots. That is, the task arrangement in the second core-time slot table is more compact and precise, very close to the actual execution situation, and there is no need to reschedule during the execution process. When the processing core runs according to the second core-time slot table, there will be few cases of task execution timeout or task completion ahead of schedule. Its overall efficiency is relatively ideal.

[0061] Step 203: Utilize each processing core to execute the second task based on the second core-time slot table in the second cycle.

[0062] After the second core-time slot table is determined, the processing core can be used to execute it in the second cycle to complete the second task.

[0063] It should also be noted that the time span of the first cycle and the second cycle involved in this embodiment is consistent with the corresponding core-time slot table. Usually in a core-time slot table, the specific time length (that is, the number of time slots included) must ensure that all task chains can be executed. In other words, the cycle may be a constant duration or a floating duration, depending on the task situation.

[0064] During the continuous operation of the processor, the above steps 201 to 203 will also be executed cyclically. That is, in one cycle, the first cycle represents the previous cycle, and the second cycle represents the current cycle. It is usually necessary to implement scheduling before the start of each cycle to ensure the smooth operation of the cycle. In the first cycle of the processor power-on operation, the corresponding core-time slot table can be manually determined based on experience. In other subsequent cycles, the core-time slot table of the next cycle can be inferred based on the time consumption data of the previous cycle. This ensures that the overall efficiency is improved as much as possible during the operation of the processor.

[0065] It can be seen from the above technical solution that the beneficial effects of this embodiment are: the second core-time slot table is inferred by the time-consuming data of the first cycle, so that the task arrangement in the second core-time slot table is more compact and precise, and is very close to the actual execution situation, avoiding task execution timeout or task completion in advance; there is no need to leave additional margin in the allocation of time slots during the scheduling process, and there is no need to reschedule along the execution process; the overall operating efficiency of the processor is improved.

[0066] Figure 2 What is shown is only a basic embodiment of the method of the present invention. By performing certain optimization and expansion on this basis, other preferred embodiments of the method can be obtained.

[0067] like Figure 3 FIG. 1 is another specific embodiment of the task processing method of the processor of the present invention. This embodiment is further expanded on the basis of the above-mentioned embodiment. The method specifically includes the following steps:

[0068] Step 301: Obtain scheduling parameters corresponding to the execution of a first task by each processing core in a first cycle.

[0069] Assume that in this embodiment, the processor has two processing cores, namely core 3 and core 4. The first task includes three specific task chains. The first task chain includes task E, task F, task G, and task H. The second task chain includes task E, task F, task G, and task H. The third task chain includes task J, task K, and task N. In each task chain, each task has a strict timing relationship and needs to be executed in sequence. The first core-time slot table in the first cycle is as follows: Figure 4 shown. Figure 4 The physical duration of each time slot is 1 millisecond.

[0070] After the first cycle is completed, the specific time consumption data can be determined. Task E, Task F, Task G, and Task H all take 0.8 milliseconds. Task e, Task f, Task g, and Task h all take 0.4 milliseconds. Task J, Task K, and Task N all take 0.3 milliseconds. Figure 4 In the first core-time slot table shown, core 3 times out in time slot 7, time slot 8, and time slot 9.

[0071] In this embodiment, the above-mentioned time-consuming data can be directly determined as a scheduling parameter. Or preferably, the load data of core 3 and core 4 in the first cycle can be combined to further determine another part of the scheduling parameters other than the time-consuming data. For example, it can be determined that in the first cycle, core 4 has a lower load and stronger performance than core 3. In other words, if the task executed in core 3 is executed by core 4, it will take less time. On the contrary, if the task executed in core 4 is executed by core 3, it will take longer. According to the actual situation, it can be calculated that if task E, task F, task G, and task H are executed by core 4, the time consumption is 0.7 milliseconds. Assuming that task e, task f, task g, and task h are executed by core 3, it takes 0.5 milliseconds. Assuming that task J, task K, and task N are executed by core 4, it takes 0.2 milliseconds. The above-mentioned time-consuming data obtained by calculation can be used as a scheduling parameter together with the time-consuming data obtained by actual measurement.

[0072] In some cases, it can be assumed that the performance of the processing core does not change significantly between the first cycle and the second cycle, that is, the tasks can be directly scheduled and allocated according to the above scheduling parameters, thereby determining the second core-time slot table.

[0073] In other cases, it can also be considered that the performance of the processing core will change significantly in the second cycle and have a clear impact on the duration of task execution. In this case, the performance of the processing core can be further considered as a variable in the process of determining the second core-time slot table. That is, the second core-time slot table can be determined specifically according to the following steps 302 or 303.

[0074] Step 302: According to the second task and the scheduling parameters, query a pre-defined scheduling table to determine a second core-time slot table.

[0075] In this embodiment, it is assumed that the specific content of the second task is the same as that of the first task, that is, the second task also includes the above three task chains.

[0076] In this step, the performance of core 3 and core 4 in the second cycle can be evaluated first to quantify their performance. For example, it is assumed that it can be determined that the performance of core 3 and core 4 will drop by 10% in the second cycle.

[0077] According to the above second task, scheduling parameters and performance changes, the pre-established scheduling table can be queried to infer the duration of each core executing each task in the second cycle, which can be used as the real basis for determining the second core-time slot table. The scheduling table can be obtained by statistically summarizing the actual duration of the processor executing various tasks under various performance states in history.

[0078] In this embodiment, the following data can be obtained by looking up the table: In the second cycle, if task E, task F, task G, and task H are executed by core 3, it is estimated that it will take 0.85 milliseconds; if they are executed by core 4, it is estimated that it will take 0.8 milliseconds. If task e, task f, task g, and task h are executed by core 3, it is estimated that it will take 0.55 milliseconds; if they are executed by core 4, it will take 0.5 milliseconds. If task J, task K, and task N are executed by core 3, it is estimated that it will take 0.4 milliseconds; if they are executed by core 4, it is estimated that it will take 0.3 milliseconds.

[0079] According to the time consumption data obtained from the above table lookup, the second core-time slot table can be determined as follows: Figure 5 shown.

[0080] Step 303: Input the second task and scheduling parameters into a preset prediction model to predict a second core-time slot table.

[0081] In this step, the actual duration of the processor executing various tasks in various performance states in history can be used as sample data to train a prediction model. The construction and training of the prediction model can be implemented based on current artificial intelligence technology, which will not be described in detail here.

[0082] When the prediction model is trained, the second task, scheduling parameters, and performance changes mentioned above can be used as input data of the model. The prediction model can output the prediction result, that is, the duration of each core executing each task in the second cycle. The second core-time slot table can be determined based on the prediction result.

[0083] Or preferably, the prediction model can be made to perform further calculations according to the prediction results, so that the prediction model can automatically complete the scheduling and allocation of the second task according to the prediction results, and directly output the second core-time slot table.

[0084] It should also be noted that in the process of determining the second core-time slot table, it is necessary to determine the task chain data corresponding to the second task; based on the task chain data and the scheduling parameters, the second core-time slot table is determined. In the three task chains mentioned above in this embodiment, each task has a strict timing relationship, and the previous task will serve as a prerequisite for the next task, so they need to be executed in sequence. The above-mentioned "sequence" is the so-called task chain data. That is to say, when determining the second core-time slot table, this task chain data must be used as another parameter for task scheduling, so as to fully reflect the sequence of tasks. Other single tasks that do not exist in the task chain and do not require prerequisites can be freely assigned to any position in the second core-time slot table.

[0085] Step 304: The second cycle is after the first cycle. Utilize each processing core to execute the second task based on the second core-time slot table in the second cycle.

[0086] The content of this step is consistent with the above-mentioned embodiment and will not be repeated here.

[0087] like Figure 6 FIG. 1 is a specific embodiment of the task processing device of the processor of the present invention. The device described in this embodiment is used to execute Figures 2-3 The physical device of the method. Its technical solution is essentially consistent with the above embodiment, and the corresponding description in the above embodiment is also applicable to this embodiment. The device in this embodiment includes:

[0088] The parameter determination module 601 is called to obtain the scheduling parameters corresponding to the execution of the first task by each processing core in the first cycle.

[0089] The second core-time slot table determination module 602 is used to determine the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameters.

[0090] The second task execution module 603 is used to utilize each processing core to execute the second task based on the second core-time slot table in the second cycle.

[0091] The second cycle follows the first cycle.

[0092] In addition Figure 6 Based on the embodiment shown, preferably, it also includes:

[0093] The calling parameter determination module 601 includes:

[0094] The first execution unit 611 is configured to utilize each processing core to execute a first task based on a first core-time slot table in a first cycle.

[0095] The scheduling parameter determination unit 612 is used to determine the scheduling parameters according to the time consumption data and the load data of each processing core in the first cycle.

[0096] The second core-time slot table determination module 602 includes:

[0097] The table lookup unit 621 is used to look up a pre-defined scheduling table according to the second task and the scheduling parameters to determine the second core-time slot table.

[0098] The model prediction unit 622 is used to input the second task and the scheduling parameters into a preset prediction model to predict and obtain a second core-time slot table.

[0099] In addition to the above-mentioned methods and devices, an embodiment of the present invention may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present invention described in the above-mentioned "Exemplary Method" section of this specification.

[0100] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present invention, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0101] In addition, an embodiment of the present invention may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enable the processor to execute the steps of the method according to various embodiments of the present invention described in the above “Exemplary Method” section of this specification.

[0102] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0103] The basic principle of the present invention is described above in conjunction with specific embodiments. However, it should be pointed out that the advantages, strengths, effects, etc. mentioned in the present invention are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present invention. In addition, the specific details disclosed above are only for the purpose of illustration and facilitation of understanding, rather than limitation, and the above details do not limit the present invention to being implemented by adopting the above specific details.

[0104] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present invention are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", and the like are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The word "such as" used here refers to the phrase "such as but not limited to", and can be used interchangeably with it.

[0105] It should also be noted that in the device, apparatus and method of the present invention, each component or each step can be decomposed and / or reassembled, and such decomposition and / or reassembly should be regarded as an equivalent solution of the present invention.

[0106] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0107] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present invention to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A task processing method of a processor, wherein the processor includes at least two processing cores, the method comprising: Obtaining scheduling parameters corresponding to the first task executed by each of the processing cores in the first cycle; Determine, according to the second task of each processing core in the second cycle and the scheduling parameter, a second core-time slot table corresponding to each processing core in the second cycle, wherein the duration required for the second task is estimated according to the time consumption data of the first task, and the second task is distributed in the core-time slot table according to the duration required for the second task to obtain the second core-time slot table, wherein the second core-time slot table does not include an additional margin in time slot allocation; Utilizing each of the processing cores, executing the second task based on the second core-time slot table in the second cycle; The second period is after the first period.

2. According to the method of claim 1, obtaining the scheduling parameters corresponding to the execution of the first task by each of the processing cores in the first cycle comprises: Utilizing each of the processing cores, executing the first task based on a first core-time slot table in the first cycle; The scheduling parameters are determined according to the time consumption data of each processing core executing the first task.

3. According to the method of claim 2, determining the scheduling parameter according to the time consumption data of each processing core executing the first task comprises: The scheduling parameters are determined according to the time consumption data and the load data of each of the processing cores in the first cycle.

4. The method according to claim 1, wherein determining the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter comprises: According to the second task and the scheduling parameters, a pre-defined scheduling table is queried to determine the second core-time slot table.

5. The method according to claim 1, wherein determining the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter comprises: The second task and the scheduling parameters are input into a preset prediction model to predict the second core-time slot table.

6. The method according to any one of claims 1 to 5, wherein determining the second core-time slot table corresponding to each processing core in the second cycle according to the second task of each processing core in the second cycle and the scheduling parameter comprises: Determining task chain data corresponding to the second task; The second core-time slot table is determined according to the task chain data and the scheduling parameters.

7. According to the method according to any one of claims 1 to 5, the second core-time slot table comprises: Each of the processing cores corresponds to a second task in each time slot of the second cycle.

8. A task processing device of a processor, the processor comprising at least two processing cores, the device comprising: Calling a parameter determination module to obtain a scheduling parameter corresponding to the execution of the first task by each of the processing cores in the first cycle; a second core-time slot table determination module, configured to determine, according to the second task of each processing core in the second cycle and the scheduling parameter, a second core-time slot table corresponding to each processing core in the second cycle, wherein the duration required for the second task is estimated according to the time consumption data of the first task, and the second task is distributed in the core-time slot table according to the duration required for the second task to obtain the second core-time slot table, and the second core-time slot table does not include an additional margin in time slot allocation; a second task execution module, configured to execute the second task based on the second core-time slot table in the second cycle by using each of the processing cores; The second period is after the first period.

9. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the task processing method of the processor according to any one of claims 1 to 7.

10. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the task processing method of the processor described in any one of claims 1 to 7.

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