Power-off protection circuit and power-off detection circuit

Abstract

The present invention provides a power-off protection circuit and a power-off detection circuit thereof, wherein the power-off detection circuit comprises: a detection end connected to the power supply voltage of a flash memory circuit; an output end connected to the flash memory circuit; the power-off detection circuit is used to determine whether the flash memory circuit is powered off by detecting the power supply voltage of the flash memory circuit, when the power supply voltage is less than a first flip threshold, the power-off detection circuit determines that a power-off occurs, and outputs a first level through an output end Write, notifying the flash memory circuit to prohibit a write operation; when the power supply voltage is greater than a second flip threshold, the power-off detection circuit determines that there is no power-off, and outputs a second level through an output end Write, notifying the flash memory circuit to allow a write operation. Compared with the prior art, the present invention can detect whether the flash memory circuit is powered off, and quickly prohibit a write operation when the flash memory circuit is powered off, thereby improving the life of the flash memory circuit.

Description

[Technical field]

[0001] The present invention relates to the field of integrated circuits, and in particular to a power-off protection circuit and a power-off detection circuit thereof. [Background technology]

[0002] Flash memory is a form of electronically erasable programmable read-only memory that allows it to be erased or written multiple times during operation. This technology is mainly used for general data storage and data exchange and transmission between computers and other digital products, such as memory cards and USB flash drives. Flash memory is currently used in more and more systems, but flash memory circuits are prone to damage.

[0003] Therefore, it is necessary to propose a new technical solution to overcome the above problems. [Summary of the invention]

[0004] The object of the present invention is to provide a power-off protection circuit and a power-off detection circuit thereof, which can detect whether a flash memory circuit is powered off and quickly prohibit write operations when the flash memory circuit is powered off, thereby improving the life of the flash memory circuit.

[0005] According to one aspect of the present invention, the present invention provides a power-off detection circuit, which includes: a detection end, which is connected to the power supply voltage of a flash memory circuit; an output end, which is connected to the flash memory circuit; the power-off detection circuit is used to determine whether the flash memory circuit is powered off by detecting the power supply voltage of the flash memory circuit, when the power supply voltage is less than a first flip threshold, the power-off detection circuit determines that a power-off occurs, and outputs a first level through the output end Write, notifying the flash memory circuit to prohibit write operations; when the power supply voltage is greater than a second flip threshold, the power-off detection circuit determines that there is no power-off, and outputs a second level through the output end Write, notifying the flash memory circuit to allow write operations.

[0006] Furthermore, the first flip threshold is equal to the second flip threshold; or the first flip threshold is not equal to the second flip threshold, when the power supply voltage changes from being greater than the first flip threshold to being less than the first flip threshold, the power-off detection circuit determines that a power-off occurs, and the output of the output terminal Write flips from the second level to the first level; when the power supply voltage changes from being less than the second flip threshold to being greater than the second flip threshold, the power-off detection circuit determines that there is no power-off, and the output of the output terminal Write flips from the first level to the second level.

[0007] Furthermore, the power-off detection circuit also includes a resistor R2, a resistor R3, a resistor R4, a first transistor and a second transistor, one end of the resistor R2 is connected to the detection end of the power-off detection circuit, and the other end thereof is connected to the first connection node A; the first connection end of the first transistor is connected to the first connection node A via the resistor R3, the second connection end thereof is connected to the ground end, and the control end thereof is connected to the first connection end thereof; one end of the resistor R4 is connected to the detection end of the power-off detection circuit, and the other end thereof is connected to the second connection node B; the first connection end of the second transistor is connected to the second connection node B, the control end thereof is connected to the first connection node A, and the second connection end thereof is connected to the ground end; the second connection node B is connected to the output end Write of the power-off detection circuit.

[0008] Furthermore, the first transistor and the second transistor are NMOS transistors MN1 and MN2, the first connection terminal, the second connection terminal and the control terminal of the first transistor are respectively the drain, source and gate of the NMOS transistor MN1; the first connection terminal, the second connection terminal and the control terminal of the second transistor are respectively the drain, source and gate of the NMOS transistor MN2.

[0009] Furthermore, the width-to-length ratio of the NMOS transistor MN1 is greater than that of the NMOS transistor MN2; the difference ΔVgs between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1 is a positive temperature coefficient voltage; and the threshold voltage Vth of the NMOS transistor MN1 is a negative temperature coefficient voltage.

[0010] Furthermore, the first transistor and the second transistor are NPN bipolar transistors NPN1 and NPN2, the first connection terminal, the second connection terminal and the control terminal of the first transistor are respectively the collector, the emitter and the base of the NPN bipolar transistor NPN1; the first connection terminal, the second connection terminal and the control terminal of the second transistor are respectively the drain, the source and the gate of the NMOS transistor MN2.

[0011] Furthermore, the emitter area of ​​the NPN bipolar transistor NPN1 is greater than the emitter area of ​​the NPN bipolar transistor NPN2; the difference ΔVbe between the base-emitter voltage of the NPN bipolar transistor NPN2 and the base-emitter voltage of NPN1 is a positive temperature coefficient voltage; and the base-emitter voltage Vbe1 of the NPN bipolar transistor NPN1 is a negative temperature coefficient voltage.

[0012] Furthermore, the power-off detection circuit also includes a resistor R1 and a switch, one end of the resistor R1 is connected to the detection end of the power-off detection circuit, and the other end thereof is connected to one end of the resistor R2; one end of the switch MP1 is connected to one end of the resistor R1, and the other end thereof is connected to the other end of the resistor R1, and when the output end Write of the power-off detection circuit outputs a first level, the switch MP1 is turned off; when the output end Write of the power-off detection circuit outputs a second level, the switch MP1 is turned on.

[0013] Furthermore, the switch is a PMOS transistor MP1, and one end, the other end and the control end of the switch are respectively a source, a drain and a gate of the PMOS transistor MP1.

[0014] Furthermore, the power-off detection circuit also includes a first inverter and a second inverter, wherein the input end of the first inverter is connected to the second connection node B, and the output end thereof is connected to the output end Write of the power-off detection circuit; the input end of the second inverter is connected to the output end Write of the power-off detection circuit, and the output end thereof is connected to the gate of the PMOS transistor MP1.

[0015] Further, the first inverter includes a PMOS transistor MP2 and an NMOS transistor MN3, the source of the PMOS transistor MP2 is connected to the detection end of the power-off detection circuit, the gate of the PMOS transistor MP2 is connected to the input end of the first inverter, and the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN3, the gate of the NMOS transistor MN3 is connected to the input end of the first inverter, and the source of the NMOS transistor MN3 is connected to the ground end; the second inverter includes a PMOS transistor MP3 and an NMOS transistor MN4, the source of the PMOS transistor MP3 is connected to the detection end of the power-off detection circuit, the gate of the PMOS transistor MP3 is connected to the input end of the second inverter, and the drain of the PMOS transistor MN4 is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4 is connected to the input end of the second inverter, and the source of the NMOS transistor MN4 is connected to the ground end.

[0016] According to another aspect of the present invention, the present invention provides a power-off protection circuit, which includes a flash memory circuit and a power-off detection circuit, the power-off detection circuit including: a detection end, which is connected to the power supply voltage of the flash memory circuit; an output end, which is connected to the flash memory circuit; the power-off detection circuit is used to determine whether the flash memory circuit is powered off by detecting the power supply voltage of the flash memory circuit, when the power supply voltage is less than a first flip threshold, the power-off detection circuit determines that a power-off occurs, and outputs a first level through the output end Write, notifying the flash memory circuit to prohibit write operations; when the power supply voltage is greater than a second flip threshold, the power-off detection circuit determines that there is no power-off, and outputs a second level through the output end Write, notifying the flash memory circuit to allow write operations.

[0017] Compared with the prior art, the present invention determines whether the flash memory circuit is powered off by detecting the power supply voltage of the flash memory circuit. If the power supply voltage of the flash memory circuit drops to a certain threshold, it is determined that a power off has occurred, and the flash memory circuit is notified to prohibit write operations, thereby improving the life of the flash memory circuit.

Brief Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0019] Figure 1 is a functional block diagram of a power-off protection circuit in one embodiment of the present invention;

[0020] Figure 2 for Figure 1 A circuit diagram of a power failure detection circuit in one embodiment is shown;

[0021] Figure 3 for Figure 1 FIG. 1 is a circuit diagram of a power-off detection circuit in another embodiment. [Specific implementation method]

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the words "connected", "connected", and "connected" herein that indicate electrical connection all refer to direct or indirect electrical connection.

[0024] The inventor has found through a large number of experiments and analyses that one of the main reasons that cause the flash memory circuit to be easily damaged is that the flash memory circuit suddenly loses power, and if the flash memory circuit is in a writing operation, it is easy to cause it to be damaged. Based on this, the present invention designs a power-off protection circuit and a power-off detection circuit, which can detect whether the flash memory circuit is powered off and quickly prohibit the writing operation when the flash memory circuit is powered off, thereby improving the life of the flash memory circuit.

[0025] Please refer to Figure 1 As shown, it is a functional block diagram of a power-off protection circuit in one embodiment of the present invention. Figure 1 The power-off protection circuit shown includes a power-off detection circuit 110 and a flash memory circuit 120 .

[0026] The detection terminal of the power failure detection circuit 110 is connected to the power supply voltage VDD of the flash memory circuit 120, the ground terminal G thereof is grounded, and the output terminal Write thereof is connected to the flash memory circuit 120. The power failure detection circuit 110 is provided with a first flip threshold and a second flip threshold.

[0027] The power-off detection circuit 110 is used to determine whether the flash memory circuit 120 is powered off by detecting the power supply voltage VDD of the flash memory circuit 120. When the power supply voltage VDD of the flash memory circuit 120 drops and is lower than the first flip threshold (for example, the first flip threshold can be set to 0.85 times the normal operating voltage of the flash memory circuit 120), the power-off detection circuit 110 determines that a power-off occurs (or determines that the flash memory circuit 120 is powered off), and outputs a first level (for example, the first level is a low level) through the output terminal Write, notifying the flash memory circuit 120 to prohibit the write operation; when the power supply voltage VDD of the flash memory circuit 120 rises and exceeds the second flip threshold, the power-off detection circuit 110 determines that the power is not off (or determines that the flash memory circuit 120 is not powered off), and outputs a second level (for example, the second level is a high level) through the output terminal Write, notifying the flash memory circuit 120 to allow the write operation. That is to say, when the power supply voltage VDD changes from being greater than the first flip threshold to being less than the first flip threshold, the power-off detection circuit 110 determines that a power-off occurs, and the output of the output terminal Write flips from the second level to the first level; when the power supply voltage VDD changes from being less than the second flip threshold to being greater than the second flip threshold, the power-off detection circuit 110 determines that there is no power-off, and the output of the output terminal Write flips from the first level to the second level.

[0028] In one embodiment, the first flip threshold is equal to the second flip threshold. In another embodiment, there is a certain difference between the first flip threshold and the second flip threshold, and the difference voltage is the hysteresis voltage.

[0029] Please refer to Figure 2 As shown, it is Figure 1 FIG. 1 is a circuit diagram of a power failure detection circuit 110 in one embodiment. Figure 2 The power-off detection circuit shown includes: resistors R1, R2, R3, R4, PMOS transistors MP1, MP2, MP3, and NMOS transistors MN1, MN2, MN3, MN4.

[0030] The following introduction Figure 2 The specific connection relationship of each device in the power-off detection circuit is shown.

[0031] One end of the resistor R1 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), and the other end thereof is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the first connection node A; the drain of the NMOS transistor MN1 is connected to the first connection node A via the resistor R3, its source is connected to the ground terminal G of the power-off detection circuit 110, and its gate is connected to its drain; one end of the resistor R4 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), and the other end thereof is connected to the second connection node B; the drain of the NMOS transistor MN2 is connected to the second connection node B, its gate is connected to the first connection node A, and its source is connected to the ground terminal G of the power-off detection circuit 110.

[0032] The PMOS transistor MP2 and the NMOS transistor MN3 form a first inverter 210, the input end of the first inverter 210 is connected to the second connection node B, and the output end thereof is connected to the output end Write of the power-off detection circuit 110. The source of the PMOS transistor MP2 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the gate thereof is connected to the input end of the first inverter 210 (or the second connection node B), the drain thereof is connected to the drain of the NMOS transistor MN3, the gate of the NMOS transistor MN3 is connected to the input end of the first inverter 210 (or the second connection node B), and the source of the NMOS transistor MN3 is connected to the ground end G of the power-off detection circuit 110.

[0033] The PMOS transistor MP3 and the NMOS transistor MN4 form a second inverter 220, the input end of the second inverter 220 is connected to the output end Write of the power-off detection circuit 110 (or the output end of the first inverter 210), and the output end is connected to the gate of the PMOS transistor MP1. The source of the PMOS transistor MP3 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the gate is connected to the input end of the second inverter 220 (or the output end Write of the power-off detection circuit 110), the drain is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4 is connected to the input end of the second inverter 220 (or the output end Write of the power-off detection circuit 110), and the source of the NMOS transistor MN4 is connected to the ground end G of the power-off detection circuit 110.

[0034] The source of the PMOS transistor MP1 is connected to one end of the resistor R1 , and the drain of the PMOS transistor MP1 is connected to the other end of the resistor R1 .

[0035] The following is a detailed introduction Figure 2 The working principle of the power-off detection circuit is shown in FIG.

[0036] The width-to-length ratio of the NMOS transistor MN1 is designed to be relatively large, and the width-to-length ratio of the NMOS transistor MN2 is designed to be relatively small. In other words, the width-to-length ratio of the NMOS transistor MN1 is greater than the width-to-length ratio of the NMOS transistor MN2.

[0037] The current IR3 flowing through the resistor R3 satisfies:

[0038] IR3=(VDD-Vth) / (R1+R2+R3)

[0039] Wherein VDD is the power supply voltage of the flash memory circuit 120 , Vth is the threshold voltage of the NMOS transistor MN1 , R1 is the resistance value of the resistor R1 , R2 is the resistance value of the resistor R2 , and R3 is the resistance value of the resistor R3 .

[0040] The voltage VR3 on resistor R3 satisfies:

[0041] VR3=(VDD-Vth).R3 / (R1+R2+R3) (1)

[0042] Due to the different width-to-length ratios of the NMOS transistors MN2 and MN1, there is a certain gate-source voltage difference ΔVgs between the two when the same current flows through them. When the following conditions are met, MN2 pulls its drain voltage down to the ground level:

[0043] VR3+Vgs1>Vgs2, where Vgs1 is the gate-source voltage of the NMOS transistor MN1, and Vgs2 is the gate-source voltage of the NMOS transistor MN2.

[0044] Therefore, the condition for the MN2 drain voltage to flip is VR3+Vgs1=Vgs2

[0045] That is, VR3 = Vgs2 - Vgs1 = ΔVgs (2)

[0046] Wherein, ΔVgs is the difference between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1,

[0047] Substituting formula (1) into formula (2) yields:

[0048] (VDD-Vth).R3 / (R1+R2+R3)=ΔVgs

[0049] The solution is:

[0050] VDD=ΔVgs.(R1+R2+R3) / R3+Vth (3)

[0051] This VDD value is the condition that causes the drain voltage of the NMOS transistor MN2 to flip. When the power supply voltage VDD of the flash memory circuit 120 is greater than this value, the drain voltage of the NMOS transistor MN2 is low, and the output signal Write is high through the first inverter 210. When the power supply voltage VDD of the flash memory circuit 120 is less than this value, the drain voltage of the NMOS transistor MN2 is high, and the output signal Write is low through the first inverter 210. The difference ΔVgs between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1 is a positive temperature coefficient voltage, and the threshold voltage Vth of the NMOS transistor MN1 is a negative temperature coefficient voltage. Therefore, a suitable (R1+R2+R3) / R3 ratio can be designed to achieve temperature compensation, thereby achieving a relatively stable flip threshold close to zero temperature coefficient.

[0052] The PMOS transistor MP1 is used as a switch here to form positive feedback, and its function is to generate a small hysteresis voltage to prevent the power supply voltage VDD of the flash memory circuit 120 from being affected by noise and causing the output signal Write to be unstable when it is near the flip threshold. The meaning of hysteresis voltage is: when the power supply voltage VDD drops from a high voltage and is lower than the first flip threshold, the output signal Write changes from a high level to a low level; when the power supply voltage VDD increases from a low voltage and exceeds the second flip threshold, the output signal Write changes from a low level to a high level. There is a certain difference between the first flip threshold and the second flip threshold, and this difference voltage is the hysteresis voltage.

[0053] The following is a detailed introduction Figure 2 The working process of the power-off detection circuit is shown.

[0054] When the output signal Write is at a high level (which may be referred to as a second level), the gate of the PMOS transistor MP1 is at a low level via the second inverter 220, the PMOS transistor MP1 is turned on, and the resistor R1 is short-circuited. As can be seen from the above derivation, at this time, the flip threshold of the power-off detection circuit 110 is the first flip threshold:

[0055] VDD=ΔVgs.(R2+R3) / R3+Vth (4)

[0056] If the power supply voltage VDD drops from a high voltage and is lower than the first flip threshold, the output signal Write changes from a high level to a low level, that is, the power-off detection circuit 110 determines that a power-off occurs and outputs a low level (which may be referred to as a first level) through the output terminal Write, notifying the flash memory circuit 120 to prohibit the write operation.

[0057] When the output signal Write is at a low level (which may be referred to as a first level), the gate of the PMOS transistor MP1 is at a high level via the second inverter 220, and the PMOS transistor MP1 is turned off. As can be seen from the above derivation, at this time, the flip threshold of the power-off detection circuit 110 is the second flip threshold:

[0058] VDD=ΔVgs.(R1+R2+R3) / R3+Vth (3)

[0059] If the power supply voltage VDD rises from a low voltage and is higher than the second flip threshold, the output signal Write changes from a low level to a high level, that is, the power-off detection circuit 110 determines that there is no power failure and outputs a high level (which can be called a second level) through the output terminal Write, notifying the flash memory circuit 120 to allow the write operation.

[0060] Please refer to Figure 3 As shown, it is Figure 1 FIG. 1 is a circuit diagram of a power failure detection circuit 110 in another embodiment. Figure 2 In comparison, the NMOS transistors MN1 and MN2 are replaced by NPN bipolar transistors NPN1 and NPN2, respectively. Figure 3 The power-off detection circuit shown includes: resistors R1, R2, R3, R4, PMOS transistors MP1, MP2, MP3, NMOS transistors MN3, MN4, and NPN bipolar transistors NPN1 and NPN2.

[0061] The following introduction Figure 3 The specific connection relationship of each device in the power-off detection circuit is shown.

[0062] One end of the resistor R1 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), and the other end thereof is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the first connection node A; the collector of the NPN bipolar transistor NPN1 is connected to the first connection node A via the resistor R3, its emitter is connected to the ground terminal G of the power-off detection circuit 110, and its base is connected to its collector; one end of the resistor R4 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), and the other end thereof is connected to the second connection node B; the collector of the NPN bipolar transistor NPN2 is connected to the second connection node B, its base is connected to the first connection node A, and its emitter is connected to the ground terminal G of the power-off detection circuit 110.

[0063] The PMOS transistor MP2 and the NMOS transistor MN3 form a first inverter 210, the input end of the first inverter 210 is connected to the second connection node B, and the output end thereof is connected to the output end Write of the power-off detection circuit 110. The source of the PMOS transistor MP2 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the gate thereof is connected to the input end of the first inverter 210 (or the second connection node B), the drain thereof is connected to the drain of the NMOS transistor MN3, the gate of the NMOS transistor MN3 is connected to the input end of the first inverter 210 (or the second connection node B), and the source of the NMOS transistor MN3 is connected to the ground end G of the power-off detection circuit 110.

[0064] The PMOS transistor MP3 and the NMOS transistor MN4 form a second inverter 220, the input end of the second inverter 220 is connected to the output end Write of the power-off detection circuit 110 (or the output end of the first inverter 210), and the output end is connected to the gate of the PMOS transistor MP1. The source of the PMOS transistor MP3 is connected to the detection end of the power-off detection circuit 110 (or the power supply voltage VDD of the flash memory circuit 120), the gate is connected to the input end of the second inverter 220 (or the output end Write of the power-off detection circuit 110), the drain is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4 is connected to the input end of the second inverter 220 (or the output end Write of the power-off detection circuit 110), and the source of the NMOS transistor MN4 is connected to the ground end G of the power-off detection circuit 110.

[0065] The source of the PMOS transistor MP1 is connected to one end of the resistor R1 , and the drain of the PMOS transistor MP1 is connected to the other end of the resistor R1 .

[0066] The following is a detailed introduction Figure 3 The working principle of the power-off detection circuit is shown in FIG.

[0067] The emitter area of ​​the NPN bipolar transistor NPN1 is designed to be relatively large, and the emitter area of ​​the NPN bipolar transistor NPN2 is designed to be relatively small. It can also be said that the emitter area of ​​the NPN bipolar transistor NPN1 is larger than the emitter area of ​​the NPN bipolar transistor NPN2.

[0068] The current IR3 flowing through the resistor R3 satisfies:

[0069] IR3=(VDD-Vbe1) / (R1+R2+R3)

[0070] Wherein VDD is the power supply voltage of the flash memory circuit 120, Vbe1 is the base-emitter voltage of the NPN bipolar transistor NPN1, R1 is the resistance value of the resistor R1, R2 is the resistance value of the resistor R2, and R3 is the resistance value of the resistor R3.

[0071] The voltage VR3 on resistor R3 satisfies:

[0072] VR3=(VDD-Vbe1).R3 / (R1+R2+R3) (5)

[0073] Due to the different emitter area designs of NPN bipolar transistors NPN1 and NPN2, there is a certain base-emitter voltage difference ΔVbe between the two when the same current flows through them. When the following conditions are met, NPN2 pulls its collector voltage down to the ground level:

[0074] VR3+Vbe1>Vbe2, wherein Vbe1 is the base-emitter voltage of the NPN bipolar transistor NPN1, and Vbe2 is the base-emitter voltage of the NPN bipolar transistor NPN2.

[0075] Therefore, the condition for NPN2 collector voltage reversal is VR3+Vbe1=Vbe2

[0076] That is, VR3 = Vbe2 - Vbe1 = ΔVbe (6)

[0077] Where ΔVbe is the difference between the base-emitter voltage of NPN2 and the base-emitter voltage of NPN1.

[0078] Substituting formula (5) into formula (6) yields:

[0079] (VDD-Vbe1).R3 / (R1+R2+R3)=ΔVbe

[0080] The solution is:

[0081] VDD=ΔVbe.(R1+R2+R3) / R3+Vbe1 (7)

[0082] This VDD value is the condition that causes the collector voltage of the NPN bipolar transistor NPN2 to flip. When the power supply voltage VDD of the flash memory circuit 120 is greater than this value, the collector voltage of the NPN bipolar transistor NPN2 is low, and the output signal Write is high through the first inverter 210; when the power supply voltage VDD of the flash memory circuit 120 is less than this value, the collector voltage of the NPN bipolar transistor NPN2 is high, and the output signal Write is low through the first inverter 210. The difference ΔVbe between the base-emitter voltage of the NPN bipolar transistor NPN2 and the base-emitter voltage of NPN1 is a positive temperature coefficient voltage, and the base-emitter voltage Vbe1 of the NPN bipolar transistor NPN1 is a negative temperature coefficient voltage. Therefore, a suitable (R1+R2+R3) / R3 ratio can be designed to achieve temperature compensation, thereby achieving a relatively stable flip threshold close to zero temperature coefficient.

[0083] The PMOS transistor MP1 is used as a switch here to form positive feedback, and its function is to generate a small hysteresis voltage to prevent the power supply voltage VDD of the flash memory circuit 120 from being affected by noise and causing the output signal Write to be unstable when it is near the flip threshold. The meaning of hysteresis voltage is: when the power supply voltage VDD drops from a high voltage and is lower than the first flip threshold, the output signal Write changes from a high level to a low level; when the power supply voltage VDD increases from a low voltage and exceeds the second flip threshold, the output signal Write changes from a low level to a high level. There is a certain difference between the first flip threshold and the second flip threshold, and this difference voltage is the hysteresis voltage.

[0084] The following is a detailed introduction Figure 3 The working process of the power-off detection circuit is shown.

[0085] When the output signal Write is at a high level (which may be referred to as a second level), the gate of the PMOS transistor MP1 is at a low level via the second inverter 220, the PMOS transistor MP1 is turned on, and the resistor R1 is short-circuited. As can be seen from the above derivation, at this time, the flip threshold of the power-off detection circuit 110 is the first flip threshold:

[0086] VDD=ΔVbe.(R2+R3) / R3+Vbe1 (8)

[0087] If the power supply voltage VDD drops from a high voltage and is lower than the first flip threshold, the output signal Write changes from a high level to a low level, that is, the power-off detection circuit 110 determines that a power-off occurs and outputs a low level (which may be referred to as a first level) through the output terminal Write, notifying the flash memory circuit 120 to prohibit the write operation.

[0088] When the output signal Write is at a low level (which may be referred to as a first level), the gate of the PMOS transistor MP1 is at a high level via the second inverter 220, and the PMOS transistor MP1 is turned off. As can be seen from the above derivation, at this time, the flip threshold of the power-off detection circuit 110 is the second flip threshold:

[0089] VDD=ΔVbe.(R1+R2+R3) / R3+Vbe1 (7)

[0090] If the power supply voltage VDD rises from a low voltage and is higher than the second flip threshold, the output signal Write changes from a low level to a high level, that is, the power-off detection circuit 110 determines that there is no power failure and outputs a high level (which can be called a second level) through the output terminal Write, notifying the flash memory circuit 120 to allow the write operation.

[0091] It should be noted that, in another embodiment, Figure 2 or Figure 3 The second inverter 220, the resistor R2 and the PMOS transistor MP1 make the first flip threshold and the second flip threshold equal, that is, there is no hysteresis voltage.

[0092] It should be noted that NMOS transistors MN1 and NPN, and NPN bipolar transistors NPN1 and NPN2 can be collectively referred to as transistors, wherein NMOS transistor MN1 and NPN bipolar transistor NPN1 are referred to as first transistors, and NMOS transistor MN2 and NPN bipolar transistor NPN2 are referred to as second transistors. Figure 2 In the embodiment shown, the first transistor and the second transistor are NMOS transistors MN1 and MN2, the first connection terminal, the second connection terminal and the control terminal of the first transistor are respectively the drain, source and gate of the NMOS transistor MN1; the first connection terminal, the second connection terminal and the control terminal of the second transistor are respectively the drain, source and gate of the NMOS transistor MN2. Figure 3 In the illustrated embodiment, the first transistor and the second transistor are NPN bipolar transistors NPN1 and NPN2, the first connection terminal, the second connection terminal and the control terminal of the first transistor are respectively the collector, the emitter and the base of the NPN bipolar transistor NPN1; the first connection terminal, the second connection terminal and the control terminal of the second transistor are respectively the drain, the source and the gate of the NMOS transistor MN2.

[0093] It should be noted that in Figure 2 and Figure 3In the embodiment, the PMOS transistor MP1 is used as a switch, and one end, the other end and the control end of the switch are the source, the drain and the gate of the PMOS transistor MP1 respectively. In other embodiments, the PMOS transistor MP1 can also be replaced by other types of switches, as long as the switch is turned off when the output end Write of the power failure detection circuit outputs the first level; and the switch is turned on when the output end Write of the power failure detection circuit outputs the second level.

[0094] In summary, the power-off detection circuit 110 in the present invention determines whether the flash memory circuit 120 is powered off by detecting the power supply voltage VDD of the flash memory circuit 120. When the power supply voltage VDD is less than the first flip threshold, the power-off detection circuit 110 determines that a power-off occurs, and outputs a first level through the output terminal Write to notify the flash memory circuit 120 to prohibit write operations; when the power supply voltage VDD is greater than the second flip threshold, the power-off detection circuit 110 determines that there is no power-off, and outputs a second level through the output terminal Write to notify the flash memory circuit 120 to allow write operations, thereby improving the life of the flash memory circuit.

[0095] In the present invention, words such as “connect”, “connected”, “connected”, “connected”, etc. indicating electrical connection, if not otherwise specified, indicate direct or indirect electrical connection.

[0096] It should be noted that any changes made by those skilled in the art to the specific embodiments of the present invention do not deviate from the scope of the claims of the present invention. Accordingly, the scope of the claims of the present invention is not limited to the above specific embodiments.

Claims

1. A power failure detection circuit, characterized in that: It includes: A detection terminal connected to a power supply voltage of a flash memory circuit; an output terminal connected to the flash memory circuit; The power-off detection circuit is used to determine whether the flash memory circuit is powered off by detecting the power supply voltage of the flash memory circuit. When the power supply voltage is less than a first flip threshold, the power-off detection circuit determines that a power-off occurs, and outputs a first level through an output terminal Write to notify the flash memory circuit to prohibit write operations; when the power supply voltage is greater than a second flip threshold, the power-off detection circuit determines that there is no power-off, and outputs a second level through an output terminal Write to notify the flash memory circuit to allow write operations. It also includes a resistor R1, a switch MP1, a resistor R2, a resistor R3, a resistor R4, a first transistor and a second transistor, a first inverter and a second inverter, One end of the resistor R1 is connected to the detection end of the power-off detection circuit, and the other end thereof is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the first connection node A; the first connection end of the first transistor is connected to the first connection node A via the resistor R3, the second connection end thereof is connected to the ground end, and the control end thereof is connected to the first connection end thereof; one end of the resistor R4 is connected to the detection end of the power-off detection circuit, and the other end thereof is connected to the second connection node B; the first connection end of the second transistor is connected to the second connection node B, the control end thereof is connected to the first connection node A, and the second connection end thereof is connected to the ground end; the second connection node B is connected to the output end Write of the power-off detection circuit, One end of the switch MP1 is connected to one end of the resistor R1, and the other end of the switch MP1 is connected to the other end of the resistor R1. When the output end Write of the power-off detection circuit outputs a first level, the switch MP1 is turned off; when the output end Write of the power-off detection circuit outputs a second level, the switch MP1 is turned on. The switch MP1 is a PMOS transistor MP1, and one end, the other end and the control end of the switch MP1 are the source, the drain and the gate of the PMOS transistor MP1 respectively. The first inverting input terminal is connected to the second connection node B, and the output terminal thereof is connected to the output terminal Write of the power failure detection circuit; The second inverting input terminal is connected to the output terminal Write of the power-off detection circuit, and the output terminal thereof is connected to the gate of the PMOS transistor MP1.

2. The power-off detection circuit according to claim 1, characterized in that: The first rollover threshold is equal to the second rollover threshold; or The first flip threshold is not equal to the second flip threshold, When the power supply voltage changes from being greater than the first flip threshold to being less than the first flip threshold, the power failure detection circuit determines that a power failure occurs, and the output of the output terminal Write flips from the second level to the first level; When the power supply voltage changes from being less than the second flip threshold to being greater than the second flip threshold, the power failure detection circuit determines that there is no power failure, and the output of the output terminal Write flips from the first level to the second level.

3. The power-off detection circuit according to claim 1, characterized in that: The first transistor and the second transistor are NMOS transistors MN1 and MN2, The first connection terminal, the second connection terminal and the control terminal of the first transistor are respectively the drain, the source and the gate of the NMOS transistor MN1; The first connection terminal, the second connection terminal and the control terminal of the second transistor are respectively the drain, the source and the gate of the NMOS transistor MN2.

4. The power-off detection circuit according to claim 3, characterized in that: The width-to-length ratio of the NMOS transistor MN1 is greater than the width-to-length ratio of the NMOS transistor MN2; The difference ΔVgs between the gate-source voltage of the NMOS transistor MN2 and the gate-source voltage of MN1 is a positive temperature coefficient voltage; The threshold voltage Vth of the NMOS transistor MN1 is a negative temperature coefficient voltage.

5. The power-off detection circuit according to claim 3, characterized in that: The first transistor and the second transistor are NPN bipolar transistors NPN1 and NPN2, The first connection terminal, the second connection terminal and the control terminal of the first transistor are respectively the collector, the emitter and the base of the NPN bipolar transistor NPN1; The first connection terminal, the second connection terminal and the control terminal of the second transistor are respectively the drain, the source and the gate of the NMOS transistor MN2.

6. The power failure detection circuit according to claim 5, characterized in that: The emitter area of ​​the NPN bipolar transistor NPN1 is greater than the emitter area of ​​the NPN bipolar transistor NPN2; The difference ΔVbe between the base-emitter voltage of the NPN bipolar transistor NPN2 and the base-emitter voltage of NPN1 is a positive temperature coefficient voltage; The base-emitter voltage Vbe1 of the NPN bipolar transistor NPN1 is a negative temperature coefficient voltage.

7. The power failure detection circuit according to claim 1, characterized in that: The first inverter includes a PMOS transistor MP2 and an NMOS transistor MN3, the source of the PMOS transistor MP2 is connected to the detection end of the power-off detection circuit, the gate of the PMOS transistor MP2 is connected to the input end of the first inverter, the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN3, the gate of the NMOS transistor MN3 is connected to the input end of the first inverter, and the source of the NMOS transistor MN3 is connected to the ground end; The second inverter includes a PMOS transistor MP3 and an NMOS transistor MN4, the source of the PMOS transistor MP3 is connected to the detection end of the power-off detection circuit, the gate of the PMOS transistor MP3 is connected to the input end of the second inverter, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4 is connected to the input end of the second inverter, and the source of the NMOS transistor MN4 is connected to the ground end.

8. A power-off protection circuit, characterized in that: It includes: Flash memory circuit; A power failure detection circuit as described in any one of claims 1 to 7.

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