transistor devices

Abstract

A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a plurality of cell regions (1), each including a plurality of transistor cells (10) at least partially integrated in the semiconductor body (100) and each including a corresponding gate electrode (16); a plurality of wiring channels (6), each disposed between two or more cell regions (1); a gate pad (31) disposed over a first surface (101) of the semiconductor body; and a plurality of gate channels (2), each coupled to the gate pad and each disposed in one of the plurality of wiring channels. Each of the plurality of gate channels is associated with one of the plurality of cell regions such that the gate electrode in each of the plurality of cell regions is connected to the associated gate channel, and each of the plurality of wiring channels includes two or more parallel and spaced apart from each other gate channels.

Description

Technical Field

[0001] This disclosure generally relates to a transistor device, and more specifically to a transistor having a plurality of transistor units. Background Technology

[0002] In a transistor device with multiple transistor cells, such as a MOSFET or IGBT, each transistor cell includes a gate electrode. A drive voltage received at the gate electrode of each transistor cell controls the switching state of that cell, where whether the transistor cell is turned on or off depends on whether the voltage across the gate-source capacitance of the transistor cell is higher or lower than a threshold voltage. The transistor cell receives the drive voltage from a gate pad connected to that pad via a gate channel, and multiple transistor cells can be connected to the same gate channel. Inevitably, each gate channel has resistance, where the resistance between the gate pad and the corresponding transistor cell depends on the location of the transistor cell's connection to the gate channel, increasing with the distance between the gate pad and the transistor cell. Furthermore, the higher the resistance, the longer the time delay between the change in the voltage level of the drive voltage received at the gate pad and the change in the switching state of the corresponding transistor cell. Therefore, there can be a considerable time delay between the moment when transistor cells connected to the same gate channel change their switching state. These time delays can cause overload of those transistor cells that turn on earlier.

[0003] Therefore, it is necessary to better control the conduction and cutoff of transistor cells in transistor devices. Summary of the Invention

[0004] One example relates to a transistor device. The transistor device includes: a semiconductor body; a plurality of cell regions, each including a plurality of transistor cells, the plurality of transistor cells being at least partially integrated in the semiconductor body and each including a respective gate electrode; a plurality of wiring channels, each disposed between two or more cell regions; a gate pad disposed above a first surface of the semiconductor body; and a plurality of gate channels, each coupled to the gate pad and each disposed in one of the plurality of wiring channels. Each of the plurality of gate channels is associated with one of the plurality of cell regions such that a gate electrode in each cell of the plurality of cell regions is connected to the associated gate channel. Furthermore, each of the plurality of wiring channels includes two or more parallel and spaced apart gate channels.

[0005] Another example relates to a transistor device. The transistor device includes: a semiconductor body; a plurality of cell regions, each including a plurality of transistor cells, the plurality of transistor cells being at least partially integrated in the semiconductor body and each including a respective gate electrode; a gate pad disposed above a first surface of the semiconductor body; and a plurality of gate channels. Each gate channel has capacitance, resistance, and propagation delay, the propagation delay being adjustable by adjusting at least one of the capacitance and resistance, wherein each of the plurality of gate channels couples a gate electrode of one of the plurality of cell regions to a gate pad. Attached Figure Description

[0006] The following description refers to the accompanying drawings. The drawings are intended to illustrate certain principles and therefore only show aspects necessary for understanding these principles. The drawings are not drawn to scale. In the drawings, the same reference numerals denote similar features.

[0007] Figure 1 A schematic top view of a transistor device is shown, which includes a gate pad, multiple cell regions, and multiple gate channels;

[0008] Figure 2 It shows Figure 1 The modified transistor device shown;

[0009] Figure 3 It shows Figure 2 The modified transistor device shown;

[0010] Figures 4A-4C It shows that it can be used Figure 2 Or an example of a resistor implemented in the transistor device shown in Figure 3;

[0011] Figure 5 Another example of a resistor is shown;

[0012] Figure 6 It shows Figure 1 Further modifications to the transistor device shown;

[0013] Figure 7 It shows Figure 1 , 2 Equivalent circuit diagram of the transistor device shown in one of 5 or 6;

[0014] Figures 8A-8D A transistor cell is shown that is connected to two cell regions of the same gate channel;

[0015] Figure 9 It shows Figure 8D The modified transistor unit shown;

[0016] Figures 10A-10CThe vertical and horizontal cross-sectional views of a segment of a transistor device are shown, in which two cell regions are adjacent to each other.

[0017] Figure 11A-11B A transistor cell according to another example is shown, wherein each of these transistor cells includes a field electrode;

[0018] Figure 12 A vertical cross-sectional view of several gate channels and two adjacent cell regions is shown;

[0019] Figures 13A-13B An example is shown for connecting the field electrode of a transistor cell in an adjacent cell region to the source electrode;

[0020] Figure 14 It shows Figure 1 A top view of a transistor device of the type shown, in which the source electrode is shown in addition to the gate pad and gate channel;

[0021] Figure 15 It shows including Figure 14 Package of transistor devices of the type shown;

[0022] Figures 16A-16C An example of a method for forming the gate channel and source electrode is shown; and

[0023] Figure 17 Showing more details Figure 16B An example of a conductive layer is shown. Detailed Implementation

[0024] In the following detailed description, reference is made to the accompanying drawings. The drawings are an integral part of the specification and, for illustrative purposes, illustrate examples of how the invention can be used and implemented. It should be understood that, unless otherwise specifically indicated, features of the various embodiments described herein can be combined with each other.

[0025] Figure 1 A schematic top view of a transistor device according to an example is shown. (Refer to...) Figure 1 The transistor device includes a semiconductor body 100 and multiple unit regions 1 11 -1 36 These unit regions 1 11 -1 36 Each of them includes multiple transistor units, which are at least partially integrated in the semiconductor body 100 and each includes a corresponding gate electrode. However, in Figure 1 The transistor cells are not shown in detail below. Examples of how these transistor cells are implemented will be explained in further detail below. Figure 1The example shown schematically illustrates the circuit symbols of transistor devices included in each cell region 1. 11 -1 36 The transistor unit in the diagram. For illustrative purposes only, this circuit symbol is the circuit symbol for an n-type enhancement MOSFET. However, this is merely an example. Any other type of transistor device can also be implemented in the semiconductor body 100. Any other type of transistor device, i.e. (by way of example only) any other type of MOSFET, IGBT (Insulated Gate Bipolar Transistor), or JFET (Junction Field Effect Transistor), can also be implemented in the semiconductor body 100.

[0026] According to one example, the semiconductor body 100 includes a single-crystal semiconductor material. Examples of single-crystal semiconductor materials include, but are not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0027] Reference Figure 1 The transistor device also includes a gate pad 31 and multiple gate channels 2. 11 -2 33 Gate pads 31 are disposed above the first surface of the semiconductor body 100, and each gate channel 2 11 -2 33 Coupled to gate pad 31.

[0028] In the following text, when in each unit region 1 11 -1 36 When no distinction is needed between them, reference numeral 1 in the attached figure indicates unit region 1. 11 -1 36 Any one or more cell regions 1 11 -1 36 Equivalently, when individual gate channels 2 are not required... 11 -2 33 When distinguishing between them, reference numeral 2 in the attached figure indicates gate channel 2. 11 -2 33 Any one or more gate channels 2 11 -2 33 .

[0029] Reference Figure 1 Each of the plurality of gate channels 2 is assigned to (associated with) at least one of the plurality of cell regions 1, such that the gate electrode of the transistor cell in at least one of the plurality of cell regions 1 is connected to the assigned (associated) gate channel. Figure 1 In the example shown, the allocation relationship between the gate channel 2 and the corresponding at least one cell region 1 is illustrated by the connection line between the gate channel 2 and the corresponding at least one cell region 1. Figure 1 In the example shown, gate channel 211 For example, it is assigned to cell region 1 11 and 1 12 That is, gate channel 2 11 Connected to cell region 1 11 and 1 12 The gate electrode of the transistor unit included in it.

[0030] Reference Figure 1 The transistor device includes multiple wiring channels 6, which may also be referred to as gate channel regions 6. Gate channels 2 are arranged in these wiring channels 61-63, such that two or more gate channels 2 are arranged in each gate channel region 61-63. In the following, reference numeral 6 is used to denote any one or more gate channel regions 61-63.

[0031] Reference Figure 1 Two or more gate channels arranged in each gate channel region 61-63 are spaced apart from each other and arranged in parallel wiring. "Parallel wiring" means that two or more gate channels in each wiring channel extend parallel to each other at least in segments.

[0032] exist Figure 1 In the example shown, two or more gate channels 2 arranged in each wiring channel 6 are spaced apart from each other in the lateral direction y. However, this is only an example. Furthermore, each wiring channel 6 is arranged between two or more cell regions 1.

[0033] exist Figure 1 In the example shown, at least two of the plurality of cell regions 1 are arranged adjacent to each other in a first lateral direction x of the semiconductor body 100 and have different gate flow channels assigned to them. Figure 1 In the example shown, for example, cell region 1 11 1 21 1 31 Arranged adjacent to each other in the first lateral direction x, and these unit regions 1 11 1 21 1 31 Each of them has a different gate flow channel assigned to it. That is, cell region 1 11 It has a gate flow channel 2 assigned to it 11 Unit area 1 21 It has a gate flow channel 2 assigned to it 21 Unit area 1 31 It has a gate flow channel 2 assigned to it 31Furthermore, the different gate channels assigned to cell regions adjacent to each other in the first lateral direction x extend at least partially in the first lateral direction x of the semiconductor body 100 and are spaced apart from each other in the aforementioned lateral direction y. This lateral direction is hereinafter referred to as the second lateral direction of the semiconductor body 100. The second lateral direction y differs from the first lateral direction x. According to one example, the second lateral direction y is substantially perpendicular to the first lateral direction x.

[0034] exist Figure 1 In the example shown, even cell regions arranged adjacent to each other have different gate flow paths assigned to them. For example, cell regions 1 arranged adjacent to each other in the second lateral direction y 11 and 1 21 Having different gate flow channels in cell region 1 11 In the case of allocating gate channel 2 11 In unit region 1 21 In the case of allocating gate channel 2 21 Specifically, those cell regions spaced at different distances from the gate pad 31 are connected to different gate channels. By assigning different gate channels even to cell regions arranged adjacent to each other, the resistance between the gate pad 31 and each cell region 1 can be adjusted individually. In this way, the switching behavior of the transistor cells in each cell region 1 can be adjusted individually. Further references are made below. Figure 7 This will be explained in detail.

[0035] The resistance between the gate pad 31 and a corresponding cell region in cell region 1 can be adjusted in various ways. Figure 1 In the example shown, the resistance between the gate pad 31 and each cell region 1 is formed by the corresponding gate channel 2. In this example, each gate channel 2 is directly connected to the gate pad 31 and extends from the gate pad 31 to the corresponding cell region 1. The resistance of each gate channel 2 depends on the length of the gate channel 2 between the gate pad 31 and the corresponding cell region 1, the cross-sectional area of ​​the gate channel 2 in a section perpendicular to the longitudinal direction of the gate channel 2, and the resistivity of the material used to implement the gate channel 2. Basically, given a cross-sectional area and a given resistivity, the resistance increases with increasing length of the gate channel 2. Equivalently, given a length and a given resistivity, the resistance decreases with increasing cross-sectional area. Furthermore, given a length and a given cross-sectional area, the resistance decreases with decreasing resistivity.

[0036] exist Figure 2Another example of adjusting the resistance between the gate pad 31 and each cell region 1 is shown. In this example, the transistor device includes a connection pad 32 and a resistor 41 connected between the connection pad 32 and the gate pad 31. Each gate channel 2 is connected to the connection pad 32. In this example, the resistance between the gate pad 31 and each cell region 1 is given by the resistance of the resistor 41 plus the resistance of the gate channel 2 assigned to the corresponding cell region 1.

[0037] according to Figure 3 Another example shown is a single resistor 4. 11 -4 33 Connected to gate pad 31 and each gate channel 2 11 -2 33 In this example, the resistance between the gate pad 31 and each cell region 1 is composed of the resistance of the gate channel allocated to the corresponding cell region 1 plus the corresponding resistor 2. 11 -2 33 The resistance is given.

[0038] Figure 2 The resistor 41 shown and Figure 3 Resistor 4 shown 11 -4 33 It can be achieved in various ways. In Figures 4A to 4C The diagram shows the resistors 41 or 4 used to implement these resistors. 11 -4 33 One example. In the following figures, reference numeral 4 indicates resistors 41, 4 11 -4 33 Any one of them. Figure 4A A top view of a region of the semiconductor body 100 in which the resistor 4 is integrated is shown. Figure 4B A vertical cross-sectional view of the first section AA in the region where resistor 4 is integrated is shown, and Figure 4C A vertical cross-sectional view of the second section BB in the region where resistor 4 is integrated is shown.

[0039] Reference Figures 4A to 4C The resistor includes resistive material 41 disposed in trenches of the semiconductor body 100, and is electrically insulated from the surrounding area of ​​the semiconductor body 100 by an insulating layer 42. According to one example, the insulating layer 42 is an oxide such as a semiconductor oxide. The resistive material 41 is a doped polycrystalline semiconductor material, such as polycrystalline silicon.

[0040] Reference Figure 4A and 4CThe resistor also includes a first contact pad 43 and a second contact pad 44, which are laterally spaced from each other and serve to connect the resistor 4 to a corresponding gate channel 2, gate pad 31, or connection pad 32. The resistance of the resistor 4 depends on the distance between the contact pads 43 and 44, the resistivity of the resistive material 41, and the cross-sectional area of ​​the resistive material 41 in a direction perpendicular to the direction in which the contact pads 43 and 44 are spaced apart. Essentially, given a cross-sectional area and a given material, the resistance increases with increasing distance between the contact pads 43 and 44. Furthermore, given a given material and a given distance, the resistance decreases with increasing cross-sectional area.

[0041] by Figures 4A to 4C The method shown for implementing resistor 4 is just one example. Another example of resistor 4 is... Figure 5 As shown in the figure. In this example, the trench and the resistive material 41 included in the trench are zigzag. The first contact pad 41 is arranged in the region of the first end of the zigzag resistive material 41, and the second contact pad 44 is arranged in the region of its second end. In this way, a fairly long distance can be achieved between the contact pads 43, 44, and thus a fairly large resistance can be achieved, wherein the area required to implement the resistor 4 is relatively small.

[0042] Figure 6 Another example of a transistor device is shown. In this example, some gate channels are connected to gate pad 31 via connecting gate channels 21, 23. More specifically, as shown... Figure 6 As shown, gate channel 2 11 2 21 2 31 The gate channel 21 is connected to the gate pad 31, and the gate channel 21 is connected to the gate pad 31. 13 2 23 2 33 The gate channel 23 is connected to the gate pad 31. Furthermore, the gate channel 2... 12 2 22 2 33 It is directly connected to the gate pad 31. The connection of the gate channels 21 and 23 can also be used to adjust the resistance between the gate pad 31 and the cell region 1.

[0043] Figure 7 The equivalent circuit diagram of the aforementioned transistor device is shown. (Refer to...) Figure 7 This transistor device can be considered to be subdivided into multiple transistors, where each transistor is formed by transistor cells included in unit region 1. Figure 7 The circuit diagram shown only displays four 1s in these cell regions. 11 1 12 1 35 136 Each unit area 1 11 -1 36 Represented by one of the transistors. For illustrative purposes only, in Figure 7 In the example shown, the transistors formed by the individual cell regions are n-type MOSFETs.

[0044] Reference Figure 7 The transistor device includes a gate node G, a source node S, and a drain node formed by a gate pad 31. Each cell region 1 11 1 12 1 35 1 36 The transistor units in the circuit are connected in parallel. Figure 7 In this context, this is represented by the drain node D of the transistor representing the cell region. 11 D 12 D 35 D 36 Connected to the drain node D of the transistor device, and the source node S of the transistor representing the cell region. 11 S 12 S 35 S 36 The source node S is connected to the transistor device. Represents cell region 1. 11 1 12 1 35 1 36 The gate node G of the transistor 11 G 12 G 35 G 36 These are referred to below as internal gate nodes. These gate nodes G 11 G 12 G 35 G 36 Each of them represents the area contained in the corresponding cell region 1. 11 1 12 1 35 1 36 The gate electrode of the transistor cell in the internal gate section. 11 G 12 G 35 G 36 Each of them is connected to the gate node G of the transistor device, where the resistor R 11 R 35 Representing gate node G and internal gate node G 11 G 12 G 35 G 36 The resistance between them.

[0045] These resistors R11 R 35 Each of these can be implemented in various ways. Figure 1 In the example shown, resistor R11 is, for example, made by dividing cell region 1 11 1 12 Gate channel 2 connected to gate pad 31 11 Formation. In Figure 2 In the example shown, the resistor R 11 For example, gate channel 2 11 This is achieved with an additional resistor 41. Figure 5 In the example shown, the resistor R 11 For example, gate channel 2 11 4 resistors and additional resistors 11 The resistance is formed. In Figure 6 In the example shown, the resistor R 11 For example, gate channel 2 11 The resistor and the resistor connecting the gate channel 21 are formed.

[0046] For illustrative purposes only, in the transistor device described above, the two cell regions are connected to the gate pad 31 via a common gate conduction channel. Gate channel 2 11 For example, cell region 1 11 and unit region 1 12 Connected to gate pad 31. This is also... Figure 7 The equivalent circuit diagram is shown, where 1 represents the cell region. 11 Gate node and representative cell region 1 of transistor device 12 The gate nodes of all transistor devices are connected to resistor R. 11 Connected to the total gate node G. Equivalently, gate channel 2... 35 Unit region 1 35 1 36 Connected to gate pad 31.

[0047] The transistor device is a voltage-controlled transistor device, which is driven by a driving voltage V received between the gate node G and the source node S formed by the gate pad 31. GS Turning on or off. More precisely, the transistor devices in each cell region 1 depend on the individual cell region 1. 11 1 12 1 35 1 36 Received internal gate-source voltage V GS_11 V GS_12 V GS_35 V GS_36 Whether the voltage level is higher or lower than the corresponding threshold voltage of the transistor cell determines whether it is turned on or off. The "internal gate-source voltage" is the voltage at the internal gate node G.11 G 12 G 35 G 36 Voltage V between source node S and source node S GS_11 V GS_12 V GS_35 V GS_36 .

[0048] Reference Figure 7 Each cell region also includes a corresponding internal gate node G 11 G 12 G 35 G 36 The internal gate-source capacitance CGS between the source node S and the source node 11 CGS 12 CGS 35 CGS 36 Each gate-source capacitance CGS 11 CGS 12 CGS 35 CGS 36 It is formed by the gate-source capacitance of the transistor cells included in the corresponding cell region. This makes cell region 1... 11 1 12 1 35 1 36 The transistor cell conduction requirements are: for the corresponding gate-source capacitance CGS 11 -CGS 36 Charge the device to make the internal gate-source voltage V GS_11 V GS_12 V GS_35 V GS_36 Higher than cell region 1 11 1 12 1 35 1 36 The threshold voltage of the transistor cell. Equivalently, this makes cell region 1... 11 1 12 1 35 1 36 The transistor cell needs to be turned off to: make the corresponding capacitor CGS 11 -CGS 36 Discharge to make the internal gate-supply voltage V GS_11 V GS_12 V GS_35 V GS_36 Below the corresponding threshold voltage.

[0049] Hereinafter, CGS represents the capacitance of any one of the cell regions in cell region 1, and R represents the resistance formed between the gate pad 31 and that cell region. This resistance R is also referred to as the gate resistance below, and includes at least the resistance of the corresponding gate channel. The gate resistance R and the gate-source capacitance CGS form an RC element. When the gate-source voltage V received by the transistor device... GS When the voltage changes, the RC element delays the turn-on and turn-off of the transistor cells in cell region 1. More specifically, when the gate-source voltage V... GS When the transistor transitions from a cutoff level to a conduction level, the gate-source capacitance of cell region 1 must be charged through the gate current channel resistor R to a level higher than the threshold voltage of the transistor cell before the transistor cell is turned on. Equivalently, when the gate-source voltage V... GS When the transistor changes from the on level to the off level, the gate-source capacitance CGS of cell region 1 must be discharged below the threshold voltage through the gate current channel resistor R before the transistor cell in cell region 1 is turned off.

[0050] The threshold voltage of a transistor cell can be adjusted through the design of the transistor cells. In one example, the transistor cells of a transistor device are implemented such that they have substantially the same threshold voltage. Furthermore, the gate-source capacitance of each transistor cell depends on the design of the respective transistor cell. In another example, the transistor cells of a transistor device are implemented such that they have substantially the same gate-source capacitance. In this case, the gate-source capacitance CGS of a cell region 1 is substantially proportional to the number of transistor cells included in that cell region 1.

[0051] Referring to the above, the gate resistance R can be adjusted. By appropriately adjusting the gate channel resistance R, the RC elements associated with each cell region 1 can be adjusted. This allows adjustment of the switching delay of each cell region 1. Each RC element associated with a cell region has an RC time constant, which is given by the gate channel resistance associated with the cell region and the gate-source capacitance CGS associated with the cell region. For example, Figure 7 Middle Unit Area 1 11 The RC time constant is determined by R 11 CGS 11 Given, where R 11 CGS represents the gate resistance. 11 This represents the gate-source capacitance. Furthermore, for example, with cell region 1... 12 The associated RC time constant is given by:

[0052] R 11 CGS 12 Given, where R 11 CGS represents the gate resistance.12 This represents the gate-source capacitance. Figure 7 In the example shown, the two cell regions have the same gate channel resistance. However, this is just an example. Cell regions can also be implemented such that each cell region is connected to the gate pad 31 via a gate channel that is exclusively connected to the corresponding cell region. In this case, the RC time constant of each cell region 1 can be adjusted. According to one example, the gate channel resistance R is implemented such that the deviation of the RC time constant of each cell region from the average RC time constant is less than 20%, less than 10%, or even less than 5%. In this case, the switching delay is substantially the same for each cell region, so that the transistor cells in each cell region 1 turn on or off substantially simultaneously. However, this is just an example. By appropriately selecting the gate channel resistance, it is also possible to make a single cell region turn on or off faster than other cell regions. This is explained in the following description.

[0053] Transistor devices are commonly used as electronic switches. In some applications, it is desirable for transistor devices to turn on or off rapidly. This can cause rapid changes in the current flowing through the transistor and the voltage across the transistor, which can lead to EMI (electromagnetic interference). To avoid or reduce EMI, in some applications, it is desirable for transistor devices to switch in such a way that the change in current through the transistor is relatively slow. This can be achieved by implementing gate current resistance such that at least one cell region switches more slowly than other cell regions. The latter can be achieved, for example, by implementing a higher gate current resistance for the cell region that switches more slowly than for other cell regions. In this case, the transistor cell in at least one cell region with higher gate current resistance turns on or off more slowly than the transistor cells in other cell regions. Thus, the entire transistor device requires a longer time to change from a switching state where all transistor cells are off (on) to a switching state where all transistor cells are on (off).

[0054] Turning a transistor cell on and off is related to switching losses. Essentially, these losses increase as the switching speed of the transistor cell decreases. According to one example, at least one cell region, located near the edge region of the semiconductor body 100, has a higher RC time constant and therefore higher switching losses than other cell regions, and the heat-related switching losses can be dissipated better from this edge region than from the inner region of the semiconductor body 100.

[0055] In addition to the gate channel resistance, each gate channel 2 may include a gate channel capacitance relative to the source node S. This capacitance can be distributed along the length of the gate channel such that the gate channel 2 can be considered to include multiple RC elements connected in series, each of which includes a portion of the gate channel resistance and a portion of the gate channel capacitance. This series circuit of the RC elements results in a propagation delay between the moment of potential change at the gate pad 31 and the moment when the potential change is received at the gate electrode of the transistor cell in the corresponding cell region 1. This propagation delay increases the delay time caused by the resistance of the gate channel 2 and the gate-source capacitance CGS. In each case, by appropriately designing the gate channel capacitance and the gate channel resistance connected to the gate channel 2 in the corresponding cell region 2, the total delay time between the potential change at the gate pad 31 and the corresponding change in the switching state of the transistor cell in a cell region 2 can be adjusted.

[0056] According to one example, gate channels 2 are implemented such that the propagation delay of each gate channel 2 differs from the average propagation delay of the gate channels by less than 20%, less than 10%, or less than 5%.

[0057] In addition to enabling precise adjustment of the switching behavior of transistor cells in each cell region 1, implementing the gate channel 2 in the manner described above allows for a more space-efficient implementation of the overall gate channel arrangement compared to conventional gate channel arrangements. This is explained in the following description.

[0058] For example, in a conventional gate channel arrangement, multiple cell regions (more than two cell regions) are connected to the same gate channel. To avoid significant differences in the RC time constants of cell regions connected to the same gate channel, the gate channel is typically implemented with very low resistance, which in turn requires a large amount of space on the semiconductor body. In many cases, a resistor is implemented between the gate pad and the low-ohm gate channel to regulate the switching speed of the transistor device.

[0059] By implementing gate channel 2 such that only one or two cell regions 1 are connected to the same gate channel 2, the resistance of the corresponding gate channel 2 only needs to accommodate the desired switching behavior of (these) associated cell regions. The additional resistor between gate pad 31 and gate channel 2 (as shown) can be omitted, and the desired resistance between gate pad 31 and cell region 1 can be achieved by appropriately designing gate channel 2, where a higher resistance results in less space required to implement gate channel 2. In other examples (e.g., see...) Figure 2 and 3 In this design, the resistance of the additional resistor can be reduced compared to the traditional gate channel design, which also reduces space consumption.

[0060] Figures 8A to 8DAn example of how a transistor cell can be implemented is shown. More specifically, Figure 8A It shows the connection to the same gate channel 2 i Two unit regions 1 ij 1 ij+1 Top view. Figure 8A The shown unit region 1 ij 1 ij+1 This refers to any pair of cell regions connected to the same gate channel, for example, connected to gate channel 2. 11 Unit region 11 11 11 12 Connected to gate channel 2 21 Unit region 1 21 1 22 And so on. In the following text, cell region 1 ij Also known as the first unit region, and unit region 1 ij+1 It is also known as the second unit region.

[0061] Figure 8B The first unit region 1 in section C1-C1 is shown. ij and the second unit region 1 in section C2-C2 ij+1 The horizontal cross-sectional view. These sections C1-C1 and C2-C2 are essentially parallel to gate channel 2. i The longitudinal direction. Figure 8C It shows the passage through the first element region 1 in section DD. ij Second Unit Area 1 ij+1 and gate channel 2 i The vertical cross-sectional view of the section. Figure 8D This shows the extension through the first element region 1 in section EE. ij Unit 2, Area 1 ij+1 and in the first unit region 1 ij With the second unit region 1 ij+1 Gate channel region 6 k Horizontal cross-sectional view.

[0062] exist Figure 8B The diagram shows that it can be used in the first unit region 1 ij Second Unit Region 1 ij+1 An example of a transistor cell implemented in [the document / system]. See [reference]. Figure 8BEach unit region includes multiple transistor units 10, each of which includes a drift region 11, a source 12, a body region 13 disposed between the drift region 11 and the source region 12, and a drain region 14, wherein the drift region 11 is disposed between the body region 13 and the drain region 14. Optionally, a field stop region 15 is disposed between the drain region 14 and the drift region 11. Furthermore, the transistor unit 10 includes a gate electrode 16 disposed near the body region 13 and separated from the body region 13 by a gate dielectric 17. In this example, the transistor unit 10 is a vertical transistor unit. That is, the source region 12 and the drain region 14 are spaced apart from each other in a vertical direction of the semiconductor body 100, wherein the vertical direction is perpendicular to the first surface 101. The first surface 101 has a gate pad 31 disposed on its top. Figure 8B (The surface is not shown in the image).

[0063] Reference Figure 8B Each unit area 1 ij 1 ij+1 The drain region 14 of the transistor cell can be formed from a continuous semiconductor region, and each cell region 1 ij 1 ij+1 The drift region 11 of the transistor cell 10 can be formed from a continuous semiconductor region. Furthermore, the gate electrodes 16 of the two transistor cells can be formed from a single electrode, and the body regions of the two (other) transistor cells 10 can be formed from a single semiconductor region.

[0064] Reference Figure 8B The drain region 14 of transistor cell 10 is connected to the drain node D of transistor device. According to one example, the drain region of each transistor cell of transistor device is formed on a continuous semiconductor region. In this case, the semiconductor region may form a drain node or be connected to the drain node of transistor device.

[0065] exist Figure 8B In the example shown, transistor cell 10 is a trench transistor cell. That is, the gate electrode 16 is disposed in a trench extending from the first surface 101 into the semiconductor body 100. However, this is only an example. According to another example (not shown), the transistor cell is a planar transistor cell. In this case, the gate electrode is disposed above the first surface of the semiconductor body.

[0066] The gate-source capacitance of transistor cell 10 is the capacitance between gate electrode 16 and source region 12. This capacitance depends in particular on the thickness and material of gate dielectric 17, and on the degree of overlap between gate electrode 16 and source region 12. The threshold voltage of transistor cell 10 depends in particular on the doping concentration of body region 13.

[0067] The transistor device can be implemented as an n-type transistor device or a p-type transistor device. In an n-type transistor device, the source region 12 and drift region 11 are n-doped, while the body region 13 is p-doped. In a p-type transistor device, the source region 12 and drift region 11 are p-doped, while the body region 13 is n-doped. Furthermore, the transistor device can be implemented as a enhancement device or a depletion device. In a enhancement device, the body region 13 is adjacent to the gate dielectric 17 (e.g., ...). Figure 8B (As shown). In the depletion device, transistor cell 10 also includes a channel region of the same doping type as source region 12 and drift region 11, wherein the channel region extends along gate dielectric 17 between source region 12 and drift region 11. Figure 8B (Not shown in the image). Furthermore, this transistor device can be implemented as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated-Gate Bipolar Transistor). In the MOSFET, the drain region 14 has the same doping type as the source region 12 and the drift region 11. In the IGBT, the drain region 14 has a doping type complementary to the doping types of the source region 12 and the drift region 11. (In the IGBT, the drain region 14 is also referred to as the collector region).

[0068] refer to Figure 8B The source region 12 of each transistor cell 10 in each cell region is connected to a corresponding source electrode 51 disposed above the first surface 101 of the semiconductor body 100. i 51 i+1 Source electrode 51 i 51 i+1 It can be disposed on top of the insulating layer 53, which is formed on the first surface 101 of the semiconductor body 100, wherein the conductive via 52 leads from the source electrode 51. i 51 i+1 Extending through the insulating layer 53 to the source region and body regions 12, 13, for connecting the source region 12 and body region 13 to the source electrode 51. i 51 i+1 .

[0069] Reference Figure 8C Connected to the first unit area 1 ij The source electrode 51 of the transistor unit i Connected to the second unit region 1 ij+1 The source electrode 51 of the transistor unit i+1 The gate channels 2i are spaced apart. i 51 i+1 Between, and with these source electrodes 51 i 51 i+1They are spaced apart. Furthermore, insulating layer 57 can be disposed on gate channel 2i and source electrode 51. i 51 i+1 In the space between. Insulating layer 57 comprises an electrically insulating material and may include at least one of the following: oxides, nitrides, imides, or combinations thereof.

[0070] Reference Figure 8D The gate electrode 16 may be an elongated electrode, wherein each of these gate electrodes 16 can be drawn from the first cell region 1. ij Passing through the gate flow channel region 6 k Extending to the second unit region 1 ij+1 Therefore, the first unit region 1 exists. ij One or more transistor cells in the, and a second cell region 1 exists. ij+1 One or more transistor cells in the first cell region 1, which have the same gate electrode 16. Body region 13 can be located from the first cell region 1. ij Passing through the gate flow channel region 6 k Extending to the second unit region 1 ij+1 The source region 12 may not extend into the gate flow channel region 6. k middle.

[0071] Reference Figure 8C and Figure 8D Gate channel 2 i The gate electrode 16 is connected in the gate flow channel region 6k (wherein...) Figure 8D (In the image, the dashed line indicates the location of the gate flow channel). (See reference...) Figure 8C Gate channel 2 i It can be arranged above the insulating layer 53 and through the conductive via 21. i Connected to each gate electrode 16, conductive vias pass through the insulating layer 53 from the gate channel 2 i Extending to gate electrode 16. According to one example, such as... Figure 8D As shown, gate channel 2 i The longitudinal direction is substantially perpendicular to the longitudinal direction of the gate electrode 16.

[0072] Figures 8A-8D The shown unit region 1 ij 1 ij+1 The internal gate-source voltage is the gate current channel 2i and the source voltage 5. ij 5 ij+1 The voltage between, where source 5 ij 5 ij+1 Connected to the source node of the transistor. The latter is explained further below. This depends on the gate flow channel 2i and the corresponding source electrode 5. ij 5 ij+1The internal gate-source voltage received between cells is contained in cell region 1. ij 1 ij+1 The transistor cells in the device are either in an on or off state. When the internal gate-source voltage forms a conductive channel in the body region 13 along the gate dielectric 17, the transistor cell is in the on state; when the internal gate-source voltage prevents the formation of such a conductive channel, the transistor cell is in the off state. For example, when the internal gate-source voltage is a positive voltage above the threshold voltage, the transistor cells of the n-type enhancement transistor device are in the on state.

[0073] exist Figures 8B to 8D In the example shown, the first and second unit regions 1 ij+1 1 ij+2 Each of them includes only an active transistor unit. That is, each transistor unit includes a transistor connected to a corresponding source electrode 51. i 51 i+1 The source region 12 and the gate channel 2 i Gate electrode 16. However, this is just an example. According to Figure 9 In another example shown, each cell region may include one or more passive transistor cells 10' arranged between active transistor cells. The passive transistor cell 10' differs from the active transistor cell 10 in that it does not include a source region 12. Furthermore, the passive transistor cell 10' has its corresponding unconnected gate channel 2. i Gate electrode 16.

[0074] Figure 10A The diagram schematically illustrates two adjacent cell regions 1 connected to different gate channels. ij+1 1 ij+2 Top view. These unit areas 1 ij+1 1 ij+2 The example is Figure 1-3 Unit region 1 shown in Figure 6 12 1 13 Unit area 1 22 1 23 Unit area 1 32 1 33 And so on. In the following text, cell region 1 ij+1 It is called the second unit region, and unit region 1 ij+2 It is referred to as the third unit region. Figure 10B These element regions 1 are shown in the vertical section FF. ij+1 1 ij+2 The vertical cross-sectional view, and Figure 10C It shows in Figure 10B The diagram shows the horizontal cross-section of section GG.

[0075] Reference Figure 10B and Figure 10C Second unit area 1 ij+1 One or more transistor units 10 and third unit region 1 ij+2 One or more transistor cells may have the same gate electrode 16 and the same source region 12, and may be connected to the same source electrode 51. i+1 Therefore, through the gate electrode 16, in connection with the second cell region 1 ij+1 The gate channel is connected to the third cell region 1 ij+2 There is a conductive connection between the gate channels. In this case, in the second and third cell regions 1 ij+1 1 ij+2 Between or in the second unit region 1 ij+1 The transistor cell and the third cell region 1 ij+2 There are no structural boundaries between the transistor cells. However, as described below, in these second and third cell regions 1 ij+1 1 ij+2 There are functional boundaries between them.

[0076] The elongated gate electrode 16 is made of a conductive material such as doped polysilicon or metal and has resistance. Referring to the above, the transistor cell is turned on or off according to the voltage between the gate electrode 16 and the source region 12, wherein, in the on state of the transistor cell, a conductive channel exists along the gate dielectric layer 17 in the body region 13, and in the off state, the conductive channel is interrupted. Due to the resistance of the gate electrode 16, when the gate-source voltage V received by the transistor device... GS When the potential of the gate channel 2 changes, and therefore when the potential of the gate channel 2 changes, the conductive channel is not formed or interrupted at any point along the gate electrode 16 at the same time. Instead, when the potential of the gate channel 2 changes, the operating state (on or off) of the transistor cell first changes at the location closest to the gate channel, and the change in operating state "propagates" from that location to locations farther away from the gate electrode 16. In the case where the gate electrode 16 is connected to two (or more) gate channels 2, the gate electrode 16 and the corresponding transistor cell 10 can be considered as being divided into two parts: a first part closer to the first gate channel, whose operating state is controlled by the first gate channel; and a second part closer to the second gate channel, whose operating state is controlled by the second gate channel. The "boundary" between these two parts of the transistor cell can be considered as the boundary between the two cell regions 1.

[0077] Figure 11A and 11BAnother example of transistor cell 10 is shown. In this example, each transistor cell also includes a field electrode 18, which is dielectrically insulated from the drift region 11 by a field electrode dielectric 19. Figure 11A It is shown in reference Figure 8B The transistor cells in the vertical sections C1-C1 and C2-C2 are described, and Figure 11B References are shown Figure 8C The transistor cells in section DD are illustrated. Figure 11A and 11B In the example shown, the field electrode 18 and the gate electrode 16 are arranged in the same trench. Furthermore, refer to... Figure 11B Field electrode 18 from the first unit region 1 ij Passing through the gate flow channel region 6 k Extending to the second unit region 1 ij+1 middle.

[0078] The field electrode 18 can be connected to the gate node G or the source node S of the transistor device. However, in Figure 11A and 11B The corresponding connections are not shown. According to one example, field electrode 18 is connected to source node S via source electrode 51. This is in... Figure 13A and 13B As shown in the figure, Figure 13A It is shown in the reference Figure 10A The diagram illustrates a vertical cross-sectional view of the semiconductor body 100 in section FF, and... Figure 13B It shows in Figure 13A As shown and referenced Figure 10B and 10C The diagram shows the horizontal section of section GG.

[0079] Figure 8A A top view is shown, and Figure 8B and 11B The wiring channel 6 is shown. k The vertical cross-sectional view at the location shows that there is only one gate flow channel 2 between the two cell regions. i Gate channel 2 in these figures i It can represent, for example Figures 1 to 3 The shown unit region 1 11 1 12 Gate channel 2 11 Unit area 1 13 1 14 Gate channel 2 12 Or unit area 1 15 1 16 Gate channel 2 13 Figure 11 shows a configuration with three gate channels 2.i 2 j 2 k Wiring channel 6 at the location k The vertical cross-section, where only gate channel 2 is located. i 2 j 2 k One of them is connected to the flow channel 2. i 2 j 2 k The gate electrode 16 below. Figure 12 Gate channel 2 in i 2 j 2 k For example, it means Figures 1 to 3 The shown unit region 1 31 1 32 Gate channel 2 11 2 21 2 31 Unit area 1 33 1 34 Gate channel 2 12 2 22 2 32 Or unit area 1 35 1 36 Gate channel 2 13 2 23 2 33 .

[0080] Reference Figure 12 Gate channel 2 i 2 j 2 k In wiring channel 6 k The elements are spaced apart from each other and insulated from each other. Optionally, a reference can be used. Figure 8A The insulating layer 57 of the described type is arranged in the gate channel 2. i 2 j 2 k between.

[0081] exist Figure 13A and 13B In the example shown, the field electrode 18 includes a connection portion 181 that extends through the gate electrode 16 to the first surface 101, is insulated from the gate electrode 16 by a dielectric, and is electrically connected to the source electrode 51. i+1 . Reference Figure 13A The connection portion 181 can be connected to the source electrode 51 through the conductive via 54 arranged in the insulating layer 53. i+1Furthermore, in this example, the connecting portion 181 is arranged in the boundary region between two unit regions, which in this example are the second unit region 1. ij+1 and the third unit area 1 ij+2 This allows the connecting portion 181 to connect adjacent unit regions 1 ij+1 1 ij+2 The gate electrode 16 of the transistor cell is separated.

[0082] As described above, the source region 12 of the transistor cell 10 is connected to the source node S of the transistor device via one or more source electrodes. (See the top view of the transistor.) Figure 14 An example of a transistor device comprising multiple separate source electrodes 511-514 is shown. Figure 14 The dashed line in the middle shows the cell region 1 below the source electrodes 511-514. 11 -1 36 The location. In Figure 14 In the example shown, the transistor device includes four source electrodes. However, this is just an example. The number of source electrodes is arbitrary and depends on the specific design of the transistor device.

[0083] exist Figure 14 In the example shown, the cell region 1 arranged between two gate channel regions 6 or between a gate channel region 6 and an edge of the semiconductor body 100 is connected to the same source electrode. More specifically, in Figure 14 In the example shown, for example, cell region 1 is arranged between gate channel regions 61 and 62. 12 1 13 1 22 1 23 1 32 1 33 Connected to the same source electrode 512. For example, the cell region 1 disposed between the edge 1001 of the semiconductor body 100 and the gate flow channel region 61. 11 1 21 1 31 Connected to the same source electrode 511. "Cell region connected to the source electrode" means that the source region 12 of the transistor cell 10 included in the cell region is connected to the source electrode 51 (where 51 represents any one of the source electrodes 511-514).

[0084] exist Figure 14 In the example shown, source electrodes 511-514 are spaced apart from each other so that several individual source electrodes 511-514 exist. These sources can be connected to the source node S of the transistor device in various ways. A top view of the transistor device is shown in the diagram. Figure 15 An example is shown in the figure.

[0085] According to one example, the source electrode 51 and the gate channel 2 are formed using the same process based on the same electrode layer. Figures 16A-16C An example of this process is shown in the figure, in which these Figures 16A-16C Each of these figures shows a vertical cross-sectional view of a portion of the semiconductor body 100 during the manufacturing process. The semiconductor body 100 is shown only schematically in these figures; that is, other structural elements of the transistor units or transistor devices included in the semiconductor body 100 are not shown.

[0086] Reference Figure 16A The method includes forming an insulating layer 53 on a first surface 101 of a semiconductor body 100, and forming a first opening 55 and a second opening 56 in the insulating layer 53. The first opening 55 is used to form Figure 8B The source connection via 52 shown has a second opening 56 for forming... Figure 8C Gate connection via 21 shown i .

[0087] Reference Figure 16B The method further includes forming an electrode layer 200 on top of the insulating layer 53, such that the electrode layer 200 covers the insulating layer 53 and fills the first opening 55 and the second opening 56. Forming the electrode layer 200 may include a deposition process. In this process, a single conductive layer may be deposited, or for two or more different conductive layers, one may be deposited on top of another. By filling the first opening 55 and the second opening 56 with at least one conductive layer, a source connection via 52 and a gate connection via 21i are formed.

[0088] Reference Figure 16C The method further includes patterning the electrode layer 200 to form a source electrode 51 and a gate channel 2, wherein in Figure 16C Only two source electrodes 51 are shown in the image. i 51 i+1 and a gate channel 2 i The patterned electrode layer 200 may include an etching process using a patterned etch mask 300 (in... Figure 16C (shown as dashed lines in the middle).

[0089] Referring to the above, electrode layer 200 may include a stack of layers having two or more conductive layers. Figure 17An example of an electrode layer 200 comprising multiple conductive layers is shown. In this example, the electrode layer 200 includes a contact layer 201 configured to provide contact with a source region (not shown) and a gate electrode. According to one example, the contact layer 201 comprises at least one of titanium (Ti) and titanium nitride (TiN). The thickness of the contact layer 201 is, for example, between 50 nanometers (nm) and 100 nm.

[0090] Furthermore, the electrode layer 200 includes a fill layer 202 configured to fill the remaining openings after the contact layer 201 has been formed in the openings 55, 56. According to one example, the fill layer 202 includes at least one of titanium (Ti) and titanium nitride (TiN). The thickness of the fill layer is, for example, between 100 nanometers (nm) and 200 nm.

[0091] Furthermore, the electrode layer 200 may include a stress compensation layer 203 and another contact layer 204 on top of the fill layer 202. The contact layer 204 comprises at least one of copper (Cu), aluminum (Al), or an Al-Cu alloy (AlCu) and is configured to have a connector, such as a bonding wire or clip, connected thereto. The thickness of the contact layer 204 is, for example, between 2 micrometers (μm) and 5 micrometers (μm). The stress compensation layer 203 compensates for mechanical stresses that may result from the difference in thermal expansion coefficients between the contact layer 204 and the fill layer 202. The thickness of the stress compensation layer 203 is, for example, between 100 nanometers (nm) and 200 nm. According to one example, the stress compensation layer 203 comprises a titanium-tungsten alloy (TiW).

[0092] When the source electrode 51 and gate channel 2 are formed on the same electrode layer 200, assuming the length of the gate channel is substantially given by the gate pad 31 and the distance between each channel and the corresponding cell region 1, the resistance of each gate channel 2 can be adjusted by the width of the gate channel. Furthermore, the resistance between the pad 31 and the cell region 1 can be adjusted by implementing one or more additional resistors 4. (Reference) Figure 3 These additional resistors can be arranged between the gate pad 31 and the gate channel 2. However, this is only one example. According to another example, the gate channel 2 is divided into two or more sections, and the resistor 4 is connected between these two or more gate channel sections.

[0093] The number of cell regions 1 in a transistor device is arbitrary. According to one example, the transistor device comprises 4 to 20 cell regions 100. According to one example, the cell regions 1 have substantially the same size. "Substantially the same size" means that the size of each cell region differs from the average size of cell region 1 by less than 20%, less than 10%, or even less than 5%.

Claims

1. A transistor device, comprising: a semiconductor body (100); a plurality of cell regions (1), each comprising a plurality of transistor cells (10) at least partially integrated in the semiconductor body (100) and each comprising a respective gate electrode (16); a plurality of wiring channels (6), each arranged between two or more of the cell regions (1); a gate pad (31) arranged above a first surface (101) of the semiconductor body (100); and a plurality of gate runners (2), each coupled to the gate pad (31) and each arranged in one of the plurality of wiring channels (6), wherein each of the plurality of gate runners (2) is associated with one of the plurality of cell regions (1) such that the gate electrodes (16) in each of the plurality of cell regions (1) are connected to the associated gate runner (2), and wherein each of the plurality of wiring channels (6) comprises two or more gate runners (2) that are parallel and spaced apart from each other.

2. The transistor device according to claim 1, wherein each of the plurality of gate runners (2) is directly coupled to the gate pad (31).

3. The transistor device according to claim 1, wherein at least one of the plurality of gate runners (2) is coupled to the gate pad (31) by a resistor (4).

4. The transistor device according to any one of claims 1-3, wherein each of the wiring channels (6) further comprises an insulating material (57) that electrically insulates the two or more gate runners (2) from each other.

5. The transistor device according to claim 4, wherein the wiring channels (6) are free of any other elements.

6. The transistor device according to any one of claims 1-3, wherein the plurality of cell regions (1) are arranged in rows and columns, wherein each column comprises at least two cell regions that are arranged adjacent to each other in a first lateral direction (x) and are associated with different gate runners; and wherein each row comprises several cell regions that are arranged adjacent to each other in a second lateral direction (y).

7. The transistor device according to claim 6, wherein the transistor device comprises a plurality of trench electrodes each extending in the second lateral direction, and wherein each of the plurality of trench electrodes forms the gate electrodes (16) of transistor cells in a different cell region, the transistor cells being arranged adjacent to each other in the second lateral direction (y).

8. The transistor device according to any one of claims 1-3, wherein each of the plurality of gate runners (2) is connected to two of the plurality of cell regions.

9. The transistor device according to any one of claims 1-3, further comprising: a plurality of source electrodes (51), ​ wherein each of the plurality of source electrodes (51) is associated with two or more of the plurality of cell regions (1) such that the source region (12) of the plurality of transistor cells (10) in each of the plurality of cell regions (1) is connected to the associated source electrode (51).

10. The transistor device according to claim 9, wherein the plurality of gate runners (2) and the plurality of source electrodes (51) are based on the same conductive layer or the same conductive layer stack (200).

11. The transistor device according to any one of claims 1-3, wherein each of the plurality of gate runners (2) has a width and a height, wherein the width is selected from between 1 micron and 15 microns and the height is selected from between 0.5 micron and 5 microns.

12. The transistor device according to any one of claims 1-3, wherein the plurality of cell regions comprises between 4 and 20 cell regions.

13. The transistor device according to any one of claims 1-3, wherein the transistor cells (10) are one of IGBT cells and MOSFET cells.

14. A transistor device, comprising: a semiconductor body (100); a plurality of cell regions (1) each comprising a plurality of transistor cells (10) at least partially integrated in the semiconductor body (100) and each comprising a respective gate electrode (16); a plurality of wiring channels (6) each arranged between two or more of the cell regions (1); a gate pad (31) arranged above a first surface (101) of the semiconductor body (100); and a plurality of gate runners (2) each coupled to the gate pad (31) and each arranged in one of the plurality of wiring channels (6), wherein each of the plurality of gate runners (2) is associated with one of the plurality of cell regions (1) such that the gate electrode (16) in each of the plurality of cell regions (1) is connected to the associated gate runner (2), wherein each of the plurality of wiring channels (6) comprises two or more gate runners (2) arranged in parallel and spaced apart from each other, wherein each gate runner (2) has a capacitance, a resistance, and a propagation delay, the propagation delay being adjustable by adjusting at least one of the capacitance and the resistance.

15. The transistor device according to claim 14, wherein the propagation delay of each of the plurality of gate runners (2) deviates less than 20%, less than 10%, or even less than 5% from an average propagation delay of the plurality of gate runners. ​

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