Display device and electronic device

Abstract

[Problem] Provided is a display device in which occurrence of bright spot defects can be suppressed. [Solution] A display device includes a light emitting unit and a drive circuit. The drive circuit includes a transistor having: a first diffusion layer that drives the light emitting unit and in which silicide formed in a silicon region is not formed; and a first contact electrode electrically connected to the first diffusion layer.

Description

Technical Field

[0001] The present technology relates to a display device including a light emitting element and an electronic device. Background Art

[0002] An organic electroluminescent display device (hereinafter referred to as an organic EL display device) using an organic electroluminescent diode (organic light emitting diode, hereinafter sometimes referred to as OLED) is a light emitting element having a characteristic of low power consumption due to self-luminescence, and has been developed for practical use.

[0003] In particular, it has been proposed to form a pixel circuit of an organic EL display device and its peripheral circuit on the same single crystal silicon substrate through a silicon semiconductor fine process, and to apply the organic EL display device to a viewfinder of an electronic device such as a small display (for example, see Patent Document 1).

[0004] Generally, in a transistor constituting a circuit, silicide formed by reacting a silicon substrate and a metal to reduce a contact resistance between the contact metal and the silicon substrate is formed in a diffusion layer.

[0005] Citation List

[0006] Patent Literature

[0007] Patent Document 1: JP-A-2013-44890 Summary of the invention

[0008] Technical issues

[0009] When the above-mentioned silicide is formed to constitute an organic EL display device, unreacted metal may diffuse into the silicon substrate and become an unnecessary leakage source. If such unreacted metal becomes a leakage source and unnecessary leakage current flows into the OLED, bright spot defects such as unnecessary light emission of the OLED may occur.

[0010] In view of the above circumstances, an object of the present technology is to provide a display device and an electronic device in which the occurrence of bright spot defects is suppressed.

[0011] Solution to the problem

[0012] In order to achieve the above-mentioned object, a display device according to an embodiment of the present technology includes a light emitting portion and a drive circuit.

[0013] The driving circuit includes a transistor that drives a light emitting portion and includes a first diffusion layer and a first contact electrode, the first diffusion layer does not include silicide formed in a silicon region, the first contact electrode being electrically connected to the first diffusion layer.

[0014] According to such a configuration, a metal layer is not formed on the diffusion layer where silicide is not formed at the silicide forming step, and thus unreacted metal generated at the silicide forming step is suppressed from being diffused into the diffusion layer where silicide is not formed. This suppresses the occurrence of bright spot defects caused by unnecessary leakage current flowing into the light emitting portion due to the unreacted metal.

[0015] The driving circuit may include a transistor including a second diffusion layer including silicide formed in a silicon region and a second contact electrode electrically connected to the second diffusion layer.

[0016] The first diffusion layer may have a lower impurity concentration at a diffusion layer surface than the second diffusion layer.

[0017] The first diffusion layer may include a deeper region than the second diffusion layer.

[0018] The driving circuit may include a transistor including a first diffusion layer connected to the light emitting portion via a first contact electrode.

[0019] The transistor including the first diffusion layer may be a drive transistor operating as a current limiting element.

[0020] The driving circuit may include an image signal writing transistor including the first diffusion layer and turning on or off a driving current flowing through the light emitting portion.

[0021] The driving circuit may further include an insulating film covering the first diffusion layer.

[0022] The light emitting portion may be an organic electroluminescent diode.

[0023] In order to achieve the above-mentioned object, an electronic device according to an embodiment of the present technology includes a display device.

[0024] The display device includes a light emitting portion and a driving circuit including a transistor driving the light emitting portion and including a first diffusion layer and a first contact electrode, the first diffusion layer not including silicide formed in a silicon region, the first contact electrode being electrically connected to the first diffusion layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] [ Figure 1 ] is a diagram showing a schematic configuration of a display device according to an embodiment of the present disclosure.

[0026] [ Figure 2 ] is an equivalent circuit diagram of the above-mentioned display device.

[0027] [ Figure 3 ] is a cross-sectional schematic diagram of the main parts and peripheral circuits of the pixel circuit of the display device of the first embodiment.

[0028] [ Figure 4 ] is a cross-sectional schematic diagram of the main parts and peripheral circuits of the pixel circuit of the display device of the second embodiment.

[0029] [ Figure 5 ] is a manufacturing process diagram showing a part of the manufacturing process of the circuit of the display device of the second embodiment.

[0030] [ Figure 6 ] is a diagram for describing the difference between the structure when silicide is formed in the diffusion layer and the structure when silicide is not formed.

[0031] [ Figure 7 ] is a manufacturing process diagram showing a part of the manufacturing process of the circuit of the display device of the third embodiment.

[0032] [ Figure 8 ] is a manufacturing process diagram showing a part of the manufacturing process of the circuit of the display device of the fourth embodiment.

[0033] [ Fig. 9 ] is a manufacturing process diagram showing a part of another manufacturing process of the circuit of the display device of the fourth embodiment.

[0034] [ Fig.10 ] is a diagram showing the appearance of a television device as an electronic device.

[0035] [ Fig.11 ] is a diagram showing the appearance of a digital camera as an electronic device.

[0036] [ Fig.12 ] is a diagram showing the appearance of a notebook personal computer as an electronic device.

[0037] [ Fig.13 ] is a diagram showing the appearance of a camera as an electronic device.

[0038] [ Fig.14 ] is a diagram showing the appearance of a mobile phone as an electronic device.

[0039] [ Fig.15 ] is a diagram showing the appearance of a head-mounted display as an electronic device. DETAILED DESCRIPTION

[0040] Hereinafter, a display device according to an embodiment of the present disclosure, specifically, an organic electroluminescent (EL) display device including an organic electroluminescent (EL) diode (hereinafter, referred to as OLED) as a light-emitting element will be described with reference to the accompanying drawings. Hereinafter, the organic EL display device may be referred to as a display device.

[0041] [Configuration of organic EL display device]

[0042] Figure 1 A schematic configuration of the display device 100 is shown.

[0043] Figure 2 is an equivalent circuit diagram of a light emitting element including a driving circuit in a display device. Figure 2 The pixel circuit is an example of a drive circuit (4Tr / 2C drive circuit) including four transistors TRDrv, TRSig, TRE1_c, and TRE1_c_2 and two capacitance portions C1 and C2.

[0044] like Figure 1 As shown, the display device 100 includes a peripheral circuit 110 and a pixel circuit 120, which are driving circuits, and are formed simultaneously on a single crystal silicon semiconductor substrate (hereinafter sometimes referred to as a silicon semiconductor substrate) 10 including a silicon region. The silicon semiconductor substrate 10 includes input and output terminals 116 configured so that a flexible wiring board can be connected thereto.

[0045] The pixel circuit 120 corresponds to an image display region of the display device 100. The display region includes a plurality of pixels arranged two-dimensionally in row and column directions over the entire surface. In the display region, an image based on a video signal input from a peripheral circuit is displayed by driving each pixel.

[0046] The peripheral circuit 110 includes horizontal driving circuits (V driver) 111 and 112 , a vertical driving circuit (H driver) 113 , a gamma voltage generator circuit (Gam) 114 , and a timing controller (Tcon) 115 .

[0047] The horizontal driving circuits 111 and 112 correspond to the scanning circuit 103 and the light emission controlling transistor control circuit 104 which will be described later.

[0048] The vertical driving circuit 113 corresponds to the image signal output circuit 105 described later.

[0049] The pixel circuit 120 and the peripheral circuit 110 each include a transistor.

[0050] like Figure 2 As shown, the display device 100 includes a first current supply unit 101 and a second current supply unit 102, as well as a scanning circuit 103, a light emission control transistor control circuit 104 and an image signal output circuit 105 as peripheral circuits.

[0051] In addition, the display device 100 includes a light emitting element 1, a current supply line (a first current supply line CSL1), a second current supply line CSL2, a scan line SCL, a first emission control line CLE1_c_1, a second emission control line CLE1_c_2, and a data line DTL in a display area.

[0052] A plurality of first current supply lines CSL1 are arranged and connected to the first current supply unit 101 .

[0053] The fixed voltage Vcc is supplied from the first current supply unit 101 to the first current supply line CSL1 .

[0054] The plurality of second current supply lines CSL2 are connected to the second current supply unit 102 , and are arranged to extend in a direction orthogonal to an arrangement direction of the first current supply lines CSL1 .

[0055] The fixed voltage Vcc is supplied from the second current supply unit 102 to the second current supply line CSL2 .

[0056] The plurality of scan lines SCL are connected to the scan circuit 103 , and are arranged to extend in a direction parallel to the arrangement direction of the first current supply line CSL1 .

[0057] Scanning signals are sequentially supplied from the scanning circuit 103 to the scanning lines SCL.

[0058] The plurality of first emission control lines CLE1_c_1 are connected to the light emission control transistor control circuit 104, and are arranged to extend in a direction parallel to an arrangement direction of the first current supply line CSL1.

[0059] The light emission control signal is sequentially supplied from the light emission control transistor control circuit 104 to the first emission control line CLE1_c_1.

[0060] The second emission control line CLE1_c_2 is connected to the light emission control transistor control circuit 104. Light emission control signals are sequentially supplied from the light emission control transistor control circuit 104 to the second emission control line CLE1_c_2.

[0061] The plurality of data lines DTL are connected to the image signal output circuit 105 , and are arranged to extend in a direction orthogonal to an arrangement direction of the first current supply lines CSL1 .

[0062] An image signal (drive signal or brightness signal) VSig and a predetermined reference potential Vofs are switched and supplied from the image signal output circuit 105 to the data line DTL.

[0063] The light emitting element 1 includes a light emitting portion (specifically, an organic EL light emitting portion) ELP and a pixel circuit 120 for driving the light emitting portion ELP.

[0064] A display area for displaying an image includes light emitting elements 1 arranged in a two-dimensional matrix. The light emitting elements 1 constitute pixels.

[0065] The display device 100 may have a configuration for monochrome display in the display area, or may have a configuration for color display therein. In the case of a color display configuration, one pixel includes, for example, three sub-pixels (a red light-emitting sub-pixel emitting red light, a green light-emitting sub-pixel emitting green light, and a blue light-emitting sub-pixel emitting blue light).

[0066] The light emitting portion ELP is formed over a plurality of transistors constituting the pixel circuit 120 via an interlayer insulating layer.

[0067] The light emitting part ELP is a current-driven optical element whose light emitting brightness varies according to the current flowing through the light emitting part ELP. In this embodiment, the light emitting part ELP is composed of an OLED. The light emitting part ELP has a known structure including an anode electrode 51, an organic material layer, a cathode electrode 53, etc. The organic material layer has a structure in which, for example, a hole transport layer, a light emitting layer, and an electron transport layer are stacked.

[0068] The pixel circuit 120 for driving the light emitting part ELP includes a driving transistor TRDrv, an image signal writing transistor TRSig, a first light emitting control transistor TREl_c_1, a second light emitting control transistor TREl_c_2, a first capacitance part C1, and a second capacitance part C2.

[0069] The anode electrode 51 is connected to the other source / drain region 24 of the driving transistor TR Drv and one source / drain region 46 of the second light emission controlling transistor TREl_c_2.

[0070] The cathode electrode 53 is connected to the ground line, and a predetermined cathode voltage Vcath is supplied to the ground line. Figure 2 , reference symbol CEL denotes a parasitic capacitance of the light emitting portion ELP.

[0071] In this embodiment, the drive transistor TRDrv, the image signal writing transistor TRSig, the first light emission control transistor TREl_c_1 and the second light emission control transistor TREl_c_2 are all made of p-channel MOSFETs and formed in an n-type well formed in a p-type silicon semiconductor substrate 10 .

[0072] The driving transistor TRDrv drives the light emitting portion ELP based on the image signal (driving signal or brightness signal) VSig held in the capacitance portion C1. The driving transistor TRDrv functions as a current limiting element.

[0073] The driving transistor TR Drv includes a gate electrode 21 , one source / drain region 23 , and another source / drain region 24 .

[0074] In the driving transistor TRDrv, one source / drain region 23 is connected to one electrode 41 of the first capacitance portion C1 via a contact electrode 70 formed in an interlayer insulating layer to be described later, and is further connected to another source / drain region 37 of the first light emission control transistor TREl_c_1.

[0075] One source / drain region 23 is connected to one electrode 41 of the first capacitance portion C1 and constitutes a second node ND2.

[0076] In the present embodiment, when the light emitting portion ELP emits light, one source / drain region 23 specifically functions as a source region.

[0077] The other source / drain region 24 is connected to the anode electrode 51 of the light emitting portion (organic EL light emitting portion) ELP via another contact electrode 71 formed in an interlayer insulating layer to be described later and a contact pad.

[0078] In the embodiment, when the light emitting portion ELP emits light, the other source / drain region 24 specifically functions as a drain region.

[0079] The gate electrode 21 is connected to another electrode 42 of the first capacitance portion C1 via a contact pad formed in the interlayer insulating layer and another contact electrode formed in the interlayer insulating layer, and constitutes a first node ND1. The gate electrode 21 is also connected to another source / drain region 34 of the image signal writing transistor TRSig.

[0080] The image signal writing transistor TRSig causes the capacitance portion C1 to hold the image signal VSig.

[0081] The image signal writing transistor TRSig includes a gate electrode 31 , one source / drain region 33 , and another source / drain region 34 .

[0082] In the image signal writing transistor TRSig, one source / drain region 33 is connected to the image signal output circuit 105 via still another contact electrode formed in the interlayer insulating layer, a contact pad, and a data line DTL.

[0083] In the embodiment, when writing an image signal, one source / drain region 33 is specifically used as a source region.

[0084] The gate electrode 31 is connected to the scanning circuit 103 via yet another contact electrode formed in the interlayer insulating layer, a contact pad, and a scanning line SCL.

[0085] The other source / drain region 34 is connected to the gate electrode 21 of the driving transistor TR Drv and the other end 42 of the first capacitance portion C1 via yet another contact electrode formed in the interlayer insulating layer.

[0086] In this embodiment, when an image signal is written, the other source / drain region 34 specifically functions as a drain region.

[0087] In the display device 100, an operation signal is supplied to each sub-pixel through the gate electrode 31 of the image signal writing transistor TRSig from the scanning circuit 103, and the image signal is held in the capacitance portion C1 through the image signal writing transistor TRSig from the image signal output circuit 105. The driving transistor TRDrv is controlled to be turned on or off in response to the signal held in the capacitance portion C1. Therefore, the driving current flows into the light emitting portion ELP, holes and electrons are recombined in the light emitting layer, and emission is caused.

[0088] The first light emission control transistor TREl_c_1 includes a gate electrode 35, one source / drain region 36 and another source / drain region 37.

[0089] The gate electrode 35 is connected to the first emission control line CLE1_c_1 via another contact electrode formed in the interlayer insulating layer.

[0090] One source / drain region 36 is connected to the current supply line CSL1 via yet another contact electrode formed in the interlayer insulating layer.

[0091] The other source / drain region 37 is connected to one source / drain region 23 of the driving transistor TR Drv and one end 41 of the first capacitance portion C1 via another contact electrode formed in the interlayer insulating layer.

[0092] The second light emission control transistor TREl_c_2 includes a gate electrode 45, a source / drain region 46 and another source / drain region 47.

[0093] The gate electrode 45 is connected to the second emission control line CLE1_c_2 via yet another contact electrode formed in the interlayer insulating layer.

[0094] One source / drain region 46 is connected to the other source / drain region 24 of the drive transistor TR Drv via yet another contact electrode formed in the interlayer insulating layer.

[0095] The other source / drain region 47 has the potential VSS.

[0096] The first capacitance portion C1 includes one electrode (one end) 41 , the other electrode (the other end) 42 , and a dielectric layer (insulating layer) interposed between the electrodes 41 and 42 .

[0097] One end 41 of the first capacitance portion C1 is connected to the second current supply line CSL2 via the second capacitance portion C2, and is connected to one source / drain region 23 of the driving transistor TR Drv and the other source / drain region 37 of the first light emission control transistor TREl_c_1.

[0098] The other end 42 of the first capacitance portion C1 is connected to the gate electrode 21 of the driving transistor TR Drv.

[0099] The second capacitance portion C2 includes one electrode (one end), another electrode (the other end), and a dielectric layer (insulating layer) interposed between these electrodes.

[0100] One end of the second capacitance portion C2 is connected to the second current supply line CSL2.

[0101] The other end of the second capacitance portion C2 is connected to one end 41 of the first capacitance portion C1 or the like.

[0102] Each of the source / drain regions includes a high concentration p-type diffusion layer and a low concentration p-type diffusion layer formed on a silicon semiconductor substrate 10 including a silicon region. Figure 3 and Figure 4 In FIG. 1 , a diffusion layer having a relatively low impurity concentration is represented as p-, and a diffusion layer having a relatively high impurity concentration is represented as p+.

[0103] The contact electrode is a conductive layer formed in the interlayer insulating layer and electrically connects a pair of conductive layers arranged through the interlayer insulating layer to each other. The conductive layer arranged through the interlayer insulating layer includes a diffusion layer, wiring such as a signal line, a scan line, a current supply line, and a lead, an electrode such as a gate electrode, an electrode forming a capacitor portion, and an electrode forming a light emitting portion.

[0104] Here, generally, in order to reduce contact resistance, silicide is provided at a boundary between a contact electrode and a diffusion layer formed on the silicon semiconductor substrate 10 .

[0105] In the present technology, in the pixel circuit 120 formed on the silicon semiconductor substrate 10 , all or part of the diffusion layers constituting a part of the plurality of transistors have a structure in which silicide is not formed.

[0106] Specifically, the display device according to the first embodiment described later has a structure in which silicide is not formed in all diffusion layers of a plurality of transistors constituting the pixel circuit 120. Figure 3 The details of the first embodiment are described.

[0107] The display device according to the second embodiment described later has a structure in which silicide is not formed in a part of the diffusion layers of the plurality of transistors constituting the pixel circuit 120. Figure 4The details of the second embodiment are described.

[0108] Note that in the first embodiment and the second embodiment, the diffusion layer constituting the transistor forming the peripheral circuit 110 has a configuration in which silicide is formed in order to reduce the contact resistance with the contact electrode.

[0109] Figure 3 and Figure 4 A partial cross-sectional schematic diagram showing a case where the driving transistor TRDrv and the second light emission control transistor TREl_c_2 constituting a part of the pixel circuit 120 are electrically connected to each other in the diffusion layer on the right side, and a partial cross-sectional schematic diagram showing a case where the transistor 60 and the transistor 82 constituting a part of the peripheral circuit 110 are electrically connected to each other in the diffusion layer on the left side. Figure 3 and Figure 4 , reference numeral 14 denotes an element isolation region.

[0110] like Figure 3 and Figure 4 As shown, the driving transistor TRDrv includes a gate electrode 21 , a gate insulating film 22 , one source / drain region 23 , another source / drain region 24 , and a sidewall 28 .

[0111] One source / drain region 23 is electrically connected to a contact electrode 70 , and the other source / drain region 24 is electrically connected to a contact electrode 71 .

[0112] The second light emission control transistor TREl_c_2 includes a gate electrode 45, a gate insulating film 48, a source / drain region 46, another source / drain region 47 and a side wall 49.

[0113] One source / drain region 46 is electrically connected to a contact electrode 71 , and the other source / drain region 47 is electrically connected to a contact electrode 72 .

[0114] The other source / drain region 24 of the driving transistor TRDrv and one source / drain region 46 of the second light emission control transistor TREl_c_2 are electrically connected to each other, and the connection is made through a shared diffusion layer.

[0115] like Figure 3 and Figure 4 As shown, in the peripheral circuit 110 , the transistor 80 includes a gate electrode 61 , a gate insulating film 62 , one source / drain region 63 , another source / drain region 64 , and a sidewall 68 .

[0116] One source / drain region 63 is electrically connected to a contact electrode 73 , and the other source / drain region 64 is electrically connected to a contact electrode 74 .

[0117] The transistor 82 includes a gate electrode 65 , a gate insulating film 76 , one source / drain region 66 , another source / drain region 67 , and a sidewall 77 .

[0118] One source / drain region 66 is electrically connected to a contact electrode 74 , and the other source / drain region 67 is electrically connected to a contact electrode 75 .

[0119] The other source / drain region 64 of the transistor 60 and one source / drain region 66 of the transistor 82 are electrically connected to each other, and the connection is made through a shared diffusion layer.

[0120] <First Embodiment>

[0121] (Cross-sectional view of display device)

[0122] like Figure 3 As shown, in the display device 100, the pixel circuit 120 (peripheral circuit 110) includes source / drain regions (the diffusion layer includes a high-concentration p-type diffusion layer and a low-concentration p-type diffusion layer) 23, 24, 46 and 47 (63, 64, 66 and 67) formed in an n-type diffusion layer (n-well) 11 of a silicon semiconductor substrate 10.

[0123] In the pixel circuit 120, the gate electrode 21 (45) is formed on the silicon semiconductor substrate 10 via the gate insulating film 22 (48). The side wall 28 (49) is formed on the side walls of the gate electrode 21 (45) and the gate insulating film 22 (48).

[0124] Furthermore, an insulating film 80 and an interlayer insulating layer 69 are formed on the entire surface of the silicon semiconductor substrate 10 including the gate insulating film 22 (48), the gate electrode 21 (45) and the sidewall 28 (49). Contact electrodes 70, 71 and 72 are formed in the insulating film 80 and the interlayer insulating layer 69.

[0125] The contact electrode 70 electrically connects one source / drain region 23 of the driving transistor TR Drv and the other source / drain region 37 of the first light emission control transistor TREl_c_1 (not shown).

[0126] The contact electrode 71 connects the other source / drain region 24 of the driving transistor TRDrv and one source / drain region 46 of the second light emission control transistor TREl_c_2 to the light emitting part ELP (not shown), more specifically, to the anode electrode 51 of the light emitting part ELP.

[0127] The contact electrode 72 electrically connects the other source / drain region 47 of the second light emission control transistor TREl_c_2 and a wiring connected to a power source VSS (not shown).

[0128] The gate electrode 21 may be formed of, for example, polysilicon.

[0129] The insulating film 80 may be formed of an oxide film, a nitride film, or a stacked film thereof.

[0130] The insulating film 80 is formed to cover at least the diffusion layer in the region where silicide is not formed. In other words, the insulating film 80 is formed in the silicide non-forming region.

[0131] In the peripheral circuit 110, each of the gate electrode 61 (65), one source / drain region 63 (66) and another source / drain region 64 (67) is electrically connected to wiring (not shown) through contact electrodes 73 and 74 (74 and 75) formed in an interlayer insulating layer 69 formed on the transistor 60 (80).

[0132] In the peripheral circuit 110, the gate electrode 61 (65) is formed on the silicon semiconductor substrate 10 via the gate insulating film 62 (76). The side wall 68 (77) is formed on the side walls of the gate electrode 61 (65) and the gate insulating film 62 (76).

[0133] The interlayer insulating layer 69 is formed on the entire surface of the silicon semiconductor substrate 10 including the gate insulating film 62 ( 76 ), the gate electrode 61 ( 65 ) and the sidewall 68 ( 77 ). Contact electrodes 73 , 74 and 75 are formed in the interlayer insulating layer 69 .

[0134] The silicide 90 is formed on each surface of the one source / drain regions 63 and 66, the other source / drain regions 64 and 67, and the gate electrodes 61 and 65 as diffusion layers. That is, the silicide 90 is formed on each surface of the one source / drain regions 63 and 66 and the other source / drain regions 64 and 67, which are diffusion layers to which the contact electrodes 73, 74, and 75 are electrically connected. The silicide 90 is also formed on the surface of the gate electrode 61 electrically connected to the other contact electrode (not shown).

[0135] As described above, in this embodiment, the diffusion layers of the plurality of transistors formed in the silicon region and constituting the pixel circuit 120 have a structure in which silicide is not formed. That is, the display device 100 has a structure in which silicide is not formed in the pixel circuit 120 but is formed in the peripheral circuit 110.

[0136] In this embodiment, the source / drain regions 23, 24, 33, 34, 36, 37, 46, and 47 of the drive transistor TRDrv, the image signal writing transistor TRSig, the first light emission control transistor TREL_c_1, and the second light emission control transistor TREL_c_2 each correspond to a first diffusion layer, which is a diffusion layer in which silicide is not formed. Then, the contact electrodes (which are electrically connected to the respective first diffusion layers) are connected to the first diffusion layers. Figure 3The configurations denoted by reference numerals 70, 71 and 72 in the figure) correspond to first contact electrodes, respectively.

[0137] The source / drain regions 63, 64, 66, and 67 of the transistors 60 and 82 formed in the peripheral circuit 120 correspond to the second diffusion layers, which are diffusion layers in which silicide is formed. Then, the contact electrodes (which are electrically connected to the respective second diffusion layers) are Figure 4 The configurations denoted by reference numerals 73, 74 and 75 in the figure) correspond to the second contact electrodes, respectively.

[0138] Here, a silicide is formed by forming a metal layer on a diffusion layer and then performing a heat treatment to react silicon atoms with metal atoms of the metal layer. The silicide is formed on the surface of the diffusion layer. Subsequently, the metal layer that does not react with the silicon atoms is removed, and the silicide is annealed to stabilize the silicide.

[0139] In the present embodiment, in the display region where the pixel circuit 120 is formed, the silicide formation process is performed in a state where the insulating film 80 is provided. Therefore, the metal layer for forming the silicide is not directly formed on the diffusion layer covered by the insulating film 80 provided in the region where the silicide is not formed. Therefore, the diffusion of the unreacted metal of the metal layer into the silicon semiconductor substrate 10 is suppressed.

[0140] This suppresses the occurrence of a sudden increase in junction current due to diffusion of unreacted metal into the silicon semiconductor substrate 10, suppresses unnecessary leakage current from flowing into the light emitting portion ELP to unnecessarily emit light from the OLED, and suppresses the generation of bright spot defects. In addition, black brightness can be improved.

[0141] In this way, a display device with high display quality can be obtained in which bright spot defects can be suppressed.

[0142] Note that in the present technology, a state in which silicide is not formed in the diffusion layer means a state in which silicide is intentionally prevented. Therefore, for example, a state in which a metal other than a metal for forming silicide is accidentally mixed is excluded.

[0143] <Second Embodiment>

[0144] (Main cross-sectional view of light emitting element)

[0145] In the following, reference will be made to Figure 4 A second embodiment is described. Similar configurations to those described above are denoted by similar reference numerals, and descriptions thereof may be omitted.

[0146] Since the peripheral circuit 110 and Figure 3 are similar to those shown, so their description will be omitted.

[0147] In this embodiment, another source / drain region 24 of the driving transistor TRDrv and one source / drain region 46 of the light emitting control transistor TREl_c_2 respectively correspond to a first diffusion layer, which is a diffusion layer in which no silicide is formed, and the contact electrode 71 is electrically connected to the other source / drain region 24 and one source / drain region 46 corresponds to the first contact electrode.

[0148] One source / drain region 23 of the driving transistor TRDrv, another source / drain region 47 of the second light emission control transistor TREl_c_2, and source / drain regions 33, 34, 36, 37, 63, 64, 66, and 67 of the image signal writing transistor TRSig, the first light emission control transistor TREl_c_1, and transistors 60 and 82 formed in the peripheral circuit 120 correspond to the second diffusion layers, which are diffusion layers in which silicide is formed. Then, the contact electrodes (which are electrically connected to the respective second diffusion layers) are connected to the contact electrodes. Figure 4 The configurations denoted by reference numerals 70, 72 to 75 in the figure) correspond to the second contact electrodes, respectively.

[0149] like Figure 4 As shown, the pixel circuit 120 (peripheral circuit 110) includes source / drain regions 23, 24, 46 and 47 (63, 64, 66 and 67) formed in the n-type diffusion layer 11 of the silicon semiconductor substrate 10 (the diffusion layer includes a high-concentration p-type diffusion layer and a low-concentration p-type diffusion layer).

[0150] In the pixel circuit 120, the gate electrode 21 (45) is formed on the silicon semiconductor substrate 10 via the gate insulating film 22 (48). The side wall 28 (49) is formed on the side walls of the gate electrode 21 (45) and the gate insulating film 22 (48).

[0151] The insulating film 80 is formed to cover the other source / drain region 24 , one source / drain region 46 , a portion of the gate electrodes 21 and 45 , and a portion of the side walls 28 and 49 .

[0152] The silicide 90 is formed in a region of the surface of the gate electrode 21 ( 45 ) where the insulating film 80 is not formed.

[0153] Silicide 90 is formed on each surface of the one source / drain region 23 and the other source / drain region 47 .

[0154] The silicide 90 is not formed on each surface of the other source / drain region 24 and the one source / drain region 46 .

[0155] An interlayer insulating layer 69 is formed on the entire surface of the silicon semiconductor substrate 10 including the gate insulating films 22 and 48, the gate electrodes 21 and 45, the side walls 28 and 49, and the insulating film 80. Contact electrodes 70 and 72 are formed in the interlayer insulating layer 69, and a contact electrode 71 is formed in the insulating film 80 and the interlayer insulating layer 69.

[0156] The contact electrode 70 electrically connects one source / drain region 23 of the driving transistor TR Drv and the other source / drain region 37 of the first light emission control transistor TREl_c_1 (not shown).

[0157] The contact electrode 71 electrically connects the other source / drain region 24 of the driving transistor TR Drv and one source / drain region 46 of the second light emission control transistor TREl_c_2 to the anode electrode 51 (not shown) of the light emitting part ELP.

[0158] The contact electrode 72 is connected to the other source / drain region 47 of the second light emission control transistor TREl_c_2 and a wiring connected to a power source VSS (not shown).

[0159] In the present embodiment, the following configuration is provided: in the diffusion layer of a plurality of transistors formed in a silicon region and constituting a pixel circuit 120, silicide is not formed in another source / drain region (diffusion layer) 24 of the driving transistor TRDrv and in a source / drain region 46 of the second light emitting control transistor TREl_c_2 electrically connected to the anode electrode 51 of the light emitting portion ELP, and silicide is formed in another diffusion layer.

[0160] In this way, when the pixel circuit 120 has a configuration in which the insulating film 80 is partially provided and silicide is not formed in some diffusion layers, the insulating film 80 suppresses diffusion of unreacted metal into the silicon semiconductor substrate 10, compared with the case where silicide is formed in all diffusion layers. Therefore, the occurrence of bright spot defects due to unnecessary leakage current flowing into the light emitting portion ELP is suppressed.

[0161] Furthermore, in the present embodiment, since silicide is formed in the diffusion layer except for the other source / drain region (diffusion layer) 24 of the driving transistor TRDrv and the one source / drain region 46 of the second light emission control transistor TREl_c_2 in the pixel circuit 120, the contact resistance between the contact metal and the source / drain region can be reduced. Therefore, signal processing can be performed at high speed in the pixel circuit 120.

[0162] As described above, in the display device of this embodiment, the occurrence of bright spot defects due to unnecessary leakage current flowing into the light emitting portion ELP is suppressed, and high-speed signal processing is enabled. Therefore, a display device with high display quality and excellent display characteristics can be obtained.

[0163] Note that the present embodiment provides a configuration in which no silicide is formed in another source / drain region (diffusion layer) 24 of the drive transistor TRDrv and one source / drain region 46 of the second light emission control transistor TREl_c_2, which (TRDrv and TREl_c_2) are electrically connected to the anode electrode 51 of the light emitting portion ELP, but the present technology is not limited thereto. For example, a structure in which no silicide is formed in the diffusion layer of the image signal writing transistor TRSig may be provided. In addition, a configuration in which no silicide is formed in both the diffusion layer of the drive transistor TRDrv and the diffusion layer of the image signal writing transistor TRSig may be provided.

[0164] (Manufacturing method)

[0165] Next, we will refer to Figure 5 A method for manufacturing the display device 100 according to the second embodiment will be described. Figure 4 An example of a portion of the driving transistor TRDrv and the second light emission control transistor TREL_c_2 is shown. Note that the manufacturing method of the first embodiment and the manufacturing method of the second embodiment are substantially the same except that the region where the insulating film 80 is formed is different from each other.

[0166] Figure 5 1 is a manufacturing process diagram showing a part of the manufacturing process of the pixel circuit 120 of the display device 100 according to the second embodiment.

[0167] First, if Figure 5 As shown in FIG. 2 (A), after forming the inter-element separation region 14 in the silicon semiconductor substrate 10, impurity ion implantation is performed to form the n-type diffusion layer 11, and then the gate insulating film 22' is deposited.

[0168] Next, polysilicon (polycrystalline silicon) used as a gate electrode is deposited on the gate insulating film 22' by a chemical vapor deposition (CVD) method to further form a resist pattern corresponding to the gate electrode. The polycrystalline silicon and the gate insulating film 22' are etched using the resist pattern as a mask to form gate electrodes 21 and 45 and gate insulating films 22 and 48.

[0169] Next, if Figure 5 As shown in (B), ion implantation is performed to form shallow junction regions 23' and 24'.

[0170] Next, a silicon oxide film is formed on the entire surface of the silicon semiconductor substrate 10 by a CVD method, and dry etching is performed to form the side walls 28 and 49. Figure 5 As shown in (C), ion implantation is performed to form one source / drain region 23 and 46 and another source / drain region (diffusion layer) 24 and 47.

[0171] Next, a gate insulating film 80' is formed on the entire surface of the silicon semiconductor substrate 10. Figure 5 As shown in (D), a resist pattern corresponding to the silicide non-forming region is formed on the gate insulating film 80', and the gate insulating film 80' is pattern-etched by dry etching or the like using the resist pattern as a mask to form an insulating film 80. In the second embodiment, the insulating film 80 is formed to cover the surface of the other source / drain region (diffusion layer) 24 of the drive transistor TRDrv and one source / drain region (diffusion layer) 46 of the second light emission control transistor TREl_c_2, and is not formed on other diffusion layers.

[0172] Here, in the formation process of the insulating film 80 in the manufacturing method for the display device according to the first embodiment, the insulating film 80 is formed in all regions to be the pixel circuits 120 , and the insulating film 80 is not formed in the region of the peripheral circuit 110 .

[0173] Next, a metal layer is deposited on the entire surface of the silicon semiconductor substrate 10 by sputtering and heated to form silicide 90. Note that examples of metal for silicide include cobalt, nickel, and titanium.

[0174] In this process, by heating the silicon semiconductor substrate 10 including the metal layer formed on the surface thereof, silicon atoms and metal atoms of the metal layer react, and a portion where the silicon and the metal layer are in contact with each other changes to silicide 90. Note that even if the metal layer is formed on the insulating film 80 and then heated, the metal layer on the insulating film 80 is still a metal.

[0175] Next, the metal layer that has not reacted with the silicon atoms is removed. Therefore, the silicide 90 remains on the gate electrode 21, one source / drain region 23, and the other source / drain region 47 on which the insulating film 80 is not formed. In addition, the silicide 90 is annealed to stabilize the silicide 90. Subsequently, as Figure 5 As shown in (E), an interlayer insulating layer 69 is formed, and contact electrodes 70, 71 and 72 are formed.

[0176] Notice, Figure 5An example is shown in which the insulating film 80 is formed to cover a portion of the gate electrode 21, but the insulating film 80 may be formed to cover the entire gate electrode 21, or may be formed to expose the gate electrode 21. Silicide is formed in a surface portion of the gate electrode 21 where the insulating film 80 is not formed.

[0177] In the above manufacturing process, when the side walls 28 and 49 are formed, the insulating film 80 provided corresponding to the silicide non-formation region can be formed at the same time. As described above, after the silicon oxide film is formed by the CVD method, the side walls 28 and 49 are formed by dry etching. At the time of dry etching, the silicon oxide film is etched so that it also remains in the portion corresponding to the silicide non-formation region, and the insulating film 80 can be formed together with the side walls 28 and 49.

[0178] Figure 6 (A) and (B) are partially enlarged cross-sectional views of the driving transistor TRDrv and the second light emission control transistor TREl_c_2.

[0179] Figure 6 (A) corresponds to a view of the case where only the side walls 28 and 49 are formed. In such a configuration, the side walls 28 and 49 define a silicide non-forming region.

[0180] As mentioned above, Figure 6 (B) corresponds to a view of a case where an insulating film and a side wall corresponding to a silicide non-formation region are formed simultaneously. Figure 6 In (B), the insulating film provided in the silicide non-forming region including the sidewall is denoted by reference numeral 81 .

[0181] exist Figure 6 In the figure, reference numeral 91 denotes a nitride film used as a contact etching stopper layer used when forming a contact electrode.

[0182] like Figure 6 As shown in FIG. 5A , the sidewalls 28 and 49 define a formation region of the silicide 90 , and no silicide is formed in a region of the diffusion layer covered by the sidewalls 28 and 49 .

[0183] The side wall 28 (49) is formed along the shape of the gate electrode 21 while covering the side wall of the gate electrode 21 (45). One end of the side wall 28 (49) is located on the other source / drain region 24 (one source / drain region 46), and the other end of the side wall 28 (49) is located on the gate electrode 21 (45). One end of the side wall 28 (49) located on the other source / drain region 24 (one source / drain region 46) forms a step 85 (87).

[0184] When the contact electrode 71 is formed on the step 85 (87), the connection fails and the opening fails. Therefore, in order not to form the contact electrode 71 on the step 85 (87), the gate electrode 21 (45) and the contact electrode 71 need to be separated by a certain distance 86 in design.

[0185] In contrast, in the display device 100 according to the present technology, as Figure 6 As shown in (B), since silicide is not formed in the other source / drain region 24 and the one source / drain region 46, an insulating film 81 is formed to cover the surfaces of the other source / drain region 24 and the one source / drain region 46.

[0186] exist Figure 6 In the configuration shown in (B), the end 81a of the insulating film 81 is located on the gate electrodes 21, 45, and the end of the insulating film 81 is not located on the surface of the other source / drain region 24 and the one source / drain region 46. Figure 6 As shown in (A), the step 85 (87) does not exist on the surface of the other source / drain region 24 (one source / drain region 46).

[0187] Therefore, compared with the case where steps 85 and 87 are provided, gate electrodes 21 , 45 and contact electrode 71 can be arranged at positions close to each other, and distance 86 between gate electrodes 21 , 45 and contact electrode 71 can be shortened.

[0188] Therefore, the degree of freedom in design, such as arrangement of gate electrodes, source / drain regions, etc. of transistors, is improved.

[0189] For example, the pixel pitch can be reduced while maintaining the layout area of ​​the transistor. Figure 6 As can be seen from (A) and (B), in the display device 100 according to the present technology, the length of the gate electrode can be increased, that is, the channel length can be increased.

[0190] Here, in the case where the size of a transistor is simply reduced, the transistor is easily affected by process variation, and the characteristics of the transistor are apt to vary.

[0191] In contrast, in this embodiment, the configuration area of ​​the transistor can be maintained, and thus the deviation of the characteristics of each transistor can be reduced, and a display device with improved brightness uniformity on the substrate surface can be obtained. In addition, the pixel pitch can be reduced, and thus a high-definition display device can be obtained.

[0192] Furthermore, for example, when the degree of freedom of design is improved, the number of contact electrodes can be increased, and the redundancy against opening failure of the contact electrodes can be increased.

[0193] Furthermore, for example, the degree of freedom of arrangement of the contact electrodes can be increased, and thus the degree of freedom of the traces of the wirings connected to the contact electrodes can be improved.

[0194] <Third Embodiment>

[0195] Through the above Figure 5 In the display device manufactured by the manufacturing process shown, when the OLED is used as a light-emitting portion, a high reverse bias voltage such as 7V or higher is applied between the anode electrode 51 and the silicon semiconductor substrate 10. When such a high reverse bias voltage is applied, a large reverse voltage is applied to the pn junction, resulting in a breakdown phenomenon (breakdown) through which a large junction leakage current flows, and in some cases, the desired display quality cannot be obtained. This is because impurity ions must be prevented from penetrating from the gate electrode to the channel layer through the gate oxide film during ion implantation, and in the process of forming a shallow junction region, the high acceleration of ion implantation is limited.

[0196] On the contrary, in this embodiment, if Figure 7 As shown, before forming the gate electrode, deep ion implantation is selectively performed with a high injection acceleration on a diffusion layer where no silicide is formed and a high voltage is applied (in this embodiment, another source / drain region 24 of the driving transistor TRDrv and a source / drain region 46 of the second light-emitting control transistor TREl_c_2 will be electrically connected to the light-emitting part ELP to form a low-concentration p region).

[0197] Therefore, if Figure 7 In the display device 100 shown in (E) of FIG. 1 , the depth of the pn junction of the other source / drain region 24 and the one source / drain region 46 (the diffusion layer to which a high voltage is applied) can be made greater than the depth of the pn junction of the one source / drain region 23 and the other source / drain region 47 (the depth of the diffusion layer). In addition, although not shown, the depth of the pn junction of the other source / drain region 24 and the one source / drain region 46 can be made greater than the depth of the pn junction in the diffusion layer of transistors other than the drive transistor TRDrv and the second light emission control transistor TREl_c_2.

[0198] In this way, the diffusion layer to which a high voltage is applied is disposed in a deeper region than other diffusion layers, and thus the electric field can be reduced.

[0199] In the following, reference will be made to Figure 7 A method of manufacturing the display device according to the present embodiment is described.

[0200] Figure 7 1 is a manufacturing process diagram showing a part of the manufacturing process of the circuit of the display device 100 of the third embodiment. Figure 7In the following, a description will be given using an example of manufacturing parts of the driving transistor TRDrv and the second light emission control transistor TREl_c_2 in the pixel circuit 120.

[0201] Similar configurations to those in the above-described embodiment are denoted by similar reference numerals, and description thereof may be omitted.

[0202] Figure 7 1 is a manufacturing process diagram showing a part of the manufacturing process of the pixel circuit of the display device according to the third embodiment.

[0203] First, after forming the inter-element separation region 14 in the silicon semiconductor substrate 10, ion implantation of impurities is performed to form the n-type diffusion layer 11. Subsequently, ions are deeply implanted at a high implantation acceleration only in the region that becomes the other source / drain region 24 and one source / drain region 46 (diffusion layer), which will be electrically connected to the anode electrode 51 and to which a high voltage will be applied, to form deep low-concentration p regions 24' and 46'. Subsequently, as Figure 7 As shown in (A), a gate insulating film 22' is formed.

[0204] Next, polysilicon (polycrystalline silicon) used as a gate electrode is formed on the gate insulating film 22' by a chemical vapor deposition (CVD) method to further form a resist pattern corresponding to the gate electrode. Subsequently, the polycrystalline silicon and the gate insulating film 22' are etched using the resist pattern as a mask to form gate electrodes 21 and 45 and gate insulating films 22 and 48.

[0205] Next, a resist pattern 95 is formed so as to cover the low concentration p regions 24' and 46' to be the other source / drain region 24 of the drive transistor TRDrv and one source / drain region 46 of the second light emission control transistor TREl_c_2 and expose the other diffusion layers.

[0206] Next, if Figure 7 As shown in (B), ion implantation is performed using the resist pattern 95 as a mask to form shallow junction regions ( Figure 7 Only shallow junction regions 23' and 47' are shown, which are diffusion layers to become another source / drain region 24 and one source / drain region 46. Subsequently, the resist pattern 95 is removed.

[0207] Next, a silicon oxide film is deposited on the entire surface of the silicon semiconductor substrate 10 by a CVD method, and dry etching is performed to form the side walls 28 and 49. Figure 7 As shown in (C), ion implantation is performed to form one source / drain region 23 and another source / drain region 47.

[0208] Therefore, if Figure 7 As shown in (C), the other source / drain region 24 and the one source / drain region 46 each have a region deeper than the diffusion layer other than those source / drain regions in the thickness direction of the silicon semiconductor substrate 10. In addition, the other source / drain region 24 and the one source / drain region 46 are regions having an impurity concentration gradient in the thickness direction of the silicon semiconductor substrate 10.

[0209] Note that, as described in the second embodiment, a configuration may be provided in which an insulating film corresponding to a silicide non-formation region described later is formed simultaneously with the formation of the sidewalls.

[0210] Next, an insulating film is deposited on the entire surface of the silicon semiconductor substrate 10. Figure 7 As shown in (D), a resist pattern corresponding to the silicide non-forming region is formed on the insulating film, and the insulating film is patterned by dry etching or the like by using the resist pattern as a mask to form an insulating film 80. In the third embodiment, the insulating film 80 is formed to cover the other source / drain region (diffusion layer) 24 of the drive transistor TRDrv and one source / drain region 46 of the second light emission control transistor TREl_c_2, and is not formed on the other diffusion layers.

[0211] Next, a metal layer is deposited on the entire surface of the silicon semiconductor substrate 10 by sputtering, and heated to form silicide 90 .

[0212] Next, the metal layer that has not reacted with the silicon atoms is removed. Therefore, the silicide 90 remains on the diffusion layer where the insulating film 80 is not formed (in Figure 7 In the embodiment, the gate electrode 21, a source / drain region 23 and a portion of the source / drain region 46 are formed. In addition, the silicide 90 is annealed to stabilize the silicide 90. Then, as shown in FIG. Figure 7 As shown in (E), an interlayer insulating layer 69 is formed, and contact electrodes 70, 71 and 72 are formed.

[0213] Therefore, in addition to the configuration in which the diffusion layer to which high voltage is applied is set to the diffusion layer in which silicide is not formed, and such a diffusion layer is set to be a diffusion layer deeper than other diffusion layers in which silicide is formed, and thus, the electric field can be mitigated and the occurrence of the breakdown phenomenon can be suppressed. This configuration is suitable for a display device to which high voltage is applied, such as an organic EL display device.

[0214] As an example, the depth of the diffusion layer in which silicide is not formed may be 300 nm or less, and the depth of the diffusion layer in which silicide is formed may be greater than 300 nm. Note that those numerical values ​​are appropriately set according to the pixel pitch and the like.

[0215] <Fourth Embodiment>

[0216] exist Figure 2 In the pixel circuit shown, an operation of making manufacturing variations of the threshold voltage Vth of the driving transistor TRDrv between pixel circuits uniform (Vth correction) can be performed by using a capacitance element (eg, the first capacitance portion C1) formed for each pixel.

[0217] Here, in a display device, when a transistor is miniaturized by achieving high definition, a capacitance element (capacitance value) is also reduced, and the ratio of parasitic capacitance is relatively increased, and the Vth correction function cannot fully function. Figure 2 In the pixel circuit shown, in the image signal writing transistor TRSig, the ratio of the parasitic capacitance of the node 34 on the gate electrode 21 side of the driving transistor TRDrv is relatively increased. In particular, when the transistor constituting the pixel circuit 120 is formed on the silicon semiconductor substrate 10, the parasitic capacitance formed in the pn junction of the other source / drain region 24 and the silicon semiconductor substrate 10 increases.

[0218] On the other hand, in the present embodiment, ion implantation is not performed to form the impurity region of the other source / drain region 24, and therefore, the surface of the other source / drain region 24 has a lower impurity concentration than the surface of the other diffusion layer.

[0219] Specifically, in the manufacturing process described in the second embodiment, ion implantation is performed after forming the side walls 28 and 49. However, in this embodiment, after forming the side walls 28 and 49, as shown in FIG. Figure 8 As shown in (A), ion implantation is performed in a state where the other source / drain region 24 and one source / drain region 46 are covered by the resist pattern 96. Therefore, the surface of the other source / drain region 24 has a lower impurity concentration than the surface of the other diffusion layer.

[0220] Then, if Figure 8 As shown in (B) of FIG. 1 , the insulating layer 80 is formed by the manufacturing process described in the second embodiment.

[0221] Here, in the display device, when the write operation of the image signal is performed, the source voltage of the driving transistor is increased to the emission voltage of the light-emitting part ELP. Due to this fluctuation of the source voltage, the gate voltage of the driving transistor is also increased due to the coupling of the holding capacitor. The ratio of the rise of the gate voltage to the rise of the source voltage is called the bootstrap gain. Due to the parasitic capacitance of the transistor in the pixel circuit, this bootstrap gain can be reduced. The parasitic capacitance of the transistor in the pixel circuit has the threshold voltage Vth of the transistor as a parameter. Therefore, due to the change of the threshold voltage Vth of the transistor in the pixel circuit, the bootstrap gain may vary for each pixel. In this case, the luminous brightness of each pixel varies, and the brightness uniformity of the screen is impaired.

[0222] On the contrary, in the present embodiment, by setting the surface of the other source / drain region (diffusion layer) 24 to which a high voltage is applied to a region where the impurity ion concentration is lower than the surface concentration of the other diffusion layer, the depletion layer width can be increased. Therefore, the electric field between the other source / drain region 24 and the n-type diffusion layer (n-well) 11 can be mitigated, the parasitic capacitance between the other source / drain region 24 and the n-type diffusion layer (n-well) 11 can be reduced, and the bootstrap gain can be improved.

[0223] Therefore, the correction accuracy of the variation in the threshold voltage Vth of the driving transistor is improved, and the brightness uniformity of the screen can be improved.

[0224] Note that Figure 8 After the process (A), Fig. 9 As shown, in the state where the diffusion layer other than the other source / drain region 24 and the one source / drain region 46 is covered with a resist pattern 97, if reference is not performed in manufacturing Figure 8 If the ion implantation described above and the contact resistance becomes a problem, the other source / drain region 24 and one source / drain region 46 can be formed under the optimal ion implantation conditions (where the reduction of parasitic capacitance and the contact resistance are compatible with each other).

[0225] [Embodiment of electronic device]

[0226] The organic EL display device of the present disclosure is incorporated in, for example, various electrical devices described later in Application Examples 1 to 6. Note that the application examples are not limited to these, and the organic EL display device of the present disclosure can be applied to, for example, other electronic devices such as various display units in portable information terminals, smartphones, portable music players, game consoles, electronic books, electronic dictionaries, and electronic viewfinders.

[0227] The organic EL display device of the present disclosure as described above has stable display quality even if miniaturized and provides high definition, and thus can provide an image of high display quality to a user of an electronic device in which the organic EL display device is incorporated.

[0228] (Application Example 1)

[0229] Fig.10 The appearance of a television device 300 as an electronic device is shown. The television device includes, for example, a video display screen unit 301 including a front panel 310 and a filter glass 320. The video display screen unit 301 includes the display device according to the above-described embodiment.

[0230] (Application Example 2)

[0231] Fig.11 The appearance of a digital camera 400 as an electronic device is shown. The digital camera includes a light emitting portion 410 for flash, for example, a display unit 420, a menu switch 430, and a shutter button 440. The display unit 420 includes the display device according to the above-described embodiment.

[0232] (Application Example 3)

[0233] Fig.12 The appearance of a notebook personal computer 500 as an electronic device is shown. The notebook personal computer includes, for example, a main body 510, a keyboard 520 for operation of inputting characters and the like, and a display unit 530 for displaying images. The display unit 530 includes the display device according to the above-described embodiment.

[0234] (Application Example 4)

[0235] Fig.13 The appearance of a video camera 600 as an electronic device is shown. The video camera includes, for example, a main body 610, a lens 620 for imaging a subject provided on the front side of the main body 610, a start / stop switch 630 for imaging, and a display unit 640. The display unit 640 includes the display device according to the above-described embodiment.

[0236] (Application Example 5)

[0237] Fig.14 The appearance of a mobile phone 700 as an electronic device is shown. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. The display 740 or the sub-display 750 includes the display device according to the above-described embodiment.

[0238] (Application Example 6)

[0239] Fig.15 The appearance of a head mounted display 800 as an electronic device is shown. The head mounted display is obtained by mounting a glasses mounted monocular display 810 on glasses 800 such as glasses, goggles, or sunglasses. The glasses mounted monocular display 810 includes the display device according to the above-described embodiment.

[0240] Furthermore, the display device according to the above-described embodiment may be applied to, for example, a head-mounted display for virtual reality (VR), augmented reality (AR), or mixed reality (MR) as another form of the head-mounted display.

[0241] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the present technology.

[0242] For example, in the above-described embodiments, an example in which a transistor is formed on a silicon semiconductor substrate has been described, but the transistor may be configured to be formed on a substrate of glass or the like on which a semiconductor film is formed as a silicon region.

[0243] In the above-described embodiments, PMOS in which the conductivity type of the channels of various transistors is p-type has been exemplified, but n-type NMOS may be used.

[0244] In addition, in the above-mentioned embodiment, a pixel circuit including four transistors (driving transistor TRDrv, image signal writing transistor TRSig, first light emission control transistor TREl_c_1 and second light emission control transistor TREl_c_2) and two capacitors (first capacitor C1 and second capacitor C2) has been illustrated. However, the present technology is not limited to this, and it is sufficient to include at least a plurality of transistors. For example, the pixel circuit may include three transistors and one capacitor, three transistors and two capacitors, or four transistors and one capacitor.

[0245] Furthermore, in the above-described embodiment, the case where there is no silicide non-formation region in the peripheral circuit has been described, but a silicide non-formation region may be provided in the peripheral circuit.

[0246] In addition, in the above-mentioned embodiments, when the light-emitting part is constructed using OLED, however, another light-emitting part of a self-luminous type may be used, such as an inorganic electroluminescent part, a light-emitting diode (LED) light-emitting part, or a semiconductor laser light-emitting part.

[0247] Note that the present technology can adopt the following configurations.

[0248] (1) A display device comprising:

[0249] a light emitting portion; and

[0250] A driving circuit includes a transistor driving a light emitting portion and including a first diffusion layer and a first contact electrode, the first diffusion layer not including silicide formed in a silicon region, the first contact electrode being electrically connected to the first diffusion layer.

[0251] (2) The display device according to (1), wherein:

[0252] The driving circuit includes a transistor including a second diffusion layer including silicide formed in a silicon region and a second contact electrode electrically connected to the second diffusion layer.

[0253] (3) The display device according to (2), wherein:

[0254] The impurity concentration at the diffusion layer surface of the first diffusion layer is lower than that of the second diffusion layer.

[0255] (4) The display device according to (2) or (3), wherein:

[0256] The first diffusion layer includes a deeper region than the second diffusion layer.

[0257] (5) The display device according to any one of (1) to (4), wherein:

[0258] The driving circuit includes a transistor having a first diffusion layer connected to the light emitting portion via a first contact electrode.

[0259] (6) The display device according to (5), wherein:

[0260] The transistor including the first diffusion layer is a drive transistor operating as a current limiting element.

[0261] (7) The display device according to any one of (1) to (6), wherein:

[0262] The driving circuit includes an image signal writing transistor including a first diffusion layer and turning on or off a driving current flowing through the light emitting portion.

[0263] (8) The display device according to any one of (1) to (7), wherein:

[0264] The driving circuit further includes an insulating film covering the first diffusion layer.

[0265] (9) The display device according to any one of (1) to (8), wherein:

[0266] The light emitting part is an organic light emitting diode.

[0267] (10) An electronic device comprising

[0268] Display device, including

[0269] The light-emitting part, and

[0270] a driving circuit including a transistor driving a light emitting portion and including a first diffusion layer and a first contact electrode, the first diffusion layer not including silicide formed in a silicon region,

[0271] The first contact electrode is electrically connected to the first diffusion layer.

[0272] Reference Numbers List

[0273] 10Silicon semiconductor substrate (silicon region)

[0274] 21, 31, 35, 61 Gate electrode (diffusion layer)

[0275] 23 A source / drain region of the driving transistor TRDrv (first diffusion layer, second diffusion layer)

[0276] 24 Another source / drain region (first diffusion layer) of the driving transistor TRDrv

[0277] 33 One source / drain region of the image signal writing transistor TRSig (first diffusion layer, second diffusion layer)

[0278] 34 Another source / drain region of the image signal writing transistor TRSig (first diffusion layer, second diffusion layer)

[0279] 36 A source / drain region of the first light emission control transistor TREl_c_1 (first diffusion layer, second diffusion layer)

[0280] 37 Another source / drain region of the first light emission control transistor TREl_c_1 (first diffusion layer, second diffusion layer)

[0281] 46 A source / drain region (first diffusion layer) of the second light emission control transistor TREl_c_2

[0282] 47 Another source / drain region (first diffusion layer) of the second light emission control transistor TREl_c_2

[0283] 63 Another source / drain region (second diffusion layer) of the transistor of the peripheral circuit

[0284] 64 Another source / drain region (second diffusion layer) of the transistor of the peripheral circuit

[0285] 60 Peripheral circuit transistors (transistors)

[0286] 70 contact electrode (first contact electrode, second contact electrode)

[0287] 71 contact electrode (first contact electrode)

[0288] 73, 74 contact electrodes (second contact electrodes)

[0289] 80, 81 insulation film

[0290] 90 Silicide

[0291] 100 display devices

[0292] 110 peripheral circuit (drive circuit)

[0293] 120 pixel circuit (driving circuit)

[0294] 300 Television equipment (electronic equipment)

[0295] 301 Video display unit (display device)

[0296] 400 digital camera (electronic equipment)

[0297] 420 display unit (display device)

[0298] 500 Notebook personal computers (electronic equipment)

[0299] 530 display unit (display device)

[0300] 600 camera (electronic equipment)

[0301] 640 display unit (display device)

[0302] 700 Mobile phones (electronic devices)

[0303] 740 display (display device)

[0304] 750 sub-display (display device)

[0305] 800 Head-mounted display (electronic device)

[0306] 810 single-eye display (display device)

[0307] ELP light emitting part

[0308] TRDrv driver transistor (transistor)

[0309] TRSig Image signal writing transistor (transistor)

[0310] TREl_c_1 first light emission control transistor (transistor)

[0311] TREl_c_2 second light emitting control transistor (transistor).

Claims

1. A display device, comprising: Luminous part; as well as The driving circuit includes: a pixel circuit, wherein the pixel circuit is located in a first silicon region and includes a first transistor and a first contact electrode, the first transistor is configured to drive the light emitting portion and includes a first diffusion layer and a second diffusion layer, the entire surface of each of the first diffusion layer and the second diffusion layer is a silicide non-forming region, no silicide is contained in the silicide non-forming region, an insulating film covers the first diffusion layer and the second diffusion layer, and the first contact electrode is electrically connected to the first diffusion layer; and A peripheral circuit, wherein the peripheral circuit is located in the second silicon region and includes a second transistor, the second transistor includes a third diffusion layer and a fourth diffusion layer, the entire surface of each of the third diffusion layer and the fourth diffusion layer is a silicide formation region, the silicide formation region contains silicide and does not contain the insulating film.

2. The display device according to claim 1, wherein: The peripheral circuit further includes a second contact electrode electrically connected to the third diffusion layer.

3. The display device according to claim 1, wherein: The impurity concentration on the diffusion layer surface of the first diffusion layer is higher than that of the second diffusion layer.

4. The display device according to claim 1, wherein: The second diffusion layer includes a deeper region than the first diffusion layer.

5. The display device according to claim 1, wherein: The first transistor is connected to the light emitting portion via the first contact electrode.

6. The display device according to claim 5, wherein: The first transistor is a drive transistor operating as a current limiting element.

7. The display device according to claim 1, wherein: The drive circuit further includes an image signal write transistor configured to turn on or off a drive current flowing through the light emitting portion.

8. The display device according to claim 1, wherein: The light emitting part is an organic electroluminescent diode.

9. An electronic device, comprising: The display device comprises: The light-emitting part, and The driving circuit includes: a pixel circuit, wherein the pixel circuit is located in a first silicon region and includes a first transistor and a first contact electrode, the first transistor is configured to drive the light emitting portion and includes a first diffusion layer and a second diffusion layer, the entire surface of each of the first diffusion layer and the second diffusion layer is a silicide non-forming region, no silicide is contained in the silicide non-forming region, an insulating film covers the first diffusion layer and the second diffusion layer, and the first contact electrode is electrically connected to the first diffusion layer; and A peripheral circuit, wherein the peripheral circuit is located in the second silicon region and includes a second transistor, the second transistor includes a third diffusion layer and a fourth diffusion layer, the entire surface of each of the third diffusion layer and the fourth diffusion layer is a silicide formation region, the silicide formation region contains silicide and does not contain the insulating film.

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