Ion trap arrays for high-throughput charge-detection mass spectrometry

Abstract

An electrostatic linear ion trap (ELIT) array comprises: a plurality of elongated charge detection cylinders arranged end to end and each defining an axial passage extending centrally therethrough; a plurality of ion mirror structures, each defining a pair of axially aligned cavities and an axial passage extending centrally therethrough, wherein a different ion mirror structure is disposed between opposite ends of each cylinder; and a front ion mirror and a rear ion mirror, each defining at least one cavity and an axial passage extending centrally therethrough, the front ion mirror being positioned at one end of the arrangement of the charge detection cylinders and the rear ion mirror being positioned at opposite ends of the arrangement of the charge detection cylinders, wherein the axial passages of the charge detection cylinders, the ion mirror structures, the front ion mirrors, and the rear ion mirrors are coaxial to define a longitudinal axis extending centrally through the ELIT array. In a second aspect, the ELIT array comprises a plurality of non-coaxial ELIT regions, wherein ions are selectively directed into each of the ELIT regions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application Serial No. 62 / 680,315, filed on June 4, 2018, the disclosure of which is incorporated herein by reference in its entirety.

[0003] Government Rights

[0004] This invention was made with government support under CHE 1531823 awarded by the National Science Foundation. The U.S. Government has certain rights in this invention. Technical Field

[0005] The present disclosure relates generally to charge detection mass spectrometry instruments, and more particularly to performing mass and charge measurements using such instruments. Background Art

[0006] Mass spectrometry provides identification of the chemical composition of a substance by separating its gaseous ions according to their mass and charge. Various instruments and techniques have been developed for determining the mass of such separated ions, and one such technique is known as charge detection mass spectrometry (CDMS). In CDMS, the mass of an ion is determined based on the measured mass-to-charge ratio of the ion (commonly referred to as "m / z") and the measured charge of the ion.

[0007] Early CDMS detectors had high uncertainties in m / z and charge measurements, which led to the development of electrostatic linear ion trap (ELIT) detectors, in which ions are forced to oscillate back and forth through a charge detection cylinder. Multiple passes of the ions through such a charge detection cylinder provide multiple measurements for each ion. And it has been shown that the uncertainty in the charge measurement increases with n. 1 / 2 Where n is the number of charge measurements. However, such multiple charge measurements necessarily limit the rate at which ion m / z and charge measurements can be obtained using current ELIT designs. Therefore, it is desirable to seek improvements in ELIT design and / or operation that increase the rate at which ion m / z and charge measurements can be obtained relative to the rate that can be obtained using current ELIT designs. Summary of the invention

[0008] The present disclosure may include one or more features mentioned in each embodiment, and / or one or more of the following features and their combinations. In a first aspect, an electrostatic linear ion trap (ELIT) array may include: a plurality of elongated charge detection cylinders arranged end to end and each defining an axial passage extending centrally therethrough; a plurality of ion mirror structures, each defining a pair of axially aligned cavities, and each defining an axial passage extending centrally through the two cavities through the ion mirror structure, wherein different ion mirror structures in the plurality of ion mirror structures are disposed between opposite ends of each pair of elongated detection cylinders arranged in pairs; and a front ion mirror and a rear ion mirror, each defining at least one cavity and an axial passage extending centrally therethrough, the front ion mirror being positioned at one end of the plurality of charge detection cylinders, and the rear ion mirror being positioned at opposite ends of the plurality of charge detection cylinders, wherein the axial passages of the plurality of charge detection cylinders, the plurality of ion mirror structures, the front ion mirrors, and the rear ion mirrors are axially aligned with each other to define a longitudinal axis extending centrally through the ELIT array.

[0009] In a second aspect, a system for separating ions may include: an ion source configured to generate ions from a sample; at least one ion separation instrument configured to separate the generated ions according to at least one molecular characteristic; and the ELIT described above in the first aspect, wherein ions leaving the at least one ion separation instrument enter the ELIT array via a front ion mirror.

[0010] In a third aspect, a system for separating ions may include: an ion source configured to generate ions from a sample; a first mass spectrometer configured to separate the generated ions according to a mass-to-charge ratio; an ion dissociation stage positioned to receive ions leaving the first mass spectrometer and configured to dissociate ions leaving the first mass spectrometer; a second mass spectrometer configured to separate dissociated ions leaving the ion dissociation stage according to a mass-to-charge ratio; and a charge detection mass spectrometer (CDMS) including the ELIT array described above in the first aspect, coupled in parallel with and to the ion dissociation stage, such that the CDMS is capable of receiving ions leaving either the first mass spectrometer and the ion dissociation stage, wherein the mass of precursor ions leaving the first mass spectrometer is measured using the CDMS, the mass-to-charge ratio of dissociated ions of precursor ions having a mass value below a threshold mass is measured using the second mass spectrometer, and the mass-to-charge ratio and charge value of dissociated ions of precursor ions having a mass value at or above the threshold mass are measured using the CDMS.

[0011] In a fourth aspect, a charge detection mass spectrometer (CDMS) may include: an ion source configured to generate and supply ions; an electrostatic linear ion trap (ELIT) array including a plurality of ion mirrors, each ion mirror defining a corresponding axial passage through it; and a plurality of charge detection cylinders, each charge detection cylinder defining a corresponding axial passage through it, the plurality of ion mirrors and the charge detection cylinders being arranged to define a plurality of ELIT regions, each ELIT region including a different charge detection cylinder among the plurality of charge detection cylinders positioned between corresponding different ion mirrors among the plurality of ion mirrors, wherein the axial passage of each of the plurality of charge detection cylinders is aligned with the axial passage of a corresponding ion mirror among the plurality of ion mirrors, the ELIT array being configured to receive at least some ions supplied by the ion source; and a device for controlling each of the plurality of ion mirrors, for trapping different ions supplied by the ion source in each of the plurality of ELIT regions, and for causing the ions trapped in each of the plurality of ELIT regions to oscillate back and forth between corresponding pairs of the plurality of ion mirrors each time they pass through a corresponding one of the plurality of charge detection cylinders.

[0012] In a fifth aspect, a method is provided for measuring ions supplied to an ion inlet of an electrostatic linear ion trap (ELIT) array, the array having a plurality of ion mirrors and a plurality of elongated charge detection cylinders, each defining a corresponding axial passage therethrough, wherein the plurality of charge detection cylinders are arranged end to end in a cascade relationship, wherein a different one of the plurality of ion mirrors is positioned between each charge detection cylinder, and wherein a first and a last one of the plurality of ion mirrors are positioned at corresponding opposite ends of the cascade arrangement, wherein the first ion mirror and the last ion mirror define, respectively, an ion inlet and an ion outlet of the ELIT array, and wherein the axial passages of each of the plurality of ion mirrors and the charge detection cylinders are co-linear with one another and define a longitudinal axis centered therethrough to form a sequence of axially aligned ELIT array regions, each ELIT array region being defined by one of the plurality of charge detection cylinders and a corresponding pair of the plurality of ion mirrors at each end thereof. The method may include: controlling at least one voltage source to apply a voltage to each of a plurality of ion mirrors to construct an ion transmission electric field therein so that ions entering the ion inlet of the ELIT pass through each of the plurality of ion mirrors and the charge detection cylinder and the ion outlet of the ELIT array, wherein each ion transmission field is configured to focus ions passing therethrough toward the longitudinal axis, and controlling at least one voltage source to sequentially modify the voltage applied to each of the plurality of ion mirrors while maintaining the voltage previously applied to the remaining ion mirrors of the plurality of ion mirrors, starting with the last ion mirror and ending with the first ion mirror, thereby sequentially constructing an ion reflection electric field in each of the plurality of ion mirrors in a manner that sequentially captures different ions in each ELIT region, wherein each ion reflection electric field is configured to cause ions entering the corresponding ion mirror from an adjacent one of the plurality of charge detection cylinders to stop and accelerate back in the opposite direction through a corresponding one of the plurality of charge detection cylinders, wherein the ions trapped in each ELIT region oscillate back and forth between the corresponding ion mirrors of the plurality of ion mirrors under the action of the ion reflection electric field constructed therein, the ions passing through a corresponding one of the plurality of charge detection cylinders each time and inducing corresponding charges thereon. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a simplified illustration of an ion mass detection system including an embodiment of an electrostatic linear ion trap (ELIT) array having control and measurement elements coupled thereto.

[0014] Figure 2A is Figure 1 A magnified view of an exemplary ion mirror of an ELIT array is shown in FIG. Mirror electrodes are controlled to generate an ion-transmitting electric field within the exemplary ion mirror.

[0015] Figure 2B is Figure 1 A magnified view of another exemplary ion mirror of an ELIT array is shown in FIG. 1 , wherein the mirror electrodes are controlled to generate an ion reflecting electric field within the exemplary ion mirror.

[0016] Figure 3 is a simplified flow chart showing an embodiment of a process. The process is used to control Figure 1 Operation of the ELIT array to determine ion mass and charge information.

[0017] FIG. 4A to FIG. 4E yes Figure 1 A simplified view of the ELIT array. Figure 3 The process shown in demonstrates the sequential control and operation of multiple ion mirrors.

[0018] Figure 5A is a simplified block diagram of an embodiment of an ion separation instrument including any ELIT array shown and described herein, and showing an example ion processing instrument which may form part of an ion source upstream of the ELIT array, and / or which may be disposed downstream of the ELIT array to further process ions leaving the ELIT array.

[0019] Figure 5B is a simplified block diagram of another embodiment of an ion separation instrument including any of the ELIT arrays shown and described herein, and illustrates an example implementation that combines a conventional ion processing instrument with any of the embodiments of the ion mass detection system shown and described herein.

[0020] Figure 6 is a simplified illustration of an ion mass detection system including yet another embodiment of an electrostatic linear ion trap (ELIT) array having control and measurement elements coupled thereto.

[0021] Fig. 7A is a simplified perspective view of an example embodiment of a single ion manipulation channel that can be Figure 6 The ion manipulation channel array shown in FIG.

[0022] Figure 7B is a simplified perspective diagram showing Fig. 7A An example operating mode of the ion manipulation channel is shown in FIG.

[0023] Figure 7C is a simplified perspective diagram showing Fig. 7A Another example operating mode of the ion manipulation channel is shown in FIG.

[0024] FIG. 8A to FIG. 8F yes Figure 6A simplified view of an ELIT array showing example control and manipulation of the ion manipulation channel array and the ELIT array.

[0025] Fig. 9 is a simplified illustration of an ion mass detection system including yet another embodiment of an electrostatic linear ion trap (ELIT) array having control and measurement elements coupled thereto. DETAILED DESCRIPTION

[0026] For the purposes of promoting an understanding of the principles of the present disclosure, reference will now be made to a number of illustrative embodiments illustrated in the drawings, and specific language will be used to describe the same.

[0027] The present disclosure relates to an electrostatic linear ion trap (ELIT) array comprising two or more ELITs or ELIT regions and means for controlling the two or more ELITs or ELIT regions such that at least two of the ELITs or ELIT regions operate simultaneously to measure the mass-to-charge ratio and the charge of the ions trapped therein. In this way, the rate of ion measurement is increased by a factor of two or more compared to conventional single ELIT systems, and a corresponding reduction in the total ion measurement time is achieved. In some embodiments, examples of such embodiments will be described below with reference to Figures 1 to 4E In detail, an ELIT array can be implemented in the form of two or more ELIT regions connected in series, i.e., cascaded and arranged in axial alignment. And the ion mirrors at the opposite ends of each of the two or more cascaded ELIT or ELIT regions are controlled in a manner that sequentially traps ions in each ELIT or ELIT region and causes each trapped ion to oscillate back and forth through a corresponding charge detector positioned in the corresponding ELIT or ELIT region to measure the mass-to-charge ratio and the charge of the trapped ion. In the embodiment described below with reference to Figures 6 to 9 In other embodiments described in detail, the ELIT array can be implemented in the form of two or more ELITs arranged in parallel relative to each other. The ion manipulation array can be controlled to direct ions sequentially or simultaneously into each of the parallel-arranged ELITs. Thereafter, the two or more ELITs are controlled in a manner that causes the ions trapped therein to oscillate back and forth through their charge detectors to measure the mass-to-charge ratio and charge of the trapped ions.

[0028] refer to Figure 1, charge detection mass spectrometer (CDMS) 10 is shown as comprising electrostatic linear ion trap (ELIT) array 14 and the embodiment of the control and measurement components coupled thereto. In the illustrated embodiment, CDMS 10 comprises an ion source 12 operably coupled to the entrance of ELIT array 14. As will be described with reference to FIG5 , ion source 12 illustratively comprises any conventional equipment or apparatus for generating ions from a sample, and may also comprise one or more equipment and / or instruments for separating, collecting, filtering, segmenting and / or normalizing ions according to one or more molecular characteristics. As an illustrative example that should not be considered as restrictive in any way, ion source 12 may comprise conventional electrospray ionization source, matrix-assisted laser desorption ionization (MALDI) source, etc., which are coupled to the entrance of a conventional mass spectrometer. The mass spectrometer may be of any conventional design, including, but not limited to, a time-of-flight (TOF) mass spectrometer, a reflectron mass spectrometer, a Fourier transform ion cyclotron resonance (FTICR) mass spectrometer, a quadrupole mass spectrometer, a triple quadrupole mass spectrometer, a magnetic sector mass spectrometer, etc. In any case, the ion outlet of the mass spectrometer is operably coupled to the ion inlet of the ELIT array 14. The sample from which the ions are generated may be any biological material or other material.

[0029] exist Figure 1 In the embodiment shown in, the ELIT array 14 is illustratively provided in the form of three ELIT or ELIT region cascade (i.e., in series or end-to-end) arrangements. Three separated charge detectors CD1, CD2, CD3 are respectively surrounded by corresponding ground cylinders GC1-GC3, and are operatively coupled together by relative ion mirrors. The first ion mirror or front ion mirror M1 is operably positioned between the ion source 12 and one end of the charge detector CD1, the second ion mirror M2 is operably positioned between the opposite end of the charge detector CD1 and one end of the charge detector CD2, the third ion mirror M3 is operably positioned between the opposite end of the charge detector CD2 and one end of the charge detector CD3, and the fourth ion mirror or rear ion mirror is operably positioned at the opposite end of the charge detector CD3. In the illustrated embodiment, each of the ion mirrors M1-M3 defines an axially aligned and adjacent but relatively facing ion mirror regions or cavities R1, R2, which are separated from each other by plates, rings or grids, which define perforations therethrough, and the ion mirror M4 illustratively defines a single ion mirror region or cavity R1. In some alternative embodiments, the ion mirror M4 may be the same as the ion mirrors M1-M3. That is, the ion mirror M4 may define axially aligned and adjacent but relatively facing ion mirror regions R1, R. Alternatively or additionally, the ion mirror M1 may be provided in the form of a single region ion mirror (e.g., region R2).

[0030] In the illustrated embodiment, the region or cavity R2 of the first ion mirror M1, the charge detector CD1, the region or cavity R1 of the second ion mirror M2, and the space between CD1 and the ion mirrors M1 and M2 together define a first ELIT or ELIT region E1 of the ELIT array 14, the region or cavity R2 of the second ion mirror M2, the charge detector CD2, the region or cavity R1 of the third ion mirror M3, and the space between CD2 and the ion mirrors M2 and M3 together define a second ELIT or ELIT region E2 of the ELIT array 14, and the region or cavity R2 of the third ion mirror M3, the charge detector CD3, the region or cavity R1 of the ion mirror M4, and the space between CD3 and the mirror electrodes M3 and M4 together define a third ELIT or ELIT region E3 of the ELIT array 14. It should be understood that in some alternative embodiments, the ELIT array 14 may include fewer cascaded ELITs or ELIT regions, for example, two cascaded ELITs or ELIT regions, while in other alternative embodiments, the ELIT array 14 may include more cascaded ELITs or ELIT regions, for example, four or more cascaded ELITs or ELIT regions. The structure and operation of any such alternative ELIT array 14 will generally follow the Figures 1 to 4E The structure and operation of the embodiments shown in FIG. 1 and described below.

[0031] In the illustrated embodiment, four respective voltage sources V1-V4 are electrically connected to the ion mirrors M1-M4, respectively. Each voltage source V1-V4 illustratively includes one or more switchable DC voltage sources that can be controlled or programmed to selectively generate a number N of programmable or controllable voltages. Where N can be any positive integer. Illustrative examples of such voltages will be described below with respect to Figure 2A and Figure 2B Described, to construct one of two different operating modes of each ion mirror M1-M4 as described in detail below, individually and / or together. In any case, the longitudinal axis 24 extends centrally through each of the charge detectors CD1-CD3 and through each of the regions or cavities R1, R2 of each ion mirror M1-M4 (and centrally through each perforation defined in each ion mirror M1-M4 and through each ion mirror M1-M4). In addition, the central axis 24 defines an ideal path of travel. Ions move along the ideal path of travel within the ELIT array 14 and its parts under the action of the electric field selectively constructed by the voltage sources V1-V4.

[0032] Voltage sources V1-V4 are illustratively shown as being electrically connected to a conventional processor 16 by a signal path of quantity P. Processor 16 includes a memory 18. Memory 18 has instructions stored therein. This instruction, when executed by processor 16, causes processor 16 to control voltage sources V1-V4 to produce a desired DC output voltage for selectively constructing an electric field in the ion mirror region or chamber R1, R2 of corresponding ion mirrors M1-M4. P can be any positive integer. In some alternative embodiments, one or more of voltage sources V1-V4 can be programmable to selectively produce one or more constant output voltages. In other alternative embodiments, one or more of voltage sources V1-V4 can be configured to produce one or more time-varying output voltages with any desired shape. It should be understood that in alternative embodiments, more or fewer voltage sources can be electrically connected to mirror electrodes M1-M4.

[0033] Each charge detector CD1-CD3 is electrically connected to a signal input of a corresponding one of three charge sensitive preamplifiers CP1-CP3, and a signal output of each charge preamplifier CP1-CP3 is electrically connected to a processor 16. Each of the charge preamplifiers CP1-CP3 is illustratively operable in a conventional manner to receive a detection signal detected by a corresponding one of the charge detectors CD1-CD3 to generate a charge detection signal corresponding thereto, and to supply the charge detection signal to the processor 16. The processor 16 is then illustratively operable to receive and digitize the charge detection signal generated by each of the charge preamplifiers CP1-CP3, and to store the digitized charge detection signal in a memory 18. The processor 16 is further illustratively coupled to one or more peripheral devices 20 (PD). The peripheral devices 20 are used to provide signal inputs to the processor 16 and / or the processor 16 provides signal outputs thereto. In some embodiments, the peripheral device 20 includes at least one of a conventional display monitor, a printer, and / or other output device, and in such embodiments, the memory 18 has instructions stored therein that, when executed by the processor 16, cause the processor 16 to control one or more of such output peripheral devices 20 to display and / or record an analysis of the stored digitized charge detection signal. In some embodiments, a conventional microchannel plate (MP) detector 22 may be disposed at the ion exit of the ELIT array 14 (i.e., at the ion exit of the ion mirror M4) and electrically connected to the processor 16. In such embodiments, the microchannel plate detector 22 is operable to supply detection signals to the processor 16 corresponding to the detected ions and / or neutrons.

[0034] As will be described in more detail below, voltage sources V1-V4 are illustratively controlled in a manner that selectively and continuously directs ions entering the ELIT array 14 from the ion source 12 into each of three separate ELIT or ELIT regions E1-E3 such that different ions are trapped within each of the three regions E1-E3 and oscillate between corresponding ion mirrors M1-M4 upon each passage through a corresponding one of the charge detectors CD1-CD3. Multiple charge and oscillation period values ​​are measured at each charge detector CD1-CD3, and the recorded results are processed to determine the charge, mass-to-charge ratio, and ion mass values ​​of the ions in each of the three ELIT or ELIT regions E1-E3. Depending on many factors including but not limited to the size of the three ELIT or ELIT regions E1-E3, the oscillation frequency of the ions and the residence time of the ions within each of the three ELIT or ELIT regions E1-E3, the trapped ions are oscillated simultaneously in at least two of the three ELIT or ELIT regions E1-E3 and in each of the three ELIT or ELIT regions E1-E3 in a typical embodiment, so that ion charge and mass-to-charge ratio measurements can be collected simultaneously from at least two of the three ELIT or ELIT regions E1-E3.

[0035] Reference now Figure 2A and Figure 2B , which shows Figure 1 An embodiment of an ion mirror MX of the ELIT array 14. Where X = 1-4. It shows an example structure and operation of the ion mirror MX. Figure 2A and Figure 2B In each of the ion mirrors M2-M4, the ion mirror MX shown comprises a cascade arrangement of seven axially spaced conductive mirror electrodes. For each of the ion mirrors M2-M4, the first electrode 301 is composed of a grounded cylinder GC. X-1 Formation, grounding tube GC X-1 Around the charge detector CD X-1 On the other hand, the first electrode 301 of the ion mirror M1 is formed by the ion outlet of the ion source 12 (IS), or as a part of the ion focusing or transition stage between the ion source 12 and the ELIT array 14. Figure 2B shows the former, while Figure 2A The latter is shown. In either case, the first mirror electrode 301 defines a through-aperture A1 centered therethrough. The through-aperture A1 serves as an ion inlet into the corresponding ion mirror MX and / or an ion outlet from the corresponding ion mirror MX. The through-aperture A1 of the first electrode 301 of the ion mirror M1 illustratively serves as an ion inlet to the ELIT array 14. The through-aperture A1 is illustratively conical in shape, which is at the GC X-1 or between the inner and outer surfaces of the IS from the GCX-1 or the first diameter P1 defined at the inner surface of the IS increases linearly to the diameter P1 defined at the inner surface of the GC. X-1 Or the enlarged diameter P2 at the outer surface of IS. The first mirror electrode 301 illustratively has a thickness D1.

[0036] The second mirror electrode 302 of the ion mirror MX is spaced apart from the first mirror electrode 301 and defines a passage through it having a diameter of P2. The third mirror electrode 303 is spaced apart from the second mirror electrode 302 and also defines a passage through it having a diameter of P2. The second mirror electrode 302 and the third mirror electrode 303 illustratively have equal thicknesses D2, D2 ≥ D1. The fourth mirror electrode 304 is spaced apart from the third mirror electrode 303. The fourth mirror electrode 304 defines a passage through it having a diameter of P2 and illustratively has a thickness D3 between approximately 2D2 and 3D2. The plate, ring or grid 30A is illustratively positioned centrally within the passage of the fourth mirror electrode 304 and defines a central through-hole CA having a diameter of P3 therethrough. In the illustrated embodiment, P3 < P1. However, in other embodiments, P3 may be greater than or equal to P1. The fifth mirror electrode 305 is spaced apart from the fourth mirror electrode 304, and the sixth mirror electrode 306 is spaced apart from the fifth mirror electrode 305. Illustratively, the fifth mirror electrode 305 and the sixth mirror electrode 306 are the same as the third mirror electrode 303 and the second mirror electrode 302 , respectively.

[0037] For each of the ion mirrors M1-M3, the seventh mirror electrode 307 is composed of a grounded tube GC X Formation, grounding tube GC X Around the charge detector CD X On the other hand, the seventh electrode 307 of the ion mirror M4 can be an independent electrode because the ion mirror M4 is the last in the sequence. In either case, the seventh mirror electrode 307 defines a perforation A2 centered therethrough, which serves as an ion inlet into the ion mirror MX and / or an ion outlet from the ion mirror MX. Perforation A2 is illustratively a mirror image of perforation A1 and has a conical shape that is conical in shape. X The outer and inner surfaces decrease linearly from the GC X The expansion diameter P2 defined at the outer surface of the GC decreases linearly to X The seventh mirror electrode 307 illustratively has a thickness of D1. In some embodiments, as in Figure 1 As shown in the example, the last ion mirror in the sequence, i.e., Figure 1 M4 in the embodiment may terminate at the plate or grid 30A, so that M4 includes only the mirror electrodes 301-303, and only a portion of the mirror electrode 4 includes the plate or grid 30A, so that M4 includes only Figure 2A and Figure 2B ion mirror region R1 depicted in FIG. In such embodiments, the central aperture CA of M4 defines the ion exit path from the ELIT array 14. Similarly, the first ion mirror in the sequence, i.e., Figure 1 M1 in may terminate at the plate or grid 30A in some embodiments, so that M1 includes only the mirror electrodes (mirror electrodes 305-307), and only a portion of the mirror electrode 304 includes the plate or grid 30A, so that M4 includes only Figure 2A and Figure 2B Ion mirror region R2 is depicted in FIG. 1 . In such embodiments, the central aperture CA of M1 defines the ion entrance to the ELIT array 14 .

[0038] The mirror electrodes 301-307 are illustratively evenly spaced apart from each other by a space S1. In some embodiments, such space S1 between the mirror electrodes 301-307 may be a void, i.e., a vacuum gap, while in other embodiments, such space S1 may be filled with one or more non-conductive materials, such as a dielectric material. The mirror electrodes 301-307 are axially aligned, i.e., co-linear, so that the longitudinal axis 24 is centered through each aligned passage and also centered through the perforations A1, A2, and CA. In embodiments in which the space S1 includes one or more non-conductive materials, such materials will also define a corresponding passage through it. The corresponding passage is axially aligned (i.e., co-linear) with the passage defined through the mirror electrodes 301-307 and has a diameter of P2 or greater.

[0039] In each ion mirror M1-M4, region R1 is defined between the perforation A1 of the mirror electrode 301 and the central perforation CA defined by the plate or grid 30A. In each ion mirror M1-M3, an adjacent region R2 is defined between the central perforation CA defined by the plate or grid 30A and the perforation A2 of the mirror electrode 307. In the illustrated embodiment, the ion mirrors M1-M3 are each shown in the form of a single mirror structure, which defines two adjacent and opposite (i.e., back-to-back) and axially aligned ion mirror regions R1, R2, which are separated by the plate 30A through which the perforation CA is defined. In some alternative embodiments, one or more of the ion mirrors M1-M3 (and / or M4 in an implementation in which M4 is configured identically to M1-M3) may alternatively be implemented as separate, axially aligned ion mirror structures, which are arranged back-to-back relative to each other and are spaced apart from each other by conventional non-conductive spacers (e.g., electrically insulating plates or rings). In some such embodiments, separate, back-to-back ion mirror structures may be coupled together, i.e., affixed or mounted to each other, and in other embodiments, such structures may be spaced apart from each other but not physically coupled together. Figure 2A and Figure 2BIn an illustrative example of this alternative embodiment of the selected portion of the ion mirror structure shown as an example component, the ion mirror defining R1 may include mirror electrodes 301–303, a transverse half of mirror electrode 304 adjacent to mirror electrode 303, and a plate, ring, or grid 30A, which is modified to fasten to the exposed end of mirror electrode 304 such that the longitudinal axis 24 passes through the perforation CA. The opposing ion mirror defining R2 may similarly include mirror electrodes 305–307, a transverse half of mirror electrode 304 adjacent to mirror electrode 305, and a plate, ring, or grid 30A. The plate, ring, or grid 30A is modified to fasten to the exposed end of mirror electrode 305 such that the longitudinal axis 24 passes through the perforation CA. Those skilled in the art will recognize other ion mirror designs that can be used and that define R1 and R2 in a single structure or in separate structures. And it should be understood that any such alternative ion mirror design is intended to fall within the scope of the present disclosure.

[0040] Within each ELIT or ELIT region E1 - E3, corresponding charge detectors CD1 - CD3 in the form of elongated conductive cylinders are positioned between the respective ion mirrors M1 - M4 of the ion mirrors and are spaced apart by space S2. Illustratively, S2 is greater than S1. However, in alternative embodiments, S2 may be less than or equal to S2. In any case, each charge detection cylinder CD1 - CD3 illustratively defines a passageway with a diameter of P4 axially therethrough. And each charge detection cylinder CD1 - CD3 is oriented relative to the ion mirrors M1 - M4 such that the longitudinal axis 24 extends centrally through its passageway. In the illustrated embodiment, P1 < P4 < P2, but in other embodiments, the diameter of P4 may be less than or equal to P1, or greater than or equal to P2. Each charge detection cylinder CD1 - CD3 is illustratively disposed within the field - free region of a corresponding one of the ground cylinders GC1 - GC3. And as described above, each ground cylinder GC1 - GC3 is positioned between the corresponding ion mirrors of the ion mirrors M1 - M4 and forms part of the corresponding ion mirror. In operation, the ground cylinders GC1 - G3 are illustratively controlled at ground potential such that the first electrode 301 and the seventh electrode 307 are always at ground potential. In some alternative embodiments, one or both of the first electrode 301 and the seventh electrode 307 in one or more of the ion mirrors M1 - M4 may be set to any desired DC reference potential. And in other alternative embodiments, one or both of the first electrode 301 and the seventh electrode 307 in one or more of the ion mirrors M1 - M4 may be electrically connected to a switchable DC voltage source or other time - varying voltage source.

[0041] As briefly described above, the voltage sources V1-V4 are illustratively controlled in a manner that causes ions entering the ELIT array 14 from the ion source 12 to be selectively captured within each ELIT or ELIT region E1-E3. More specifically, the voltage sources V1-V4 are controlled in a manner that sequentially captures ions in each ELIT or ELIT region, illustratively starting with E3 and ending with E1, and that causes each trapped ion to oscillate between corresponding ion mirrors in the ion mirrors M1-M4 within a corresponding ELIT or ELIT region in the ELIT or ELIT regions E1-E3. Each such captured oscillating ion therefore repeatedly passes through a corresponding one of the charge detectors CD1-CD3 in a corresponding one of the three ELIT or ELIT regions E1-E3, and each time a corresponding oscillating ion passes through each charge detector CD1-CD3, the charge and oscillation period values ​​are measured and recorded at the corresponding charge detectors CD1-CD3. The measurements are recorded and processed to determine the charge, mass-to-charge ratio, and mass values ​​for each of the three ions.

[0042] In each ELIT or ELIT region E1-E3 of the ELIT array 14, ion transmission and ion reflection electric fields are selectively constructed in regions R1, R2 of the ion mirrors M1-M4 by controlling the voltage sources V1-V4, capturing ions and causing the ions to oscillate between relative regions of the corresponding ion mirrors M1-M4. In this regard, in one embodiment, each voltage source VX is illustratively configured to generate seven DC voltages DC1-DC7, and each of the voltages DC1-DC7 is provided to a corresponding one of the mirror electrodes 301-307 of the corresponding ion mirror MX. In some embodiments in which one or more of the mirror electrodes 301-307 are always maintained at ground potential, one or more of such mirror electrodes 301-307 may alternatively be electrically connected to the ground reference of the voltage source VX, and the corresponding one or more voltage outputs DC1-DC7 may be omitted. Alternatively or additionally, in embodiments in which any two or more of the mirror electrodes 301-307 are controlled to the same non-zero DC value, any such two or more mirror electrodes 301-307 may be electrically connected to a single one of the voltage outputs DC1-DC7, and redundant ones of the output voltages DC1-DC7 may be omitted.

[0043] As in Figure 2A and Figure 2B As shown in the example, by selectively applying voltages DC1-DC7, each ion mirror MX can be in ion transmission mode ( Figure 2A ) and ion reflectron mode ( Figure 2B) are controlled between, in the ion transmission mode, the voltage DC1-DC7 generated by the voltage source VX constructs an ion transmission electric field in each of the regions R1 and R2 of the ion mirror MX, and in the ion reflection mode, the voltage DC1-DC7 generated by the voltage source VX constructs an ion capture or reflection electric field in each of the regions R1 and R2 of the ion mirror MX. In the ion transmission mode, the voltages DC1-DC7 are selected to construct an ion transmission electric field TEF1 in the region R1 of the ion mirror MX, and to construct another ion transmission electric field TEF2 in the region R2 of the ion mirror MX. Figure 2A Example ion transmission electric field lines are depicted in each of the ion mirror regions R1 and R2 of the ion mirror shown in FIG. The ion transmission electric fields TEF1 and TEF2 are illustratively constructed to focus ions toward a central longitudinal axis 24 within the ion mirror MX so as to maintain a narrow ion trajectory about the axis 24 as the ions pass through the two regions R1, R2 of the ion mirror MX into the adjacent charge detection cylinder CDX.

[0044] In the ion reflection mode, voltages DC1-DC7 are selected for constructing an ion reflection electric field REF1 in region R1 of the ion mirror MX and for constructing another ion reflection electric field REF2 in region R2 of the ion mirror MX. Figure 2B Exemplary ion reflection electric field lines are depicted in each of the ion mirror regions R1 and R2 of the ion mirror shown in . The ion reflection electric fields REF2 and REF2 are illustratively constructed to cause ions to travel axially toward the central perforation CA of MX into the corresponding regions R1, R2, and to reverse direction and be accelerated by the reflection electric fields REF1, REF2 in a relative direction axially away from the central perforation CA. Each ion reflection electric field REF1, REF2 does this by the following steps: first, the ions traveling into the corresponding regions R1, R2 of the ion mirror MX are decelerated and stopped, and then the ions are accelerated back in the opposite direction through the corresponding regions R1, R2, while the ions are focused toward the longitudinal axis 24, so that the ions travel away from the corresponding regions R1, R2 along a narrow trajectory in the opposite direction from which the ions entered the corresponding regions R1, R2. Therefore, along or near the central longitudinal axis 24 from the charge detection cylinder CD X-1 Ions travelling into region R1 of ion mirror MX are reflected by electric field REF1 towards charge detection cylinder CD along or near central longitudinal axis 24. X-1 Reflected back and enters the charge detection tube CD X-1, and another ion that travels from the charge detection cylinder CDX along or near the central longitudinal axis 24 into region R2 of the ion mirror MX is reflected by the reflected electric field REF2 back toward the charge detection cylinder CDX along or near the central longitudinal axis 24 and into the charge detection cylinder CDX. Ions that traverse the length of the ELIT or ELIT regions E1-E3 and are reflected by the ion reflected electric field REF in the ion regions R1, R2 of the corresponding ion mirrors M1-M4 in a manner that enables the ions to continue traveling back and forth through the charge detection cylinder CD between these ion mirrors as just described should be considered to be trapped in the ELIT or ELIT regions E1-E3.

[0045] An example set of output voltages DC1-DC7, generated by voltage sources V1-V4, respectively, for controlling a corresponding one of ion mirrors M1-M4 in the ion transmission mode and reflection mode described above are shown below in Table 1. It will be understood that the following values ​​of DC1-DC7 are provided by way of example only, and other values ​​of one or more of DC1-DC7 may be used instead.

[0046] Table 1

[0047]

[0048] exist Figure 2A and Figure 2B In the examples shown and described above, voltage sources V1-V4 are controlled to construct or maintain the same electric field, such as the ion transmission electric field TEF or the ion reflection electric field REF, in each ion mirror region R1, R2 of each ion mirror at any point in time. Such control may also be performed in embodiments in which one or more ion mirror structures are provided in the form of separate, back-to-back ion mirrors as described above. However, it should be understood that such control represents only one example ion mirror control arrangement, and in alternative embodiments, voltage sources V1-V4 (and perhaps one or more additional voltage sources) may be controlled to construct different electric fields in the relatively facing regions R1, R2 of one or more ion mirrors (whether provided as a single ion mirror structure or as separate ion mirror structures) at any particular moment or moments. For example, using Figure 2B In the arrangement shown in which an ion reflection electric field REF is constructed in R1 and R2, voltage sources V1-V4 (and any additional voltage sources) can alternatively be selectively controlled to maintain the ion reflection electric field REF in R1 while constructing the ion transmission electric field TEF in R2, or vice versa.

[0049] Reference now Figure 3, which shows a simplified flow chart of process 100. Process 100 is used to control voltage sources V1-V4 to selectively and sequentially control ion mirrors M1-M4 between the above-mentioned transmission and reflection modes of ion mirrors M1-M4, so as to cause ions entering the ELIT array 14 from the ion source 12 to be trapped in each of the three separated ELIT or ELIT regions E1-E3, so that each trapped ion repeatedly passes through a corresponding one of the charge detectors CD1-CD3 of a corresponding one of the three ELIT or ELIT regions E1-E3. At each charge detector CD1-CD3, each time a corresponding oscillating ion passes through it, the charge and oscillation period values ​​are measured and recorded, and then the ion charge, mass-to-charge ratio and mass value are determined based on the recorded data. In the illustrated embodiment, process 100 is illustratively stored in the memory 18 in the form of instructions, which, when executed by the processor 16, cause the processor 16 to perform the functions described. In alternative embodiments where one or more voltage sources V1-V4 may be programmed independently of processor 16, one or more aspects of process 100 may be performed in whole or in part by one or more such programmable voltage sources V1-V4. However, for purposes of this disclosure, process 100 will be described as being performed solely by processor 16. Figures 4A-4E , process 100 is described as operating on positively charged ions, but it should be understood that process 100 may alternatively operate on one or more negatively charged particles.

[0050] refer to Figure 4A , process 100 begins at step 102, wherein processor 16 is operable to control voltage sources V1-V4 to set voltage DC1-DC7 of each voltage source V1-V4 in such a manner that all ion mirrors M1-M4 operate in ion transmission mode, such that transmission electric fields TEF1, TEF2 constructed in corresponding regions R1, R2 of each operate to allow ions to pass therethrough while focusing the ions toward the longitudinal axis 24 so as to follow a narrow trajectory through the ELIT array 14. In an example embodiment, voltage sources V1-V4 are illustratively controlled at step 102 of process 100 to generate voltages DC1-DC7 according to an all-pass transmission mode as shown in Table 1 hereinabove. In any case, in the case where each voltage source V1-V4 is set at step 102 to control ion mirrors M1-M4 to operate in ion transmission mode, ions entering M1 from ion source 12 pass through all ion mirrors M1-M4 and all charge detectors CD1-CD3 and exit M4, as determined by Figure 4A As shown in the example ion trajectory 50 depicted in FIG. Figure 4AAs shown in FIG. 1 , the ion mirrors M1-M4 are controlled to their corresponding transmission modes so that one or more ions enter the ELIT array 14 from the ion source 12 and pass through the entire ELIT array 14. Figure 4A The ion trajectory 50 depicted in FIG. 5 may illustratively represent a single ion or a collection of ions.

[0051] After step 102, process 100 proceeds to step 104, wherein processor 16 is operable to pause and determine when to proceed to step 106. In one embodiment of step 102, ELIT array 14 is illustratively controlled in a "random capture mode". Therein, ion mirrors M1-M4 remain in their transmission mode for a selected time period, during which one or more ions generated by ion source 12 are expected to enter and travel through ELIT array 14. As a non-limiting example, the selected time period spent by processor 16 at step 104 before moving to step 106 when operating in random capture mode is on the order of 1-3 milliseconds (ms), depending on the axial length of ELIT array 14 and the speed of ions entering ELIT array 14. However, it should be understood that in other embodiments, such selected time periods may be greater than 3ms or less than 1ms. Before the selected time period has passed, process 100 follows the "no" branch of step 104 and then loops back to the beginning of step 104. After the selected time period has elapsed, process 100 follows the "yes" branch of step 104 and proceeds to step 106. In some alternative embodiments of step 104, such as in embodiments including a microchannel plate detector 22, processor 16 may be configured to proceed to step 106 only after detector 22 has detected one or more ions, with or without an additional delay period, thereby ensuring that the ions are moved through the ELIT array 14 prior to proceeding to step 106. In other alternative embodiments, the ELIT array 14 may illustratively be controlled by processor 16 in a "triggered capture mode," wherein ion mirrors M1-M4 are maintained in their ion transmission modes until ions are detected at charge detector CD3. Until such detection, process 100 follows the "no" branch of step 104 and then loops back to the beginning of step 104. Detection of ions by processor 16 at charge detector CD3 indicates that the ions are passing through charge detector CD3 toward ion mirror M4 and acts as a trigger event. This triggering event causes processor 16 to follow the “yes” branch of step 104 and proceed to step 106 of process 100 .

[0052] After the "yes" branch of step 104 and referring to Figure 4B, the processor 16 at step 106 is operable to control the voltage source V4 to set its output voltage DC1-DC7 in a manner that changes or switches the operation of the ion mirror M4 from an ion transmission mode of operation to an ion reflection mode of operation, in which an ion reflection electric field R41 is constructed within the region R1 of M4. As described above, the ion reflection electric field R41 operates to direct one or more ions entering the region R1 of M4 as described above with respect to Figure 2B The ground is reflected back toward ion mirror M3 (and through charge detector CD3). At step 106, the output voltages DC1-DC7 generated by voltage sources V1-V3, respectively, remain unchanged so that ion mirrors M1-M3 each remain in ion transmission mode. As a result, ions traveling toward ion mirror M4 in ELIT array 14 are reflected back to ion mirror M3 and will be focused toward axis 24 as the ions move toward the ion inlet of M3, as shown in FIG. Figure 4B The ion trajectory 50 is shown in FIG.

[0053] After step 106, process 100 proceeds to step 108. Therein, processor 16 is operable to pause and determine when to proceed to step 110. In an embodiment of step 108 in which the ELIT array 14 is controlled by processor 16 in a random capture mode, ion mirrors M1-M3 remain in their transmission mode for a selected time period at step 108. During this period, ions may enter the ELIT or ELIT region E3. As a non-limiting example, the selected time period spent by processor 16 at step 108 before moving to step 110 when operating in a random capture mode is on the order of 0.1 milliseconds (ms), but it should be understood that in other embodiments, such selected time periods may be greater than 0.1ms or less than 0.1ms. Before the selected time period has passed, process 100 follows the "no" branch of step 108 and then loops back to the beginning of step 108. After the selected time period has passed, process 100 follows the "yes" branch of step 108 and proceeds to step 110. In an alternative embodiment of step 108 in which the ELIT array 14 is controlled by the processor 16 in a triggered capture mode, the ion mirrors M1-M3 remain in their ion transmission mode until an ion is detected at the charge detector CD3. Until this detection, the process 100 follows the "no" branch of step 108 and then loops back to the beginning of step 108. The detection of the ion by the processor 16 at the charge detector CD3 ensures that the ion moves through the charge detector CD3 and acts as a triggering event. The triggering event causes the processor 16 to follow the "yes" branch of step 108 and proceed to step 110 of the process 100.

[0054] After the "yes" branch of step 108 and referring to Figure 4C, the processor 16 is operable at step 110 to control the voltage source V3 to set its output voltage DC1-DC7 in a manner that changes or switches the operation of the ion mirror M3 from an ion transmission operation mode to an ion reflection operation mode, in which an ion reflection electric field R31 is constructed in region R1 of M3, and an ion reflection electric field R32 is constructed in region R2 of M3. As a result, ions are trapped in the ELIT or ELIT region E3, and due to the reflection electric field R32 constructed in region R2 of the ion mirror M3 and R41 constructed in region R1 of the ion mirror M4, as shown in Figure 4C As shown in the ion trajectory 503 depicted in FIG, each time the trapped ion passes through the charge detection cylinder CD3, it oscillates between M3 and M4. Each time the ion passes through the charge detection cylinder CD3, it induces a charge on the cylinder CD3, which is detected by the charge preamplifier CP3 (see FIG. Figure 1 ). At step 112, as the ions oscillate back and forth between the ion mirrors M3, M4 and pass through the charge detection cylinder CD3, the processor 16 is operable to record the amplitude and timing of each such CD3 charge detection event and store it in the memory 18.

[0055] As described above, the ion reflection electric field R31 operates to reflect ions entering region R1 of M3 back toward ion mirror M2 (and through charge detector CD2), as described above with respect to Figure 2B At steps 110 and 112, the output voltages DC1-DC7 generated by the voltage sources V1-V2, respectively, remain unchanged, so that the ion mirrors M1-M2 are each maintained in the ion transmission mode. As a result, ions traveling toward the ion mirror M3 in the ELIT array 14 are reflected back to the ion mirror M2 and are focused toward the axis 24 as they move toward the ion inlet of M1, as shown in FIG. Figure 4C The ion trajectory shown in 50 1,2 shown.

[0056] After steps 110 and 112, process 100 proceeds to step 114. Therein, processor 16 is operable to pause and determine when to proceed to step 116. In an embodiment of step 114 in which the ELIT array 14 is controlled by processor 16 in a random capture mode, ion mirrors M1–M2 remain in their transmission mode for a selected time period at step 114. During this period, one or more ions may enter the ELIT or ELIT region E2. As a non-limiting example, the selected time period spent by processor 16 at step 114 before moving to step 116 when operating in a random capture mode is on the order of 0.1 milliseconds (ms), but it should be understood that in other embodiments, such selected time periods may be greater than 0.1ms or less than 0.1ms. Before the selected time period has passed, process 100 follows the "no" branch of step 114 and then loops back to the beginning of step 108. After the selected time period has passed, process 100 follows the "yes" branch of step 114 and proceeds to step 116. In an embodiment of step 114 in which the ELIT array 14 is controlled by the processor 16 in a triggered capture mode, the ion mirrors M1-M2 are maintained in their ion transmission mode until ions are detected at the charge detector CD2. Until this detection, the process 100 follows the "no" branch of step 114 and then loops back to the beginning of step 114. The detection of ions by the processor 16 at the charge detector CD2 ensures that the ions move through the charge detector CD2 and acts as a triggering event. The triggering event causes the processor 16 to follow the "yes" branch of step 114 and proceed to step 116 of the process 100.

[0057] As described above, the ion reflection electric field R21 operates to reflect ions entering region R1 of M2 back toward ion mirror M1 (and through charge detector CD1), as described above with respect to Figure 2B At steps 116 and 118, the output voltage DC1-DC7 generated by the voltage source V1 is unchanged, so that the ion mirror M1 remains in the ion transmission mode. As a result, ions traveling toward the ion mirror M2 in the ELIT array 14 are reflected back to the ion mirror M1 and are focused toward the axis 24 as the ions move toward the ion inlet of M1, as shown in FIG. Figure 4D The ion trajectory 501 is shown in FIG.

[0058] Following the "yes" branch of step 114, and as ions in the ELIT or ELIT region E3 continue to oscillate back and forth between ion mirrors M3 and M4 through charge detection cylinder CD3, process 100 proceeds to step 116. Figure 4D, the processor 16 is operable at step 116 to control the voltage source V2 to set its output voltage DC1-DC7 in a manner that changes or switches the operation of the ion mirror M2 from an ion transmission operation mode to an ion reflection operation mode, in which an ion reflection electric field R21 is constructed in region R1 of M2, and an ion reflection electric field R22 is constructed in region R2 of M2. As a result, ions are trapped in the ELIT or ELIT region E2, and due to the reflection electric field R22 constructed in region R2 of the ion mirror M2 and the reflection electric field R31 constructed in region R1 of the ion mirror M3, as shown in Figure 4D As shown in the ion trajectory 502 depicted in FIG, the trapped ion oscillates between M2 and M3 each time it passes through the charge detection cylinder CD2. Each time the ion passes through the charge detection cylinder CD2, it induces a charge on the cylinder CD2, which is detected by the charge preamplifier CP2 (see FIG. Figure 1 ). At step 118, as the ion oscillates back and forth between the ion mirrors M2, M3 and through the charge detection cylinder CD2, the processor 16 is operable to record the amplitude and timing of each such CD2 charge detection event and store it in the memory 18. Thus, after step 116, an ion oscillates back and forth between the ion mirrors M3 and M4 through the charge detection cylinder CD3 of the ELIT or ELIT region E3, and, at the same time, another ion oscillates back and forth between the ion mirrors M2 and M3 through the charge detection cylinder CD2 of the ELIT or ELIT region E2.

[0059] After steps 116 and 118, process 100 proceeds to step 120. Therein, processor 16 is operable to pause and determine when to proceed to step 122. In an embodiment of step 120 in which the ELIT array 14 is controlled by processor 16 in a random capture mode, ion mirror M1 remains operating in its transmission mode at step 120 for a selected time period, during which one or more ions may enter the ELIT or ELIT region E1. As a non-limiting example, the selected time period spent by processor 16 at step 120 before moving to step 122 when operating in a random capture mode is on the order of 0.1 milliseconds (ms), but it should be understood that in other embodiments, such selected time periods may be greater than 0.1ms or less than 0.1ms. Before the selected time period has passed, process 100 follows the "no" branch of step 120 and then loops back to the beginning of step 120. After the selected time period has passed, process 100 follows the "yes" branch of step 120 and proceeds to step 122. In an embodiment of step 120 in which the ELIT array 14 is controlled by the processor 16 in a triggered capture mode, the ion mirror M1 is maintained in its ion transmission mode of operation until an ion is detected at the charge detector CD1. Until such detection, the process 100 follows the "no" branch of step 120 and then loops back to the beginning of step 120. The detection of the ion by the processor 16 at the charge detector CD1 ensures that the ion moves through the charge detector CD1 and acts as a trigger event that causes the processor 16 to follow the "yes" branch of step 120 and proceed to step 122 of the process 100.

[0060] After the "yes" branch of step 120, and while the ion in the ELIT or ELIT region E3 continues to oscillate back and forth between ion mirrors M3 and M4 through charge detection cylinder CD3, and while another ion in the ELIT or ELIT region E2 simultaneously continues to oscillate back and forth between ion mirrors M2 and M3 through charge detection cylinder CD2, process 100 proceeds to step 122. Figure 4E , the processor 16 is operable at step 122 to control the voltage source V1 to set its output voltage DC1-DC7 in a manner that changes or switches the operation of the ion mirror M1 from an ion transmission operation mode to an ion reflection operation mode, in which an ion reflection electric field R11 is constructed in region R1 of M1, and an ion reflection electric field R12 is constructed in region R1 of M1. As a result, ions are trapped in the ELIT or ELIT region E1, and due to the reflection electric field R12 constructed in region R2 of the ion mirror M1 and the particle reflection field R21 constructed in region R2 of the ion mirror M2, respectively, as in Figure 4EAs shown in the ion trajectory 501 depicted in FIG, each time the trapped ion passes through the charge detection cylinder CD1, it oscillates between M1 and M2. Each time the ion passes through the charge detection cylinder CD1, it induces a charge on the cylinder CD1, which is detected by the charge preamplifier CP1 (see FIG. Figure 1 ). At step 124, as the ion oscillates back and forth between the ion mirrors M1, M2 and through the charge detection cylinder CD1, the processor 16 is operable to record the amplitude and timing of each such CD1 charge detection event and store it in the memory 18. Therefore, after step 122, the ion passes through the charge detection cylinder CD3 of the ELIT or ELIT region E3 and oscillates back and forth between the ion mirrors M3 and M4, and, at the same time, another ion passes through the charge detection cylinder CD2 of the ELIT or ELIT region E2 and oscillates back and forth between the ion mirrors M2 and M3, and at the same time, another ion also passes through the charge detection cylinder CD1 of the ELIT or ELIT region E1 and oscillates back and forth between the ion mirrors M1 and M2.

[0061] After steps 122 and 124, process 100 proceeds to step 126, where processor 16 is operable to pause and determine when to proceed to step 128. In one embodiment, processor 16 is configured, i.e., programmed, to allow ions to oscillate back and forth while passing through each of the ELIT or ELIT regions E1-E3 within a selected time period, i.e., the total ion cycle measurement time, during which processor 16 records ion detection events, i.e., ion detection events detected by each of charge detectors CD1-CD3. As a non-limiting example, the selected time period spent by processor 16 at step 126 before moving to step 128 is on the order of 100-300 milliseconds (ms), but it should be understood that in other embodiments, such selected time periods may be greater than 300ms or less than 100ms. Before the selected time period has passed, process 100 follows the "no" branch of step 126 and loops back to the beginning of step 126. After the selected time period has elapsed, process 100 follows the "yes" branch of step 126 and proceeds to steps 128 and 140. In some alternative embodiments of process 100, at step 126, voltage sources V1-V4 may illustratively be controlled by processor 16 to allow ions to oscillate back and forth through charge detectors CD1-CD3 a selected number of times, i.e., a total number of measurement cycles, during which processor 16 records ion detection events (i.e., detected by each of charge detectors CD1-CD3). Before the processor counts a selected number of ion detection events for one or more charge detectors CD1-CD3, process 100 follows the "no" branch of step 126 and then loops back to the beginning of step 126. Processor 16 detects the selected number of ion detection events as a trigger event, which causes processor 16 to follow the "yes" branch of step 126 and proceed to steps 128 and 140 of process 100.

[0062] Following the "yes" branch of step 126, processor 16 at step 128 is operable to control voltage sources V1-V4 to set each output voltage DC1-DC7 in a manner that changes or switches the operation of all ion mirrors M1-M4 from an ion reflection mode of operation to an ion transmission mode of operation, in which ion mirrors M1-M4 each operate to allow ions to pass therethrough. Illustratively, at step 128 of process 100, voltage sources V1-V4 are illustratively controlled to generate voltages DC1-DC7 according to an all-through transmission mode as shown in Table I above. This is reconstructed in Figure 4A, in which: (i) all ions within the ELIT array 14 are focused toward the axis 24 by the ion transmission electric field TEF1, TEF2 constructed in each of the ion mirrors M1-M4, so that the ions move through the ELIT array 14 and out of the ELIT array 14, and (ii) all ions entering M1 from the ion source 12 pass through all ion mirrors M1-M4 and all charge detectors CD1-CD3.

[0063] After step 128, the processor 16 is operable to pause a selected time period at step 130 to allow ions contained in the ELIT array 14 to travel out of the ELIT array 14. As a non-limiting example, the selected time period spent by the processor 12 at step 130 is on the order of 1-3 milliseconds (ms) before looping back to step 102 to restart the process 100. However, it should be understood that in other embodiments, such selected time periods may be greater than 3ms or less than 1ms. Before the selected time period has passed, the process 100 follows the "no" branch of step 130 and then loops back to the beginning of step 130. After the selected time period has passed, the process 100 follows the "yes" branch of step 130 and loops back to step 102 to restart the process 100.

[0064] Also after the "yes" branch of step 126, process 100 additionally proceeds to step 140 to analyze the data collected during steps 112, 118, and 124 of process 100 just described. In the illustrated embodiment, data analysis step 140 illustratively includes step 142, in which processor 16 is operable to calculate the Fourier transform of the recorded set of stored charge detection signals provided by each of charge preamplifiers CP1-CP3. Processor 16 is illustratively operable to perform step 142 using any conventional digital Fourier transform (DFT) technique, such as, but not limited to, a conventional fast Fourier transform (FFT) algorithm. In any case, the processor 16 can be operated at step 142 to calculate three Fourier transforms FT1, FT2 and FT3, wherein FT1 is the Fourier transform of a recorded set of charge detection signals provided by the first charge preamplifier CP1 and therefore corresponds to a charge detection event detected by the charge detection cylinder CD1 of the ELIT or ELIT region E1, FT2 is the Fourier transform of a recorded set of charge detection signals provided by the first charge preamplifier CP2 and therefore corresponds to a charge detection event detected by the charge detection cylinder CD2 of the ELIT or ELIT region E2, and FT3 is the Fourier transform of a recorded set of charge detection signals provided by the first charge preamplifier CP3 and therefore corresponds to a charge detection event detected by the charge detection cylinder CD3 of the ELIT or ELIT region E3.

[0065] After step 142, process 100 proceeds to step 144. In step 144, processor 16 is operable to calculate three sets of ion mass-to-charge values ​​(m / z1, m / z2, and m / z3), ion charge values ​​(z1, z2, and z3), and ion mass values ​​(m1, m2, and m3), each set based on a corresponding one of the calculated Fourier transform values ​​(FT1, FT2, FT3). Thereafter, in step 146, processor 16 is operable to store the calculated results in memory 18 and / or control one or more peripheral devices 20 to display the results for viewing and / or further analysis.

[0066] It is generally understood that the mass-to-charge ratio (m / z) of an ion oscillating back and forth between oppositely facing ion mirrors of an ELIT or any of the ELIT regions E1-E3 is inversely proportional to the square of the fundamental frequency ff of the oscillating ions according to the following equation: m / z = C / ff 2, where C is a constant that is a function of the ion energy and of the size of the corresponding ELIT or ELIT region, and the fundamental frequency ff is determined directly from the corresponding calculated Fourier transform. Thus, ff1 is the fundamental frequency of FT1, ff2 is the fundamental frequency of FT2, and ff3 is the fundamental frequency of FT3. Typically, C is determined using conventional ion trajectory simulations. In any case, the value of the ion charge z is proportional to the amplitude FT of the fundamental frequency of the corresponding Fourier transform FT, taking into account the number of ion oscillation periods. MAG In some cases, to determine the ion charge value, the amplitude of one or more harmonic frequencies of the FFT may be added to the amplitude of the fundamental frequency. In any case, the ion mass m is then calculated as the product of m / z and z. Thus, for a recorded set of charge detection signals provided by the first charge preamplifier CP1, the processor 16 at step 144 is operable to calculate m / z1=C / ff1 2 , z1=F(FT MAG1 ) and m1 = (m / z1)(z1). For a recorded set of charge detection signals provided by the second charge preamplifier CP2, the processor 16 is similarly operable at step 144 to calculate m / z2 = C / ff2 2 , z2=F(FT MAG2 ) and m2=(m / z2)(z2), and for a recorded set of charge detection signals provided by the third charge preamplifier CP3, the processor 16 is similarly operable at step 144 to calculate m / z3=C / ff3 2 , z3=F(FT MAG3 ) and m3 = (m / z3)(z3).

[0067] Reference now Figure 5A , shows a simplified block diagram of an embodiment of an ion separation instrument 60, which may include any of the ELIT arrays 14, 205, 302 shown and described herein, and which may include any of the charge detection mass spectrometers (CDMS) 10, 200, 300 shown and described herein, and which may include any number of ion processing instruments that may form part of the ion source 12 upstream of the ELIT array, and / or which may include any number of ion processing instruments that may be disposed downstream of the ELIT array to further process ions leaving the ELIT array. In this regard, the ion source 12 may be disposed downstream of the ELIT array to further process ions leaving the ELIT array. Figure 5A is shown as including a number Q of ion source stages IS1-IS Q , which may be or form part of the ion source 12. Alternatively or additionally, the ion processing instrument 70 may be Figure 5A1 and 2 are shown as being coupled to the ion outlet of the ELIT array 14, 205, 302, wherein the ion processing instrument 70 may include any number of ion processing stages OS1-OS R , where R can be any positive integer.

[0068] Focusing on the ion source 12, it should be understood that the source 12 of ions entering the ELIT 10 can be or include ion source stages IS1-IS2. Q ion source 12 may include any conventional ion source as described above in the form of one or more of the conventional ion sources described above, and may also include one or more conventional instruments for separating ions according to one or more molecular properties (e.g., according to ion mass, ion mass-to-charge ratio, ion mobility, ion retention time, etc.) and / or one or more conventional ion processing instruments for collecting and / or storing ions (e.g., one or more quadrupoles, hexapole and / or other ion traps), one or more conventional ion processing instruments for filtering ions (e.g., according to one or more molecular properties, such as ion mass, ion mass-to-charge ratio, ion mobility, ion retention time, etc.), one or more conventional ion processing instruments for fragmenting or otherwise dissociating ions, one or more conventional ion processing instruments for normalizing ion charge states, etc. It should be understood that ion source 12 may include any of such conventional ion sources, ion separation instruments and / or ion processing instruments in any order or any combination thereof, and some embodiments may include multiple adjacent or spaced-apart any of such conventional ion sources, ion separation instruments and / or ion processing instruments.

[0069] Turning now to the ion processing instrument 70, it will be appreciated that the instrument 70 may be or include one or more ion processing stages OS1-OS2. R in the form of: one or more conventional instruments for separating ions according to one or more molecular properties (e.g., according to ion mass, ion mass-to-charge ratio, ion mobility, ion retention time, etc.); and / or one or more conventional ion processing instruments for collecting and / or storing ions (e.g., one or more quadrupoles, hexapole and / or other ion traps), for filtering ions (e.g., according to one or more molecular properties such as ion mass, ion mass-to-charge ratio, ion mobility, ion retention time, etc.), for fragmenting or otherwise dissociating ions, for normalizing ion charge state, etc. It should be understood that the ion processing instrument 70 may include any one or any combination of any such conventional ion separation instruments and / or ion processing instruments in any order, and some embodiments may include multiple adjacent or spaced-apart any such conventional ion separation instruments and / or ion processing instruments. In any embodiment including one or more mass spectrometers, any one or more of such mass spectrometers may be used as described above with respect to Figure 1 described in any form.

[0070] As Figure 5A A specific embodiment of the ion separation instrument 60 shown in (which should not be considered limiting in any way) ion source 12 illustratively includes 3 stages, and ion processing instrument 70 is omitted. In this example embodiment, ion source stage IS1 is a conventional ion source, such as electrospray, MALDI, etc., ion source stage IS2 is a conventional mass filter, such as a quadrupole or hexapole ion guide operating as a high-pass or bandpass filter, and ion source stage IS3 is a mass spectrometer of any type described above. In this embodiment, ion source stage IS2 is controlled in a conventional manner to preselect ions with desired molecular characteristics for analysis by a downstream mass spectrometer, and is used to deliver only such preselected ions to the mass spectrometer, wherein the ions analyzed by the ELIT array 14, 205, 302 will be preselected ions separated by the mass spectrometer according to mass-to-charge ratio. The preselected ions leaving the ion filter may be, for example, ions having a specific ion mass or mass-to-charge ratio, ions having an ion mass or ion mass-to-charge ratio above and / or below a specific ion mass or ion mass-to-charge ratio, ions having an ion mass or ion mass-to-charge ratio within a specific ion mass or ion mass-to-charge ratio range, etc. In some alternative embodiments of this example, the ion source stage IS2 may be a mass spectrometer, and the ion source stage IS3 may be an ion filter, and the ion filter may be otherwise operated as just described to preselect ions leaving the mass spectrometer that have desired molecular properties for analysis by the downstream ELIT array 14, 205, 302. In other alternative embodiments of this example, the ion source stage IS2 may be an ion filter, and the ion source stage IS3 may include a mass spectrometer followed by another ion filter, wherein each ion filter operates as described above.

[0071] As Figure 5A In another specific embodiment of the ion separation instrument 60 shown in FIG. 1 , (which should not be considered limiting in any way), the ion source 12 illustratively includes 2 stages, and the ion processing instrument 70 is omitted. In this example embodiment, the ion source stage IS1 is a conventional ion source, such as electrospray, MALDI, etc., and the ion source stage IS2 is a conventional mass spectrometer of any type described above. This is the above description of Figure 1 A CDMS embodiment is described in which the ELIT array 14, 205, 302 is operable to analyze ions exiting the mass spectrometer.

[0072] As Figure 5AIn another specific embodiment of the ion separation instrument 60 shown in (which should not be considered as limiting in any way), the ion source 12 illustratively includes 2 stages, and the ion processing instrument 70 is omitted. In this example embodiment, the ion source stage IS1 is a conventional ion source, such as electrospray, MALDI, etc., and the ion processing stage OS2 is a conventional single-stage or multi-stage ion mobility spectrometer. In this embodiment, the ion mobility spectrometer is operable to separate ions generated by the ion source stage IS1 over time according to one or more functions of ion mobility, and the ELIT array 14, 205, 302 is operable to analyze ions leaving the ion mobility spectrometer. In an alternative embodiment of this example, the ion source 12 may include only a single-stage IS1 in the form of a conventional ion source, and the ion processing instrument 70 may include a conventional single-stage or multi-stage ion mobility spectrometer as a single-stage OS1 (or as an OS1 of a multi-stage instrument 70). In this alternative embodiment, the ELIT array 14, 205, 302 is operable to analyze ions generated by the ion source stage IS1, and the ion mobility spectrometer OS1 is operable to separate ions leaving the ELIT array 14, 205, 302 over time according to one or more equations of ion mobility. As another alternative embodiment of this example, a single-stage or multi-stage ion mobility spectrometer may be after the ion source stage IS1 and the ELIT array 14, 205, 302. In this alternative embodiment, the ion mobility spectrometer after the ion source stage IS1 is operable to separate ions generated by the ion source stage IS1 over time according to one or more functions of ion mobility, the ELIT array 14, 205, 302 is operable to analyze ions leaving the ion source stage ion mobility spectrometer, and the ion mobility spectrometer of the ion processing stage OS1 after the ELIT array 14, 205, 302 is operable to separate ions leaving the ELIT array 14, 205, 302 over time according to one or more equations of ion mobility. In any implementation of the embodiments described in this paragraph, additional variations may include a mass spectrometer operably positioned upstream and / or downstream of the ion source 12 and / or a single-stage or multi-stage ion mobility spectrometer in the ion manipulation instrument 210 .

[0073] As Figure 5AIn another specific embodiment of the ion separation instrument 60 shown in (which should not be considered as limiting in any way), the ion source 12 illustratively includes 2 stages, and the ion processing instrument 70 is omitted. In this example embodiment, the ion source stage IS1 is a conventional liquid chromatograph, such as HPLC, etc., which is configured to separate molecules in a solution according to molecular retention time, and the ion source stage IS2 is a conventional ion source, such as electrospray, etc. In this embodiment, the liquid chromatograph is operable to separate molecular components in a solution, the ion source stage IS2 is operable to generate ions from a solution flow leaving the liquid chromatograph, and the ELIT array 14, 205, 302 is operable to analyze the ions generated by the ion source stage IS2. In an alternative embodiment of this example, the ion source stage IS1 can alternatively be a conventional size exclusion chromatograph (SEC), which is operable to separate molecules in a solution according to size. In another alternative embodiment, the ion source stage IS1 can include a conventional liquid chromatograph after a conventional SEC, and vice versa. In this embodiment, ions are generated by ion source stage IS2 from a twice separated solution, one separation based on molecular retention time followed by a second separation based on molecular size, or vice versa. In any of the embodiments described in this paragraph, additional variations may include a mass spectrometer operably positioned between ion source stage IS2 and ELIT 14, 205, 302.

[0074] Reference now Figure 5B, a simplified block diagram of another embodiment of an ion separation instrument 80 is shown, which illustratively includes a multi-stage mass spectrometer 82, and also includes any CDMS instrument 10, 200, 300 shown and described herein implemented as a high ion mass analysis component. In the illustrated embodiment, the multi-stage mass spectrometer 82 includes an ion source (IS) 12 as shown and described herein, the ion source (IS) 12 is followed by a first conventional mass spectrometer (MSI) 84, and the ion source (IS) 12 is coupled to the first conventional mass spectrometer (MS1) 84, the first conventional mass spectrometer (MSI) 84 is followed by a conventional ion dissociation stage (ID) 86, and the first conventional mass spectrometer (MSI) 84 is coupled to the conventional ion dissociation stage (ID) 86, which is operable to, for example, pass The ions leaving the mass spectrometer 84 are dissociated by one or more of collision induced dissociation (CID), surface induced dissociation (SID), electron capture dissociation (ECD) and / or photoinduced dissociation (PID), and the conventional ion dissociation stage (ID) 86 is followed by a second conventional mass spectrometer (MS2) 88, and the conventional ion dissociation stage (ID) 86 is coupled to the second conventional mass spectrometer (MS2) 88, followed by a conventional ion detector (D) 90, such as a microchannel plate detector or other conventional ion detector. The CDMS 10, 200, 300 is coupled in parallel with the ion dissociation stage 86 and coupled to the ion dissociation stage 86, so that the CDMS 10, 200, 300 can selectively receive ions from the mass spectrometer 84 and / or from the ion dissociation stage 86.

[0075] For example, MS / MS using only an ion separation instrument 82 is a well-established method, wherein precursor ions with a specific molecular weight are selected by a first mass spectrometer 84 (MS1) based on their m / z values. In the ion dissociation stage 86, the mass-selected precursor ions are fragmented, for example, by collision-induced dissociation, surface-induced dissociation, electron capture dissociation, or photoinduced dissociation. The fragment ions are then analyzed by a second mass spectrometer 86 (MS2). In both MS1 and MS2, only the m / z values ​​of the precursor ions and the fragment ions are measured. For high-quality ions, the charge state cannot be resolved, and therefore the precursor ions with a specific molecular weight cannot be selected based only on the m / z value. However, by coupling the instrument 82 to the CDMS10, 200, 300 shown and described herein, it is possible to select a narrow range of m / z values, and then use CDMS10, 200, 300 to determine the mass of the precursor ions selected by m / z. The mass spectrometers 84, 88 can be, for example, one or any combination of a sector magnetic field mass spectrometer, a time-of-flight mass spectrometer, or a quadrupole mass spectrometer, but in alternative embodiments, other mass spectrometer types can be used. In any case, the precursor ions selected by m / z with known mass leaving MS1 can be segmented on the ion dissociation stage 86, and the resulting fragment ions can be analyzed by MS2 (wherein only the m / z ratio is measured) and / or by CDMS instruments 10, 200, 300 (wherein, the m / z ratio and charge are measured simultaneously). Low-quality fragments, i.e., the dissociated ions of precursor ions having mass values ​​below a threshold mass value (e.g., 10,000Da or other mass values), can therefore be analyzed by conventional MS using MS2, while high-quality fragments (wherein the charge state is not resolved), i.e., the dissociated ions of precursor ions having mass values ​​equal to or higher than the threshold mass value, can be analyzed by CDMS10, 200, 300.

[0076] Reference now Figure 6 , shows another CDMS 200, which includes yet another embodiment of an electrostatic linear ion trap (ELIT) array 205, which has control and measurement elements coupled thereto. In the illustrated embodiment, the ELIT array 205 includes three separate ELITs 202, 204, 206, each with Figure 1 For example, the ELIT 202 includes a charge detection cylinder CD1 surrounded by a grounded chamber GC1, wherein one end of the grounded chamber GC1 defines one of the mirror electrodes of an ion mirror M1, and the opposite end of the grounded chamber GC1 defines one of the mirror electrodes of another ion mirror M2, and wherein the ion mirrors M1, M2 are arranged at opposite ends of the charge detection cylinder 202. The ion mirror M1 is illustratively structurally and functionally similar to the charge detection cylinder CD1. Figures 1 to 2BEach of the ion mirrors M1-M3 shown is identical. And ion mirror M2 is illustratively structurally and functionally identical to Figures 1 to 2B The ion mirror M4 shown is identical in structure and function to that in Figures 1 to 2B The voltage source V1 shown in FIG is illustratively the same voltage source V1 as that shown in FIG. 1 and is operably coupled to the ion mirror M1 and is structurally and functionally identical to that shown in FIG. Figures 1 to 2B Another voltage source V2 illustratively identical to the voltage source V4 shown in FIG is operably coupled to the ion mirror M2. The ion mirror M1 defines an ion entrance aperture AI1 which is structurally and functionally identical to the ion mirror M2. Figure 2A The aperture A1 of the ion mirror MX shown is illustratively identical, and the ion mirror M2 defines an exit aperture AO1 which is structurally and operationally identical to that described with respect to FIG. Figure 1 and Figure 2B The apertures CA of the described ion mirrors M4 are illustratively identical. A longitudinal axis 241 extends centrally through the ELIT 202 and illustratively bisects the apertures AI1 and AO1. The charge preamplifier CP1 is electrically coupled to the charge detection cylinder CD1 and is structurally and functionally identical to the apertures CA of the described ion mirrors M4. Figure 1 The charge preamplifier CP1 shown and described above is illustratively identical.

[0077] ELIT 204 is illustratively identical to ELIT 202 just described, wherein ion mirrors M3, M4 correspond to ion mirrors M1, M2 of ELIT 202, wherein voltage sources V3, V4 correspond to voltage sources V1, V2 of ELIT 202, and wherein inlet / exit apertures AI2 / AO2 define a longitudinal axis 242 extending through ELIT 204 and illustratively bisecting apertures AI2, AO2. Charge amplifier CP2 is electrically coupled to charge detection cylinder CD2 of ELIT 204 and is structurally and functionally identical to that of ELIT 202. Figure 1 The same as the charge preamplifier CP2 shown in and described above.

[0078] ELIT 206 is similarly illustratively identical to ELIT 202 just described. Wherein ion mirrors M5, M6 correspond to ion mirrors M1, M2 of ELIT 202, wherein voltage sources V5, V6 correspond to voltage sources V1, V2 of ELIT 202, and where inlet / exit apertures AI3 / AO3 define a longitudinal axis 243 extending through ELIT 206 and illustratively bisecting apertures AI3, AO3. Charge amplifier CP3 is electrically coupled to charge detection cylinder CD3 of ELIT 206 and is structurally and functionally identical to that of ELIT 202. Figure 1 The charge preamplifier CP3 shown in and described above is illustratively the same.

[0079] Voltage sources V1-V6 and charge preamplifiers CP1-CP3 are operatively coupled to a processor 210, which includes a processor 210 as described above. Figure 1 A memory 212 is described, wherein the memory 212 illustratively has instructions stored therein that, when executed by the processor 210, cause the processor 210 to control the operation of the voltage sources V1-V6 to control the ion mirrors M1-M6 between the ion transmission and ion reflection operating modes as described above. Alternatively, one or more of the voltage sources V1-V6 may be programmed to operate as described above. In any case, the instructions stored in the memory 212 also illustratively include instructions that, when executed by the processor 210, cause the processor to receive, process and record (store) charge signals detected by the charge preamplifiers CP1-CP3, and process the recorded charge signal information to calculate the mass of ions trapped within each ELIT 202, 204, 206 as described above. Illustratively, the processor 210 is coupled to one or more peripheral devices 214, which may be connected to the peripheral devices 214 described above. Figure 1 The one or more peripheral devices 20 described are identical.

[0080] exist Figure 6 In the embodiment shown in FIG. 1 , an embodiment of an ion manipulation array 208 is shown as being operatively coupled between the ion source 12 and the ion inlet apertures AI1 - AI3 of each ELIT 202, 204, 206 in the ELIT array 205. The ion source 12 is illustratively shown as being operatively coupled to the ion source 12 and the ion inlet apertures AI1 - AI3 of each ELIT 202, 204, 206 in the ELIT array 205. Figure 1 and / or Figure 5A The ion manipulation voltage source V is configured to generate ions and supply ions to the ion manipulation array 208 via the ion aperture IA. ST The processor 210 is operatively coupled to and between the processor 210 and the ion manipulation array 208. As will be described in detail below, the processor 210 is illustratively configured (ie, programmed) to control the ion manipulation voltage source V ST, thereby causing the ion manipulation array 208 to selectively manipulate and direct ions exiting the ion aperture IA of the ion source 12 to enter the ELITs 202, 204, and 206 via their corresponding entrance apertures AI1-AI3. The processor 210 is further illustratively configured (i.e., programmed) to control voltage sources V1-V6 for causing the ion mirrors M1-M6 of the ELITs 202, 204, 206 to selectively switch between ion transmission mode and ion reflection mode to trap ions in each ELIT 202, 204, 206, and then causing such ions to oscillate back and forth between the corresponding ion mirrors M1 / M2, M3 / M4, and M5 / M6 and through the corresponding charge detection cylinders CD1-CD3 of the ELITs 202, 204, 206 so as to measure and record ion charge detection events detected by the corresponding charge preamplifiers CP1-CP3 as described above.

[0081] Although ELIT 202, 204 and 206 are Figure 6 241-243 are shown as being arranged so that their corresponding longitudinal axes 241-243 are parallel to each other, but it will be appreciated that this arrangement is provided by way of example only and that other arrangements may be contemplated. In alternative embodiments, for example, the longitudinal axis of one or more ELITs may not be parallel to the longitudinal axis of one or another of the ELITs, and / or two or more longitudinal axes (but not all) of the ELITs may be coaxial. For purposes of implementing ion manipulation array 208, it is sufficient that the longitudinal axis of at least one of the ELITs is not coaxial with the longitudinal axis of one or more of the remaining ELITs.

[0082] In the illustrated embodiment, the ion manipulation array 208 illustratively includes three groups of four conductive pads P1-P4, P5-P8, and P9-P12 arranged on each of two spaced apart planar substrates such that each of the conductive pads P1-P12 on one planar substrate is aligned with and faces a corresponding one of the conductive pads on the other substrate. Figure 6 In the embodiment shown in FIG. 2 , only one substrate 220 is shown.

[0083] Reference now Figures 7A to 7C , which shows a portion of the ion manipulation array 208, which shows the control and operation of the ion manipulation array 208 to selectively manipulate ions to desired locations. Figure 7B and Figure 7CAs shown in the example in FIG. 1 , voltage sources DC1-DC4 of the illustrated portion of ion manipulation 208 are controlled to cause ions exiting ion aperture IA of ion source 12 in the direction indicated by arrow A to change their direction by approximately 90 degrees so as to be directed along a path that is aligned, i.e., co-linear, with ion entrance aperture AI1 of ELIT 202. Although not shown in the drawings, any number of conventional flat ion blankets and / or other conventional ion focusing structures may be used to focus the ion trajectories exiting ion aperture IA of the ion source and / or to align the ion trajectories selectively varied by ion manipulation array 208 with ion entrance apertures AI1-AI3 of corresponding ELITs 202, 204, 206.

[0084] Specific reference Fig. 7A , a pattern of four substantially identical and spaced apart conductive pads P11-P41 is formed on an inner major surface 220A of one substrate 220, the substrate 220 having an opposing outer major surface 220B, and an identical pattern of four substantially identical and spaced apart conductive pads P12-P42 is formed on an inner major surface 222A of another substrate 222, the other substrate 222 having an opposing outer surface 222B. The inner surfaces 220A, 222A of the substrates 220, 222 are spaced apart in a substantially parallel relationship, and the conductive pads P11-P41 are juxtaposed above a corresponding one of the conductive pads P12-P42. The spaced apart inner major surfaces 220A and 222A of the substrates 220, 222 are illustratively defined with a distance D therebetween. P In one embodiment, the width D of the channel 225 is P is about 5 cm, but in other embodiments, the distance D P It may be greater or less than 5 centimeters. In any case, substrates 220, 222 together comprise the portion of ion manipulation array 208 shown.

[0085] Opposing pad pairs P31, P32 and P41, P42 are upstream of opposing pad pairs P11, P12 and P21, P22, and, conversely, opposing pad pairs P11, P12 and P21, P22 are downstream of opposing pad pairs P41, P42 and P31, P32. In this regard, the "unchanged ion travel direction" through channel 225 is "upstream" as that term is used herein, and is generally parallel to the direction A of ions leaving ion source 12. The lateral edges 220C, 222C of substrates 220, 222 are aligned, as are the opposing lateral edges 220D, 222D. And as that term is used herein, the "changing direction of ion travel" through the channel 225 is from the aligned edges 220C, 222C towards the aligned edges 220D, 222D, and is generally perpendicular to these aligned edges 220C, 222C and 220D, 222D.

[0086] exist Figure 6 In the embodiment shown in FIG. 1 , the ion manipulation voltage source V ST Illustratively configured to generate at least 12 switchable DC voltages, each DC voltage operably connected to a corresponding opposing pair of conductive pads P1-P12. Fig. 7A 12 DC voltages are shown in FIG. 1 . A first DC voltage DC1 is electrically connected to each of the juxtaposed conductive pads P11, P12, a second DC voltage DC2 is electrically connected to each of the juxtaposed conductive pads P21, P22, a third DC voltage DC3 is electrically connected to each of the juxtaposed conductive pads P31, P32, and a fourth DC voltage DC4 is electrically connected to each of the juxtaposed conductive pads P41, P42. In the illustrated embodiment, each of the DC voltages DC1-DC12 is electrically connected to each of the juxtaposed conductive pads P11, P12, for example, via the processor 210 and / or via a voltage source V ST , but in alternative embodiments, two or more of the DC voltages DC1-DC12 may be controlled together as a group. In any case, it should be understood that although the voltages DC1-DC12 are shown and disclosed as DC voltages, the present disclosure contemplates other embodiments in which the voltage source V ST Alternatively or additionally configured to generate any number of AV voltages (such as, for example, one or more RF voltages), and to supply any one or more of such AC voltages to a corresponding one or corresponding pairs of conductive pads in embodiments including them, and / or to one or more ion blankets or other ion focusing structures.

[0087] Reference now Figure 7B and Figure 7C , will use Fig. 7A and Figure 7BThe four opposing pairs of conductive pads P11 / P12, P21 / P22, P31 / P32, and P41 / P42 in FIG. 1 are described as illustrative examples. Figure 6 The operation of the ion manipulation channel array 208 is shown in FIG. Figure 6 The four conductive pads P5-P8 and the four conductive pads P9-P12 shown on the substrate 220 in FIG. 1 also each include pairs of conductive pads that are opposite, aligned, and juxtaposed and disposed on the inner surfaces 220A, 222A of the corresponding substrates 220, 222. Moreover, each of the four opposite pairs of conductive pads can be connected to the substrate 220 by a voltage source V ST The corresponding switchable DC (and / or AC) voltages DC5-DC12 generated are controlled. In any case, for clarity of explanation, Figure 7B and 7C The DC voltages DC1-DC4 are omitted in the figure, but are shown in the figure as the voltage source V ST The DC voltages DC1-DC4 are generated and applied to the connected pairs of conductive pads P11 / P12, P21 / P22, P31 / P32, and P41 / P42. Figure 7B , the illustrated portion of the ion manipulation array 208 is shown in a state in which the reference potential V 参考 is applied to each of the conductive pad pairs P11 / P12, P21 / P22 and is less than V 参考 A potential of –XV is applied to each of the conductive pad pairs P31 / P32 and P41 / P42. Illustratively, V 参考 can be any positive or negative voltage, or can be zero volts, for example, ground potential, while -XV can be less than V 参考 Any voltage, positive voltage, negative voltage or zero voltage, is applied to the substrate 220, so as to construct an electric field E1 which is parallel to the sides 220C / 222C and 220D / 222D of the substrates 220, 222 and which extends along the unchanged ion travel direction, i.e., as in Figure 7B As depicted in FIG. 1 , from the downstream conductive pad pairs P11 / P12, P21 / P22 toward the upstream conductive pad pairs P31 / P32 and P41 / P42. Figure 7B , ions A leaving the ion source 12 via the ion aperture IA enter the channel 225 between the downstream conductive pad pairs P11 / P12, P21 / P22 and are manipulated or directed (or guided) by the electric field E1 along an unchanged ion travel direction 230, which is in the same direction as the electric field E1 and is aligned (i.e., co-linear) with the ion aperture IA of the ion source 12. Such ions A are directed along the channel 225 as in Figure 7BThe unchanged direction of travel shown in illustratively directs through channel 225 .

[0088] Now specific reference Figure 7C , when it is desired to change the direction of ion A from Figure 7B When the unchanged ion traveling direction shown in FIG. 1 is changed into the changed ion traveling direction, the voltage source V ST The generated DC voltages DC1 and DC3 are switched so that the reference potential V 参考 is applied to each of the conductive pad pairs P21 / P22, P31 / P32 and is less than V 参考 A potential of -XV is applied to each of the conductive pad pairs P11 / P12, P41 / P42 to construct an electric field E2. The electric field E2 is perpendicular to the sides 220C / 222C and 220D / 222D of the substrates 220, 222, and extends along the unchanged ion travel direction, i.e., as in Figure 7C As depicted in FIG. 2 , from the edge 220C / 222C of the substrate 220, 222 toward the edge 220D / 222D of the substrate 220, 222. Figure 7C The electric field E2 constructed as shown in FIG. 1 , ions A leaving the ion source 12 through the ion hole IA and entering the channel 225 are manipulated or guided (or directed) by the electric field E2 along a changing ion travel direction 240, which is the same direction as the electric field E2 and is aligned (i.e., co-linear) with the ion hole IA of the ion source 12. Figure 7C As shown in FIG. 1 , such ions A are illustratively directed through channel 225 between conductive pad pairs P11 / P12, P41 / P42 along an unchanged direction of travel. In some embodiments, one or more conventional ion blankets and / or other conventional ion focusing structures may be used to direct ions A along the path between conductive pad pairs P11 / P12, P41 / P42. Figure 7C The ion trajectory 240 shown in FIG. 2 confines the ions.

[0089] Reference again Figure 6 The instructions stored in the memory 212 illustratively include instructions that, when executed by the processor 210, cause the processor 210 to control the ion manipulation voltage source V in the following manner: STselectively generating and switching voltages DC1-DC12 in a manner that guides ions along the ion manipulation array 208 and subsequently guides the ions into the ion entrance apertures AI1-AI3 of each corresponding ELIT 202, 204, 206; and, also controlling the voltage sources V1-V6 to selectively generate and switch the DC voltages generated thereby in a manner that controls the corresponding ion mirrors M1-M6 between ion transmission and ion reflection modes of the corresponding ion mirrors M1-M6 to capture ions guided by the ion manipulation array 208 into each ELIT 202, 204, 206, and then causing each trapped ion to oscillate back and forth between the corresponding ion mirrors M1-M6 of each ELIT 202, 204, 206, while the processor 210 is as described above with respect to Figures 1 to 4B As described above, the corresponding ion charge detection information is recorded in the memory 214. FIG. 8A to FIG. 8F , an example of such a process will be described as operating on one or more positively charged ions, but it should be understood that process 100 may alternatively operate on one or more negatively charged particles. In the following description, reference to any specific one or more of the conductive pads P1-P12 will be understood as reference to, for example, Fig. 7A 1. As shown, opposed, juxtaposed, spaced-apart pairs of conductive pads are disposed on the inner surfaces 220A, 222A of the substrates 220, 222, respectively, and reference to voltages applied to any particular one or more of the conductive pads P1-P12 will be understood as, for example, with respect to Figure 7B and Figure 7C is shown applied to two such opposing, juxtaposed, spaced-apart pairs of conductive pads. It should further be understood that FIG. 8A to FIG. 8F The DC voltage V 参考 can be any positive or negative voltage, or can be zero volts, for example, ground potential. FIG. 8A to FIG. 8F The DC voltage -XV shown in the figure can be less than V 参考 Any voltage, positive voltage, negative voltage or zero voltage, so as to construct a corresponding electric field in channel 225, such as Figure 7B and Figure 7C As shown in the example, the electric field is controlled to be at V 参考 The conductive pad extends toward the conductive pad controlled to be at -XV.

[0090] refer to Fig. 8A , the processor 210 is operable to control the voltage source V ST , to apply –XV to each of pads P5-P7, and then V 参考 is applied to each of the pads P1-P4. In some embodiments, as in Fig. 8AAs depicted in V ST V 参考 is applied to each of the pads P9-P12, but in other embodiments, V ST In any case, the electric field resulting from such voltage application in channel 225 of ion manipulation array 208 directs ions exiting ion aperture IA of ion source 12 through channel 225 along ion trajectory 250 shown in an unchanged ion travel direction.

[0091] refer to Figure 8B , the processor 210 may then be operable to control the voltage source V ST , to switch the voltage applied to pads P2 and P4 to -XV, and otherwise maintain the previously applied voltages at P1, P3, and P5-P12. The electric field established within channel 225 of ion manipulation array 208 resulting from such switched voltage application directs ion trajectories 252 along the changed ion travel direction along ion entrance aperture AI1 toward M1 of ELIT 202, manipulating ions previously traveling from ion source 12 along the unchanged ion travel direction along the ion trajectory 252 at Fig. 8A ions traveling along the ion trajectory 250 shown in . Simultaneously with, before or after this switching, the processor 210 is operable to control the voltage sources V1 and V2 to generate voltages that cause both ion mirrors M1 and M2 to be switched, for example as described with respect to Figures 1 to 2B As described above, the ion transmission mode is used. Figure 8B As shown in the ion trajectory 252 depicted in , ions traveling along the ion trajectory 252 through the channel 225 of the ion manipulation array 208 are directed into the entrance aperture AI1 of the ELIT 202, through M1, and are guided by the ion transmission field constructed in each of the ion mirrors M1 and M2 through M1, through the charge detection cylinder CD1 and through M2. In some embodiments, one or more conventional ion blankets and / or other conventional ion focusing structures may be operably positioned between the ion manipulation array 208 and the ion mirror M1 of the ELIT 202 to direct ions traveling along the ion trajectory 252 into the ion entrance aperture AI1 of the ELIT 202. In any case, the processor 210 is operable at some point thereafter to control V2 to generate a voltage that causes the ion mirror M2 to switch from an ion transmission operating mode to an ion reflection operating mode, for example, as also described with respect to Figures 1 to 2B The timing of this switching of M2 illustratively depends on whether the operation of ELIT 202 is controlled by processor 210 in a random trapping mode or in a triggered trapping mode, as described with respect to Figure 3 As described.

[0092] refer to Figure 8C , the processor 210 is then operable to control the voltage source V1 to generate a voltage that causes the ion mirror M1 to switch from the ion transmission mode to the ion reflection mode of operation. The timing of this switching of M1 illustratively depends on whether the operation of the ELIT 202 is controlled by the processor 210 in a random trapping mode or in a triggered trapping mode (as described with respect to FIG. Figure 3 described), but in any case, as in Figure 8C As shown in the ion trajectory 252 depicted in FIG, the switching of M1 to its ion reflectron mode traps the ion within the ELIT 202. With the ion trapped within the ELIT 202 and with both M1 and M2 being controlled by voltage sources V1 and V2, respectively, to operate in their ion reflectron modes, the ion trapped within the ELIT 202 oscillates back and forth between the ion mirrors M1 and M2, each time passing through the charge detection cylinder CD1 and inducing a corresponding charge thereon, as described above with respect to FIG. Figure 3 As described above, the charge is detected by the charge preamplifier CP1 and recorded in the memory 212 by the processor 210 .

[0093] Simultaneously with or subsequent to the control of the ELIT 202 just described, and with the ions oscillating back and forth within the ELIT 202 between the ion mirrors M1, M2, as also described above, Figure 8C As shown in FIG. , the processor 210 is operable to control V ST , to switch the voltage applied to pads P2 and P4 back to V 参考 , switching the voltage applied to pads P5–P8 from -VX to V 参考 , and the voltage applied to pads P9–P12 is increased from V 参考 Switch to -XV. The electric field resulting from such voltage application in the channel 225 of the ion manipulation array 208 again directs ions exiting the ion aperture IA of the ion source 12 through the channel 225 along the ion trajectory 250 shown in an unchanged direction of ion travel.

[0094] Reference now Fig.8D , the processor 210 may then be operable to control the voltage source V ST , to switch the voltage applied to pads P6 and P8 to -XV, and otherwise maintain the previously applied voltages at P1-P4, P5, P7, and P9-P12. The electric field established within channel 225 of ion manipulation array 208 resulting from such switched voltage application directs ion trajectories 254 along the changed ion travel direction along ion entrance aperture AI2 toward M2 of ELIT 204, manipulating ions previously traveling from ion source 12 along the unchanged ion travel direction along the ion trajectory 254 at Figure 8Cions traveling along the ion trajectory 250 shown in . Simultaneously with, before or after this switching, the processor 210 is operable to control voltage sources V3 and V4 to generate voltages that cause both ion mirrors M3 and M4 to operate in their ion transmission modes. As a result, as shown by Fig.8D As shown in the ion trajectory 254 depicted in , ions traveling along the ion trajectory 254 through the channel 225 of the ion manipulation array 208 are directed into the entrance aperture AI2 of the ELIT 204, through M3 and are guided by the ion transmission field constructed in each of the ion mirrors M3 and M4 through M3, through the charge detection cylinder CD2 and through M4. In some embodiments, one or more conventional ion blankets and / or other conventional ion focusing structures may be operably positioned between the ion manipulation array 208 and the ion mirror M3 of the ELIT 204 to direct ions traveling along the ion trajectory 254 into the ion entrance aperture AI2 of the ELIT 204. In any case, the processor 210 is operable at some point thereafter to control V4 to generate a voltage that causes the ion mirror M4 to switch from an ion transmission operating mode to an ion reflection operating mode so as to reflect the ions back toward M3. The timing of this switching of M4 illustratively depends on whether the operation of the ELIT 204 is controlled by the processor 210 in a random capture mode or in a triggered capture mode, as described with respect to FIG. Figure 3 As described.

[0095] exist Fig.8D After the operating state shown in Figure 8C Similar to that described, the processor 210 is operable to control the voltage source V3 to generate a voltage that causes the ion mirror M3 to switch from the ion transmission mode to the ion reflection mode of operation. The timing of this switching of M3 illustratively depends on whether the operation of the ELIT 204 is controlled by the processor 210 in a random capture mode or in a triggered capture mode (as described with respect to FIG. Figure 3 However, in any case, as in Fig. 8E As shown in the ion trajectory 254 depicted in FIG, the switching of M3 to its ion reflectron mode traps the ion within the ELIT 204. With the ion trapped within the ELIT 204 and both M3 and M4 being controlled by voltage sources V3 and V4, respectively, to operate in their ion reflectron modes, the ion trapped within the ELIT 204 oscillates back and forth between the ion mirrors M3 and M4, each time passing through the charge detection cylinder CD2 and inducing a corresponding charge thereon, as described above with respect to FIG. Figure 3 As described above, the charge is detected by the charge preamplifier CP2 and recorded in the memory 212 by the processor 210. Fig. 8EIn the operating state shown in , ions oscillate back and forth simultaneously within each of ELITs 202 and 204 , and therefore, ion charge / timing measurements taken from each of charge preamplifiers CP1 and CP2 are collected and stored simultaneously by processor 210 .

[0096] Just about Fig. 8E Simultaneously or subsequently to the control of ELIT 204 described above, and in the event that ions are simultaneously oscillating within each of ELITs 202 and 204, processor 210 is operable to control V ST , used to switch the voltage applied to pads P6 and P8 back to V 参考 , so that pads P1-P12 are controlled to be in Figure 8C As shown in Figure 8C As shown in FIG. 1 , the electric field resulting from such voltage application in the channel 225 of the ion manipulation array 208 once again directs ions exiting the ion aperture IA of the ion source 12 through the channel 225 along the ion trajectory 250 shown in an unchanged ion travel direction. Thereafter, the processor 210 is operable to control the voltage source V ST , to switch the voltage applied to pads P9 and P11 to V 参考 , and otherwise maintaining previously applied voltages at P1-P8, P5, and P11-P12. The electric field established within channel 225 of ion manipulation array 208 resulting from such switched voltage application directs ion trajectories 256 along the changed ion travel direction toward ion entrance aperture AI3 of ion mirror M5 of ELIT 206, manipulating ions previously traveling from ion source 12 along the unchanged ion travel direction along the ion trajectory 256 at Figure 8C ions traveling along the ion trajectory 250 shown in . Simultaneously with, before or after this switching, the processor 210 is operable to control voltage sources V5 and V6 to produce voltages that cause both ion mirrors M5 and M6 to operate in their ion transmission modes. As a result, as shown by Fig. 8E As shown in the ion trajectory 256 depicted in FIG, ions traveling along the ion trajectory 253 through the channel 225 of the ion manipulation array 208 are directed into the entrance aperture AI3 of the ELIT 206, through M5, and are guided by the ion transmission field constructed in each of the ion mirrors M5 and M6 through M5, through the charge detection cylinder CD3 and through M6. In some embodiments, one or more conventional ion blankets and / or other conventional ion focusing structures may be operably positioned between the ion manipulation array 208 and the ion mirror M5 of the ELIT 206 to direct ions traveling along the ion trajectory 256 into the ion entrance aperture AI3 of the ELIT 206.

[0097] In any case, processor 210 is operable at some point thereafter to control V6 to produce a voltage that causes ion mirror M6 to switch from an ion transmission mode of operation to an ion reflection mode of operation so as to reflect ions back toward M5. The timing of this switching of M6 illustratively depends on whether the operation of ELIT 206 is controlled by processor 210 in a random capture mode or in a triggered capture mode, as described with respect to FIG. Figure 3 Thereafter, the processor 210 performs the operation similar to that described with respect to Figure 8C The described ELIT 206 is operable to control the voltage source V5 to generate a voltage that causes the ion mirror M5 to switch from the ion transmission mode to the ion reflection mode of operation. The timing of this switching of M5 illustratively depends on whether the operation of the ELIT 206 is controlled by the processor 210 in the random capture mode or in the triggered capture mode, as described with respect to FIG. Figure 3 described, but in any case, as in Fig.8F As shown in the ion trajectory 256 depicted in FIG, the switching of M5 to its ion reflectron mode traps the ion within the ELIT 206. With the ion trapped within the ELIT 206 and with both M5 and M6 being controlled by voltage sources V5 and V6, respectively, to operate in their ion reflectron modes, the ion trapped within the ELIT 206 oscillates back and forth between ion mirrors M5 and M6, each time passing through the charge detection cylinder CD3 and inducing a corresponding charge thereon, as described above with respect to FIG. Figure 3 As described above, the charge is detected by the charge preamplifier CP3 and recorded in the memory 212 by the processor 210. Fig.8F In the operating state shown in , ions oscillate back and forth simultaneously within each of ELITs 202, 204 and 206, and therefore, ion charge / timing measurements taken from each of charge preamplifiers CP1, CP2 and CP3 are collected and stored simultaneously by processor 210.

[0098] If still Fig.8F As shown in FIG. 1 , concurrently with or subsequent to the control of ELIT 206 just described, and with ions oscillating simultaneously within each of ELITs 202, 204, and 206, processor 210 is operable to control V ST , used to switch the voltage applied to pads P5–P8 to -XV, and to switch the voltage applied to pads P10 and P12 to V 参考 (or for switching the voltage applied to P9 and P11 to -XV) so that the pads P1-P12 are controlled to be at Fig. 8A The voltage shown in (or described with respect to) Fig. 8AAs shown in , the electric field resulting from the application of such voltages in the channel 225 of the ion manipulation array 208 once again directs ions exiting the ion aperture IA of the ion source 12 through the channel 225 along the illustrated ion trajectory 250 in an unchanged ion travel direction.

[0099] After the ions have oscillated back and forth within each of the ELITs 202, 204, and 206 for the total ion cycle measurement time or total number of measurement cycles, e.g., as described above with respect to Figure 3 As described in step 126 of process 100 shown in FIG. 1 , processor 210 is operable to control voltage sources V1-V6 for switching each of ion mirrors M1-M6 to its ion transmission mode of operation, thereby causing the ions trapped therein to exit ELITs 202, 204, 206 via ion exit apertures AO1-AO3, respectively. The operation of CDMS 200 then illustratively returns to the above description of Figure 8B Concurrently or at another convenient time, the collection of recorded ion charge / timing measurements is processed by processor 210, e.g., as described in Figure 3 The process 100 shown in FIG. 1 is described in conjunction with step 140 of the process 100 for determining the charge, mass-to-charge ratio, and mass value of each ion processed by a corresponding one of the ELITs 202 , 204 , 206 .

[0100] Depending on a number of factors, including but not limited to the size of the ELITS 202, 204, 206, the frequency or frequencies of ion oscillations through each ELIT 202, 204, 206, and the total number of measurement cycles / total ion cycle measurement time in each ELIT 202, 204, 206, ions may oscillate back and forth simultaneously within at least two of the ELITs 202, 204, and 206, and thus, ion charge / timing measurements taken from corresponding ones of the charge preamplifiers CP1, CP2, and CP3 may be collected and stored simultaneously by the processor 210. Fig.8FIn the embodiment shown in , for example, ions oscillate back and forth simultaneously in at least two of the ELITs 202, 204, and 206, and therefore, ion charge / timing measurements taken from each of the charge preamplifiers CP1, CP2, and CP3 are collected and stored simultaneously by the processor 210. In other embodiments, the total number of measurement cycles or the total ion cycle measurement time of the ELIT 202 may expire before at least one ion is trapped in the ELIT 206 as shown above. In such cases, the processor 210 may control the voltage sources V1 and V2 to switch the ion mirrors M1 and M2 to their transmission operating modes, thereby causing the ions oscillating therein to leave through the ion mirror M2 before the ions become oscillating in the ELIT 206. In such embodiments, the ions may not oscillate back and forth simultaneously in all of the ELITs 202, 204, and 206, but may oscillate back and forth in at least two of the ELITs 202, 204, and 206 at any one time.

[0101] Reference now Fig. 9 , shows another CDMS 300, which includes yet another embodiment of an electrostatic linear ion trap (ELIT) array 302 having control and measurement elements coupled thereto. In the illustrated embodiment, the ELIT array 302 includes three separate ELITs E1-E3, each with Figure 6 The ELITs 202, 204, 206 shown in FIG. are configured identically. Fig. 9 In the embodiment shown in FIG. , the structure and function are similar to those in FIG. Figures 1 to 2B The voltage source V1 shown in FIG. 1 is illustratively the same voltage source V1 as that shown in FIG. 1 , which is operably coupled to the ion mirror M1 of each ELIT E1 - E3 and is structurally and functionally identical to that shown in FIG. Figures 1 to 2B The voltage source V4 shown in the figure is illustratively the same as another voltage source V2 operably coupled to the ion mirror M2 of each ELIT E1-E3. In alternative embodiments, the ion mirrors M1 of two or more ELITs E1-E3 may be combined into a single ion mirror, and / or the ion mirrors M2 of two or more ELITs E1-E3 may be combined into a single ion mirror. In any case, the voltage sources V1, V2 are electrically coupled to the processor 304, and the three charge preamplifiers CP1-CP3 are electrically coupled between the processor 304 and the corresponding charge detection cylinders CD1-CD3 of a corresponding ELIT E1-E3. The memory 306 illustratively includes instructions that, when executed by the processor 304, cause the processor 304 to control the voltage sources V1 and V2 to control the operation of the ELITs E1-E3 as described below. Illustratively, the processor 304 is operably coupled to one or more peripheral devices 308, which may be connected to the peripheral devices 308 described above. Figure 1The one or more peripheral devices 20 described are identical.

[0102] CDMS 300 is similar in some respects to CDMS 200 in that CDMS 300 includes ion source 12 operably coupled to ion manipulation array 208, the structure and operation of which are described above. The instructions stored in memory 306 also illustratively include instructions that, when executed by processor 304, cause processor 304 to control ion manipulation array voltage source V as described below. ST .

[0103] exist Fig. 9 In the embodiment shown in FIG. 1 , CDMS 300 also illustratively includes three conventional ion traps IT1-IT3, each having a corresponding ion inlet TI1-TI3 and an opposite ion outlet TO1-TO3. Ion trap IT1 is illustratively positioned between a set of conductive pads P1-P4 and an ion mirror M1 of ELIT E1, such that a longitudinal axis 241 extending centrally through ELIT E1 bisects the ion inlet TI1 and ion outlet TO1 of IT1, and further Fig. 9 centered between the pad pairs P1 / P2 and P3 / P4 shown in . The ion trap IT2 is illustratively positioned between a set of conductive pads P5-P8 and the ion mirror M1 of the ELIT E2, such that a longitudinal axis 242 extending centrally through the ELIT E2 bisects the ion inlet TI2 and the ion outlet TO2 of IT2, and also passes centrally between the pad pairs P5 / P6 and P7 / P8, and the ion trap IT3 is similarly positioned between a set of conductive pads P9-P12 and the ion mirror M1 of the ELITE3, such that a longitudinal axis 243 extending centrally through the ELIT E3 bisects the ion inlet TI3 and the ion outlet TO3 of IT3, and also passes centrally between the pad pairs P9 / P10 and P11 / P12. The ion traps IT1–IT3 can be any conventional ion traps, examples of which can include, but are not limited to, conventional quadrupole ion traps, conventional hexapole ion traps, etc.

[0104] Ion trap voltage source V IT is operably coupled between processor 304 and each of ion traps IT1-IT3. Voltage source V IT Illustratively it is configured to generate suitable DC and AC voltages, such as RF voltages, for separately and individually controlling the operation of each of the ion traps IT1 - IT3 in a conventional manner.

[0105] Processor 304 is illustratively configured (eg, programmed) to control the ion manipulation array voltage source V ST , to sequentially manipulate one or more ions exiting the ion aperture IA of the ion source 12 (e.g., Figures 8A-8Fion traps IT1-IT3). In some embodiments, one or more conventional ion blankets and / or other ion focusing structures may be positioned between ion manipulation array 208 and one or more ion traps IT1-IT3 to direct ions from ion manipulation array 208 into ion entrances TI1-TI3 of corresponding ion traps IT1-IT3. Processor 304 is also configured (e.g., programmed) to control ion trap voltage source V IT The ion traps IT1 - IT3 are used to generate corresponding control voltages for controlling the ion inlets TI1 - TI3 of the ion traps IT1 - IT3 to receive ions therein, and for controlling the ion traps IT1 - IT3 in a conventional manner to capture and confine the ions therein.

[0106] When the ion traps IT1-IT3 are full of ions, the processor 304 is configured (i.e., programmed) to control V1 and V2 to generate a suitable DC voltage, which controls the ion mirrors M1 and M2 of the ELIT E1-E2 to operate in their ion transmission operation mode, so that any ions moving therein leave through the ion exit apertures AO1-AO3, respectively. When at least one ion is trapped in each ion trap IT1-IT3 through the control of the ion manipulation array 208 and the ion traps IT1-IT3 just described, the processor 304 is configured (i.e., programmed) to control V2 to generate a suitable DC voltage, which controls the ion mirror M2 of the ELIT E1-E3 to operate in its ion reflection operation mode. Thereafter, the processor 304 is configured to control the ion trap voltage source V IT To generate a suitable voltage, the voltage causes the ion outlets TO1-TO3 of the corresponding ion traps IT1-IT3 to open simultaneously to guide the ions trapped therein into a corresponding one of the ELIT E1-E3 via the corresponding ion entrance perforations AI1-AI3 of the corresponding ion mirror M1. When the processor 304 determines that the ions have entered each of the ELIT E1-E3, for example, after some time period after the ion traps IT1-IT3 are opened simultaneously, or after charge detection by each charge preamplifier CP1-CP3, the processor 304 can be operated to control the voltage source V1 to generate a suitable DC voltage, the voltage controls the ion mirror M1 of the ELT E1-E3 to operate in its ion reflection operation mode, thereby trapping the ions in each of the ELIT E1-E3.

[0107] With the ion mirrors M1 and M2 of each ELIT E1-E3 operating in the ion reflection mode of operation, the ions in each ELIT E1-E3 simultaneously oscillate back and forth between M1 and M2, each time passing through a corresponding one of the charge detection cylinders CD1-CD3. The corresponding charges induced on the charge detection cylinders CD1-CD3 are detected by the corresponding charge preamplifiers CP1-CP3, and the charge detection signals generated by the charge preamplifiers CP1-CP3 are stored in the memory 306 by the processor 304 and subsequently processed by the processor 304, for example, as described in relation to Figure 3 , for determining the charge, mass-to-charge ratio, and mass value of each ion processed by a corresponding one of the ELITs E1-E3.

[0108] Although the embodiments of CDMS 200 and 300 are respectively Figures 6 to 8F and Fig. 9 , it will be appreciated that one or both of such systems 200, 300 may alternatively include fewer (e.g., 2) or more (e.g., 4 or more) ELITs. In any such alternative embodiments, the control and operation of the various components will generally follow the concepts described above, and those skilled in the art will recognize that any modifications to system 200 and / or system 300 required to implement any such alternative embodiments will only involve mechanical steps. In addition, although the embodiments of CDMS systems 200 and 300 are respectively described in Figures 6 to 8F as well as Fig. 9 200, 300 are each shown to include an example ion manipulation array 208, but it should be understood that one or more other ion guide structures may alternatively or additionally be used to manipulate or guide ions as described above, and any such alternative ion guide structures are intended to fall within the scope of the present disclosure. As a non-limiting example, an array of DC quadrupole beam deflectors may be used with one or both of systems 200, 300 to manipulate or guide ions as described. In such embodiments, as described above, one or more focusing lenses and / or ion blankets may also be used to focus ions into different ion traps.

[0109] It should be understood that the dimensions of the various components of any of the ELIT arrays 14, 205, 302 shown in the figures and described above, and the amplitude of the electric field established in any of the systems 10, 60, 80, 200, 300, can be illustratively selected to establish a desired ion oscillation duty cycle within the ELIT or one or more of the ELIT regions E1-E3, which duty cycle corresponds to the ratio of the time spent by the ions in the corresponding charge detection cylinder CD1-CD3 to the total time spent by the ions traversing the combination of the corresponding ion mirror and the corresponding charge detection cylinder CD1-CD3 during one complete oscillation cycle. For example, in order to reduce noise in the determination of the fundamental frequency amplitude caused by harmonic frequency components of the measurement signal, a duty cycle of approximately 50% can be desired in one or more of the ELIT or ELIT regions. Detailed information regarding such sizing and operating considerations for achieving a desired duty cycle (e.g., such as 50%) is shown and described in co-pending U.S. patent application serial number 62 / 616,860 filed on January 12, 2018, co-pending U.S. patent application serial number 62 / 680,343 filed on June 4, 2018, and co-pending international patent application number PCT / US2019 / 013251 filed on January 11, 2019, all of which are entitled ELECTROSTATIC LINEAR ION TRAP DESIGN FOR CHARGE DETECTION MASS SPECTROMETRY, the disclosures of which are expressly incorporated herein by reference in their entirety.

[0110] It should also be understood that in any of the systems 10, 60, 80, 200, 300 shown in the figures and described herein, one or more charge calibration or resetting apparatuses may be used with the charge detection cylinders of any one or more ELIT arrays 14, 205, 302 and / or in any one or more of the regions E1-E3 of the ELIT array 14. An example of such a charge calibration and resetting apparatus is shown and described in co-pending U.S. patent application Ser. No. 62 / 680,272 filed Jun. 4, 2018 and co-pending International Patent Application No. PCT / US2019 / 013284 filed Jan. 11, 2019, both of which are entitled APPARATUS AND METHOD FOR CALIBRATING OR RESETTING A CHARGE DETECTOR, the disclosures of which are expressly incorporated herein by reference in their entireties.

[0111] It should also be understood that in any of the systems 10, 60, 80, 200, 300 shown in the figures and described herein, one or more charge detection optimization techniques can be used with any one or more ELIT arrays 14, 205, 302 and / or with one or more regions E1-E3 in the ELIT array 14, for example, to trigger a capture or other charge detection event. Examples of some such charge detection optimization techniques are shown and described in co-pending U.S. patent application Ser. No. 62 / 680,296 filed Jun. 4, 2018 and co-pending International Patent Application No. PCT / US2019 / 013280 filed Jan. 11, 2019, both of which are entitled APPARATUS AND METHOD FOR CAPTURING IONS IN AN ELECTROSTATIC LINEAR IONTRAP, the disclosures of which are expressly incorporated herein by reference in their entirety.

[0112] It should further be understood that in any of the systems 10, 60, 80, 200, 300 shown in the figures and described herein, one or more ion source optimization devices and / or techniques can be used with one or more embodiments of the ion source 12, in co-pending U.S. patent application serial number 62 / 680,223, filed on June 4, 2018 and entitled HYBRID ION FUNNEL-ION CARPET (FUNPET) ATMOSPHERIC PRESSURE INTERFACE FOR CHARGE DETECTION MASS SPECTROMETRY, and in co-pending U.S. patent application serial number 62 / 680,223, filed on January 11, 2019 and entitled INTERFACE FOR TRANSPORTING IONS FROM AN ATMOSPHERIC PRESSURE ENVIRONMENT TO A LOW PRESSURE ENVIRONMENT Some examples of these devices and / or techniques are shown and described in co-pending International Patent Application No. PCT / US2019 / 035379, filed with the U.S. Department of Defense (DOD) and the U.S. Department of Defense (DOD), the disclosures of which are expressly incorporated herein by reference in their entirety.

[0113] It should be further understood that any system 10, 60, 80, 200, 300 shown in the figures and described herein may be implemented according to real-time analysis and / or real-time control techniques, some examples of which are shown and described in co-pending U.S. patent application serial number 62 / 680,245 filed on June 4, 2018 and co-pending international patent application number PCT / US2019 / 013277 filed on January 11, 2019, both of which are entitled CHARGE DETECTION MASS SPECTROMETRY WITH REAL TIME ANALYSIS AND SIGNAL OPTIMIZATION, the disclosures of which are expressly incorporated herein by reference in their entirety.

[0114] It is further understood that in any of the systems 10, 60, 80, 200, 300 shown in the drawings and described herein, one or more ion inlet trajectory control devices and / or techniques may be implemented to provide simultaneous measurement of multiple individual ions within one or more ELIT or ELIT regions of any ELIT array shown in the drawings and described herein. Examples of some such ion inlet trajectory control devices and / or techniques are shown and described in co-pending U.S. patent application serial number 62 / 774,703 filed on December 3, 2018 and co-pending international patent application number PCT / US2019 / 013285 filed on January 11, 2019, both of which are entitled APPARATUS AND METHOD FOR SIMULTANEOUSLY ANALYZING MULTIPLE IONS WITH AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are expressly incorporated herein by reference in their entirety.

[0115] Although the present disclosure has been shown and described in detail in the foregoing drawings and specification, the present disclosure should be considered to be illustrative rather than restrictive in nature, and it should be understood that only illustrative embodiments thereof have been shown and described and that all changes and modifications that fall within the spirit of the present disclosure are desired to be protected.

Claims

1. An electrostatic linear ion trap array, comprising: a plurality of elongated charge detection cylinders arranged end to end and each defining an axial passage extending centrally therethrough, a plurality of ion mirror structures, each defining a pair of axially aligned cavities and each defining an axial passage through the ion mirror structure extending centrally through the two cavities, wherein different ones of the plurality of ion mirror structures are respectively disposed between adjacent elongated charge detection cylinders, and a front ion mirror and a rear ion mirror, each defining at least one cavity and an axial passage extending centrally therethrough, the front ion mirror being positioned at one end of the plurality of elongated charge detection cylinders, and the rear ion mirror being positioned at an opposite end of the plurality of elongated charge detection cylinders, the axial passage of the front ion mirror defining an ion inlet to the electrostatic linear ion trap array, the rear ion mirror defining an ion outlet of the electrostatic linear ion trap array, and the plurality of ion mirror structures being disposed between the front ion mirror and the rear ion mirror, Wherein, the axial passages of the plurality of elongated charge detection cylinders, the plurality of ion mirror structures, the front ion mirror and the rear ion mirror are axially aligned with each other to define a longitudinal axis centered through the electrostatic linear ion trap array.

2. The electrostatic linear ion trap array according to claim 1, wherein: Each of the plurality of ion mirror structures comprises a single ion mirror defining a single cavity, a first through-hole at one end of the ion mirror leading to the single cavity, a second through-hole at an opposite end of the ion mirror and leading to the single cavity, and a plate or ring centrally located with respect to the single cavity and axially bisecting the single cavity into a pair of axially aligned cavities, the plate or ring defining a third through-hole passing therethrough and leading to the two axially aligned cavities, And wherein a longitudinal axis of the electrostatic linear ion trap array extends centrally through the first through-hole, the second through-hole, the third through-hole and a pair of axially aligned cavities of each of the plurality of ion mirror structures.

3. The electrostatic linear ion trap array according to claim 1, wherein: Each of the multiple ion mirror structures includes a first ion mirror and a second ion mirror, wherein the first ion mirror defines a first cavity, a first through-hole at one end of the first ion mirror and leading to the first cavity, and a second through-hole at the opposite end of the first ion mirror and leading to the first cavity, the second ion mirror defines a second cavity, a third through-hole at one end of the second ion mirror and leading to the second cavity, and a fourth through-hole at the opposite end of the second ion mirror and leading to the second cavity, the first ion mirror and the second ion mirror are arranged back to back, wherein the second through-hole of the first ion mirror is spaced apart from and axially aligned with the third through-hole of the second ion mirror, so that the first cavity and the second cavity together define the pair of axially aligned cavities, And wherein the longitudinal axis of the electrostatic linear ion trap array extends centrally through the first through-hole to the fourth through-hole and centrally through the first cavity and the second cavity of each of the plurality of ion mirror structures.

4. The electrostatic linear ion trap array according to claim 3, wherein: The first ion mirror and the second ion mirror are fixed to each other.

5. The electrostatic linear ion trap array according to any one of claims 1 to 4, wherein: the front ion mirror defining a first cavity, a first through-hole at one end of the front ion mirror leading to the first cavity, a second through-hole at an opposite end of the front ion mirror and leading to the first cavity, and a plate or ring centrally located with respect to the first cavity and axially bisecting the first cavity into second and third axially aligned cavities, the plate or ring defining a third through-hole therethrough and leading to the second and third axially aligned cavities, and wherein the longitudinal axis of the electrostatic linear ion trap array extends centrally through the first aperture, the second aperture, the third aperture and the second and third axially aligned cavities of the front ion mirror, And wherein the first through-hole of the front ion mirror defines an ion entrance to the electrostatic linear ion trap array, and the second through-hole of the front ion mirror is positioned opposite the exposed end of the elongated charge detection cylinder at one end of the plurality of elongated charge detection cylinders.

6. The electrostatic linear ion trap array according to any one of claims 1 to 4, wherein: the front ion mirror defining a single cavity, a first aperture at one end of the front ion mirror opening into the single cavity of the front ion mirror, and a second aperture at an opposite end of the front ion mirror and opening into the single cavity of the front ion mirror, and wherein the longitudinal axis of the electrostatic linear ion trap array extends centrally through the first and second perforations of the front ion mirror and the single cavity of the front ion mirror, And wherein the first through-hole of the front ion mirror defines an ion entrance to the electrostatic linear ion trap array, and the second through-hole of the front ion mirror is positioned opposite the exposed end of the elongated charge detection cylinder at one end of the plurality of elongated charge detection cylinders.

7. The electrostatic linear ion trap array according to any one of claims 1 to 4, wherein: the back ion mirror defining a first cavity, a first through-hole at one end of the back ion mirror leading to the first cavity, a second through-hole at an opposite end of the back ion mirror and leading to the first cavity, and a plate or ring centrally located with respect to the first cavity of the back ion mirror and axially bisecting the first cavity of the back ion mirror into second and third axially aligned cavities, the plate or ring defining a third through-hole extending therethrough and leading to the second and third axially aligned cavities of the back ion mirror, and wherein the longitudinal axis of the electrostatic linear ion trap array extends centrally through the first aperture, the second aperture, the third aperture and the second and third axially aligned cavities of the rear ion mirror, And wherein the first through-hole of the rear ion mirror is positioned opposite the exposed ends of the elongated charge detection cylinders at opposite ends of the plurality of elongated charge detection cylinders, and the second through-hole of the rear ion mirror defines an ion outlet of the electrostatic linear ion trap array.

8. The electrostatic linear ion trap array according to any one of claims 1 to 4, wherein: the back ion mirror defining a single cavity, a first aperture at one end of the back ion mirror opening into the single cavity of the back ion mirror, and a second aperture at an opposite end of the back ion mirror and opening into the single cavity of the back ion mirror, and wherein the longitudinal axis of the electrostatic linear ion trap array extends centrally through the first and second perforations of the rear ion mirror and the single cavity of the rear ion mirror, And wherein the first through-hole of the rear ion mirror is positioned opposite the exposed ends of the elongated charge detection cylinders at opposite ends of the plurality of elongated charge detection cylinders, and the second through-hole of the rear ion mirror defines an ion outlet of the electrostatic linear ion trap array.

9. The electrostatic linear ion trap array according to any one of claims 1 to 4, further comprising: A device for selectively constructing an ion transmission electric field or an ion reflection electric field in the cavity of the front ion mirror and the rear ion mirror and in the cavity of each of the multiple ion mirror structures, the ion transmission electric field is configured to focus ions passing through the front ion mirror, the rear ion mirror and a corresponding one of the multiple ion mirror structures toward the longitudinal axis, and the ion reflection electric field is configured to stop ions entering the front ion mirror, the rear ion mirror and a corresponding one of the multiple ion mirror structures from a corresponding one of the multiple elongated charge detection cylinders and accelerate back in the opposite direction through a corresponding one of the multiple elongated charge detection cylinders while also focusing the ions toward the longitudinal axis.

10. The electrostatic linear ion trap array according to any one of claims 1 to 4, further comprising: At least one voltage source is operatively coupled to the front ion mirror, the rear ion mirror, and each of the multiple ion mirror structures and is configured to generate a voltage for selectively constructing an ion transmission electric field or an ion reflection electric field therein, wherein the ion transmission electric field is configured to focus ions passing through the front ion mirror, the rear ion mirror, and a corresponding one of the multiple ion mirror structures toward the longitudinal axis, and the ion reflection electric field is configured to stop ions entering the front ion mirror, the rear ion mirror, and a corresponding one of the multiple ion mirror structures from a corresponding one of the multiple elongated charge detection cylinders and accelerate back in the opposite direction through a corresponding one of the multiple elongated charge detection cylinders while also focusing the ions toward the longitudinal axis.

11. The electrostatic linear ion trap array according to claim 10, further comprising: a processor operatively coupled to the at least one voltage source, and A memory having instructions stored therein, which, when executed by the processor, cause the processor to control the at least one voltage source to construct an ion transmission electric field about the front ion mirror, the rear ion mirror, and the cavity of each of the multiple ion mirror structures, so that ions entering the front ion mirror pass through each of the following: the front ion mirror, the rear ion mirror, each of the multiple ion mirror structures, and each of the multiple elongated charge detection cylinders, and leave the electrostatic linear ion trap array.

12. The electrostatic linear ion trap array according to claim 11, wherein: The instructions stored in the memory also include instructions that, when executed by the processor, cause the processor to control the at least one voltage source to establish an ion reflection electric field with respect to at least one cavity of the rear ion mirror while maintaining an ion transmission electric field in the cavities of the front ion mirror and the multiple ion mirror structures.

13. The electrostatic linear ion trap array according to claim 12, wherein: The electrostatic linear ion trap array defines a plurality of axially aligned electrostatic linear ion trap regions, each of the electrostatic linear ion trap regions comprising a different one of the plurality of elongated charge detection cylinders and a cavity of a corresponding one of the front ion mirror, the rear ion mirror, and the plurality of ion mirror structures, And wherein, the instructions stored in the memory also include instructions, which, when executed by the processor, cause the processor to control the at least one voltage source to sequentially construct the ion reflection electric field with respect to the cavity of each of the multiple ion mirror structures, which starts with the following ion mirror structure among the multiple ion mirror structures, that is, the ion mirror structure is positioned at one end of an elongated charge detection cylinder among the multiple elongated charge detection cylinders that is set to be adjacent to the rear ion mirror, while maintaining the ion transmission electric field in the cavity of the front ion mirror and each of the remaining multiple ion mirror structures, and then control the at least one voltage source to construct the ion reflection electric field with respect to at least one cavity of the front ion mirror in the following manner, the manner continuously traps different ions among the ions entering the front ion mirror in each of the multiple electrostatic linear ion trap regions, so that the ions trapped in each of the multiple electrostatic linear ion trap regions oscillate back and forth between the corresponding ion mirror structures each time they pass through the corresponding elongated charge detection cylinder of the multiple elongated charge detection cylinders.

14. The electrostatic linear ion trap array according to claim 13, further comprising: a plurality of charge preamplifiers, each charge preamplifier having an input operatively coupled to a different one of the plurality of elongated charge detection cylinders and each having an output operatively coupled to the processor, each of the plurality of charge preamplifiers being configured to generate a charge detection signal upon detecting a charge induced on a corresponding one of the plurality of elongated charge detection cylinders when a corresponding ion passes through the corresponding one of the plurality of elongated charge detection cylinders, And wherein the instructions stored in the memory further include instructions that, when executed by the processor, cause the processor to record a charge detection signal generated by each of the plurality of charge preamplifiers.

15. The electrostatic linear ion trap array according to claim 14, wherein: The instructions stored in the memory also include instructions that, when executed by the processor, cause the processor to control the at least one voltage source to trap one of the ions entering the front ion mirror in any one of the multiple electrostatic linear ion trap regions by: controlling the at least one voltage source to construct the ion reflection electric field in the cavity of the front ion mirror and the corresponding upstream one of the multiple ion mirror structures after a certain time delay since controlling the at least one voltage source to construct the ion reflection electric field in the cavity of the rear ion mirror and the corresponding downstream one of the multiple ion mirror structures.

16. The electrostatic linear ion trap array according to claim 14, wherein: The instructions stored in the memory also include instructions that, when executed by the processor, cause the processor to control the at least one voltage source to trap one of the ions entering the front ion mirror in any one of the multiple electrostatic linear ion trap regions by: upon detecting a charge detection signal generated by a corresponding one of the multiple charge preamplifiers, controlling the at least one voltage source to construct the ion reflection electric field in the cavity of the front ion mirror and a corresponding upstream one of the multiple ion mirror structures.

17. The electrostatic linear ion trap array according to any one of claims 14 to 16, wherein: The instructions stored in the memory also include instructions that, when executed by the processor, cause the processor to determine at least one of an ion mass-to-charge ratio and an ion mass and a corresponding ion charge based on the recorded charge detection signals generated by each of the plurality of charge preamplifiers.

18. A system for separating ions, comprising: an ion source configured to generate ions from the sample, at least one ion separation instrument configured to separate the generated ions according to at least one molecular characteristic, and According to any one of claims 1 to 17, ions leaving the at least one ion separation instrument are transmitted into the electrostatic linear ion trap array via the front ion mirror.

19. The system of claim 18, wherein: The at least one ion separation instrument includes one or any combination of the following: at least one instrument for separating ions according to mass-to-charge ratio, at least one instrument for separating ions in time according to ion mobility, at least one instrument for separating ions according to ion retention time, and at least one instrument for separating ions according to molecular size.

20. The system of claim 18, wherein: The at least one ion separation instrument comprises one or a combination of a mass spectrometer and an ion mobility spectrometer.

21. The system of any one of claims 18 to 20, further comprising at least one ion processing instrument positioned between the ion source and the at least one ion separation instrument, the at least one ion processing instrument positioned between the ion source and the at least one ion separation instrument comprising one or any combination of: at least one instrument for collecting or storing ions, at least one instrument for filtering ions according to molecular properties, at least one instrument for dissociating ions, and at least one instrument for changing the charge state of ions.

22. The system according to any one of claims 18 to 20 further includes at least one ion processing instrument positioned between the at least one ion separation instrument and the electrostatic linear ion trap array, the at least one ion processing instrument positioned between the at least one ion separation instrument and the electrostatic linear ion trap array comprising one or any combination of the following: at least one instrument for collecting or storing ions, at least one instrument for filtering ions according to molecular properties, at least one instrument for dissociating ions, and at least one instrument for changing the charge state of ions.

23. A system according to any one of claims 18 to 20, wherein: The system also includes at least one ion separation instrument positioned to receive ions exiting the electrostatic linear ion trap array and to separate the received ions according to at least one molecular characteristic.

24. The system according to claim 23 further includes at least one ion processing instrument positioned between the electrostatic linear ion trap array and the at least one ion separation instrument positioned to receive ions leaving the electrostatic linear ion trap array, and the at least one ion processing instrument positioned between the electrostatic linear ion trap array and the at least one ion separation instrument positioned to receive ions leaving the electrostatic linear ion trap array includes one or any combination of the following: at least one instrument for collecting or storing ions, at least one instrument for filtering ions according to molecular properties, at least one instrument for dissociating ions, and at least one instrument for changing the charge state of ions.

25. The system of claim 23 further comprises at least one ion processing instrument positioned to receive ions leaving the at least one ion separation instrument, the at least one ion separation instrument itself being positioned to receive ions leaving the electrostatic linear ion trap array, the at least one ion processing instrument comprising one or any combination of: at least one instrument for collecting or storing ions, at least one instrument for filtering ions based on molecular properties, at least one instrument for dissociating ions, and at least one instrument for changing the charge state of ions.

26. A system according to any one of claims 18 to 20, wherein: The system also includes at least one ion processing instrument positioned to receive ions leaving the electrostatic linear ion trap array, and the at least one ion processing instrument positioned to receive ions leaving the electrostatic linear ion trap array includes one or any combination of the following: at least one instrument for collecting or storing ions, at least one instrument for filtering ions based on molecular properties, at least one instrument for dissociating ions, and at least one instrument for changing the charge state of ions.

27. A system for separating ions, comprising: an ion source configured to generate ions from the sample, a first mass spectrometer configured to separate the generated ions according to mass-to-charge ratio, an ion dissociation stage positioned to receive ions exiting the first mass spectrometer and configured to dissociate ions exiting the first mass spectrometer, a second mass spectrometer configured to separate dissociated ions leaving the ion dissociation stage according to mass-to-charge ratio, and a charge detection mass spectrometer comprising an electrostatic linear ion trap array according to any one of claims 1 to 17, the charge detection mass spectrometer being coupled in parallel with and to the ion dissociation stage so that the charge detection mass spectrometer is capable of receiving ions leaving either of the first mass spectrometer and the ion dissociation stage, wherein a charge detection mass spectrometer is used to measure the mass of precursor ions leaving the first mass spectrometer, the second mass spectrometer is used to measure the mass-to-charge ratio of dissociated ions of precursor ions having a mass value below a threshold mass, and the charge detection mass spectrometer is used to measure the mass-to-charge ratio and charge value of dissociated ions of precursor ions having a mass value at or above the threshold mass.

28. A charge detection mass spectrometer comprising: an ion source configured to generate and supply ions, An electrostatic linear ion trap array, comprising: a plurality of ion mirrors, each ion mirror defining a corresponding axial passage therethrough; and a plurality of elongated charge detection cylinders, each elongated charge detection cylinder defining a corresponding axial passage therethrough, the plurality of ion mirrors and the elongated charge detection cylinders being arranged to define a plurality of electrostatic linear ion trap regions, each electrostatic linear ion trap region comprising a different elongated charge detection cylinder among the plurality of elongated charge detection cylinders positioned between corresponding different pairs among the plurality of ion mirrors, wherein the axial passage of each of the plurality of elongated charge detection cylinders is aligned with the axial passage of the corresponding pair of the plurality of ion mirrors, the plurality of ion mirrors comprising a front ion mirror positioned at one end of the electrostatic linear ion trap array and a rear ion mirror positioned at the opposite end of the electrostatic linear ion trap array, the axial passage of the front ion mirror defining an ion inlet to the electrostatic linear ion trap array, the axial passage of the rear ion mirror defining an ion outlet to the electrostatic linear ion trap array, the electrostatic linear ion trap array being configured to receive at least some ions supplied by the ion source into the axial passage of the front ion mirror, and, means for controlling each of the plurality of ion mirrors to trap different ones of the ions supplied by the ion source in each of the plurality of electrostatic linear ion trap regions and causing the ions trapped in each of the plurality of electrostatic linear ion trap regions to oscillate back and forth between corresponding pairs of the plurality of ion mirrors each time they pass through a corresponding one of the plurality of elongated charge detection cylinders, Wherein, the multiple electrostatic linear ion trap regions are arranged in a straight line with each other, so that the axial passages of the multiple ion mirrors and the axial passages of the multiple slender charge detection tubes are coaxial, and the longitudinal axis extending through the electrostatic linear ion trap array is centered on each of the axial passages of each of the multiple ion mirrors and each of the multiple slender charge detection tubes.

29. The charge detection mass spectrometer of claim 28, wherein: The means for controlling each of the plurality of ion mirrors includes means for directing ions supplied by the ion source into and through an axially aligned axial passageway of each of a plurality of electrostatic linear ion trap regions of the electrostatic linear ion trap array.

30. The charge detection mass spectrometer of claim 28 or 29, further comprising, a plurality of charge preamplifiers each having an input and an output, the input being coupled to a corresponding one of the plurality of elongated charge detection cylinders, each of the plurality of charge preamplifiers being configured to generate a charge detection signal at its output upon detection at the corresponding input of charges induced on a corresponding one of the plurality of elongated charge detection cylinders as a result of ions passing axially through the elongated charge detection cylinder, a processor operatively coupled to an output of each of the plurality of charge preamplifiers, and, a memory having instructions stored therein that, when executed by the processor, cause the processor to monitor outputs of the plurality of charge preamplifiers and record in the memory a plurality of sets of charge detection signals, each set of charge detection signals comprising recorded charge detection signals generated by a different one of the plurality of charge preamplifiers.

31. The charge detection mass spectrometer of claim 30, wherein: The instructions stored in the memory also include instructions that, when executed by the processor, cause the processor to process a plurality of recorded sets of charge detection signals to determine a corresponding plurality of ion charge values ​​and associated ion mass-to-charge ratios or mass values.

32. A charge detection mass spectrometer according to claim 28 or 29, wherein: The ion source comprises: an ion generator configured to generate the ions from the sample, and at least one instrument configured to separate at least some of the generated ions according to at least one molecular characteristic, Wherein, the electrostatic linear ion trap array is configured to receive at least some of the separated ions.

33. The charge detection mass spectrometer of claim 32, wherein: The at least one instrument configured to separate at least some of the generated ions includes at least one mass spectrometer configured to separate ions according to their mass-to-charge ratio.

34. A charge detection mass spectrometer according to claim 28 or 29, wherein: At least one of the plurality of electrostatic linear ion trap regions is configured to selectively allow ions to escape therefrom, And also includes at least one instrument for separating at least some ions that leave at least one of the plurality of electrostatic linear ion trap regions based on at least one molecular characteristic.

35. A method of measuring ions supplied to an ion inlet of an electrostatic linear ion trap array having a plurality of ion mirrors and a plurality of elongated charge detection cylinders, each defining a corresponding axial passageway therethrough, wherein: The plurality of elongated charge detection cylinders are arranged end-to-end in a cascade relationship, wherein different ones of the plurality of ion mirrors are respectively positioned between adjacent elongated charge detection cylinders, and wherein a first and a last one of the plurality of ion mirrors are positioned at corresponding opposite ends of the cascade arrangement, wherein the first ion mirror and the last ion mirror respectively define an ion inlet and an ion outlet of the electrostatic linear ion trap array, and wherein the axial passages of each of the plurality of ion mirrors and the elongated charge detection cylinders are co-linear with each other and define a longitudinal axis centered therethrough to form a sequence of axially aligned electrostatic linear ion trap regions, each electrostatic linear ion trap region being defined by one of the plurality of elongated charge detection cylinders and a corresponding pair of the plurality of ion mirrors at each end thereof, the method comprising: controlling at least one voltage source to apply a voltage to each of the plurality of ion mirrors to construct an ion transmission electric field therein, so that ions entering the ion entrance of the electrostatic linear ion trap array pass through each of the plurality of ion mirrors and the elongated charge detection cylinder and the ion exit of the electrostatic linear ion trap array, wherein each ion transmission electric field is configured to focus ions passing therethrough toward the longitudinal axis, and controlling the at least one voltage source to sequentially modify the voltage applied to each of the plurality of ion mirrors while maintaining the previously applied voltage to the remaining ion mirrors of the plurality of ion mirrors, starting with the last ion mirror and ending with the first ion mirror, thereby constructing an ion reflection electric field in each of the plurality of ion mirrors in a manner to sequentially trap different ions in each electrostatic linear ion trap region, wherein each ion reflection electric field is configured to cause ions entering the corresponding ion mirror from an adjacent one of the plurality of elongated charge detection cylinders to stop and accelerate back through the corresponding one of the plurality of elongated charge detection cylinders in the opposite direction, In which, under the action of the ion reflection electric field constructed in the ion mirror, the ions trapped in each electrostatic linear ion trap region oscillate back and forth between the corresponding ion mirrors of the multiple ion mirrors, and the ions pass through a corresponding one of the multiple slender charge detection cylinders each time and induce corresponding charges on it.

36. The method of claim 35, further comprising: detecting a charge induced on each of the plurality of elongated charge detection cylinders, the charge induced by a corresponding trapped ion during each passage through the elongated charge detection cylinder, and, The charge induced on each of the plurality of elongated charge detection cylinders by the corresponding trapped ion is recorded in a memory for the duration of a corresponding charge measurement event.

37. The method of claim 36, wherein: Each charge measurement event has a duration defined by one of an elapsed predetermined period of time and a predetermined number of passes of a corresponding ion through a corresponding elongated charge detection cylinder.

38. The method of claim 37, further comprising: For each of the electrostatic linear ion trap regions, at least one of an ion mass-to-charge ratio and an ion mass and an ion charge are determined based on the recorded charge.

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