Display device

Abstract

A display device is provided. The display device includes a substrate layer, a circuit layer, a light-emitting element layer, and a thin-film encapsulation layer. The substrate layer includes a display area and a non-display area. The circuit layer includes a plurality of insulating layers, at least one of which has an opening. The light-emitting element layer includes: a light-emitting region superimposed on the display area; a valley region superimposed on the opening and having a concave shape; and a peak region superimposed on the non-display area, and the light-emitting element layer is located on the circuit layer. The thin-film encapsulation layer includes an organic encapsulation layer covering at least a portion of the peak region, the light-emitting region, and the valley region.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0133196, filed on October 24, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects of embodiments of this disclosure relate to a display device. More specifically, one or more aspects of embodiments of this disclosure relate to a display device including an input sensor. Background Technology

[0003] Various display devices are being developed for use in multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and / or gaming devices. The display devices include pixels that provide images, thin-film encapsulation layers covering the pixels, and input sensors located on the thin-film encapsulation layers.

[0004] The thin-film encapsulation layer comprises an organic layer and an inorganic layer. The organic layer is formed by solidifying a liquid organic material. A method is being developed to control the expansion of the organic material to allow the formation of a structure with fluidity in the desired region.

[0005] In recent years, research has been conducted to reduce the unused space of the display panel in display devices, and essentially simultaneously, there is a need (or expectation) for development related to organic material extension structures to prevent organic materials from spilling out of the display panel (or to reduce the likelihood of organic materials spilling out of the display panel). Summary of the Invention

[0006] One or more aspects of embodiments of this disclosure relate to a display device having reduced unused space.

[0007] One or more aspects of the embodiments of this disclosure provide a display device capable of effectively (or appropriately) blocking (or reducing) the flow of an organic encapsulation layer of a thin-film encapsulation layer.

[0008] Embodiments of this disclosure provide a display device comprising: a substrate layer including a display area and a non-display area defined adjacent to the display area; a circuit layer located on the substrate layer and including a plurality of insulating layers, at least one of the plurality of insulating layers having an opening defined to pass through the at least one of the plurality of insulating layers and superimposed on the non-display area; a light-emitting element layer located on the circuit layer and including a light-emitting area superimposed on the display area, a valley region superimposed on the opening and having a concave shape, and a peak region superimposed on the non-display area; and a thin-film encapsulation layer located on the light-emitting element layer and including an organic encapsulation layer covering at least a portion of the light-emitting area and the valley region and covering at least a portion of the peak region. The light-emitting element layer includes a light-emitting element and a pixel defining layer, the light-emitting element including a first electrode located on the circuit layer, a light-emitting layer located on the first electrode, and a second electrode located on the light-emitting layer, the pixel defining layer exposing a portion of the first electrode.

[0009] The display device also includes an input sensor located on a thin-film encapsulation layer and comprising multiple sensing electrodes and multiple signal lines connected to the multiple sensing electrodes. The signal line located at the outermost position in the non-display area overlaps with the valley area.

[0010] The plurality of insulating layers include: a first insulating layer having an opening defined through the first insulating layer; and a second insulating layer located on the first insulating layer to cover the opening, a portion of the second insulating layer having a concave shape and overlapping the opening, and a valley region defined on the concave portion of the second insulating layer.

[0011] The plurality of insulating layers include: a first insulating layer; and a second insulating layer having an opening defined to extend through the second insulating layer and located on the first insulating layer, and a valley region defined on a portion of the first insulating layer exposed through the opening.

[0012] The display device also includes a peak portion located on the substrate layer and superimposed on the peak region, the peak portion comprising multiple layers, and at least one of the multiple layers of the peak portion being formed by the same process as that used for the pixel defining layer and one of the multiple insulating layers.

[0013] The display device also includes a dam superimposed on and spaced apart from the peak region, the dam comprising multiple layers, and at least one of the multiple layers of the dam being formed by the same process as one of the multiple insulating layers and pixel defining layers.

[0014] The thin-film encapsulation layer further includes a first inorganic encapsulation layer and a second inorganic encapsulation layer, with an organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the first inorganic encapsulation layer and the second inorganic encapsulation layer contacting each other in at least a portion of the peak portion.

[0015] The valley region includes an insulating pattern comprising multiple layers, at least one of the multiple layers of the insulating pattern being formed by the same process as that used for the pixel defining layer and one of the multiple insulating layers, and the distance from the substrate layer to the insulating pattern being less than the distance from the substrate layer to the peak portion.

[0016] The insulating pattern includes a first insulating pattern and a second insulating pattern spaced apart from the first insulating pattern.

[0017] Contact peak portion of the insulating pattern.

[0018] The emissive layer and pixel-defining layer are located in the emissive region.

[0019] The emissive layer is located in the emissive region, and the pixel-limiting layer is located in the emissive region, valley region, and peak region.

[0020] Embodiments of this disclosure provide a display device comprising: a substrate layer including a display area and a non-display area adjacent to the display area; a plurality of insulating layers, at least one of the plurality of insulating layers having an opening defined to pass through the at least one of the plurality of insulating layers and superimposed on the non-display area; a light-emitting element, at least a portion of which is superimposed on the display area and located on the plurality of insulating layers; a pixel defining layer located on the plurality of insulating layers and including a light-emitting area, a valley region superimposed on the opening and having a concave shape, and a peak region superimposed on the non-display area; and a thin-film encapsulation layer located on the light-emitting element and including an organic encapsulation layer covering at least a portion of the peak region, the light-emitting area, and the valley region.

[0021] The display device also includes an input sensor located on a thin-film encapsulation layer and comprising multiple sensing electrodes and multiple signal lines connected to the multiple sensing electrodes. The signal line located at the outermost position in the non-display area is superimposed on the valley region.

[0022] The light-emitting element includes a first electrode located on the plurality of insulating layers, a light-emitting layer located on the first electrode and superimposed on the display area, and a second electrode located on the light-emitting layer, wherein the pixel defining layer exposes a portion of the first electrode located in the light-emitting area.

[0023] The plurality of insulating layers include: a first insulating layer having an opening defined through the first insulating layer, and a second insulating layer located on the first insulating layer to cover the opening; a portion of the second insulating layer has a concave shape overlapping the opening, and a valley region is defined on the concave portion of the second insulating layer.

[0024] The plurality of insulating layers include: a first insulating layer; and a second insulating layer having an opening defined through the second insulating layer and located on the first insulating layer, and a valley region defined on a portion of the first insulating layer exposed through the opening.

[0025] The display device also includes a peak portion located on the substrate layer and superimposed on the peak region, the peak portion comprising multiple layers, and at least one of the multiple layers of the peak portion being formed by the same process as that used for the pixel defining layer and one of the multiple insulating layers.

[0026] The thin-film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially arranged on a substrate layer. The organic encapsulation layer covers a portion of the peak portion, a valley region, and a light-emitting element, and the first and second inorganic encapsulation layers are in contact with each other in at least a portion of the peak portion.

[0027] The valley region includes the insulating pattern, and the distance from the substrate layer to the insulating pattern is less than the distance from the substrate layer to the peak portion.

[0028] The pixel-defining layer is provided with holes that are defined in the valley region for passing through the pixel-defining layer.

[0029] Embodiments of this disclosure provide a display device comprising: a substrate layer including a display area and a non-display area adjacent to the display area; a circuit layer located on the substrate layer and including a plurality of insulating layers; a light-emitting element superimposed on the display area and including a first electrode, a light-emitting layer, and a second electrode located on the circuit layer; a pixel defining layer located on the plurality of insulating layers and exposing the first electrode; a peak portion located in the non-display area and spaced apart from the light-emitting element; a thin-film encapsulation layer covering the peak portion, the light-emitting element, and the pixel defining layer; a plurality of sensing electrodes located on the thin-film encapsulation layer; and a plurality of signal lines connected to the plurality of sensing electrodes. At least one of the plurality of insulating layers has an opening extending through it and superimposed on the non-display area, a region defined between the peak portion and the light-emitting element and superimposed on the opening is defined as a valley region, and at least one of the plurality of signal lines is superimposed on the valley region.

[0030] The thin-film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially arranged on a substrate layer. The organic encapsulation layer covers a portion of the peak portion, a valley region, and a light-emitting element, and the first and second inorganic encapsulation layers are in contact with each other in at least a portion of the peak portion.

[0031] The plurality of insulating layers include: a first insulating layer with an opening defined through the first insulating layer; and a second insulating layer located on the first insulating layer to cover the opening, a portion of the second insulating layer having a concave shape overlapping the opening, and a valley region defined on the concave portion of the second insulating layer.

[0032] The plurality of insulating layers include: a first insulating layer; and a second insulating layer having an opening defined to pass through the second insulating layer and located on the first insulating layer, and a valley region defined on the portion of the first insulating layer exposed through the opening.

[0033] The peak portion comprises multiple layers, and at least one of the multiple layers of the peak portion is formed by the same process as that used for one of the pixel defining layers and the multiple insulating layers.

[0034] The valley region includes an insulating pattern comprising multiple layers, at least one of the multiple layers of the insulating pattern being formed by the same process as that used for the pixel defining layer and one of the multiple insulating layers, and the distance from the substrate layer to the insulating pattern being less than the distance from the substrate layer to the peak portion.

[0035] The insulating pattern includes a first insulating pattern and a second insulating pattern spaced apart from the first insulating pattern.

[0036] The valley region includes an insulating pattern, and the insulating pattern has a concave shape.

[0037] Based on the above, the unused space of the display device can be reduced.

[0038] In addition, it can effectively (or appropriately) block (or reduce) the flow of organic encapsulation layers that form thin-film encapsulation layers. Attached Figure Description

[0039] The above and other advantages of this disclosure will become readily apparent when considered in conjunction with the accompanying drawings, and by referring to the following detailed description, in which:

[0040] Figure 1A This is a perspective view showing a display device according to an exemplary embodiment of the present disclosure;

[0041] Figure 1B This is a cross-sectional view showing a display device according to an exemplary embodiment of the present disclosure;

[0042] Figure 2A This is a cross-sectional view showing a display module according to an exemplary embodiment of the present disclosure;

[0043] Figure 2B This is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0044] Figure 3AThis is an equivalent circuit diagram showing pixels according to an example embodiment of the present disclosure;

[0045] Figure 3B This is an enlarged cross-sectional view showing a display panel according to an exemplary embodiment of the present disclosure;

[0046] Figures 4A to 4C This is a cross-sectional view showing a thin-film encapsulation layer according to an exemplary embodiment of the present disclosure;

[0047] Figure 5A This is a cross-sectional view showing an input sensor according to an exemplary embodiment of the present disclosure;

[0048] Figure 5B This is a plan view illustrating an input sensor according to an exemplary embodiment of the present disclosure;

[0049] Figure 5C It is along Figure 5B A sectional view taken by line I-I';

[0050] Figure 5D It is along Figure 5B A sectional view taken from line II-II';

[0051] Figure 6A and Figure 6B This is a cross-sectional view showing a display module according to an exemplary embodiment of the present disclosure;

[0052] Figures 7 to 9 This is a partial cross-sectional view showing a display module according to an exemplary embodiment of the present disclosure; and

[0053] Figures 10A to 10C and Figures 11 to 13 This is a cross-sectional view showing a display module according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0054] This disclosure can be modified and implemented in many different forms, and therefore specific embodiments will be illustrated in the accompanying drawings and described in more detail below. However, this disclosure should not be limited to the specific form disclosed and should be construed as including all modifications, equivalents, or substitutions included within the spirit and scope of this disclosure.

[0055] The same reference numerals always refer to the same elements. In the drawings, the thickness, scale, and dimensions of components are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When expressions such as "at least one of," "one of," and "selected from" follow a list of elements, they modify the entire list of elements, not individual elements within that list. Furthermore, when describing embodiments of this disclosure, the use of "may" refers to "one or more embodiments of this disclosure."

[0056] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, first component, first region, first layer, or first part discussed below may be referred to as a second element, second component, second region, second layer, or second part. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense, unless expressly stated herein.

[0058] In this disclosure, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be "directly on" the other element (without any intermediate elements in between), or intermediate elements may be present. Similarly, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "below" another element, the element may be "directly below" the other element (without any intermediate elements in between), or intermediate elements may be present. Furthermore, the term "on" in this disclosure can indicate that a portion of an element is positioned both below and above another element.

[0059] It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0060] Furthermore, in this disclosure, when an element is referred to as being "directly connected" to another element, there is no intermediate element between the layer, film, region, and / or substrate and the other layer, film, region, and / or substrate. For example, the term "directly connected" can mean that two layers or two components are joined without the use of additional adhesives between them.

[0061] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings.

[0062] Figure 1A This is a perspective view showing a display device DD according to an exemplary embodiment of the present disclosure. Figure 1B This is a cross-sectional view showing a display device DD according to an exemplary embodiment of the present disclosure.

[0063] Reference Figure 1A The display device DD may include a display surface DD-IS. The display surface DD-IS may include a display area DD-DA and a non-display area DD-NDA defined therein. The display area DD-DA may be the area through which an image IM is displayed. Figure 1A The application icon is shown as the image IM. The non-display area DD-NDA can be an area through which the image IM is not displayed. Pixels can be arranged in the display area DD-DA and may not be arranged in the non-display area DD-NDA. A pixel can refer to the effective pixels that provide the image IM.

[0064] The display area DD-DA is substantially parallel to the surface defined by the first direction DR1 and the second direction DR2. The third direction DR3 indicates the normal direction of the display area DD-DA, that is, the thickness direction of the display device DD. The front (or upper) surface and the rear (or lower) surface of each component are separated from each other by the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2 and the third direction DR3 are relative to each other and can be changed to other directions.

[0065] Figure 1AA display device DD, which can be applied to a mobile phone terminal, is shown as a representative example. In some embodiments, an electronic module, a camera module, and a power module mounted on a motherboard can be placed together with the display device DD on a bracket / housing to form a mobile phone terminal. The display device DD according to this disclosure can be applied to large electronic items such as televisions and / or monitors, as well as small and / or medium-sized electronic items such as tablet computers, car navigation units, gaming units, and / or smartwatches.

[0066] The bezel area of ​​the display device DD may be defined by a non-display area DD-NDA. The non-display area DD-NDA may be defined as adjacent to the display area DD-DA. The non-display area DD-NDA may surround the display area DD-DA. However, according to another example embodiment, the non-display area DD-NDA and the display area DD-DA may have shapes designed relative to each other. According to another example embodiment, the non-display area DD-NDA may be omitted.

[0067] In the exemplary embodiments of this disclosure, the display device DD includes a flat-shaped display surface DD-IS; however, the display surface DD-IS is not limited to a flat shape. The display device DD may include a curved display surface or a three-dimensional display surface. A three-dimensional display surface may include multiple display areas facing different directions from each other.

[0068] Reference Figure 1B The display device DD may include a window WM, an optical layer LM, a display module DM, a protective film PM, a first adhesive layer AM1, a second adhesive layer AM2, and a third adhesive layer AM3. The display module DM may be located between the protective film PM and the optical layer LM. The optical layer LM may be located between the display module DM and the window WM. The first adhesive layer AM1 attaches the display module DM to the protective film PM, the second adhesive layer AM2 attaches the display module DM to the optical layer LM, and the third adhesive layer AM3 attaches the optical layer LM to the window WM. In some embodiments, the first adhesive layer AM1, the second adhesive layer AM2, and / or the third adhesive layer AM3 may be omitted.

[0069] The protective film PM protects the display module DM. The protective film PM provides (including) an externally exposed surface and an adhesive surface attached to the first adhesive layer AM1. The protective film PM prevents or reduces the ingress of external moisture into the display module DM and substantially absorbs external impacts.

[0070] The window WM protects the display module DM from external impacts and provides an input surface for the user. The window WM may include a plastic film as its base component. The window WM may have a multi-layered structure. The base component of the window WM may have a multi-layered structure selected from glass substrates, plastic films, and plastic substrates. The window WM may also include a frame pattern. The multi-layered structure can be formed by a continuous process or an adhesive bonding process. Furthermore, the window WM may include functional layers located on the base component. Functional layers may include a hard coating, an anti-fingerprint layer, an anti-reflective layer, and / or a self-healing layer.

[0071] An optical layer LM can reduce the reflectivity of external light incident upon it. The optical layer LM may include at least a polarizer. The optical layer LM may also include a retarder. According to embodiments of this disclosure, the optical layer LM may be omitted.

[0072] The display module DM may include a display panel DP and an input sensor IS. The display panel DP may be an organic light-emitting display panel; however, the display panel DP should not be particularly limited. For example, the display panel DP may be a quantum dot light-emitting display panel as another type of self-emitting display panel. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods. In the following, organic light-emitting display panels will be described as representative examples of display panel DPs.

[0073] The input sensor IS is located directly on the display panel DP. In this disclosure, "directly on" means formed by a continuous process, rather than attached using a separate adhesive layer.

[0074] The display panel (DP) can generate an image (IM) corresponding to the image data input to it (see reference). Figure 1A In this example embodiment, the organic light-emitting display panel is described as a representative example; however, the display panel DP should not be limited to organic light-emitting display panels.

[0075] An input sensor (IS) can acquire coordinate information from external inputs. For example, an input sensor (IS) can sense external inputs using capacitive methods. The operation of an input sensor (IS) should not be subject to special restrictions. For example, an input sensor (IS) can sense external inputs using electromagnetic induction and / or pressure sensing methods.

[0076] In some embodiments, the display module DM according to exemplary embodiments of this disclosure may further include an anti-reflective layer. The anti-reflective layer may include a color filter or a stacked structure of conductive / insulating / conductive layers. Light incident on the display module DM from the outside can be absorbed, destructively interfered with, and / or polarized by the anti-reflective layer, thus reducing the reflectivity of external light. The anti-reflective layer can replace the function of the optical layer LM.

[0077] Each of the first adhesive layer AM1, the second adhesive layer AM2, and the third adhesive layer AM3 can be an organic adhesive layer, such as an optically transparent adhesive (OCA) film, an optically transparent resin (OCR), and / or a pressure-sensitive adhesive (PSA) film. The organic adhesive layer may include adhesive materials such as polyurethane adhesives, acrylic adhesives, polyester adhesives, epoxy adhesives, and / or polyvinyl acetate adhesives.

[0078] In some embodiments, depending on the shape of the display panel DP, the display device DD may further include a frame structure supporting the aforementioned components. For example, in the case where the display device DD includes a foldable display panel, the frame structure may have a joining structure or a hinge structure.

[0079] Figure 2A This is a cross-sectional view showing a display module DM according to an exemplary embodiment of the present disclosure. Figure 2B This is a plan view showing a display panel DP according to an example embodiment of the present disclosure. Figure 3A This is an equivalent circuit diagram illustrating a pixel PXi according to an example embodiment of the present disclosure. Figure 3B This is an enlarged cross-sectional view showing a display panel DP according to an exemplary embodiment of the present disclosure.

[0080] Reference Figure 2A The display module DM may include a display panel DP and an input sensor IS. The display panel DP may include a substrate layer BL, a circuit layer DP-CL disposed on the substrate layer BL, a light-emitting element layer DP-OLED, and a thin-film encapsulation layer TFE. The substrate layer BL may include at least one plastic film. The substrate layer BL may include a plastic substrate, a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate as a flexible substrate.

[0081] The DP-CL circuit layer may include at least one insulating intermediate layer, multiple conductive layers, and a semiconductor layer. The conductive layers of the DP-CL circuit layer may form the signal lines or driving circuitry of a pixel. The DP-OLED light-emitting element layer may include an OLED light-emitting element (see...). Figure 3A A thin-film encapsulation layer (TFE) can encapsulate the DP-OLED light-emitting element layer. The TFE can include inorganic and organic layers. Specifically, the TFE can include at least two inorganic layers and an organic layer located between the two inorganic layers. The inorganic layers protect the DP-OLED light-emitting element layer from moisture and oxygen, while the organic layers protect it from foreign substances such as dust particles. The inorganic layers can include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide layers. The organic layers can include acrylic organic layers; however, the organic layers should not be limited to or restricted by this.

[0082] The input sensor IS can be located directly on the thin-film encapsulation layer TFE. The input sensor IS can include sensing electrodes and signal lines. The sensing electrodes and signal lines can have a single-layer or multi-layer structure.

[0083] The sensing electrodes and signal lines may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and / or graphene. The sensing electrodes and signal lines may include metal layers, including, for example, molybdenum, silver, titanium, copper, aluminum, or any alloy thereof. The sensing electrodes and signal lines may have the same or different layer structures. A more detailed description of the input sensor IS will be provided later.

[0084] like Figure 2B As shown, the display panel DP may include a display area DP-DA and a non-display area DP-NDA. In this example embodiment, the non-display area DP-NDA may be defined along the edge of the display area DP-DA. The display area DP-DA and the non-display area DP-NDA of the display panel DP may correspond to the display area DD-DA and the non-display area DD-NDA of the display device DD, respectively. The display area DP-DA and the non-display area DP-NDA of the display panel DP do not necessarily have to be the same as the display area DD-DA and the non-display area DD-NDA of the display device DD, and may vary depending on the structure / design of the display panel DP.

[0085] The display panel DP may include a driving circuit GDC, multiple signal lines SL-Vint, SL-VDD, EL, GL, DL and SL-D, power electrodes, and multiple pixels PX. The area where the pixels PX are arranged can be defined as the display area DP-DA.

[0086] The driving circuit GDC may include a scan driving circuit GDC. The scan driving circuit GDC can generate multiple scan signals and can sequentially output the scan signals to multiple scan lines GL. In addition, the scan driving circuit GDC can generate multiple light emission control signals and can sequentially output the light emission control signals to multiple light emission control lines EL.

[0087] exist Figure 2B In this embodiment, multiple scan signals and multiple light emission control signals are output from a single scan driver circuit GDC; however, they should not be limited to or restricted by this. According to another embodiment, the multiple scan driver circuits can divide and output multiple scan signals, and can also divide and output multiple light emission control signals. According to another embodiment, the driver circuit that generates and outputs multiple scan signals and the driver circuit that generates and outputs multiple light emission control signals can be arranged separately from each other. Another scan driver circuit can be further disposed in the display panel DP to face the second direction DR2. Figure 2B The scanning drive circuit GDC is shown in the figure.

[0088] The scan drive circuit GDC may be included in the circuit layer DP-CL. The scan drive circuit GDC may include multiple thin-film transistors formed using the same process as the drive circuit of the pixel PX.

[0089] In some embodiments, the display panel DP may further include data driving circuitry bonded to the pad (also known as a "soldering pad") PD using a chip-on-film (COF) method. In exemplary embodiments of this disclosure, the data driving circuitry may also be integrated into the circuit layer DP-CL.

[0090] Signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D may include scan line GL, light control line EL, data line DL, power line SL-VDD, initialization voltage line SL-Vint, and dummy signal line SL-D. Signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D may be included in the circuit layer DP-CL, and some lines of signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D may be omitted. Pad PD may be connected to the ends of signal lines GL, DL, EL, SL-VDD, SL-Vint, and SL-D.

[0091] Scan lines GL can be connected to the corresponding pixels in pixel PX, and data lines DL can be connected to the corresponding pixels in pixel PX. Each of the light emission control lines EL can be arranged substantially parallel to the corresponding scan line in scan lines GL.

[0092] The power line SL-VDD can be connected to the pixel PX and can provide a first power voltage to the pixel PX. The power line SL-VDD can include multiple lines extending in a first direction DR1 and multiple lines extending in a second direction DR2.

[0093] The initialization voltage line SL-Vint can initialize the voltage Vint (see...) Figure 3A The initialization voltage line SL-Vint can include multiple lines extending in the first direction DR1 and multiple lines extending in the second direction DR2.

[0094] The dummy signal line SL-D can provide a control signal to the scan drive circuit GDC. The dummy signal line SL-D can also provide a second power voltage to the power electrodes. This second power voltage can have a different level than the first power voltage. The second power voltage can also have a lower level than the first power voltage.

[0095] Figure 3AThe i-th pixel PXi, connected to the k-th data line DLk among multiple data lines DL, is shown as a representative example. The i-th pixel PXi is activated in response to the i-th scan signal Si applied to the i-th scan line GLi.

[0096] The i-th pixel PXi may include a pixel driving circuit CC to control a light-emitting element OLED. The light-emitting element OLED may emit light at a predetermined (or set) brightness in response to the amount of current supplied from the pixel driving circuit CC. The potential of a first power supply voltage ELVDD may be set to be higher than the potential of a second power supply voltage ELVSS. The first power supply voltage ELVDD is supplied to the power line SL-VDD.

[0097] The pixel driving circuit CC may include seven thin-film transistors T1 to T7 and a capacitor Cst. However, the pixel driving circuit CC including seven thin-film transistors T1 to T7 and a capacitor Cst is only an example, and the pixel driving circuit CC can be changed in various ways.

[0098] The driving transistor controls the driving current supplied to the OLED light-emitting element. The output electrode of the second transistor T2 can be electrically connected to the OLED light-emitting element. The output electrode of the second transistor T2 can be connected to the OLED light-emitting element via the sixth transistor (or pixel transistor) T6.

[0099] The sixth transistor T6 can be connected between the output electrode of the first transistor T1 and the first electrode EL1 (see reference). Figure 3B Between the first electrode EL1 and the second electrode EL2, the first electrode EL1 is the anode electrode of the OLED light-emitting element. The control electrode of the sixth transistor T6 can be connected to the i-th light-emitting control line ELi.

[0100] The control electrode of the control transistor can receive control signals. The control signal applied to the i-th pixel PXi may include the (i-1)-th scan signal Si-1 applied to the (i-1)-th scan line GLi-1, the i-th scan signal Si, the (i+1)-th scan signal Si+1 applied to the (i+1)-th scan line GLi+1, the data signal Dk, and the i-th emission control signal Ei. In an example embodiment, the control transistor may include a first transistor T1 and third transistors T3 through seventh transistors T7.

[0101] The first transistor T1 may include a sensing electrode connected to the k-th data line DLk, a control electrode connected to the i-th scan line GLi, and an output electrode connected to the output electrode of the second transistor T2. The first transistor T1 may be turned on in response to a scan signal Si (hereinafter referred to as the "i-th scan signal") applied to the i-th scan line GLi, and may provide the data signal Dk applied to the k-th data line DLk to the capacitor Cst.

[0102] Reference Figure 3B A display panel (DP) may include multiple insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers, semiconductor layers, and conductive layers can be formed through coating and deposition processes. Then, the insulating layers, semiconductor layers, and conductive layers can be selectively patterned using photolithography. The semiconductor patterns, conductive patterns, and signal lines included in the circuit layer (DP-CL) and the light-emitting element layer (DP-OLED) can be formed using the methods described above.

[0103] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The substrate layer BL may have a multilayer structure. For example, the substrate layer BL may have a three-layer structure comprising a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In some embodiments, the synthetic resin layer may be a polyimide resin layer; however, the synthetic resin layer is not particularly limited. The synthetic resin layer may include at least one of acrylic resins, methacrylic resins, polyisoprene, ethylene resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. Furthermore, the substrate layer BL may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate.

[0104] At least one inorganic layer may be formed on the upper surface of the substrate layer BL. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Multiple inorganic layers may be provided. The inorganic layer may form a barrier layer and / or a buffer layer. In this example embodiment, the display panel DP may include a buffer layer BFL.

[0105] The buffer layer (BFL) can improve the adhesion between the substrate layer (BL) and the semiconductor pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately on top of each other.

[0106] Semiconductor patterns may be disposed on the buffer layer BFL. Semiconductor patterns may include polycrystalline silicon; however, semiconductor patterns should not be limited to or restricted by this. Semiconductor patterns may include amorphous silicon and / or metal oxides.

[0107] Figure 3B Only some semiconductor patterns are shown in the planar view, and additional semiconductor patterns can be further disposed on other areas of pixel PX. Semiconductor patterns can be arranged in a specific (or predetermined) configuration on pixel PX. Semiconductor patterns can have different electrical characteristics depending on their doping state. Semiconductor patterns can include doped and undoped regions. Doped regions can be doped with N-type or P-type dopant. A P-type transistor can include a doped region doped with P-type dopant.

[0108] Doped regions can have higher conductivity than undoped regions and can be essentially used as electrodes or signal lines. Undoped regions can correspond to the active (or channel) portion of a transistor. For example, a portion of a semiconductor pattern can be the active portion of a transistor, another portion of the semiconductor pattern can be the source or drain of a transistor, and said other portion of the semiconductor pattern can be a connection electrode or a connection signal line.

[0109] like Figure 3B As shown, the source S1, active portion A1, and drain D1 of the first transistor T1 can be formed by a semiconductor pattern, and the source S6, active portion A6, and drain D6 of the sixth transistor T6 can be formed by a semiconductor pattern. The sources S1 and S6, and the drains D1 and D6, can extend in opposite directions from the active portions A1 and A6 in the cross-section. A portion of the connecting signal line can be formed by a semiconductor pattern.

[0110] The first intermediate insulating layer 10 may be located on the buffer layer BFL. The first intermediate insulating layer 10 may be stacked together with the pixel PX and may cover the semiconductor pattern. The first intermediate insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first intermediate insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this example embodiment, the first intermediate insulating layer 10 may be a silicon oxide layer with a single-layer structure. In some embodiments, the insulating layer of the circuit layer DP-CL (described in more detail later) may also include an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above.

[0111] Gates G1 and G6 can be disposed on the first intermediate insulating layer 10. Gate G1 can be part of a metal pattern. Gates G1 and G6 can be stacked with active portions A1 and A6, respectively. Gates G1 and G6 can act as masks in the doping process of the semiconductor pattern.

[0112] The second intermediate insulating layer 20 may be located on the first intermediate insulating layer 10 to cover gates G1 and G6. The second intermediate insulating layer 20 may be stacked together with the pixel PX. The second intermediate insulating layer 20 may include inorganic and / or organic layers and may have a single-layer or multi-layer structure. In this example embodiment, the second intermediate insulating layer 20 may be a silicon oxide layer with a single-layer structure.

[0113] The first connection electrode SD1 can be located on the second intermediate insulating layer 20. The first connection electrode SD1 can be connected to the connection signal line through the contact hole CNT-1 defined by the first intermediate insulating layer 10 and the second intermediate insulating layer 20.

[0114] The first insulating layer 30 may be located on the second intermediate insulating layer 20. The first insulating layer 30 may be, but is not limited to, an organic layer. The second connecting electrode SD2 may be located on the first insulating layer 30. The second connecting electrode SD2 may be connected to the first connecting electrode SD1 through a contact hole CNT-2 defined by the first insulating layer 30.

[0115] A second insulating layer 40 may be located on the first insulating layer 30 to cover the second connecting electrode SD2. The second insulating layer 40 may be, but is not limited to, an organic layer. A first electrode EL1 may be located on the second insulating layer 40. The first electrode EL1 may be connected to the second connecting electrode SD2 through a contact hole CNT-3 defined through the second insulating layer 40. An opening OP may be defined through the pixel defining layer PDL. At least a portion of the first electrode EL1 may be exposed through the opening OP of the pixel defining layer PDL.

[0116] like Figure 3B As shown, the display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may surround the light-emitting area PXA. In this example embodiment, the light-emitting area PXA may be defined to correspond to the portion of the first electrode EL1 exposed by the opening OP of the pixel-defining layer PDL.

[0117] A hole control layer (HCL) can be commonly disposed within the emitting region PXA and the non-emitting region NPXA. The HCL may include a hole transport layer and may also include a hole injection layer. An emitting layer (EML) may be located on the HCL. The EML may be located in the region corresponding to the opening (OP). That is, the EML may be formed in each pixel PX after being divided into multiple parts.

[0118] The electronic control layer (ECL) can be located on the light-emitting layer (EML). The ECL may include an electron transport layer and may also include an electron injection layer. A hole control layer (HCL) and the ECL can be jointly formed in multiple pixels (PX) using an aperture mask. The second electrode (EL2) can be located on the ECL. The second electrode (EL2) can have a monolithic shape and can be jointly disposed in multiple pixels (PX).

[0119] The thin-film encapsulation layer TFE can be located on the second electrode EL2. The thin-film encapsulation layer TFE can be disposed together within the pixel PX. In this example embodiment, the thin-film encapsulation layer TFE can directly cover the second electrode EL2. In an example embodiment of this disclosure, a capping layer can be further disposed between the thin-film encapsulation layer TFE and the second electrode EL2 to cover the second electrode EL2. In this case, the thin-film encapsulation layer TFE can directly cover the capping layer.

[0120] Figures 4A to 4C These are cross-sectional views showing thin-film encapsulation layers TFE1, TFE2, and TFE3 according to exemplary embodiments of the present disclosure.

[0121] Reference Figure 4A The thin-film encapsulation layer TFE1 may include n inorganic layers IOL1 to IOLn. The thin-film encapsulation layer TFE1 may include n-1 organic layers OL1 to OLn-1, and the n-1 organic layers OL1 to OLn-1 may be stacked alternately with the n inorganic layers IOL1 to IOLn. The n-1 organic layers OL1 to OLn-1 may have an average thickness greater than that of the n inorganic layers IOL1 to IOLn.

[0122] Each of the n inorganic layers IOL1 to IOLn can have a single-layer structure of a single material or a multi-layer structure of different materials. Each of the n-1 organic layers OL1 to OLn-1 can be formed by deposition, printing, or coating of organic monomers. The organic monomers may include acrylic monomers.

[0123] like Figure 4B and Figure 4C As shown, the inorganic layers included in each of the thin-film encapsulation layers TFE2 and TFE3 may comprise the same or different inorganic materials, and may have the same or different thicknesses. The organic layers included in the thin-film encapsulation layers TFE2 and TFE3 may comprise the same or different organic materials, and may have the same or different thicknesses.

[0124] like Figure 4B As shown, the thin-film encapsulation layer TFE2 may include a first inorganic encapsulation layer IOL1, a first organic encapsulation layer OL1, a second inorganic encapsulation layer IOL2, a second organic encapsulation layer OL2, and a third inorganic encapsulation layer IOL3.

[0125] The first inorganic encapsulation layer IOL1 can have a two-layer structure with a first sublayer S11 and a second sublayer S22. The first sublayer S11 and the second sublayer S22 can be made of different inorganic materials.

[0126] like Figure 4CAs shown, the thin-film encapsulation layer TFE3 may include a first inorganic encapsulation layer IOL10, a first organic encapsulation layer OL1, and a second inorganic encapsulation layer IOL20. The first inorganic encapsulation layer IOL10 may have a two-layer structure with a first sublayer S10 and a second sublayer S20. The first sublayer S10 and the second sublayer S20 may have different inorganic materials. The second inorganic encapsulation layer IOL20 may have a two-layer structure. The second inorganic encapsulation layer IOL20 may include a first sublayer S100 and a second sublayer S200 deposited under different environments. The first sublayer S100 may be deposited under low power conditions, and the second sublayer S200 may be deposited under high power conditions. The first sublayer S100 and the second sublayer S200 may include the same inorganic material.

[0127] Figure 5A This is a cross-sectional view showing an input sensor IS according to an exemplary embodiment of the present disclosure. Figure 5B This is a plan view illustrating an input sensor IS according to an exemplary embodiment of the present disclosure. Figure 5C It is along Figure 5B A sectional view taken by line I-I'. Figure 5D It is along Figure 5B The sectional view taken from line II-II'.

[0128] Reference Figure 5A The input sensor IS may include a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1, a second sensing insulating layer IS-IL2, a second conductive layer IS-CL2, and a third sensing insulating layer IS-IL3. The first sensing insulating layer IS-IL1 may be located directly on the thin-film encapsulation layer TFE. In the exemplary embodiments of this disclosure, the first sensing insulating layer IS-IL1 may be omitted.

[0129] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a monolayer structure or a multilayer structure of layers stacked on a third-direction DR3. The conductive layer with a multilayer structure may include at least two layers selected from transparent conductive layers and metal layers. The conductive layer with a multilayer structure may include metal layers containing different metals from each other. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and / or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or any alloy thereof. For example, each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may have a titanium / aluminum / titanium trilayer structure. A metal with relatively high durability and low reflectivity may be applied as the top layer of the trilayer structure, and a metal with high conductivity may be applied as the bottom layer of the trilayer structure.

[0130] Each of the first conductive layer IS-CL1 and the second conductive layer IS-CL2 may include multiple conductive patterns. Hereinafter, the first conductive layer IS-CL1 will be described as including a first conductive pattern, and the second conductive layer IS-CL2 will be described as including a second conductive pattern. Each of the first and second conductive patterns may include a sensing electrode and a signal line connected to the sensing electrode.

[0131] Each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3 may include an inorganic layer or an organic layer. In this example embodiment, the first sensing insulating layer IS-IL1 and the second sensing insulating layer IS-IL2 may be inorganic layers. Inorganic layers may include at least one selected from alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The third sensing insulating layer IS-IL3 may include an organic layer. Organic layers may include at least one selected from acrylic resins, methacrylic resins, polyisoprene, ethylene resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0132] In this example embodiment, the second sensing insulating layer IS-IL2 may cover the sensing region IS-DA, which is described in more detail below. For example, the second sensing insulating layer IS-IL2 may completely overlap with the sensing region IS-DA. In some embodiments, the second sensing insulating layer IS-IL2 may include a plurality of insulating patterns. The insulating patterns may be disposed at each intersection region of the sensing unit SU to insulate the first sensing electrodes IE1-1 to IE1-10 and the second sensing electrodes IE2-1 to IE2-8.

[0133] like Figure 5B As shown, the input sensor IS may include a first electrode group EG1, a second electrode group EG2, and signal line groups connected to the first electrode group EG1 and the second electrode group EG2. In this example embodiment, an input sensor IS including two signal line groups SG1 and SG2 is shown as a representative example. The input sensor IS may include a sensing area IS-DA and a line area IS-NDA corresponding to the display area DP-DA and the non-display area DP-NDA of the display panel DP, respectively. The sensing area IS-DA may be defined as the area in which the first electrode group EG1 and the second electrode group EG2 are located. The first signal line group SG1 and the second signal line group SG2 may be located in the line area IS-NDA.

[0134] In this example embodiment, the input sensor IS can be, but is not limited to, a capacitive (or similar) touch sensor. One of the electrode groups EG1 and EG2 can receive a drive signal, and the other of the electrode groups EG1 and EG2 can output the capacitance change between the first electrode group EG1 and the second electrode group EG2 as a sensing signal.

[0135] The first electrode group EG1 may include a plurality of first sensing electrodes IE1-1 to IE1-10. A first electrode group EG1 including ten first sensing electrodes IE1-1 to IE1-10 is shown as a representative example. The first sensing electrodes IE1-1 to IE1-10 may have a shape extending in the second direction DR2. The second electrode group EG2 may include a plurality of second sensing electrodes IE2-1 to IE2-8. A second electrode group EG2 including eight second sensing electrodes IE2-1 to IE2-8 is shown as a representative example. The second sensing electrodes IE2-1 to IE2-8 may have a shape extending in the first direction DR1. The second sensing electrodes IE2-1 to IE2-8 may have a length greater than the length of the first sensing electrodes IE1-1 to IE1-10.

[0136] The first signal line group SG1 may include the same number of first signal lines as the number of first sensing electrodes IE1-1 to IE1-10. Each first signal line may be connected to only one end of the first sensing electrodes IE1-1 to IE1-10. In this example embodiment, both ends of the first sensing electrodes IE1-1 to IE1-10 may be connected to the first signal lines.

[0137] The second signal line group SG2 may include the same number of second signal lines as the number of second sensing electrodes IE2-1 to IE2-8. Each second signal line may be connected to only one end of the second sensing electrodes IE2-1 to IE2-8. In this example embodiment, the eight signal lines of the second signal line group SG2 are respectively connected to the lower ends of the second sensing electrodes IE2-1 to IE2-8.

[0138] In this example embodiment, the first signal line can be divided into two groups. One group can be defined as a first-side signal line group SG1-1, and the other group can be defined as a second-side signal line group SG1-2. The first-side signal line group SG1-1 can be connected to some of the first sensing electrodes IE1-1 to IE1-10, and the second-side signal line group SG1-2 can be connected to the other first sensing electrodes IE1-1 to IE1-10. The first-side signal line group SG1-1 and the second-side signal line group SG1-2 can be spaced apart from each other in the second direction DR2, and the sensing region IS-DA is located between the first-side signal line group SG1-1 and the second-side signal line group SG1-2. Since the first signal line is divided into two groups and positioned on both sides, the width of the line region IS-NDA on each side of the sensing region IS-DA can be reduced.

[0139] The first side signal line group SG1-1 can be electrically connected to either the odd-numbered or even-numbered sensing electrodes among the first sensing electrodes IE1-1 to IE1-10. The second side signal line group SG1-2 can be connected to sensing electrodes not connected to the first side signal line group SG1-1. In this example embodiment, the five signal lines in the first side signal line group SG1-1 are respectively connected to the right end of the even-numbered first sensing electrodes.

[0140] Each of the first sensing electrodes IE1-1 to IE1-10 may include a plurality of first sensor portions SP1 and a plurality of first connecting portions CP1. The first sensor portions SP1 may be arranged on the second direction DR2. Each of the first connecting portions CP1 may connect two adjacent first sensor portions SP1.

[0141] Each of the second sensing electrodes IE2-1 to IE2-8 may include a plurality of second sensor portions SP2 and a plurality of second connecting portions CP2. The second sensor portions SP2 may be arranged on the first direction DR1. Each of the second connecting portions CP2 may connect two adjacent second sensor portions SP2.

[0142] Reference Figure 5B The sensing area IS-DA can be divided into multiple sensing units SU. The sensing units SU can have the same area as each other. Each sensing unit SU can include a corresponding intersection region among the intersection regions defined by the first sensing electrodes IE1-1 to IE1-10 and the second sensing electrodes IE2-1 to IE2-8. The intersection region can be an area in which a bridging pattern is provided.

[0143] In exemplary embodiments of this disclosure, the sensing units SU may include the same grid pattern. In this disclosure, the grid pattern may be defined by intersecting grid lines of the sensing electrodes. In exemplary embodiments of this disclosure, the sensing units SU may be classified into multiple groups based on the shape of the grid pattern in the sensing unit SU. Sensing units SU included in the same group may have the same grid pattern.

[0144] Figure 5C It shows along Figure 5B The cross section taken by line I-I'. Figure 5C An example is shown in which the first connecting portion CP1 and the second connecting portion CP2 intersect. In this example embodiment, the first connecting portion CP1 may correspond to a bridging pattern. In the example embodiment of this disclosure, the second connecting portion CP2 may correspond to a bridging pattern.

[0145] Reference Figure 5B and Figure 5C The first connection portion CP1 can be formed using the first conductive layer IS-CL1; and the first sensor portion SP1, the second sensor portion SP2, and the second connection portion CP2 can be formed using the second conductive layer IS-CL2. The first sensor portion SP1 can be connected to the first connection portion CP1 through a contact hole CNT-I defined by the second sensing insulating layer IS-IL2.

[0146] In this example embodiment, the first connecting portion CP1 intersects with the second connecting portion CP2; however, they should not be limited thereto or thereby restricted. For example, each of the first connecting portions CP1 can be changed to a curved shape “∧” and / or a curved shape “∨” so as not to overlap with the second connecting portion CP2. When viewed in a plan view, the first connecting portion CP1 with the curved shape “∧” and / or the curved shape “∨” can overlap with the second sensor portion SP2.

[0147] According to this disclosure, the signal lines of the first signal line group SG1 and the second signal line group SG2 may include at least one of the portions located on the same layer as the first sensing electrodes IE1-1 to IE1-10 and the portions located on the same layer as the second sensing electrodes IE2-1 to IE2-8.

[0148] Figure 5D It shows along Figure 5BA cross-section taken from line II-II'. The fourth signal line SG1-14 and the fifth signal line SG1-15 of the first signal line group SG1-1 are shown as representative examples. The signal lines of the first signal line group SG1 and the second signal line group SG2 may include at least a portion located on the same layer as the second sensing electrodes IE2-1 to IE2-8. The signal lines of the first signal line group SG1 and the second signal line group SG2 may be formed using the second conductive layer IS-CL2.

[0149] The signal lines of the first signal line group SG1 and the second signal line group SG2 may further include portions formed using a first conductive layer IS-CL1. The portions formed using a second conductive layer IS-CL2 and the portions formed using the first conductive layer IS-CL1 can be connected to each other through contact holes defined by a second sensing insulating layer IS-IL2. Signal lines having the aforementioned two-layer structure can have low resistance.

[0150] Figure 6A and Figure 6B This is a cross-sectional view showing display modules DM and DM-1 according to an exemplary embodiment of the present disclosure.

[0151] Figures 7 to 9 This is a partial cross-sectional view showing a display module DM according to an exemplary embodiment of the present disclosure.

[0152] Figures 10A to 10C and Figures 11 to 13 This is a cross-sectional view showing display modules DM-2, DM-3, DM-4, ​​DM-5, DM-6 and DM-7 according to exemplary embodiments of the present disclosure.

[0153] Figure 6A It is along Figure 5B The cross-sectional view taken by line III-III' corresponds to a portion of the display module DM. The stacked structure of the buffer layer BFL, circuit layer DP-CL, light-emitting element layer DP-OLED, and thin-film encapsulation layer TFE located in the display area DA can be compared with the reference. Figure 3B , Figures 4A to 4C The described stacked structures are essentially the same; therefore, redundant details will not be provided. However, the hole control layer (HCL) and the electronic control layer (ECL) are not shown. The stacked structure of the input sensor IS in the display area DA may also be the same as the reference. Figures 5A to 5D The constructions described are essentially the same; therefore, redundant details will not be provided. A thin-film encapsulation layer TFE, comprising a first inorganic encapsulation layer IOL1, an organic encapsulation layer OL, and a second inorganic encapsulation layer IOL2, is shown as a representative example. The non-display area NDA will be described primarily below.

[0154] The scan drive circuit GDC forming the circuit layer DP-CL can be located in the non-display area NDA. The scan drive circuit GDC may include at least one transistor GDC-T formed using the same process as the pixel transistor T6. The scan drive circuit GDC may include signal lines located on the same layer as the sensing electrode of the pixel transistor T6. The initialization voltage line SL-Vint can be located on the same layer as the sensing electrode of the pixel transistor T6. The initialization voltage line SL-Vint and the sensing electrode of the pixel transistor T6 can be formed using the same process; therefore, they can have the same layer structure and the same materials.

[0155] The substrate layer BL may include the display area DA and the non-display area NDA. The non-display area NDA of the substrate layer BL may surround the display area DA. The non-display area NDA may be the edge portion of the display panel DP.

[0156] The circuit layer DP-CL of the example embodiment may include a first insulating layer 30 and a second insulating layer 40 sequentially stacked on a second intermediate insulating layer 20. Both the first insulating layer 30 and the second insulating layer 40 may be independently organic layers comprising organic materials. The first insulating layer 30 and the second insulating layer 40 may be patterned.

[0157] like Figure 6A As shown, in the display module DM, the first insulating layer 30 can be patterned on the second intermediate insulating layer 20. For example, the opening OP1 can be defined to penetrate the first insulating layer 30 to expose the second intermediate insulating layer 20.

[0158] The second insulating layer 40 may be located on the first insulating layer 30. Alternatively, the second insulating layer 40 may be located on the first insulating layer 30 and the second intermediate insulating layer 20 exposed through the opening OP1. Therefore, due to the height difference between the first insulating layer 30 and the second intermediate insulating layer 20, a step difference may be formed on a portion of the second insulating layer 40. Due to the step difference, some areas of the second insulating layer 40 may have a concave shape.

[0159] A DP-OLED light-emitting element layer can be formed on a DP-CL circuit layer. The DP-OLED light-emitting element layer may include a light-emitting region EA, a valley region VA, and a peak region PA. At least a portion of the light-emitting region EA may be stacked with the display region DA. The valley region VA may be defined as adjacent to the light-emitting region EA. The valley region VA may be adjacent to openings OP1 and OP2 (see...). Figure 6B They can be stacked and can have a concave shape. Openings OP1 and OP2 (see...) Figure 6BThe descriptions of the peak region PA are the same as those described here. The peak region PA can be defined as adjacent to the valley region VA. That is, the valley region VA can be defined between the luminescent region EA and the peak region PA. The peak region PA can be overlaid with the non-display region NDA.

[0160] The DP-OLED light-emitting element layer may include a light-emitting element OLED and a pixel-defining layer PDL located on the circuit layer DP-CL. The light-emitting element OLED may include a first electrode EL1 located on the circuit layer DP-CL, a light-emitting layer EML located on the first electrode EL1, and a second electrode EL2 located on the light-emitting layer EML. The pixel-defining layer PDL may expose a portion of the first electrode EL1. The light-emitting layer EML may be located on the first electrode EL1 exposed through the pixel-defining layer PDL.

[0161] In this disclosure, the layer referred to as the "insulating layer" may include a material substantially the same as that of the pixel-defining layer (PDL) and may be formed by a process identical to that of the PDL. The insulating layer may include light-emitting regions, valley regions, and peak regions. The light-emitting regions of the insulating layer may perform functions substantially the same as those of the PDL. For example, the insulating layer may expose a portion of the first electrode EL1 in the light-emitting region EA. The description of the light-emitting regions of each insulating layer may be substantially the same as the description of the PDL. The descriptions of the valley regions VA and peak regions PA of the DP-OLED light-emitting element layer may be equivalently applied to the valley regions and peak regions of the insulating layer.

[0162] According to an embodiment, a portion of the light-emitting element (OLED) can be located in the light-emitting region EA. For example, the light-emitting layer (EML) can be located in the light-emitting region EA. The light-emitting layer (EML) can be stacked with the display region DA. The image IM can be displayed through the display region DA by light emitted from the light-emitting layer (EML). Because the light-emitting region EA is defined in the light-emitting element layer DP-OLED and the display region DA is defined in the substrate layer BL, the light-emitting region EA and the display region DA can be mismatched.

[0163] Display modules DM and DM-1 may include a peak portion PK located on the substrate layer BL and superimposed on the peak region PA. The peak portion PK may include multiple layers. For example, the multiple layers may include a first peak portion PK1 and a second peak portion PK2 stacked sequentially. According to an embodiment, at least one of the layers of the peak portion PK may be formed by the same process as that used for the first insulating layer 30, the second insulating layer 40, and the pixel defining layer PDL. The first peak portion PK1 may include the same material as the second insulating layer 40 and may be formed by the same process as that used for the second insulating layer 40. The second peak portion PK2 may include the same material as the pixel defining layer PDL and may be formed by the same process as that used for the pixel defining layer PDL; however, the exemplary embodiments should not be limited thereto or thereby restricted. In addition to the first peak portion PK1 and the second peak portion PK2, the peak portion PK may also include another layer. For example, the peak portion PK may also include a layer PK0 formed by the same process as that used for the first insulating layer 30. Since the peak portion PK includes layer PK0 (formed by the same process as the first insulating layer 30), the first peak portion PK1 and the second peak portion PK2, the peak portion PK can have a relatively convex shape compared to the circuit layer DP-CL.

[0164] According to an example embodiment, the peak region PA may further include dam DAMs spaced apart from the peak portion PK. The dam DAMs may include multiple layers. For example, the multiple layers may include a first dam DAM1, a second dam DAM2, and a third dam DAM3 stacked sequentially. In the example embodiment, the first dam DAM1 may have a single-layer structure and may be formed using the same process as the second insulating layer 40. The second dam DAM2 may be located on the first dam DAM1. The second dam DAM2 may have a single-layer structure and may be formed using the same process as the pixel defining layer PDL. The third dam DAM3 may be located on the second dam DAM2. The third dam DAM3 may have a single-layer or multi-layer structure. The third dam DAM3 may include an organic material.

[0165] The valley region VA can be defined between the peak region PA and the luminescent region EA. (See reference...) Figure 6A The valley region VA can be defined above the second insulating layer 40 between the peak portion PK and the luminescent region EA.

[0166] As described above, the peak portion PK may comprise multiple layers, and these multiple layers may include layer PK0, the first peak portion PK1, and the second peak portion PK2, formed using the same process as the first insulating layer 30. Because the opening OP1 is defined to extend through the first insulating layer 30, a step difference may occur between the first peak portion PK1 on the first insulating layer 30 and the second insulating layer 40 superimposed with the opening OP1. Since the valley region VA is defined as the area located above the second insulating layer 40 between the peak portion PK and the luminescent region EA, the valley region VA may have a concave shape relative to the luminescent region EA and the peak portion PK; however, embodiments should not be limited to or construed as such.

[0167] Reference Figure 6B In the display module DM-1, the first insulating layer 30 may be located on the second intermediate insulating layer 20. The second insulating layer 40 may be patterned on the first insulating layer 30. For example, the opening OP2 may be defined to penetrate the second insulating layer 40 to expose the first insulating layer 30. The valley region VA may be defined as the area above the first insulating layer 30 exposed by the opening OP2 defined between the peak portion PK and the light-emitting region EA.

[0168] The peak portion PK may include a first peak portion PK1 formed by the same process as that used for the second insulating layer 40. Due to the height difference between the first peak portion PK1 and the first insulating layer 30 in which the valley region VA is defined, the valley region VA may have a concave shape relative to the peak portion PK and the light-emitting region EA.

[0169] The thin-film encapsulation layer TFE can be located on the light-emitting element layer DP-OLED. The thin-film encapsulation layer TFE may include a first inorganic encapsulation layer IOL1, an organic encapsulation layer OL, and a second inorganic encapsulation layer IOL2.

[0170] The first inorganic encapsulation layer IOL1 can cover the light-emitting region EA, valley region VA, and peak region PA of the DP-OLED light-emitting element layer. For example, the first inorganic encapsulation layer IOL1 can cover the peak portion PK and dam DAM of the peak region PA. The organic encapsulation layer OL can be located on the first inorganic encapsulation layer IOL1 and can be in contact with the first inorganic encapsulation layer IOL1. The organic encapsulation layer OL can be formed by providing a liquid organic material on the first inorganic encapsulation layer IOL1 and solidifying the liquid organic material. The liquid organic material can be provided by vapor deposition, printing, or slot coating methods; however, the method of forming the liquid organic material should not be limited to or restricted by these methods. According to another embodiment, the organic encapsulation layer OL can be formed by an inkjet process.

[0171] The peak portion PK and dam portion DAM can be formed around the exterior of the display area DA, and the flow of the liquid organic material can be controlled so that the organic encapsulation layer OL does not overflow to the exterior of the display panel DP. The liquid organic material can flow from the display area DA through the valley area VA to the peak portion PK. Because the valley area VA has a concave shape and the peak portion PK has a relatively convex shape due to the multiple layers stacked on top of each other, the step difference can be large, and the liquid organic material will not easily cross the peak portion PK. Therefore, the end portion ED of the organic encapsulation layer OL may not cross between the peak portion PK and the dam portion DAM or outside the dam portion DAM. In some embodiments, the end portion ED of the organic encapsulation layer OL may contact at least a portion of the peak portion PK.

[0172] The second inorganic encapsulation layer IOL2 can be located on and in contact with the organic encapsulation layer OL. The second inorganic encapsulation layer IOL2 can cover the light-emitting region EA, valley region VA, and peak region PA of the DP-OLED light-emitting element layer. The second inorganic encapsulation layer IOL2 can be completely stacked with the first inorganic encapsulation layer IOL1. The end of the second inorganic encapsulation layer IOL2 can be in contact with the first inorganic encapsulation layer IOL1. The end ED of the organic encapsulation layer OL may not be located outside the peak portion PK; therefore, the first inorganic encapsulation layer IOL1 and the second inorganic encapsulation layer IOL2 can be in contact with each other in at least a portion of the peak portion PK.

[0173] According to an embodiment, the input sensor IS can be located on the thin-film encapsulation layer TFE. Figure 6A The second sensing insulating layer IS-IL2, the first sensor portion SP1, the signal lines SG1-11 to SG1-15 of the first side signal line group SG1-1 and the third sensing insulating layer IS-IL3 located on the second inorganic encapsulation layer IOL2 are shown as representative examples.

[0174] According to the embodiment, each of the signal lines SG1-11 to SG1-15 may not be superimposed on the peak portion PK. In addition, the signal line SG1-15 located at the outermost position of the non-display area NDA may be superimposed on the valley area VA.

[0175] Simultaneously, since the valley region VA has a concave shape relative to the luminescent region EA and the peak region PA, the valley region VA can be fully filled with the liquid organic material of the organic encapsulation layer OL. For example, the organic encapsulation layer OL can be formed to have sufficient thickness in the valley region VA. Therefore, signal lines SG1-11 to SG1-15 can be stacked with the organic encapsulation layer OL, and short circuits in signal lines SG1-11 to SG1-15 can be prevented (or signal lines SG1-11 to SG1-15 can be protected from short circuits).

[0176] Figure 7 , Figure 8 and Figure 9 This schematically illustrates the expansion of the liquid organic material relative to the valley region VA and the peak portion PK when the liquid organic material is injected / sprayed inside and outside the valley region VA. Figure 7 As shown, when liquid organic material is injected / sprayed onto the pixel defining layer (PDL), the organic encapsulation layer (OL) may not be sufficiently formed in the valley region (VA). In other words, the organic encapsulation layer (OL) may not be completely formed in the valley region (VA), or at least a portion of the organic encapsulation layer (OL) formed in the valley region (VA) may not have sufficient thickness. Therefore, at least a portion of the signal lines SG1-11 to SG1-15 may be short-circuited.

[0177] Reference Figure 8 and Figure 9 When liquid organic material is injected / sprayed inside the valley region VA, the organic encapsulation layer OL can be completely formed within the valley region VA and can have a predetermined (or set) thickness within the valley region VA. The outermost signal line SG1-15 among signal lines SG1-11 to SG1-15 can be superimposed on the organic encapsulation layer OL, preventing it from short-circuiting (or protecting it from being short-circuited). The remaining organic encapsulation layer R-OL can be formed between the peak portion PK and the dam DAM; however, this prevents liquid organic material from overflowing to the outside of the display panel DP, and the organic encapsulation layer OL may not be formed outside the dam DAM.

[0178] In some embodiments, the first inorganic encapsulation layer IOL1 may be subjected to hydrophobic or hydrophilic plasma treatment to control the flow rate and velocity of the liquid organic material.

[0179] Reference Figure 10A , Figure 10B and Figure 10C The display modules DM-2, DM-3, and DM-4 have insulating patterns IP that can be located in the area corresponding to the valley area VA. Figure 10A In the display module DM-2, the opening OP1 can be defined to penetrate the first insulating layer 30, and the valley region VA can be defined on the second insulating layer 40. (See reference...) Figure 10A The valley region VA can be defined as the area on the second insulating layer 40 exposed through the aperture HO between the second insulating layer 40 and the peak portion PK. One or more insulating patterns IP can be located in the valley region VA on the second insulating layer 40. The insulating patterns IP can have a height lower than the height of the peak portion PK.

[0180] According to an example embodiment, the insulating pattern IP may include one or more layers. For example, the insulating pattern IP may include multiple layers. For example, the insulating pattern IP may include a first insulating pattern layer IP1-1 and a second insulating pattern layer IP1-2 stacked sequentially. In the example embodiment, at least one of the layers of the insulating pattern IP may be formed using the same process as that used for the first insulating layer 30, the second insulating layer 40, and the pixel defining layer PDL. For example, the first insulating pattern layer IP1-1 may be formed using the same process as that used for the second insulating layer 40, and may include the same material as the second insulating layer 40. The second insulating pattern layer IP1-2 may be formed using the same process as that used for the pixel defining layer PDL, and may include the same material as the pixel defining layer PDL. However, the example embodiment should not be limited thereto or thereby restricted.

[0181] The insulating pattern IP can control the flow rate and velocity of the liquid organic material. For example, the insulating pattern IP can reduce the flow velocity of the liquid organic material. Since the insulating pattern IP is located in the valley region VA, the velocity of the liquid organic material flowing toward the end of the substrate layer BL can be reduced. According to an example embodiment, the protruding insulating pattern IP can compensate for the thickness of the organic encapsulation layer OL, and therefore, the organic encapsulation layer OL can have a substantially uniform thickness in the non-display region NDA corresponding to the droplet point of the injected / sprayed liquid organic material.

[0182] Reference Figure 10B In the display module DM-3, the opening OP2 can be defined to pass through the second insulating layer 40. The valley region VA can be defined as the area on the first insulating layer 30 exposed through the hole HO between the second insulating layer 40 and the peak portion PK. Therefore, the insulating pattern IP can be located on the first insulating layer 30.

[0183] Reference Figure 10C The DP-OLED light-emitting element layer of the display module DM-4 may include a light-emitting element OLED and a pixel-defining layer PDL. The pixel-defining layer PDL may include a light-emitting region, a valley region, and a peak region. The pixel-defining layer PDL may expose a portion of the first electrode EL1 in the light-emitting region.

[0184] When the pixel-defined layer (PDL) is described as including luminescent regions, valley regions, and peak regions, the above descriptions of the luminescent region EA, valley region VA, and peak region PA can be applied to the luminescent region, valley region, and peak region of the pixel-defined layer (PDL), respectively. For example, Figure 10A and Figure 10B The display modules DM-2 and DM-3 may have a structure in which the aperture HO is defined to pass through the pixel-defining layer PDL in the valley region VA. Figure 10CThe display module DM-4 may have a structure in which no holes are defined to pass through the pixel defining layer PDL in the valley region VA. For example, the pixel defining layer PDL of the display module DM-4 may extend to the non-display region NDA, may be connected to the second insulating pattern layer IP1-2 of the insulating pattern IP and the second peak portion PK2 of the peak portion PK, and may cover the valley region VA and the peak portion PK.

[0185] As described above, the second insulating pattern layer IP1-2 of the insulating pattern IP and the second peak portion PK2 of the peak portion PK can be formed using the same process as the pixel defining layer PDL. Therefore, the pixel defining layer PDL can be connected to... Figure 10C The second insulating pattern layer IP1-2 and the second peak portion PK2.

[0186] Insulating patterns (IP) can be set within valley areas (VA) without limitation in number or location. (See reference...) Figure 11 The display module DM-5, with its insulating pattern IP-1, can have a downwardly extending convex shape. (See reference...) Figure 12 The display module DM-6, with its insulating pattern IP-2, can contact the peak portion PK. The peak portion PK and the insulating pattern IP-2 together can have a stepped shape. (See reference...) Figure 13 The display module DM-7 allows multiple insulating patterns IP to be located within the valley region VA. The insulating patterns IP can include a first insulating pattern IP1 and a second insulating pattern IP2. The first insulating pattern IP1 and the second insulating pattern IP2 can be spaced apart from each other.

[0187] The display modules DM-1, DM-2, DM-3, DM-4, ​​DM-5, DM-6, and DM-7 according to exemplary embodiments of this disclosure may include at least one of a peak portion PK, a valley region VA, and an insulating pattern IP. Therefore, the flow rate and velocity of the liquid organic material in the organic encapsulation layer OL can be controlled, and short circuits in signal lines SG1-11 to SG1-15 can be prevented or protected from short circuits.

[0188] As used herein, the term “use” and its variants can be considered synonymous with the term “utilize” and its variants, respectively.

[0189] In addition, the terms “basically,” “about,” and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent biases in measurements or calculations that would be recognized by a person skilled in the art.

[0190] Furthermore, any numerical range stated herein is intended to include all subranges with the same numerical precision contained within the stated range. For example, the range “1.0 to 10.0” is intended to include all subranges between the stated minimum value of 1.0 and the stated maximum value of 10.0 (and including both the stated minimum value of 1.0 and the stated maximum value of 10.0), that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit stated herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit stated in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly state any subranges contained within the range expressly stated herein.

[0191] The apparatuses and / or any other related apparatuses or components described herein according to embodiments of the present disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the apparatus may be formed on an integrated circuit (IC) chip or on separate IC chips. Furthermore, various components of the apparatus may be implemented on flexible printed circuit films, tape-on-a-package (TCP), printed circuit boards (PCBs), or formed on the same substrate. Additionally, various components of the apparatus may be processes or threads executing computer program instructions and interacting with other system components to perform the various functions described herein, running on one or more processors in one or more computing devices. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of exemplary embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0192] Although exemplary embodiments of this disclosure have been described, it is understood that this disclosure should not be limited to these exemplary embodiments, but rather various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure as claimed.

[0193] Therefore, the subject matter disclosed should not be limited to any single embodiment described herein, and the scope of this disclosure should be determined by the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: The substrate layer includes a display area and a non-display area adjacent to the display area; A circuit layer, located on the substrate layer, the circuit layer including a plurality of insulating layers, at least one of the plurality of insulating layers having an opening defined to pass through the at least one of the plurality of insulating layers and overlap with the non-display area; A light-emitting element layer is located on the circuit layer. The light-emitting element layer includes: a light-emitting region, at least a portion of which is superimposed on the display region; a peak region, which is superimposed on the non-display region; and a valley region, which is superimposed on the opening, has a concave shape relative to the light-emitting region and the peak region, and is disposed between the light-emitting region and the peak region. A thin-film encapsulation layer, located on the light-emitting element layer, includes an organic encapsulation layer that covers at least a portion of the light-emitting region, the valley region, and the peak region, and completely fills the valley region; and An input sensor, located on the thin-film encapsulation layer, includes multiple sensing electrodes and multiple signal lines connected to the sensing electrodes. Among these, the signal line located at the outermost position of the non-display area is superimposed on the valley area, and... The light-emitting element layer includes: a light-emitting element, comprising a first electrode located on the circuit layer, a light-emitting layer located on the first electrode, and a second electrode located on the light-emitting layer; and a pixel defining layer that exposes a portion of the first electrode.

2. The display device according to claim 1, wherein, The plurality of insulating layers include: A first insulating layer, having the opening defined to extend through the first insulating layer; and A second insulating layer, situated on top of the first insulating layer to cover the opening, wherein a portion of the second insulating layer has a concave shape and overlaps with the opening, and The valley region is defined on the portion of the second insulating layer having the concave shape.

3. The display device according to claim 1, wherein, The plurality of insulating layers include: First insulating layer; and A second insulating layer has an opening defined to extend through the second insulating layer, the second insulating layer being located on the first insulating layer, and The valley region is defined on the portion of the first insulating layer exposed through the opening.

4. The display device according to claim 1, further comprising a peak portion located on the substrate layer, the peak portion being superimposed on the peak region. in, The peak portion comprises multiple layers, and at least one of the multiple layers of the peak portion is formed by the same process as that used for one of the pixel defining layer and the multiple insulating layers.

5. The display device according to claim 4, further comprising a dam superimposed on and spaced apart from the peak region. in, The dam comprises multiple layers, and at least one of the multiple layers of the dam is formed by the same process as that used for one of the multiple insulating layers and the pixel defining layer.

6. The display device according to claim 4, wherein, The thin-film encapsulation layer further includes a first inorganic encapsulation layer and a second inorganic encapsulation layer. Wherein, the organic encapsulation layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and The first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other in at least a portion of the peak portion.

7. The display device according to claim 4, wherein, The valley region includes an insulating pattern. The insulating pattern comprises multiple layers, at least one of the multiple layers of the insulating pattern being formed by the same process as that used for the pixel defining layer and one of the multiple insulating layers, and The distance from the substrate layer to the insulating pattern is less than the distance from the substrate layer to the peak portion.

8. The display device according to claim 7, wherein, The insulating pattern includes a first insulating pattern and a second insulating pattern spaced apart from the first insulating pattern.

9. The display device according to claim 7, wherein, The insulating pattern contacts the peak portion.

10. The display device according to claim 1, wherein, A portion of the light-emitting area is superimposed on the display area, and the remaining portion of the light-emitting area is superimposed on the non-display area.

11. The display device according to claim 10, wherein, The light-emitting layer and the pixel-defining layer are located in the light-emitting region.

12. The display device according to claim 10, wherein, The light-emitting layer is located in the light-emitting region, and the pixel-defining layer is located in the light-emitting region, the valley region, and the peak region.

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