Display device

Abstract

A display device is provided. The display device includes a signal line, a first transistor, a light-emitting element, a second transistor, a first scan line, a third transistor, and a second scan line. Among them, the signal line extends in a first direction, the first transistor is configured to control a driving current, the light-emitting element is electrically connected to a second electrode of the first transistor, the second transistor is electrically connected to a first electrode of the first transistor and is configured to transmit a data voltage, the first scan line is electrically connected to a gate electrode of the second transistor and extends in the first direction, the third transistor includes a first electrode electrically connected to the second electrode of the first transistor and a second electrode electrically connected to the gate electrode of the first transistor, and the second scan line is electrically connected to the gate electrode of the third transistor and extends in the first direction. Among them, the second scan line overlaps with one selected from the signal line and the first scan line.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2019 - 0126756, filed on October 14, 2019, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device. Background art

[0004] With the development of multimedia, the importance of display devices is increasing. Accordingly, various types of display devices, such as organic light - emitting display (OLED) devices and liquid - crystal display (LCD) devices, have been used.

[0005] Among the commonly available display devices, an OLED device includes an organic light - emitting diode which is a self - emitting element. The organic light - emitting diode may include two opposite electrodes and an organic light - emitting layer therebetween. Electrons and holes provided by the two opposite electrodes recombine in the organic light - emitting layer to generate excitons, and the generated excitons transition from the excited state to the ground state, thereby emitting light.

[0006] Because such an OLED device does not require a separate light source, the OLED device can not only be formed to have low power consumption, be thin and lightweight, but also have high - quality characteristics such as a wide viewing angle, high brightness and contrast, and a fast response speed, and thus has attracted attention as a next - generation display device.

[0007] p - type metal - oxide - semiconductor (PMOS) transistors are generally used as transistors in OLED devices, but OLED devices using n - type metal - oxide - semiconductor (NMOS) transistors or using PMOS transistors and NMOS transistors together have been studied. Summary of the invention

[0008] In an organic light - emitting display device using a p - type metal - oxide - semiconductor (PMOS) transistor and an n - type metal - oxide - semiconductor (NMOS) transistor together, a lower light - blocking pattern can be used to shield the lower part of the NMOS transistor from light. In this case, the gate electrode of the PMOS transistor and the lower light - blocking pattern may be formed in the same layer, and thus additional space can be utilized to make more space available for one pixel. Therefore, it may be difficult to improve the resolution.

[0009] It should be noted that the aspects and features of the present disclosure are not limited to the above - mentioned aspects and features, and through the following description, other aspects and features of the present disclosure will be apparent to those skilled in the art.

[0010] An embodiment of a display device includes a signal line, a first transistor, a light-emitting element, a second transistor, a first scan line, a third transistor, and a second scan line. Among them, the signal line extends in a first direction. The first transistor is configured to control a driving current flowing from a first electrode of the first transistor to a second electrode of the first transistor according to a voltage applied to a gate electrode of the first transistor. The light-emitting element is electrically connected to the second electrode of the first transistor and is configured to emit light according to the driving current. The second transistor is electrically connected to the first electrode of the first transistor and is configured to transmit a data voltage. The first scan line is electrically connected to a gate electrode of the second transistor and extends in the first direction. The third transistor includes a first electrode electrically connected to the second electrode of the first transistor and a second electrode electrically connected to the gate electrode of the first transistor. And the second scan line is electrically connected to a gate electrode of the third transistor and extends in the first direction. Among them, the second scan line overlaps with one selected from the signal line and the first scan line.

[0011] An embodiment of a display device includes a substrate, a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second semiconductor layer, a third insulating layer, and a second conductive layer. Among them, the first semiconductor layer is located on the substrate. The first insulating layer covers the first semiconductor layer and is located on the substrate. The first conductive layer is located on the first insulating layer and includes a first scan line extending in a first direction. The second insulating layer covers the first conductive layer and is located on the first insulating layer. The second semiconductor layer is located on the second insulating layer. The third insulating layer covers the second semiconductor layer and is located on the second insulating layer. And the second conductive layer is located on the third insulating layer and includes a second scan line extending in the first direction. Among them, the first scan line overlaps with the second scan line.

[0012] In the display device according to the embodiment, the gate electrode of the PMOS transistor can be used as the lower light-blocking pattern of the NMOS transistor without adding a separate lower light-blocking pattern. Accordingly, no extra space is required for the separate lower light-blocking pattern, and the space for one pixel is reduced, thereby improving the resolution of the organic light-emitting display device.

[0013] Aspects and features according to the exemplary embodiments are not limited by the above, and more various aspects and features are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] By describing aspects of the present disclosure in more detail with reference to the accompanying drawings, the above and other exemplary embodiments and features of the present disclosure will become more apparent. In the drawings:

[0015] Figure 1 is a schematic block diagram showing a display device according to an exemplary embodiment;

[0016] Figure 2is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment;

[0017] Figure 3 is a layout diagram of a pixel of a display device according to an exemplary embodiment;

[0018] Figure 4 is Figure 3 a layout diagram of a lower semiconductor layer and an upper semiconductor layer of;

[0019] Figure 5 is a cross-sectional view taken along line V-V' of Figure 3 ;

[0020] Figure 6 is a cross-sectional view taken along line VI-VI' of Figure 3 ;

[0021] Figure 7 is Figure 3 a layout diagram of a first conductive layer and a second conductive layer of;

[0022] Figure 8 is a cross-sectional view taken along line A-A' and line B-B' of Figure 3 ;

[0023] Figure 9 is a cross-sectional view taken along line C-C' and line D-D' of Figure 3 ;

[0024] Figure 10 is a layout diagram of a first conductive layer and a second conductive layer according to an exemplary embodiment;

[0025] Figure 11 is a cross-sectional view taken along line E-E' and line F-F' of Figure 10 ;

[0026] Figure 12 is a cross-sectional view taken along line G-G' and line H-H' of Figure 10 ;

[0027] Figure 13 is a layout diagram of a first conductive layer and a second conductive layer according to an exemplary embodiment;

[0028] Figure 14 is a cross-sectional view taken along line XIV-XIV' of Figure 13 ; and

[0029] Figure 15 is a cross-sectional view taken along line XV-XV' of Figure 13 ; Detailed Description

[0030] The subject matter of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings that show some embodiments of the present disclosure. However, the subject matter of the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0031] It will also be understood that when a layer is referred to as being “on” another layer or substrate, the layer can be directly on the other layer or substrate, or an intermediate layer may also be present. Throughout the specification, like reference numerals indicate like components. In the drawings, for clarity, the thicknesses of layers and regions may be exaggerated.

[0032] Although terms such as “first,” “second,” etc. may be used herein to describe various elements, these components should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, without departing from the spirit and scope of the present disclosure, the first element discussed below may be referred to as the second element. A description of an element as the “first” element may not require or imply the existence of a second element or other elements. Terms such as “first,” “second,” etc. may also be used to distinguish different categories or groups of elements. For the sake of brevity, terms such as “first,” “second,” etc. may respectively denote (e.g., may indicate) “first class (or first group),” “second class (or second group),” etc. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0033] At the end of the detailed description, those skilled in the art will realize that many changes and modifications can be made to the disclosed embodiments without departing from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense and not for purposes of limitation.

[0034] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. An organic light-emitting display device will be described below as an example of a display device.

[0035] Figure 1 is a schematic block diagram showing a display device 1 according to an exemplary embodiment.

[0036] Referring to Figure 1 , the display device 1 includes a display unit 10 having a plurality of pixels PX, a scan driver 20, a data driver 30, a light emission control driver 40, and a timing controller 50.

[0037] The display unit 10 includes a plurality of pixels PX arranged in a matrix form (e.g., in a matrix pattern) and positioned at intersections or crossings of a plurality of scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn. For example, in some embodiments, the pixel PX may correspond to a region where a data line from the plurality of data lines DL1 to DLm intersects with a first scan line from the plurality of first scan lines SL11 to SL1n, a second scan line from the plurality of second scan lines SL21 to SL2n, a third scan line from the plurality of third scan lines SL31 to SL3n, a fourth scan line from the plurality of fourth scan lines SL41 to SL4n, and an emission control line from the plurality of emission control lines EL1 to ELn.

[0038] The plurality of scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n and the plurality of emission control lines EL1 to ELn may extend in a row direction, and the plurality of data lines DL1 to DLm may extend in a column direction. The row direction and the column direction may be switched relative to each other. The supply line of the initialization voltage VINT may branch for each row and may extend in the row direction. For example, the supply line of the initialization voltage VINT may include a first portion extending in the column direction and a plurality of second portions branching from the first portion and extending in the row direction. The supply line of the first power supply voltage ELVDD may branch for each column and may extend in the column direction. For example, the first power supply voltage ELVDD may include a first portion extending in the row direction and a plurality of second portions branching from the first portion and extending in the column direction. However, the present disclosure is not limited thereto, and the extending directions of the supply line of the initialization voltage VINT and the supply line of the first power supply voltage ELVDD may be modified differently.

[0039] Three scan lines SL11, SL21, and SL31, one data line DL1, one emission control line EL1, one supply line of the initialization voltage VINT, and one supply line of the first power supply voltage ELVDD may pass through an exemplary pixel PX (e.g., the pixel PX in the first row and the first column). Similarly, such lines may pass through at least some of the other pixels PX.

[0040] The scan driver 20 generates three scan signals and transmits the three generated scan signals to each of the plurality of pixels PX through a plurality of scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n. For example, the scan driver 20 sequentially supplies the scan signals to the plurality of first scan lines SL11 to SL1n, the plurality of second scan lines SL21 to SL2n, and the plurality of third scan lines SL31 to SL3n, and the plurality of fourth scan lines SL41 to SL4n are connected to the plurality of first scan lines SL11 to SL1n of adjacent pixels PX so that the same scan signal (the same scan signal transmitted through the plurality of first scan lines SL11 to SL1n) as the plurality of first scan lines SL11 to SL1n of the adjacent pixels PX is transmitted through the plurality of fourth scan lines SL41 to SL4n.

[0041] The data driver 30 transmits data signals to each of the plurality of pixels PX through a plurality of data lines DL1 to DLm. Whenever the first scan signal is supplied to the plurality of first scan lines SL11 to SL1n, the data signal is supplied to the pixels PX selected by the first scan signal.

[0042] The light emission control driver 40 generates a light emission control signal and transmits the generated light emission control signal to each of the plurality of pixels PX through a plurality of light emission control lines EL1 to ELn. The light emission control signal controls the light emission time of the pixel PX. The light emission control driver 40 may be omitted when the scan driver 20 generates the light emission control signal and the scan signal, or when the internal structure of the pixel PX incorporates the emission function of the light emission control driver 40.

[0043] In some embodiments, the display device 1 includes at least one signal line. For example, in some embodiments, the display device 1 includes a plurality of signal lines. In some embodiments, at least one of the plurality of signal lines extends in the row direction. In some embodiments, at least one of the plurality of signal lines crosses at least one of the plurality of pixels PX and overlaps a portion of the second scan line that intersects the pixel PX. In some embodiments, at least one of the plurality of signal lines is a light emission control line or an initialization voltage line.

[0044] The timing controller 50 converts multiple image signals R, G, and B transmitted from the outside into multiple image data signals DR, DG, and DB, and transmits the multiple image data signals DR, DG, and DB to the data driver 30. Additionally, the timing controller 50 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK. The timing controller 50 generates control signals for controlling the driving of the scan driver 20, the data driver 30, and the light emission control driver 40, and the timing controller 50 transmits the generated control signals to the scan driver 20, the data driver 30, and the light emission control driver 40. For example, the timing controller 50 generates and transmits a scan driving control signal SCS for controlling the scan driver 20, a data driving control signal DCS for controlling the data driver 30, and a light emission driving control signal ECS for controlling the light emission control driver 40.

[0045] Each of the plurality of pixels PX receives a first power supply voltage ELVDD and a second power supply voltage ELVSS. The first power supply voltage ELVDD may be a set or predetermined high-level voltage, and the second power supply voltage ELVSS may be a voltage lower than the first power supply voltage ELVDD.

[0046] Since the driving current supplied to the light-emitting element (e.g., the light-emitting element of the pixel PX) depends on the data signal transmitted through each of the plurality of data lines DL1 to DLm, each of the plurality of pixels PX emits light having a set or predetermined luminance.

[0047] The first power supply voltage ELVDD, the second power supply voltage ELVSS, the initialization voltage VINT, and the like may be supplied from an external voltage source.

[0048] Figure 2 is an equivalent circuit diagram of a pixel PX of the display device 1 according to an exemplary embodiment.

[0049] Refer to Figure 2 , the circuit of a pixel PX of the display device 1 includes an organic light-emitting diode OLED, a plurality of transistors T1 to T7, and a storage capacitor Cst. A data signal DATA, a first scan signal GW_P[n], a second scan signal GW_N[n], a third scan signal GI_N[n], a fourth scan signal GW_P[n+1], a light emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT are applied to the circuit of a pixel PX.

[0050] The fourth scan signal GW_P[n+1] may be a scan signal that is substantially the same as the first scan signal of an adjacent pixel PX. For example, there may be four scan lines that cross a pixel PX, but among the four scan lines, the scan line that transmits the fourth scan signal may be interconnected with the scan line of the adjacent pixel PX (e.g., may be connected to the scan line of the adjacent pixel PX), and the first scan signal of the adjacent pixel PX is transmitted through the scan line of the adjacent pixel PX, so that the same scan signal can be transmitted through the scan line through which the fourth scan signal GW_P[n+1] is transmitted. For example, as described above, each pixel PX may include substantially three scan signals (e.g., substantially three scan signals are applied to the circuit of each pixel PX).

[0051] The organic light-emitting diode OLED includes an anode and a cathode. The storage capacitor Cst includes a first electrode and a second electrode.

[0052] The plurality of transistors may include a first transistor T1 to a seventh transistor T7. Each of the plurality of transistors T1 to T7 includes a gate electrode, a first electrode, and a second electrode. For each of the plurality of transistors T1 to T7, one selected from the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0053] Each of the plurality of transistors T1 to T7 may be a thin-film transistor. Each of the plurality of transistors T1 to T7 may be one selected from a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor. In an exemplary embodiment, the first transistor T1 used as a driving transistor, the second transistor T2 used as a data transfer transistor, the fifth transistor T5 used as a first light control transistor, the sixth transistor T6 used as a second light control transistor, and the seventh transistor T7 used as a second initialization transistor are PMOS transistors. On the other hand, the third transistor T3 used as a compensation transistor and the fourth transistor T4 used as a first initialization transistor are NMOS transistors. PMOS transistors and NMOS transistors have different characteristics, and by forming the third transistor T3 and the fourth transistor T4 with NMOS transistors having relatively excellent off characteristics, leakage of the driving current during the light-emitting period of the organic light-emitting diode OLED can be reduced. For example, in some embodiments, the third transistor T3 and the fourth transistor T4 are NMOS transistors.

[0054] Hereinafter, each component will be described in more detail.

[0055] The gate electrode of the first transistor T1 is connected to the first electrode of the storage capacitor Cst. As disclosed herein, when one component is described as being connected to a second component, the two components may be electrically connected, for example. The first electrode of the first transistor T1 is connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5. The second electrode of the first transistor T1 is connected to the anode of the organic light-emitting diode OLED via the sixth transistor T6. The first transistor T1 receives the data signal DATA according to the switching operation of the second transistor T2 and supplies a driving current to the organic light-emitting diode OLED.

[0056] The gate electrode of the second transistor T2 is connected to the terminal of the first scan signal GW_P[n]. The first electrode of the second transistor T2 is connected to the terminal of the data signal DATA. The second electrode of the second transistor T2 is connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5 while being connected to the first electrode of the first transistor T1. The second transistor T2 is turned on in response to the first scan signal GW_P[n] to perform a switching operation of transmitting the data signal DATA to the first electrode of the first transistor T1.

[0057] The gate electrode of the third transistor T3 is connected to the terminal of the second scan signal GW_N[n]. The first electrode of the third transistor T3 is connected to the anode of the organic light-emitting diode OLED via the sixth transistor T6 while being connected to the second electrode of the first transistor T1. The second electrode of the third transistor T3 is connected to the first electrode of the storage capacitor Cst, the first electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 is turned on in response to the second scan signal GW_N[n] to connect the gate electrode and the second electrode of the first transistor T1 so that the first transistor T1 is diode-connected. During the period when the second scan signal GW_N[n] is valid, the third transistor T3 forms the diode connection of the first transistor T1. Accordingly, due to the diode connection, a voltage difference is generated between the first electrode and the gate electrode of the first transistor T1, and the voltage difference corresponds to the threshold voltage of the first transistor T1. As a result, during the period when the first scan signal GW_P[n] and the second scan signal GW_N[n] are valid, the sum of the data signal DATA and the voltage difference (i.e., the threshold voltage) supplied to the first electrode of the first transistor T1 is applied to the gate electrode of the first transistor T1. Therefore, the data signal DATA is compensated by the threshold voltage of the first transistor T1. The compensated data signal DATA is applied to the gate electrode of the first transistor T1. Accordingly, the uniformity of the driving current can be improved by reducing the influence of the threshold voltage of the first transistor T1.

[0058] The gate electrode of the fourth transistor T4 is connected to the terminal of the third scan signal GI_N[n]. The second electrode of the fourth transistor T4 is connected to the terminal of the initialization voltage VINT. The first electrode of the fourth transistor T4 is connected to the first electrode of the storage capacitor Cst, the second electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on in response to the third scan signal GI_N[n] to transmit the initialization voltage VINT to the gate electrode of the first transistor T1, thereby performing an operation of initializing the voltage of the gate electrode of the first transistor T1.

[0059] The gate electrode of the fifth transistor T5 is connected to the terminal of the light emission control signal EM. The first electrode of the fifth transistor T5 is connected to the terminal of the first power supply voltage ELVDD. The second electrode of the fifth transistor T5 is connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2.

[0060] The gate electrode of the sixth transistor T6 is connected to the terminal of the light emission control signal EM. The first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3. The second electrode of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED.

[0061] The fifth transistor T5 and the sixth transistor T6 are turned on simultaneously (e.g., synchronously) in response to the light emission control signal EM, and thus, a driving current flows through the organic light emitting diode OLED.

[0062] The gate electrode of the seventh transistor T7 is connected to the terminal of the fourth scan signal GW_P[n+1]. The first electrode of the seventh transistor T7 is connected to the anode of the organic light emitting diode OLED. The second electrode of the seventh transistor T7 is connected to the terminal of the initialization voltage VINT. In some embodiments, the seventh transistor T7 is turned on in response to the fourth scan signal GW_P[n+1] to initialize the anode of the organic light emitting diode OLED.

[0063] In the present exemplary embodiment, the case where the gate electrode of the seventh transistor T7 receives the fourth scan signal GW_P[n+1] is shown. In some embodiments, the circuit of the pixel PX can be configured such that the gate electrode of the seventh transistor T7 receives the light emission control signal EM. In this case, the seventh transistor T7 is turned on in response to the light emission control signal EM to initialize the anode of the organic light emitting diode OLED.

[0064] The second electrode of the storage capacitor Cst is connected to the terminal of the first power supply voltage ELVDD. The first electrode of the storage capacitor Cst is connected to the gate electrode of the first transistor T1, the second electrode of the third transistor T3, and the first electrode of the fourth transistor T4. The cathode of the organic light-emitting diode OLED is connected to the terminal of the second power supply voltage ELVSS. The organic light-emitting diode OLED receives a driving current from the first transistor T1 and emits light to display an image.

[0065] The planar layout and cross-sectional structure of the above-described pixel PX will be described in more detail below.

[0066] Figure 3 is a layout diagram of a pixel PX of the display device 1 according to an exemplary embodiment. Figure 4 is Figure 3 a layout diagram of the lower semiconductor layer 100 and the upper semiconductor layer 300. Figure 5 is along Figure 3 the cross-sectional view taken along the V-V' line of Figure 6 is along Figure 3 the cross-sectional view taken along the line VI-VI' of

[0067] In the exemplary embodiments to be described below, even if a component is the same as or substantially the same as the component described above with reference to Figure 1 and Figure 2 a new reference numeral is assigned to the component in order to facilitate the explanation of the arrangement of the components and the connection relationship between the components.

[0068] Referring to Figures 3 to 6 , as described above, the pixel PX includes a plurality of transistors (hereinafter understood to represent Figure 2 the plurality of transistors T1 to T7), a storage capacitor (hereinafter understood to represent Figure 2 the storage capacitor Cst), and an organic light-emitting diode (hereinafter understood to represent Figure 2 the organic light-emitting diode OLED).

[0069] Each of the plurality of transistors T1 to T7 includes a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. A top-gate type (e.g., arranged) transistor in which the gate electrode is located above the semiconductor layer can be applied to (e.g., can be used for) all of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 which are PMOS transistors, and the third transistor T3 and the fourth transistor T4 which are NMOS transistors, but the present disclosure is not limited thereto.

[0070] The storage capacitor Cst includes a conductive layer forming an electrode and an insulating layer located between the conductive layers. The organic light-emitting diode OLED includes a conductive layer forming an anode and a cathode and an organic light-emitting layer located between the conductive layers. The above-described elements can be electrically coupled to each other through wirings formed of a conductive layer and / or vias formed of a conductive material. The conductive material, conductive layer, semiconductor layer, insulating layer, organic light-emitting layer, and the like as described above are located on the substrate SUB1.

[0071] The multiple layers of the pixel PX can be arranged in the order of the substrate SUB1, buffer layer SUB2, lower semiconductor layer 100, first insulating layer 710, first conductive layer 200, second insulating layer 720, upper semiconductor layer 300, third insulating layer 730, second conductive layer 400, fourth insulating layer 740, and third conductive layer 500. Each of the above-described multiple layers can be formed as a single-layer film, but in some embodiments, each of the above-described multiple layers can be formed as a stacked film including multiple films. Another layer can also be located between these layers.

[0072] The substrate SUB1 supports the layers located thereon. When the display device 1 is formed as a bottom-emission type or a double-sided emission type (e.g., arrangement), a transparent substrate can be used. When the display device 1 is formed as a top-emission type (e.g., arrangement), a translucent or opaque substrate as well as a transparent substrate can be applied.

[0073] The substrate SUB1 can include insulating materials such as glass, quartz, polymer resin, and / or the like. Examples of the polymer resin can include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a composition thereof. The substrate SUB1 can also include a metal material.

[0074] The substrate SUB1 can be a flexible substrate having characteristics such as bendable, foldable, rollable, and / or the like, or the substrate SUB1 can be a rigid substrate. Examples of the material forming the flexible substrate can include PI, but the present disclosure is not limited thereto.

[0075] The buffer layer SUB2 can be located on the entire surface of the substrate SUB1. The buffer layer SUB2 can prevent or reduce the diffusion of impurity ions, prevent or reduce the penetration of moisture and / or external air, and perform a surface flattening function. The buffer layer SUB2 can include silicon nitride, silicon oxide, silicon oxynitride, and / or the like. The buffer layer SUB2 can be omitted (e.g., can be omitted depending on the above) according to the type (e.g., kind) of the substrate SUB1, process conditions, and / or similar conditions.

[0076] The lower semiconductor layer 100 is an active layer that forms the channels of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0077] The lower semiconductor layer 100 can be divided for each pixel unit. In a plan view, the lower semiconductor layer 100 can have a suitable pattern. For example, the lower semiconductor layer 100 can include a first longitudinal portion 110 and a second longitudinal portion 120 that generally extend in the column direction, and a first transverse portion 130 that generally extends in the row direction. The first longitudinal portion 110, the second longitudinal portion 120, and the first transverse portion 130 can be physically connected to each other (e.g., can be physically or directly in contact with each other).

[0078] The first longitudinal portion 110 can be adjacent to the left side of the pixel PX, and the second longitudinal portion 120 can be adjacent to the right side of the pixel PX. For example, the first longitudinal portion 110 can be closer to the left side of the pixel PX than the right side of the pixel PX, and the second longitudinal portion 120 can be closer to the right side of the pixel PX than the left side of the pixel PX. The first longitudinal portion 110 and the second longitudinal portion 120 can be spaced apart from each other (e.g., spaced apart from each other in the row direction). The first transverse portion 130 can connect the middle portion of the first longitudinal portion 110 to the upper portion of the second longitudinal portion 120. For example, most of the second longitudinal portion 120 can be located below the first transverse portion 130.

[0079] In this specification, the "first region 111" of the first longitudinal portion 110 can indicate a region that is located above the connection portion between the first longitudinal portion 110 and the first transverse portion 130 in a plan view (e.g., located above the connection position between the first longitudinal portion 110 and the first transverse portion 130), and the "second region 112" of the first longitudinal portion 110 can indicate a region that is located below the connection portion between the first longitudinal portion 110 and the first transverse portion 130 in a plan view (e.g., located below the connection position between the first longitudinal portion 110 and the first transverse portion 130).

[0080] In addition, the "third region 121" of the second longitudinal portion 120 may indicate a region that extends downward in a plan view from a connection portion between the second longitudinal portion 120 and the first lateral portion 130, and the length by which this region extends downward is equal to or substantially equal to the length by which the first longitudinal portion 110 (e.g., the second region 112 of the first longitudinal portion 110) extends downward from a connection portion between the first longitudinal portion 110 and the first lateral portion 130 in the plan view. The "fourth region 122" of the second longitudinal portion 120 may indicate a region that extends downward from the third region 121. For example, the third region 121 may be directly connected to (e.g., may be directly or physically in contact with) the first lateral portion 130 and may be positioned at an upper side of the second longitudinal portion 120, and the fourth region 122 may extend downward from the third region 121, may be connected to the first lateral portion 130 through the third region 121, and may be positioned at a lower side of the second longitudinal portion 120.

[0081] The channel of the second transistor T2 may be located in the first region 111 of the first longitudinal portion 110, and the channel of the fifth transistor T5 may be located in the second region 112 of the first longitudinal portion 110. The channel of the sixth transistor T6 may be located in the third region 121 of the second longitudinal portion 120, and the channel of the seventh transistor T7 may be located in the fourth region 122 of the second longitudinal portion 120. The channel of the first transistor T1 may be located in the first lateral portion 130.

[0082] As shown in the figure, the first lateral portion 130 may connect the first longitudinal portion 110 to the second longitudinal portion 120 at the shortest distance, and may include a first bent portion 131 as its left side portion and a second bent portion 132 as its right side portion. When the first lateral portion 130 is bent multiple times, the total length of the first lateral portion 130 may increase.

[0083] The lower semiconductor layer 100 may include polysilicon. The polysilicon may be formed by crystallizing amorphous silicon. Examples of methods for crystallizing amorphous silicon may include a rapid thermal annealing (RTA) method, a solid phase crystallization (SPC) method, an excimer laser annealing (ELA) method, a metal-induced crystallization (MIC) method, a metal-induced lateral crystallization (MILC) method, a sequential lateral solidification (SLS) method, and similar methods, but are not limited thereto. In some embodiments, the lower semiconductor layer 100 may include single crystal silicon, low temperature polysilicon, amorphous silicon, and / or the like.

[0084] The region (source / drain region) of the lower semiconductor layer 100 coupled to the source electrode / drain electrode of each of the plurality of transistors T1, T2, T5, T6, and T7 (e.g., coupled to the source electrode and / or drain electrode) can be doped with impurity ions (e.g., p-type impurity ions in the case of PMOS transistors). A trivalent dopant such as boron (B) can be used as the p-type impurity ion.

[0085] The first insulating layer 710 can be located on the lower semiconductor layer 100 and generally on the entire surface of the substrate SUB1. For example, the first insulating layer 710 can be located on the lower semiconductor layer 100 and on the buffer layer SUB2. The first insulating layer 710 can be a gate insulating film having a gate insulating function.

[0086] The first insulating layer 710 can include a silicon compound, a metal oxide, and / or the like. For example, the first insulating layer 710 can include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and / or the like. The above materials can be used alone or in combination. The first insulating layer 710 can be formed as a single-layer film or a multi-layer film having stacked films of different materials.

[0087] The first conductive layer 200 is located on the first insulating layer 710. The first conductive layer 200 can include a first scan line 210 that transmits a first scan signal (hereinafter understood to represent Figure 2 the first scan signal GW_P[n]), a gate electrode 240 of the first transistor T1, a light emission control line 220 that transmits a light emission control signal (hereinafter understood to represent Figure 2 the light emission control signal EM), and a fourth scan line 230 that transmits a fourth scan signal (hereinafter understood to represent Figure 2 the fourth scan signal GW_P[n+1]).

[0088] The first scan line 210 can include a gate electrode of the second transistor T2, the light emission control line 220 can include a gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6, and the fourth scan line 230 can include a gate electrode of the seventh transistor T7.

[0089] Each of the first scan line 210, the light emission control line 220, and the fourth scan line 230 can extend in the row direction. Each of the first scan line 210, the light emission control line 220, and the fourth scan line 230 can extend in the row direction beyond the boundary of the pixel PX toward an adjacent pixel PX (e.g., a neighboring or nearest pixel PX).

[0090] In a plan view, a first scan line 210 may be positioned above a pixel PX. The first scan line 210 may overlap with a first region 111 of a first longitudinal portion 110 of a lower semiconductor layer 100, and a gate electrode of a second transistor T2 may be located in an overlapping region between the first scan line 210 and the first region 111. For example, the gate electrode of the second transistor T2 may be located in a region where the first scan line 210 overlaps with the first region 111. A portion of the first longitudinal portion 110 of the lower semiconductor layer 100 positioned above the overlapping region (e.g., a portion of the first region 111) may be a first electrode region of the second transistor T2, and a portion of the first longitudinal portion 110 of the lower semiconductor layer 100 positioned below the overlapping region (e.g., a portion of the first region 111) may be a second electrode region of the second transistor T2. A channel region of the second transistor T2 may be positioned between its first electrode region and the second electrode region, and the channel region of the second transistor T2 may overlap with the first scan line 210. The first scan line 210 may not overlap with the second longitudinal portion 120.

[0091] The first scan line 210 extends in the same direction as a second scan line 410 that will be described below, and at least a portion thereof may overlap with the second scan line 410. A more detailed description thereof is provided herein below.

[0092] In a plan view, a light emission control line 220 is positioned below the first scan line 210 and may overlap with a second region 112 of the first longitudinal portion 110 of the lower semiconductor layer 100 and a third region 121 of the second longitudinal portion 120 of the lower semiconductor layer 100.

[0093] A gate electrode of a fifth transistor T5 may be located in an overlapping region between the second region 112 of the first longitudinal portion 110 of the lower semiconductor layer 100 and the light emission control line 220. For example, the gate electrode of the fifth transistor T5 may be located in a region where the light emission control line 220 overlaps with the second region 112. A portion of the first longitudinal portion 110 of the lower semiconductor layer 100 positioned below the overlapping region (e.g., a portion of the second region 112) may be a first electrode region of the fifth transistor T5, and a portion of the first longitudinal portion 110 of the lower semiconductor layer 100 positioned above the overlapping region (e.g., a portion of the second region 112) may be a second electrode region of the fifth transistor T5. A channel region of the fifth transistor T5 may be positioned between its first electrode region and the second electrode region, and the channel region of the fifth transistor T5 may overlap with the light emission control line 220.

[0094] In addition, the gate electrode of the sixth transistor T6 may be located in an overlapping region between the third region 121 of the second longitudinal portion 120 and the light emission control line 220. For example, the gate electrode of the sixth transistor T6 may be located in a region where the light emission control line 220 overlaps with the third region 121. A portion of the second longitudinal portion 120 of the lower semiconductor layer 100 positioned above the overlapping region (e.g., a portion of the third region 121) may be the first electrode region of the sixth transistor T6, and a portion of the second longitudinal portion 120 of the lower semiconductor layer 100 positioned below the overlapping region (e.g., a portion of the third region 121) may be the second electrode region of the sixth transistor T6. The channel region of the sixth transistor T6 may be positioned between its first electrode region and the second electrode region, and the channel region of the sixth transistor T6 may overlap with the light emission control line 220.

[0095] In their corresponding overlapping regions, the width of the gate electrode of the second transistor T2, the width of the gate electrode of the fifth transistor T5, and the width of the gate electrode of the sixth transistor T6 may be greater than the width of the lines near these gate electrodes, but the present disclosure is not limited thereto.

[0096] In a plan view, the fourth scan line 230 may be positioned at a lower portion of the pixel PX. The gate electrode of the seventh transistor T7 may be located in an overlapping region between the fourth region 122 of the second longitudinal portion 120 and the fourth scan line 230. For example, the gate electrode of the seventh transistor T7 may be located in a region where the fourth scan line 230 overlaps with the fourth region 122. A portion of the second longitudinal portion 120 of the lower semiconductor layer 100 positioned above the overlapping region (e.g., a portion of the fourth region 122) may be the first electrode region of the seventh transistor T7, and a portion of the second longitudinal portion 120 of the lower semiconductor layer 100 positioned below the overlapping region (e.g., a portion of the fourth region 122) may be the second electrode region of the seventh transistor T7. The channel region of the seventh transistor T7 may be positioned between its first electrode region and the second electrode region, and the channel region of the seventh transistor T7 may overlap with the fourth scan line 230.

[0097] The fourth scan line 230 extends in the same direction as the third scan line 420, which will be described below, and at least a portion thereof (e.g., at least a portion of the fourth scan line 230) may overlap with the third scan line 420. A more detailed description thereof is provided herein below.

[0098] In a plan view, the gate electrode 240 of the first transistor T1 may be positioned at a central portion of the pixel PX. In a plan view, the gate electrode 240 of the first transistor T1 may be positioned between the first scan line 210 and the light emission control line 220. The gate electrode 240 of the first transistor T1 may be divided for each pixel unit. In some embodiments, the first conductive layer 200 may be divided for each pixel unit.

[0099] The gate electrode 240 of the first transistor T1 overlaps with the first lateral portion 130 of the lower semiconductor layer 100. A portion of the first lateral portion 130 of the lower semiconductor layer 100 may be the first electrode region of the first transistor T1, and this portion is located on the left side of the overlapping region between the gate electrode 240 and the first lateral portion 130. The portion of the first lateral portion 130 of the lower semiconductor layer 100 that is located on the right side of the overlapping region may be the second electrode region of the first transistor T1. The channel region of the first transistor T1 may be positioned between its first electrode region and the second electrode region, and the channel region of the first transistor T1 may overlap with the gate electrode 240 of the first transistor T1.

[0100] The first conductive layer 200 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 200 may be formed as a single-layer film or a multi-layer film.

[0101] The second insulating layer 720 may be located on the first conductive layer 200 and is generally located above the entire surface of the substrate SUB1. The second insulating layer 720 is used to insulate the first conductive layer 200 and the upper semiconductor layer 300 from each other. The second insulating layer 720 may be an interlayer insulating film.

[0102] The second insulating layer 720 may include an inorganic insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and / or zinc oxide) and / or an organic insulating material (such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and / or benzocyclobutene (BCB)). The second insulating layer 720 may be formed as a single-layer film or a multi-layer film of a stacked film with different materials.

[0103] The upper semiconductor layer 300 may be located on the second insulating layer 720. The upper semiconductor layer 300 may include an upper semiconductor pattern 310 and a storage capacitor electrode 320, and the upper semiconductor pattern 310 is an active layer for forming the channels of the third transistor T3 and the fourth transistor T4. The upper semiconductor layer 300 may be divided for each pixel unit.

[0104] In a plan view, the upper semiconductor pattern 310 may have a suitable pattern. For example, the upper semiconductor pattern 310 may include a third longitudinal portion 311 and a fourth longitudinal portion 312 that generally extend in the column direction and a second lateral portion 313 that generally extends in the row direction. The third longitudinal portion 311, the fourth longitudinal portion 312, and the second lateral portion 313 may be physically connected to each other (for example, may be physically or directly in contact with each other).

[0105] The third longitudinal part 311 may be adjacent to the left side of the pixel PX, and the fourth longitudinal part 312 may be adjacent to the right side of the pixel PX. For example, the third longitudinal part 311 may be closer to the left side of the pixel PX than the right side of the pixel PX, and the fourth longitudinal part 312 may be closer to the right side of the pixel PX than the left side of the pixel PX. The third longitudinal part 311 and the fourth longitudinal part 312 may be spaced apart from each other. The second transverse part 313 may connect the lower part of the third longitudinal part 311 to the upper part of the fourth longitudinal part 312. For example, most of the fourth longitudinal parts 312 may be located below the third longitudinal part 311.

[0106] The second scan line 410 overlaps with the fourth longitudinal part 312 of the upper semiconductor pattern 310. A part of the fourth longitudinal part 312 of the upper semiconductor pattern 310 may be the first electrode region of the third transistor T3, and this part is located below the overlapping region between the second scan line 410 and the fourth longitudinal part 312. The part of the fourth longitudinal part 312 of the upper semiconductor pattern 310 that is located above the overlapping region may be the second electrode region of the third transistor T3. The channel region of the third transistor T3 may be located between its first electrode region and the second electrode region, and the channel region of the third transistor T3 may overlap with the second scan line 410.

[0107] The third scan line 420 overlaps with the third longitudinal part 311 of the upper semiconductor pattern 310. A part of the third longitudinal part 311 of the upper semiconductor pattern 310 may be the first electrode region of the fourth transistor T4, and this part is located below the overlapping region between the third scan line 420 and the third longitudinal part 311, and the part of the third longitudinal part 311 of the upper semiconductor pattern 310 that is located above the overlapping region may be the second electrode region of the fourth transistor T4. The channel region of the fourth transistor T4 may be located between its first electrode region and the second electrode region, and the channel region of the fourth transistor T4 may overlap with the third scan line 420.

[0108] In the plan view, the storage capacitor electrode 320 may be located at the central part of the pixel PX. The storage capacitor electrode 320 overlaps with the gate electrode 240 of the first transistor T1 below the storage capacitor electrode 320, and the second insulating layer 720 is located between the storage capacitor electrode 320 and the gate electrode 240 to form the storage capacitor Cst. The gate electrode 240 of the first transistor T1 may be the first electrode of the storage capacitor Cst, the part of the storage capacitor electrode 320 that overlaps with the gate electrode 240 may be the second electrode of the storage capacitor Cst, and the second insulating layer 720 between the storage capacitor electrode 320 and the gate electrode 240 may be the dielectric of the storage capacitor Cst. The storage capacitor electrode 320 may include an opening that overlaps with the gate electrode 240 of the first transistor T1 located below the storage capacitor electrode 320.

[0109] The upper semiconductor layer 300 may include an oxide semiconductor. For example, the upper semiconductor layer 300 may include a binary compound (AB x ) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), and / or the like, a ternary compound (AB x C y ) or a quaternary compound (AB x C y D z ). In one exemplary embodiment, the upper semiconductor layer 300 may include ITZO (oxide containing indium, tin, and zinc) or IGZO (oxide containing indium, gallium, and zinc).

[0110] The third insulating layer 730 may be located on the upper semiconductor layer 300 and generally on the entire surface of the substrate SUB1. For example, in some embodiments, the third insulating layer 730 is located on the upper semiconductor layer 300 and the second insulating layer 720. The third insulating layer 730 may be a gate insulating film having a gate insulating function.

[0111] The third insulating layer 730 may include a silicon compound, a metal oxide, and / or the like. For example, the third insulating layer 730 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and / or the like. The above materials may be used alone or in combination. The third insulating layer 730 may be formed as a single-layer film or a multi-layer film of a stacked film having different materials.

[0112] The second conductive layer 400 is located on the third insulating layer 730. The second conductive layer 400 may include a second scan line 410 for transmitting a second scan signal (understood hereinafter as representing Figure 2 the second scan signal GW_N[n]), a third scan line 420 for transmitting a third scan signal (understood hereinafter as representing Figure 2 the third scan signal GI_N[n]), a first initialization voltage line 430 for transmitting an initialization voltage (understood hereinafter as representing Figure 2 the initialization voltage VINT), and a second initialization voltage line 440.

[0113] Each of the second scan line 410, the third scan line 420, the first initialization voltage line 430, and the second initialization voltage line 440 may extend in the row direction. Each of the second scan line 410, the third scan line 420, the first initialization voltage line 430, and the second initialization voltage line 440 may extend in the row direction beyond the boundary of the pixel PX toward an adjacent pixel PX (e.g., a neighboring or nearest pixel PX). The second scan line 410, the third scan line 420, the first initialization voltage line 430, and the second initialization voltage line 440 may overlap with the lower semiconductor layer 100.

[0114] The position of the third scan line 420 may be closer to the lower portion of the pixel PX than the second scan line 410. The second scan line 410 and the third scan line 420 extend in the same directions as the first scan line 210 and the fourth scan line 230, respectively, and may be positioned such that at least a portion of the second scan line 410 and the third scan line 420 overlap with the first scan line 210 and the fourth scan line 230, respectively. Accordingly, each of the first scan line 210 and the fourth scan line 230 may be used as a gate electrode of a transistor (e.g., the second transistor T2 or the seventh transistor T7), and may also be used as a lower light-blocking pattern of another transistor adjacent to the transistor (e.g., the third transistor T3 or the fourth transistor T4). For a more detailed description thereof, reference will be made to Figures 7 to 9 .

[0115] Figure 7 is Figure 3 a layout diagram of the first conductive layer 200 and the second conductive layer 400. Figure 8 is a cross-sectional view taken along Figure 3 lines A-A' and B-B' of Figure 9 is a cross-sectional view taken along Figure 3 lines C-C' and D-D' of

[0116] Reference is made to Figure 3 and Figures 7 to 9, the entire second scan line 410 may overlap with the first scan line 210, while only a portion of the first scan line 210 may overlap with the second scan line 410. In some embodiments, the entire third scan line 420 may overlap with the fourth scan line 230, while only a portion of the fourth scan line 230 may overlap with the third scan line 420. For example, the width of the second scan line 410 in the column direction may be less than or equal to the width of the first scan line 210 in the column direction, and the second scan line 410 may completely overlap with the first scan line 210, while only a portion of the first scan line 210 may overlap with the second scan line 410. For example, a portion of the first scan line 210 may overlap with the entire second scan line 410. In some embodiments, the width of the third scan line 420 in the column direction may be less than or equal to the width of the fourth scan line 230 in the column direction, and the third scan line 420 may completely overlap with the fourth scan line 230, while only a portion of the fourth scan line 230 may overlap with the third scan line 420. For example, a portion of the fourth scan line 230 may overlap with the entire third scan line 420.

[0117] The shape of the second scan line 410 may be the same as or substantially the same as the shape of the first scan line 210, and the shape of the third scan line 420 may be the same as or substantially the same as the shape of the fourth scan line 230. Here, the term "the same or substantially the same shape" does not necessarily mean the same size (e.g., dimensions), but means that they can be formed with the same or substantially the same pattern. For example, although the second scan line 410 and the third scan line 420 may respectively have the same overall pattern as the first scan line 210 and the fourth scan line 230, the second scan line 410 and the third scan line 420 may respectively have the same or different sizes (e.g., widths) compared to the first scan line 210 and the fourth scan line 230.

[0118] In addition, in one pixel PX, the area of the first scan line 210 in the plan view may be greater than the area of the second scan line 410 in the plan view, and the area of the fourth scan line 230 in the plan view may be greater than the area of the third scan line 420 in the plan view.

[0119] However, the present disclosure is not limited thereto. For example, in some embodiments, only in the region where the first scan line 210 and the second scan line 410 overlap with the upper semiconductor pattern 310, the width of the first scan line 210 in the column direction may be greater than or equal to the width of the second scan line 410 in the column direction, and the first scan line 210 may completely overlap with the second scan line 410 at the region where the first scan line 210 and the second scan line 410 overlap with the upper semiconductor pattern 310. Outside the region where the first scan line 210 and the second scan line 410 overlap with the upper semiconductor pattern 310, the width of the first scan line 210 in the column direction may be less than the width of the second scan line 410 in the column direction. In some embodiments, outside the region where the first scan line 210 and the second scan line 410 overlap with the upper semiconductor pattern 310, the first scan line 210 and the second scan line 410 may partially overlap with each other or may not overlap. In some embodiments, only in the region where the fourth scan line 230 and the third scan line 420 overlap with the upper semiconductor pattern 310, the width of the fourth scan line 230 in the column direction may be greater than or equal to the width of the third scan line 420 in the column direction, and the fourth scan line 230 may completely overlap with the third scan line 420 at the region where the fourth scan line 230 and the third scan line 420 overlap with the upper semiconductor pattern 310. Outside the region where the fourth scan line 230 and the third scan line 420 overlap with the upper semiconductor pattern 310, the width of the fourth scan line 230 in the column direction may be less than the width of the third scan line 420 in the column direction. In some embodiments, outside the region where the fourth scan line 230 and the third scan line 420 overlap with the upper semiconductor pattern 310, the fourth scan line 230 and the third scan line 420 may partially overlap with each other or may not overlap.

[0120] The width of the channel region CT3 of the third transistor T3 in the column direction may not be greater than the width of the second scan line 410 in the column direction, and the first scan line 210 may completely overlap with the channel region CT3 of the third transistor T3. For example, the width of the first scan line 210 in the column direction may be greater than or equal to the width of the channel region CT3 of the third transistor T3 in the column direction, and in the plan view, the first scan line 210 may surround the channel region CT3 of the third transistor T3.

[0121] In some embodiments, the width of the channel region CT4 of the fourth transistor T4 in the column direction may not be greater than the width of the third scan line 420 in the column direction, and the fourth scan line 230 may completely overlap with the channel region CT4 of the fourth transistor T4. For example, the width of the fourth scan line 230 in the column direction may be greater than or equal to the width of the channel region CT4 of the fourth transistor T4 in the column direction, and in the plan view, the fourth scan line 230 may surround the channel region CT4 of the fourth transistor T4.

[0122] The second transistor T2 is formed on the lower semiconductor layer 100 in a region where the lower semiconductor layer 100 and the first scan line 210 overlap each other. The third transistor T3 is formed in a region where the upper semiconductor pattern 310 and the second scan line 410 overlap each other. The second scan line 410 overlaps with the first scan line 210 such that the second transistor T2 can overlap with the second scan line 410, and the third transistor T3 can overlap with the first scan line 210. For example, the second transistor T2 and the third transistor T3 can be formed along one scan line (e.g., the first scan line 210 or the second scan line 410). For example, the second transistor T2 and the third transistor T3 can be formed alternately in the extending direction of the first scan line 210 and the extending direction of the second scan line 410.

[0123] In addition, the seventh transistor T7 is formed on the lower semiconductor layer 100 in a region where the lower semiconductor layer 100 and the fourth scan line 230 overlap each other. The fourth transistor T4 is formed in a region where the upper semiconductor pattern 310 and the third scan line 420 overlap each other. The third scan line 420 overlaps with the fourth scan line 230 such that the seventh transistor T7 can overlap with the third scan line 420, and the fourth transistor T4 can overlap with the fourth scan line 230. For example, the fourth transistor T4 and the seventh transistor T7 can be formed along one scan line (e.g., the fourth scan line 230 or the third scan line 420). For example, the fourth transistor T4 and the seventh transistor T7 can be formed alternately in the extending direction of the fourth scan line 230 and the extending direction of the third scan line 420.

[0124] Each of the first scan line 210 and the fourth scan line 230 can perform the function of a gate electrode in one transistor and can also perform the function of a lower light-blocking pattern in another transistor adjacent to the one transistor. The lower light-blocking pattern indicates a component for preventing or reducing light incident from the lower part of the display device 1 from entering the upper semiconductor pattern 310 positioned above the lower light-blocking pattern. The lower light-blocking pattern can overlap with the channel regions of the transistors (e.g., the third transistor T3 and the fourth transistor T4) having channels formed in the upper semiconductor pattern 310.

[0125] For example, the first scan line 210 can be located between the lower semiconductor layer 100 and the second scan line 410 in the region where the second transistor T2 is disposed (hereinafter referred to as the second transistor region AT2) to perform the function of the gate electrode of the second transistor T2. Additionally, in the region where the third transistor T3 is disposed on the right side of the second transistor T2 (hereinafter referred to as the third transistor region AT3), the first scan line 210 can be located below the upper semiconductor pattern 310 and the second scan line 410 to perform the function of the lower light-blocking pattern of the third transistor T3.

[0126] In some embodiments, the fourth scan line 230 may be positioned below the upper semiconductor pattern 310 and the third scan line 420 in the region where the fourth transistor T4 is disposed (hereinafter, referred to as the fourth transistor region AT4) to perform the function of the lower light-blocking pattern of the fourth transistor T4. Additionally, in the region where the seventh transistor T7 is disposed on the right side of the fourth transistor T4 (hereinafter, referred to as the seventh transistor region AT7), the fourth scan line 230 may be positioned between the lower semiconductor layer 100 and the third scan line 420 to perform the function of the gate electrode of the seventh transistor T7.

[0127] As described above, since one scan line (e.g., the first scan line 210 or the fourth scan line 230) serves as a gate electrode and a lower light-blocking pattern in different regions (e.g., the gate electrode in the second transistor region AT2 and the lower light-blocking pattern in the third transistor region AT3 for the first scan line 210, or the gate electrode in the seventh transistor region AT7 and the lower light-blocking pattern in the fourth transistor region AT4 for the fourth scan line 230), a separate lower light-blocking pattern may not be required. For example, in one pixel PX, a separate space utilized for designing the above-mentioned separate lower light-blocking pattern may not be required, thereby reducing the space utilized for that one pixel PX. Accordingly, more pixels PX may be located in the display device 1, and thus the resolution may be improved.

[0128] Referring again to Figures 3 to 6 , in a plan view, the first initialization voltage line 430 and the second initialization voltage line 440 may be positioned between the fourth scan line 230 and the emission control line 220. The first initialization voltage line 430 may be positioned above the second initialization voltage line 440. In some embodiments, the second initialization voltage line 440 may be electrically connected to the first initialization voltage line 430 through a contact hole outside the display unit 1, or may directly receive the initialization voltage VINT from an external voltage source, and the initialization voltage VINT is equal to the voltage at the first initialization voltage line 430. In another exemplary embodiment, either the first initialization voltage line 430 or the second initialization voltage line 440 may be omitted.

[0129] The second scan line 410 may include the gate electrode of the third transistor T3, the third scan line 420 may include the gate electrode of the fourth transistor T4, and the emission control line 220 may include the gate electrode of the sixth transistor T6. The widths of the gate electrodes of the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be greater than the widths of the lines near the gate electrodes of the third transistor T3, the fourth transistor T4, and the sixth transistor T6, but the present disclosure is not limited thereto.

[0130] The second conductive layer 400 may include at least one selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu.

[0131] The fourth insulating layer 740 covers the second conductive layer 400. The fourth insulating layer 740 may generally be located above the entire surface of the substrate SUB1. For example, in some embodiments, the fourth insulating layer 740 may be located on the second conductive layer 400. The fourth insulating layer 740 is used to insulate the second conductive layer 400 and the third conductive layer 500 from each other. The fourth insulating layer 740 may be an interlayer insulating film. The fourth insulating layer 740 may include the same material as the second insulating layer 720 described above, or may include at least one material selected from the exemplified materials constituting the second insulating layer 720. In some embodiments, the fourth insulating layer 740 may include at least one material selected from a plurality of materials that may be included in the second insulating layer 720. The fourth insulating layer 740 may be formed as a single-layer film or a multi-layer film including stacked films of different materials.

[0132] The third conductive layer 500 may be located on the fourth insulating layer 740. The third conductive layer 500 may include data lines 560 for transmitting data signals (hereinafter understood to represent Figure 2 the data signal DATA), a first power supply voltage line 570 for supplying a first power supply voltage (hereinafter understood to represent Figure 2 the first power supply voltage ELVDD), and a plurality of data patterns 510, 520, 530, 540, and 550.

[0133] The data lines 560 may extend in the column direction. The data lines 560 may extend in the column direction toward adjacent pixels PX (e.g., neighboring or the nearest pixel PX) beyond the boundary of the pixel PX. The data lines 560 may be adjacent to the left side of the pixel PX. The data lines 560 may overlap with the first longitudinal portion 110 of the lower semiconductor layer 100.

[0134] The data lines 560 may be in contact with (e.g., electrically contact) a first region 111 of the first longitudinal portion 110 of the lower semiconductor layer 100 through first contact holes CNT1, and the first contact holes CNT1 expose the first region 111 of the first longitudinal portion 110 of the lower semiconductor layer 100 while passing through the fourth insulating layer 740, the third insulating layer 730, the second insulating layer 720, and the first insulating layer 710. In a plan view, the first contact holes CNT1 may be located above the first scan line 210, but the present disclosure is not limited thereto.

[0135] The first power supply voltage line 570 may extend in the column direction. The first power supply voltage line 570 may extend in the column direction towards an adjacent pixel PX (e.g., a neighboring or nearest pixel PX) beyond the boundary of the pixel PX. The first power supply voltage line 570 may be substantially adjacent to the left side of the pixel PX at the right side of the data line 560, but the present disclosure is not limited thereto. For example, the first power supply voltage line 570 may be located at the right side of the data line 560 and may be closer to the left side of the pixel PX than the right side of the pixel PX.

[0136] The first power supply voltage line 570 may be in contact with (e.g., electrically contact) a second region 112 of a first longitudinal portion 110 of the lower semiconductor layer 100 through a second contact hole CNT2, and the second contact hole CNT2 exposes the second region 112 of the first longitudinal portion 110 of the lower semiconductor layer 100 while passing through the fourth insulating layer 740, the third insulating layer 730, the second insulating layer 720, and the first insulating layer 710. In a plan view, the second contact hole CNT2 may be positioned below the light emission control line 220, but the present disclosure is not limited thereto.

[0137] The first power supply voltage line 570 may be in contact with (e.g., electrically contact) the storage capacitor electrode 320 through a third contact hole CNT3, and the third contact hole CNT3 exposes the storage capacitor electrode 320 while passing through the fourth insulating layer 740 and the third insulating layer 730.

[0138] The plurality of data patterns may include a first data pattern 510, a second data pattern 520, a third data pattern 530, a fourth data pattern 540, and a fifth data pattern 550. Each of the plurality of data patterns 510, 520, 530, 540, and 550 has a shape that extends substantially in the column direction, and the length of the plurality of data patterns 510, 520, 530, 540, and 550 in the column direction is less than the length of the pixel PX in the column direction. The plurality of data patterns 510, 520, 530, 540, and 550 are physically spaced apart from each other. The spaced-apart portions of the plurality of data patterns 510, 520, 530, 540, and 550 are electrically coupled to each other.

[0139] The first data pattern 510 may overlap with the gate electrode 240 of the first transistor T1. In the overlapping region between the first data pattern 510 and the gate electrode 240, the first data pattern 510 may be electrically connected to the gate electrode 240 of the first transistor T1 through the fourth contact hole CNT4, while the fourth contact hole CNT4 exposes the gate electrode 240 of the first transistor T1 while passing through the fourth insulating layer 740, the third insulating layer 730, and the second insulating layer 720. The fourth contact hole CNT4 may be positioned in the opening of the storage capacitor electrode 320. The first data pattern 510 in the fourth contact hole CNT4 and the adjacent storage capacitor electrode 320 may be insulated from each other by the third insulating layer 730 and the fourth insulating layer 740.

[0140] In addition, the first data pattern 510 may extend upward from the overlapping region between the first data pattern 510 and the gate electrode 240 of the first transistor T1, and cross or intersect with the first scan line 210 and the second scan line 410 while being insulated from the first scan line 210 and the second scan line 410. The first data pattern 510 may further extend upward to overlap with the upper semiconductor pattern 310. In the overlapping region (e.g., the region where the first data pattern 510 and the upper semiconductor pattern 310 overlap), the first data pattern 510 may be electrically connected to the upper semiconductor pattern 310 through the fifth contact hole CNT5, while the fifth contact hole CNT5 exposes the upper semiconductor pattern 310 while passing through the fourth insulating layer 740 and the third insulating layer 730.

[0141] The second data pattern 520 may overlap with the first lateral portion 130 of the lower semiconductor layer 100 and / or the third region 121 of the second longitudinal portion 120. In the overlapping region between the second data pattern 520 and the first lateral portion 130 and / or the third region 121, the second data pattern 520 may be in contact (e.g., electrical contact) with the first lateral portion 130 of the lower semiconductor layer 100 and / or the third region 121 of the second longitudinal portion 120 through the sixth contact hole CNT6, while the sixth contact hole CNT6 exposes the first lateral portion 130 of the lower semiconductor layer 100 and / or the third region 121 of the second longitudinal portion 120 while passing through the fourth insulating layer 740, the third insulating layer 730, the second insulating layer 720, and the first insulating layer 710.

[0142] In addition, the second data pattern 520 may extend upward from an overlapping region between the second data pattern 520 and a third region 121 of the first lateral portion 130 and / or the second longitudinal portion 120 of the lower semiconductor layer 100 to overlap with a fourth longitudinal portion 312 of the upper semiconductor pattern 310. In the overlapping region between the second data pattern 520 and the fourth longitudinal portion 312, the second data pattern 520 may be in contact with (e.g., electrically connected to) the fourth longitudinal portion 312 of the upper semiconductor pattern 310 through a seventh contact hole CNT7, and the seventh contact hole CNT7 exposes the fourth longitudinal portion 312 of the upper semiconductor pattern 310 while passing through the fourth insulating layer 740 and the third insulating layer 730. Accordingly, the lower semiconductor layer 100 and the fourth longitudinal portion 312 of the upper semiconductor pattern 310 may be electrically coupled to each other through the second data pattern 520.

[0143] The third data pattern 530 may overlap with a third longitudinal portion 311 of the upper semiconductor pattern 310. In the overlapping region between the third data pattern 530 and the third longitudinal portion 311, the third data pattern 530 may be in contact with (e.g., electrically connected to) the third longitudinal portion 311 of the upper semiconductor pattern 310 through an eighth contact hole CNT8, and the eighth contact hole CNT8 exposes the third longitudinal portion 311 of the upper semiconductor pattern 310 while passing through the fourth insulating layer 740 and the third insulating layer 730.

[0144] In addition, in a plan view, the third data pattern 530 may extend upward from an overlapping region between the third data pattern 530 and the third longitudinal portion 311 of the upper semiconductor pattern 310 and cross or intersect with the second initialization voltage line 440 while being insulated from the second initialization voltage line 440. The third data pattern 530 may further extend upward from a crossing region or an intersecting region between the third data pattern 530 and the second initialization voltage line 440 to overlap with the first initialization voltage line 430. In the overlapping region between the third data pattern 530 and the first initialization voltage line 430, the third data pattern 530 may be in contact with (e.g., electrically connected to) the first initialization voltage line 430 through a ninth contact hole CNT9, and the ninth contact hole CNT9 exposes the first initialization voltage line 430 while passing through the fourth insulating layer 740. Accordingly, the third longitudinal portion 311 of the upper semiconductor pattern 310 may be electrically coupled to the first initialization voltage line 430 through the ninth contact hole CNT9. For example, the third longitudinal portion 311 of the upper semiconductor pattern 310 may be electrically coupled to the first initialization voltage line 430 through the third data pattern 530.

[0145] The fourth data pattern 540 may overlap with a fourth region 122 of a second longitudinal portion 120 of the lower semiconductor layer 100. In an overlapping region between the fourth data pattern 540 and the fourth region 122, the fourth data pattern 540 may contact (e.g., electrically contact) the fourth region 122 of the second longitudinal portion 120 of the lower semiconductor layer 100 through a tenth contact hole CNT10, while the tenth contact hole CNT10 exposes the fourth region 122 of the second longitudinal portion 120 of the lower semiconductor layer 100 while passing through the fourth insulating layer 740, the third insulating layer 730, the second insulating layer 720, and the first insulating layer 710. The tenth contact hole CNT10 may be positioned below the third scan line 420 and the fourth scan line 230, but the present disclosure is not limited thereto.

[0146] In addition, the fourth data pattern 540 may further extend upward from the overlapping region between the fourth data pattern 540 and the fourth region 122 of the second longitudinal portion 120 of the lower semiconductor layer 100 to cross or intersect with the third scan line 420 and the fourth scan line 230 while being insulated from the third scan line 420 and the fourth scan line 230. The fourth data pattern 540 may further extend upward from the crossing or intersecting region between the fourth data pattern 540 and the third scan line 420 and the fourth scan line 230 to overlap with the second initialization voltage line 440. In an overlapping region between the fourth data pattern 540 and the second initialization voltage line 440, the fourth data pattern 540 may contact (e.g., electrically contact) the second initialization voltage line 440 through an eleventh contact hole CNT11, while the eleventh contact hole CNT11 exposes the second initialization voltage line 440 while passing through the fourth insulating layer 740. Accordingly, the fourth region 122 of the second longitudinal portion 120 of the lower semiconductor layer 100 may be electrically connected to the second initialization voltage line 440 through the eleventh contact hole CNT11. For example, the fourth region 122 of the second longitudinal portion 120 of the lower semiconductor layer 100 may be electrically coupled to the second initialization voltage line 440 through the fourth data pattern 540.

[0147] The fifth data pattern 550 may overlap with a third region 121 of a second longitudinal portion 120 of the lower semiconductor layer 100. In an overlapping region between the fifth data pattern 550 and the third region 121, the fifth data pattern 550 may contact (e.g., electrically contact) the third region 121 of the second longitudinal portion 120 of the lower semiconductor layer 100 through a twelfth contact hole CNT12, while the twelfth contact hole CNT12 exposes the third region 121 of the second longitudinal portion 120 of the lower semiconductor layer 100 while passing through the fourth insulating layer 740, the third insulating layer 730, the second insulating layer 720, and the first insulating layer 710. The fifth data pattern 550 may be coupled (e.g., electrically coupled) to an anode ANO of the organic light emitting diode. A more detailed description thereof is provided hereinbelow.

[0148] The third conductive layer 500 may include at least one selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The third conductive layer 500 may be formed as a single-layer film or a multi-layer film. For example, the third conductive layer 500 may be formed as a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, and / or the like.

[0149] In some embodiments, the fifth insulating layer, the fourth conductive layer 600, the organic light-emitting layer, and the fifth conductive layer may be sequentially located on the third conductive layer 500. The anode ANO of the organic light-emitting diode may be formed by the fourth conductive layer 600, and its cathode may be formed by the fifth conductive layer. The anode ANO may be electrically connected to the fifth data pattern 550 through a contact hole passing through the fifth insulating layer.

[0150] Hereinafter, other exemplary embodiments will be described. In the following exemplary embodiments, the repeated description of components identical to those of the above exemplary embodiments will be simplified or not repeated, and the differences will be mainly described.

[0151] Figure 10 is a layout diagram of the first conductive layer 200_1 and the second conductive layer 400 according to another exemplary embodiment. Figure 11 is along Figure 10 sectional views taken along lines E-E' and F-F'. Figure 12 is along Figure 10 sectional views taken along lines G-G' and H-H'.

[0152] Referring to Figures 10 to 12 this exemplary embodiment is different from the exemplary embodiment described with reference to Figure 4 in that the first conductive layer 200_1 includes a first light-emitting control line 221_1 and a second light-emitting control line 222_1, the second scanning line 410 overlaps with the first light-emitting control line 221_1, and the third scanning line 420 overlaps with the second light-emitting control line 222_1.

[0153] For example, the first conductive layer 200_1 may include a first light-emitting control line 221_1 and a second light-emitting control line 222_1, as well as a first scanning line 210, a fourth scanning line 230, and a gate electrode 240 of the first transistor T1. The second conductive layer 400 includes a second scanning line 410, a third scanning line 420, a first initialization voltage line 430, and a second initialization voltage line 440.

[0154] The second scan line 410 extends in the same direction as the first light emission control line 221_1 (e.g., in the row direction), and the second scan line 410 overlaps with the first light emission control line 221_1. The overlapping region between the second scan line 410 and the first light emission control line 221_1 may overlap with the fifth transistor T5 and the third transistor T3. In addition, the third scan line 420 extends in the same direction as the second light emission control line 222_1 (e.g., in the row direction), and the third scan line 420 overlaps with the second light emission control line 222_1. The overlapping region between the third scan line 420 and the second light emission control line 222_1 may overlap with the fourth transistor T4 and the sixth transistor T6.

[0155] Accordingly, the first light emission control line 221_1 may function as the gate electrode of the fifth transistor T5 in the region where the fifth transistor T5 is disposed (hereinafter, referred to as the fifth transistor region AT5), and may function as the lower light-blocking pattern of the third transistor T3 in the third transistor region AT3. In addition, the second light emission control line 222_1 may function as the gate electrode of the sixth transistor T6 in the region where the sixth transistor T6 is disposed (hereinafter, referred to as the sixth transistor region AT6), and may function as the lower light-blocking pattern of the fourth transistor T4 in the fourth transistor region AT4.

[0156] In this case, a separate lower light-blocking pattern may not be required, and thus, in one pixel PX, a separate space used for designing a separate lower light-blocking pattern may not be required. The space used for the one pixel PX is reduced, and more pixels PX may be located in the display device 1, and thus the resolution may be improved. In addition, in the case of the present exemplary embodiment, the plurality of light emission control lines 221_1 and 222_1 function as the lower light-blocking patterns of the third transistor T3 and the fourth transistor T4, and the third transistor T3 and the fourth transistor T4 are NMOS transistors, and the light emission control lines may be maintained at a low-level voltage for a long time during light emission, and thus the turn-off characteristics of the third transistor T3 and the fourth transistor T4 may be advantageous. Accordingly, the occurrence of leakage current may be prevented or reduced, and the display device 1 may be driven more stably.

[0157] Figure 13 is a layout diagram of the first conductive layer 200_2 and the second conductive layer 400_2 according to another exemplary embodiment. Figure 14 is along Figure 13 a cross-sectional view taken along line XIV-XIV'. Figure 15 is along Figure 13 a cross-sectional view taken along line XV-XV'.

[0158] Referring to Figures 13 to 15 this, the present exemplary embodiment is the same as that referring to Figure 4The exemplary embodiment described is different in that the first conductive layer 200_2 includes a first initialization voltage line 250 and a second initialization voltage line 260, the second scan line 410 overlaps with the first initialization voltage line 250, and the third scan line 420 overlaps with the second initialization voltage line 260.

[0159] For example, the first conductive layer 200_2 includes a first initialization voltage line 250, a second initialization voltage line 260, a first scan line 210, a light emission control line 220, a fourth scan line 230, and a gate electrode 240 of the first transistor T1. The second conductive layer 400_2 includes a second scan line 410 and a third scan line 420. For example, the first initialization voltage line 250 and the second initialization voltage line 260 may be located in the same layer as the first scan line 210, the light emission control line 220, the fourth scan line 230, and the gate electrode 240 of the first transistor T1.

[0160] The second scan line 410 extends in the same direction as the first initialization voltage line 250 (e.g., in the row direction), and the second scan line 410 overlaps with the first initialization voltage line 250. The overlapping region between the second scan line 410 and the first initialization voltage line 250 may overlap with the third transistor T3. In addition, the third scan line 420 extends in the same direction as the second initialization voltage line 260 (e.g., in the row direction), and the third scan line 420 overlaps with the second initialization voltage line 260. The overlapping region between the third scan line 420 and the second initialization voltage line 260 may overlap with the fourth transistor T4.

[0161] Accordingly, the first initialization voltage line 250 and the second initialization voltage line 260 that transmit the initialization voltage from an external power source may perform the function of the lower light-blocking pattern. For example, the first initialization voltage line 250 may perform the function of the lower light-blocking pattern of the third transistor T3 in the third transistor region AT3, and the second initialization voltage line 260 may perform the function of the lower light-blocking pattern of the fourth transistor T4 in the fourth transistor region AT4.

[0162] In this case, a separate lower light-blocking pattern may not be required, and thus, in one pixel PX, a separate space used for designing a separate lower light-blocking pattern may not be required. The space used for this one pixel PX is reduced, and more pixels PX may be located in the display device 1, and thus the resolution may be improved.

[0163] Although some of the embodiments of the present disclosure have been described with reference to the drawings, those skilled in the art will understand that various modifications can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the above embodiments should be considered only for descriptive purposes and not for purposes of limitation.

Claims

1. A display device, comprising: a substrate; a first semiconductor layer, the first semiconductor layer being located on the surface of the substrate; a first scan line, the first scan line being located above the first semiconductor layer; a second semiconductor layer, the second semiconductor layer being located above the first scan line; a second scan line, the second scan line being located above the second semiconductor layer; a first transistor configured to control a driving current flowing from a first electrode of the first transistor to a second electrode of the first transistor according to a voltage applied to a gate electrode of the first transistor; a light-emitting element electrically connected to the second electrode of the first transistor and configured to emit light according to the driving current; a second transistor electrically connected to the first electrode of the first transistor and configured to transmit a data voltage; the first semiconductor layer forms a channel region of the first transistor and a channel region of the second transistor; the first scan line is electrically connected to a gate electrode of the second transistor and extends in a first direction; a third transistor configured to apply a voltage to the gate electrode of the first transistor and including a first electrode electrically connected to the second electrode of the first transistor and a second electrode electrically connected to the gate electrode of the first transistor; the second semiconductor layer forms a channel region of the third transistor; and the second scan line is electrically connected to a gate electrode of the third transistor and extends in the first direction, wherein the second scan line overlaps the first scan line in a second direction perpendicular to the surface of the substrate, wherein the channel region of the third transistor overlaps between the first scan line and the second scan line in the second direction, wherein the first scan line is configured to supply a first scan signal to the gate electrode of the second transistor, and the second scan line is configured to supply a second scan signal to the gate electrode of the third transistor, the second scan signal being different from the first scan signal, and wherein the first scan line and the second scan line are respectively connected to a scan driver to allow the first scan signal and the second scan signal to be independently supplied to respective gate electrodes of the second transistor and the third transistor.

2. The display device according to claim 1, wherein, the first transistor and the second transistor are p-type metal oxide semiconductor transistors, and the third transistor is an n-type metal oxide semiconductor transistor.

3. The display device according to claim 2, wherein, the p-type metal oxide semiconductor transistor includes polysilicon, and the n-type metal oxide semiconductor transistor includes an oxide semiconductor.

4. The display device according to claim 1, wherein, the second transistor includes a channel region overlapping the first scan line.

5. The display device according to claim 4, wherein, The channel region of the second transistor overlaps with the second scan line, and the first scan line is located between the channel region of the second transistor and the second scan line.

6. The display device according to claim 1, wherein the width of the first scan line in a third direction perpendicular to the first direction and the second direction is greater than the width of the second scan line in the third direction.

7. The display device according to claim 6, wherein the entire second scan line overlaps with the first scan line.

8. The display device according to claim 1, further comprising: a fourth transistor, the first electrode of the fourth transistor being electrically connected to the second electrode of the third transistor; a third scan line, the third scan line being electrically connected to the gate electrode of the fourth transistor; a fifth transistor, the fifth transistor being electrically connected to the second electrode of the fourth transistor; and a fourth scan line, the fourth scan line being electrically connected to the gate electrode of the fifth transistor, wherein the third scan line and the fourth scan line extend in the first direction and overlap with each other.

9. The display device according to claim 8, wherein the fourth transistor includes a channel region overlapping with the third scan line, and the channel region of the fourth transistor overlaps with the fourth scan line.

10. The display device according to claim 9, wherein the channel region of the fourth transistor is located between the third scan line and the fourth scan line.

11. The display device according to claim 10, wherein the fifth transistor includes a channel region overlapping with the fourth scan line.

12. The display device according to claim 8, wherein the fourth transistor is an n-type metal oxide semiconductor transistor, and the fifth transistor is a p-type metal oxide semiconductor transistor.

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