Cholesteric liquid crystal electronic paper display panel and driving method thereof

Abstract

The invention relates to the technical field of cholesteric liquid crystal electronic paper display, and discloses a cholesteric liquid crystal electronic paper display panel and a driving method thereof, and the cholesteric liquid crystal electronic paper display panel comprises an upper substrate, a lower substrate, a grid scanning line and a signal line, the electrode strip blocks continuously extend in the direction of a grid scanning line, each electrode strip block corresponds to one row of pixels, a single pixel corresponds to one pixel electrode, the electrode strip block corresponding to each row of pixels is conducted with the ITO electrode in the corresponding row through a conductive spacer, the ITO electrode is located on the periphery of a display area of the display panel, and in the direction of a signal line, the ITO electrode is connected with the electrode strip block in the corresponding row. The size of a single pixel is larger than the width L of each electrode strip block and larger than or equal to the width L'of a pixel electrode, and the distance S between every two adjacent electrode strip blocks is larger than or equal to the width W of a grid scanning line. According to the display panel and the driving method thereof, by optimizing the common electrode structure and the driving time sequence, the display performance and the refreshing efficiency of cholesteric liquid crystal electronic paper are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of cholesteric liquid crystal electronic paper display, and particularly relates to a cholesteric liquid crystal electronic paper display panel and a driving method thereof. Background Art

[0002] As an electronic device that simulates the display characteristics of paper, the cholesteric liquid crystal display technology of electronic paper achieves a bistable display effect through the selective reflection of a twisted liquid crystal layer. As Figure 1 shown, a typical active cholesteric liquid crystal display device adopts an upper and lower substrate structure. A common electrode is provided on the upper substrate and is connected to the AC common-level signal of the lower substrate through conductive particles. The lower substrate integrates a thin-film switch array to control pixel electrodes. Figure 2 is a common driving principle diagram of an active cholesteric liquid crystal display. The opening and closing of thin-film switches are controlled by gate scan lines, and pixel electrodes are charged through signal lines to the required corresponding voltages. During the driving process, a high voltage is first applied to make the liquid crystal enter the vertical state, and then the voltage returns to zero and is converted to the planar state to achieve color display. Then, a medium voltage is adjusted to form black display. However, for a common refresh timing as Figure 3 shown, in the existing line-by-line scanning driving method, under the control of gate scan lines, the timing differences of pixels in different rows result in inherent defects in the voltage conversion process. When the pixels in the first row complete the conversion from high voltage to zero voltage and enter the planar state, the pixels in the last row are still in the high voltage state, and will experience intermediate voltage interference related to the scanning time during subsequent conversions. This non-synchronous voltage change will hinder the complete conversion of liquid crystal molecules to the planar state, resulting in display color distortion and contrast reduction, seriously affecting the uniformity of the display screen and the color reproduction accuracy. Summary of the Invention

[0003] To solve the technical problems existing in the background art, the present invention proposes a cholesteric liquid crystal electronic paper display panel and a driving method thereof.

[0004] A cholesteric liquid crystal electronic paper display panel proposed by the present invention includes an upper substrate, a lower substrate, gate scan lines, and signal lines. A plurality of electrode strips that jointly form a common electrode are provided on the upper substrate. The electrode strips continuously extend in the direction of the gate scan lines. Each electrode strip corresponds to one row of pixels, and a single pixel corresponds to a pixel electrode. The electrode strips corresponding to each row of pixels are conducted to the ITO electrodes of the corresponding row through conductive spacers. The ITO electrodes are located outside the display area of the display panel. Among them, in the direction of the signal lines, the size of a single pixel > the width L of the electrode strip ≥ the width L' of the pixel electrode, and the distance S between two adjacent electrode strips ≥ the width W of the gate scan line.

[0005] Preferably, each ITO electrode corresponds to one row of pixels, is aligned with the direction of the gate scanning line, and the ITO electrodes of any one row of pixels are disconnected from the ITO electrodes of the remaining rows of pixels.

[0006] Preferably, the ITO electrode is connected to the common terminal AC common-level input signal through a thin-film switch, and the gate of the thin-film switch is connected to the same driving signal as the gate scanning line of the pixels corresponding to the ITO electrode.

[0007] Preferably, the voltage change of the electrode strip corresponding to each row of pixels is synchronized with the voltage change of the corresponding pixel electrode.

[0008] Preferably, the conductive spacer is made by exposing and developing a conductive photoresist material.

[0009] A driving method for a cholesteric liquid crystal electronic paper display panel proposed by the present invention is applied to the cholesteric liquid crystal electronic paper display panel described in any one of the above, and the driving method includes: Placing the cholesteric liquid crystal electronic paper display panel into the vertical state; Reducing the common terminal AC common-level input signal to 0V; Sequentially turning on the gate scanning line signals, controlling the corresponding thin-film switches to conduct, so that the AC common-level voltages of the common electrodes of each row of pixels are synchronized with the voltage changes of the pixel electrodes; Applying a pulsed voltage to the pixel electrodes to directly drive the liquid crystal to switch to the target display state in the vertical state, and the target display state includes a planar state, a focal conic state or a multi-level gray scale display.

[0010] Preferably, the applying a pulsed voltage to the pixel electrodes to directly drive the liquid crystal to switch to the target display state in the vertical state is specifically: When the display switches from the vertical state to the planar state, the AC common-level voltage of the nth row of pixels is controlled by the nth row gate scanning line signal, and only when the corresponding gate scanning line is turned on, the AC common-level voltage drops to 0V, so that the electrode strip corresponding to the nth row of pixels and the pixel electrode voltage synchronously return to zero, and the liquid crystal enters the planar state.

[0011] Preferably, the applying a pulsed voltage to the pixel electrodes to directly drive the liquid crystal to switch to the target display state in the vertical state is specifically: After the cholesteric liquid crystal enters the vertical state, directly reducing the AC common-level voltage to 0V in the vertical state, applying a pulsed voltage to the pixel electrodes, and controlling the liquid crystal to enter the planar state, the focal conic state or the multi-level gray scale display according to the amplitude of the pulsed voltage.

[0012] Preferably, the voltage range of the applied pulsed voltage is 0V to 20V, and the pulse time of the pulsed voltage is between 50ms and 500ms.

[0013] In the present invention, the proposed cholesteric liquid crystal electronic paper display panel and its driving method significantly improve the display performance and refresh efficiency of cholesteric liquid crystal electronic paper by optimizing the common electrode structure and driving timing. The strip-shaped common electrode design combined with row-level synchronous control makes the common electrode voltage of each row of pixels strictly synchronized to zero with the pixel electrode voltage, avoiding the residual intermediate voltage caused by progressive scanning. The direct driving in the vertical state eliminates the switching step, shortens the refresh cycle, and avoids the white flash phenomenon during the refresh process. Description of the Drawings

[0014] Figure 1 Schematic diagram of the structure of a single-layer cholesteric display device in the prior art; Figure 2 Schematic diagram of the driving principle of an active cholesteric liquid crystal display in the prior art; Figure 3 Schematic diagram of the refresh timing in the prior art; Figure 4 Schematic diagram of the driving principle of a cholesteric liquid crystal electronic paper display panel proposed by the present invention; Figure 5 Schematic cross-sectional structure of a cholesteric liquid crystal electronic paper display panel proposed by the present invention Figure 1 ; Figure 6 Schematic cross-sectional structure of a cholesteric liquid crystal electronic paper display panel proposed by the present invention Figure 2 ; Figure 7 Schematic diagram of the refresh timing of a cholesteric liquid crystal electronic paper display panel proposed by the present invention Figure 1 ; Figure 8 Schematic diagram of the refresh timing of a cholesteric liquid crystal electronic paper display panel proposed by the present invention Figure 2 ; Figure 9 Schematic diagram of the working process of a driving method of a cholesteric liquid crystal electronic paper display panel proposed by the present invention.

[0015] Legend: 1. Upper substrate; 2. Lower substrate; 3. Common electrode; 4. Pixel electrode; 5. Insulating layer 1; 6. Insulating layer 2; 7. Black matrix; 8. Gate scanning line; 9. Support structure; 10. Liquid crystal molecules; 11. Black ink; 12. ITO electrode; 13. Conductive spacer; 14. Thin film switch; 15. Signal line. Detailed Embodiments

[0016] Refer to Figures 4 - 8, a cholesteric liquid crystal electronic paper display panel proposed by the present invention, including an upper substrate 1, a lower substrate 2, a gate scanning line 8 and a signal line 15. On the upper substrate 1, a plurality of electrode strip blocks that jointly form a common electrode 3 are provided. The electrode strip blocks continuously extend in the direction of the gate scanning line 8. Each electrode strip block corresponds to one row of pixels, and a single pixel corresponds to a pixel electrode 4. The electrode strip blocks corresponding to each row of pixels are electrically connected to the ITO electrodes 12 of the corresponding row through conductive spacers 13. The ITO electrodes 12 are located on the periphery of the display area of the display panel. Among them, in the direction of the signal line 15, the size of a single pixel > the width L of the electrode strip block ≥ the width L' of the pixel electrode 4, and the spacing S between two adjacent electrode strip blocks ≥ the width W of the gate scanning line 8.

[0017] It should be noted that cholesteric liquid crystal (Cholesteric Liquid Crystal) will present various states under different conditions. The common ones include the H state, the P state, and the FC state. The following is a detailed description of these states: 1. H state (Homeotropic State, vertical state) Characteristics: The liquid crystal molecules are arranged perpendicular to the substrate surface, the helical structure is destroyed, and the helical axis of the cholesteric phase disappears.

[0018] Forming conditions: Usually formed under the action of a strong electric field or surface treatment (such as a vertical alignment layer).

[0019] Optical properties: It appears as a transparent state because the molecular arrangement is uniform, and light will not be scattered or selectively reflected when passing through.

[0020] Applications: Used in electro-optical devices, such as fast-switching transparent / scattering state displays.

[0021] 2. P state (Planar State, planar state) Characteristics: The liquid crystal molecules are arranged in a plane parallel to the substrate, the helical axis is perpendicular to the substrate surface, and the helical structure is complete.

[0022] Forming conditions: The state naturally presented by cholesteric liquid crystal under no external electric field or weak electric field.

[0023] Optical properties: It shows selective reflection, and the wavelength of the reflected light is determined by the pitch, usually presenting bright colors.

[0024] Applications: Used in reflective displays, optical filters, and color display devices.

[0025] Specifically, as Figure 4 shown, S1, S2,..., Sm are m signal lines 15 arranged in columns, and G1, G2,..., Gn are n gate scanning lines 8 arranged in rows.

[0026] Specifically, as Figure 5 shown, the common electrode 3 of the upper substrate 1 is divided from the whole surface into strip-shaped designs. The common electrode 3 remains unchanged in the direction of the gate scanning line 8 and adopts a disconnection design in the direction of the signal line 15. In the direction of the signal line 15, the size of a single pixel > the width L of the common electrode 3 ≥ the width L' of the pixel electrode 4; the pitch S of the common electrodes 3 ≥ the width W of the gate scanning line 8.

[0027] In this embodiment, each ITO electrode 12 corresponds to a row of pixels, is aligned with the direction of the gate scanning line 8, and the ITO electrodes 12 of any row of pixels are disconnected from the ITO electrodes 12 of the remaining rows of pixels.

[0028] In this embodiment, the ITO electrode 12 is connected to the common terminal AC common-level input signal through the thin-film switch 14, and the gate of the thin-film switch 14 is connected to the gate scanning line 8 of the corresponding row of pixels of the ITO electrode 12 to access the same driving signal.

[0029] In this embodiment, the voltage change of the electrode strip corresponding to each row of pixels is synchronized with the voltage change of the corresponding pixel electrode 4.

[0030] In this embodiment, the conductive spacer 13 is made by exposing and developing a conductive photoresist material.

[0031] Specifically, as Figure 6 shown, the common electrode 3 corresponding to each row of pixels is conducted with the ITO electrode 12 of the lower substrate 2 through the conductive spacer 13. The conductive spacer 13 can be made by exposing and developing a conductive photoresist material, or can be made by sputtering an ITO film on a common PS photoresist material. The ITO electrode 12 is located at the periphery of the display area and is disconnected from the ITO electrodes 12 of other rows of pixels. The ITO electrode 12 is connected to the AC common-level input signal through the thin-film switch 14, and the gate of the thin-film switch 14 is consistent with the signal of the gate scanning line 8 of this row of pixels.

[0032] Referring to Figures 4 - 9 , a driving method for a cholesteric liquid crystal electronic paper display panel proposed by the present invention is applied to the cholesteric liquid crystal electronic paper display panel of any one of the above, and the driving method includes the following steps: S1. Place the cholesteric liquid crystal electronic paper display panel in the vertical state; S2. Reduce the common terminal AC common-level input signal to 0V; S3. Turn on the gate scanning line signal row by row, control the corresponding row of thin-film switches 14 to conduct, and make the AC common-level voltage of the common electrodes of each row of pixels synchronized with the voltage change of the pixel electrode 4; S4. Apply a pulse voltage to the pixel electrode 4 to directly drive the liquid crystal to switch to the target display state in the vertical state, and the target display state includes the planar state, the focal conic state or multi-level gray-scale display.

[0033] Example 1

[0034] In this embodiment, a pulse voltage is applied to the pixel electrode 4 to directly drive the liquid crystal to switch to the target display state in the vertical state. Specifically:[[ID=⑥]] [[ID=⑦]]When the display switches from the vertical state to the planar state, the AC common voltage of the nth row of pixels is controlled by the signal of the nth row of gate scan lines 8. Only when the corresponding gate scan line 8 is turned on, the AC common voltage drops to 0V, so that the voltage of the electrode strip corresponding to the nth row of pixels and the pixel electrode 4 synchronously returns to zero, and the liquid crystal enters the planar state. [[ID=⑧]] [[ID=⑨]]

[0035] [[ID=⑩]]Specifically, as[[ID=⑪]] Figure 7 [[ID=⑫]]shown, when the display switches from the vertical state to the planar state, the source drive signals of the m signal lines 15 corresponding to the G1 row of gate scan lines 8 change from a high voltage to 0V to charge the pixel electrode 4. At the same time, the AC common input signal 1 also changes from a high voltage to 0V, and the voltage across the liquid crystal in the G1 row of pixels changes from a high voltage to 0V, and the liquid crystal changes to the planar state. [[ID=⑬]] [[ID=⑭]]

[0036] [[ID=⑮]]The voltage change of the AC common input signal n is controlled by the signal of the gate scan line 8 of the Gn row. Therefore, only when the gate scan line 8 of the Gn row is turned on, the voltage of the AC common input signal n will drop to 0V. The voltage change of the common electrode 3 of each row of pixels can be synchronized with the voltage change of the pixel electrode 4, and the planar state effect is better, and the picture display effect is better. [[ID=⑯]] [[ID=⑰]]

[0037] [[ID=⑱]]Example 2[[ID=⑲]] [[ID=⑳]]

[0038] [[ID=㉑]]In this embodiment, a pulse voltage is applied to the pixel electrode 4 to directly drive the liquid crystal to switch to the target display state in the vertical state. Specifically:[[ID=㉒]] [[ID=㉓]]After the cholesteric liquid crystal enters the vertical state, the AC common voltage is directly reduced to 0V in the vertical state, and a pulse voltage is applied to the pixel electrode 4, and the liquid crystal is controlled to enter the planar state, the focal conic state or the multi-level gray scale display according to the amplitude of the pulse voltage. [[ID=㉔]] [[ID=㉕]]

[0039] [[ID=㉖]]In this embodiment, the voltage range of the applied pulse voltage is 0V to 20V, and the pulse time of the pulse voltage is between 50ms and 500ms. [[ID=㉗]] [[ID=㉘]]

[0040] [[ID=㉙]]Specifically, after the cholesteric liquid crystal enters the vertical state, it does not refresh and enters the planar state. Directly in the vertical state, the AC common voltage is reduced to 0V. [[ID=㉚]] [[ID=㉛]]

[0041] [[ID=㉜]]Specifically, taking the 655nm liquid crystal as an example, the correspondence between the amplitude of the pulse voltage and the target display state is specifically:[[ID=㉝]] [[ID=㉞]]When the amplitude of the pulse voltage is 0V to 6V, the liquid crystal is driven to enter the planar state;[[ID=㉟]] [[ID=㊱]]When the amplitude of the pulse voltage is 7V to 15V, the liquid crystal is driven to achieve gray scale display; When the amplitude of the pulse voltage is 16V - 20V, it drives the liquid crystal into the focal conic state, showing black.

[0042] Taking 655nm cholesteric liquid crystal as an example, as Figure 8 shown, when a voltage in the range of 0 - 6V is applied in the vertical state, the liquid crystal can enter the planar state; when a voltage in the range of 16 - 18V is applied, the liquid crystal can enter the focal conic state; when a voltage in the range of 7 - 15V is applied, displays of different gray levels can be achieved.

[0043] As Figure 8 shown, this driving method can subtract the time for P - state refreshing compared with the original driving, improve the frame refreshing speed, and avoid the problem of white flash during the frame refreshing process.

[0044] As mentioned above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, making equivalent substitutions or changes, should be covered by the protection scope of the present invention.

Claims

1. A cholesteric liquid crystal electronic paper display panel, comprising an upper substrate (1), a lower substrate (2), a gate scanning line (8), and a signal line (15), characterized in that, On the upper substrate (1), there are multiple electrode strip blocks that jointly form a common electrode (3). The electrode strip blocks continuously extend in the direction of the gate scan line (8). Each electrode strip block corresponds to one row of pixels, and a single pixel corresponds to a pixel electrode (4). The electrode strip blocks corresponding to each row of pixels are electrically connected to the ITO electrodes (12) of the corresponding row through conductive spacers (13). The ITO electrodes (12) are located on the periphery of the display area of the display panel. Among them, in the direction of the signal line (15), the size of a single pixel > the width L of the electrode strip block ≥ the width L' of the pixel electrode (4), and the spacing S between two adjacent electrode strip blocks ≥ the width W of the gate scan line (8).

2. The cholesteric liquid crystal electronic paper display panel according to claim 1, characterized in that, Each ITO electrode (12) corresponds to one row of pixels and is aligned with the direction of the gate scan line (8). The ITO electrodes (12) of any row of pixels are disconnected from the ITO electrodes (12) of the remaining rows of pixels.

3. The cholesteric liquid crystal electronic paper display panel according to claim 2, wherein The ITO electrode (12) is connected to the common terminal AC common-level input signal through a thin-film switch (14). The gate of the thin-film switch (14) is connected to the same driving signal as the gate scan line (8) of the pixels corresponding to the ITO electrode (12).

4. The cholesteric liquid crystal electronic paper display panel according to claim 1, wherein The voltage change of the electrode strip block corresponding to each row of pixels is synchronized with the voltage change of the corresponding pixel electrode (4).

5. The cholesteric liquid crystal electronic paper display panel according to claim 1, characterized in that, The conductive spacer (13) is made by exposing and developing a conductive photoresist material.

6. A driving method for a cholesteric liquid crystal electronic paper display panel, characterized in that, Applied to the cholesteric liquid crystal electronic paper display panel according to any one of claims 1-5, the driving method includes: Placing the cholesteric liquid crystal electronic paper display panel into the vertical state; Reducing the common terminal AC common-level input signal to 0V; Sequentially turning on the gate scan line signals, controlling the corresponding thin-film switches (14) to conduct, so that the AC common-level voltages of the common electrodes of each row of pixels are synchronized with the voltage changes of the pixel electrodes (4); Applying a pulsed voltage to the pixel electrode (4) to directly drive the liquid crystal to switch to the target display state in the vertical state. The target display state includes the planar state, the focal conic state, or multi-level gray-scale display.

7. The driving method of the cholesteric liquid crystal electronic paper display panel according to claim 6, characterized in that, The applying a pulsed voltage to the pixel electrode (4) to directly drive the liquid crystal to switch to the target display state in the vertical state is specifically: When the display switches from the vertical state to the planar state, the AC common-level voltage of the nth row of pixels is controlled by the signal of the nth row of gate scan lines (8). Only when the corresponding gate scan line (8) is turned on, the AC common-level voltage drops to 0V, so that the voltage of the electrode strip block corresponding to the nth row of pixels and the pixel electrode (4) is synchronized to zero, and the liquid crystal enters the planar state.

8. The driving method of the cholesteric liquid crystal electronic paper display panel according to claim 6, characterized in that, The applying a pulsed voltage to the pixel electrode (4) to directly drive the liquid crystal to switch to the target display state in the vertical state is specifically: After the cholesteric liquid crystal enters the vertical state, directly reducing the AC common-level voltage to 0V in the vertical state, applying a pulsed voltage to the pixel electrode (4), and controlling the liquid crystal to enter the planar state, the focal conic state, or multi-level gray-scale display according to the amplitude of the pulsed voltage.

9. The driving method of the cholesteric liquid crystal electronic paper display panel according to claim 8, characterized in that The voltage range of the applied pulsed voltage is 0V~20V, and the pulse time of the pulsed voltage is between 50ms and 500ms.

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