Method and system for determining fast pass write operation in step programming pulse operation

Abstract

The present invention discloses a method and system for determining a fast-through write operation in a step programming pulse operation. The fast-through write operation is to simultaneously apply a bit line voltage in the step programming pulse operation. The method includes: estimating the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference according to a plurality of bit line voltages varying within a first range and a plurality of voltage differences relative to a verification voltage varying within a second range, and obtaining a reduction amount topographic map. Estimating the number of programming guns required to apply the step programming pulse operation to reach the programming verification voltage according to a plurality of the bit line voltages and a plurality of the voltage differences, and obtaining a programming gun number topographic map. After superimposing the reduction amount topographic map and the programming gun number topographic map, the operation area formed by the application range of the bit line voltage and the application range of the voltage difference is determined.

Description

Technical Field

[0001] The present invention relates to a memory operation technology, and more particularly to a method and system for determining a Quick PassWrite (QPW) operation in an Increment Step Pulse Programming (ISPP) operation. Background Art

[0002] In response to the wide application of various electronic products, flash memory is growing steadily in the market. In order to increase the storage capacity, the structure of the memory cell has also been developed into a memory cell that can store multiple bits, such as a multi-level cell (MLC), which uses different levels of the threshold voltage of the storage transistor to correspond to the stored data, thus achieving multi-bit storage. Flash memory is more exemplified by NAND-type flash memory, but is not limited thereto.

[0003] Since the threshold voltages of multiple transistors in the memory are not completely consistent, the threshold voltage of each order of these transistors is actually a distribution of packets. When the memory cell is a multi-level cell (MLC) structure, it will have multiple packets scattered between 0V and the program-verify (PV) voltage. If the width of the packet distribution is large, the tails of two adjacent packets are likely to overlap. If the threshold voltage corresponding to the read data falls in the overlapping area, it may cause data judgment errors, which requires some subsequent complex procedures to correct the error code.

[0004] If the width of the distribution of the threshold voltage packets can be reduced, it is expected that the overlap area can be reduced. This is one of the topics that need to be further developed in the operation of multi-level memory cells. Summary of the invention

[0005] The present invention provides a method and system for determining a fast through write operation in a step programming pulse operation. The present invention can determine the time point of introducing the fast through write operation in the step programming pulse operation, wherein the bit line voltage of the fast through write operation can also be set accordingly, so that the optimized operation region formed by the bit line voltage and the time point of the fast through write operation can be estimated.

[0006] In one embodiment, the present invention provides a method for determining a fast-through write operation in a step programming pulse operation. The step programming pulse operation is first applied to a plurality of memory cells of a memory cell array, and the fast-through write operation is to start the fast-through write operation after the gate voltage reaches a pre-programming verification voltage that is smaller than a programming verification voltage. There is a voltage difference from the pre-programming verification voltage to the programming verification voltage, and the fast-through write operation is to simultaneously apply a bit line voltage in the step programming pulse operation. The method for determining the fast-through write operation includes estimating the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference according to a plurality of the bit line voltages that vary within a first range and a plurality of the voltage differences that vary within a second range, and obtaining a reduction amount topographic map. Furthermore, estimating the number of programming guns required to apply the step programming pulse operation to reach the programming verification voltage according to the plurality of the bit line voltages and the plurality of the voltage differences, and obtaining a programming gun number topographic map. After superimposing the reduction amount topographic map and the programming gun number topographic map, an operation region formed by the application range of the bit line voltage and the application range of the voltage difference is determined.

[0007] In one embodiment, for the method of determining a fast pass write operation, the reduction amount of the threshold voltage distribution width is estimated for each bit line voltage at a step voltage, which includes estimating a change curve of the threshold voltage relative to the gate voltage for different voltage differences corresponding to the bit line voltage and the step voltage. According to the change curve, a slope at the programming verification voltage at the voltage difference is estimated. According to the slope and the step voltage, the reduction amount relative to the bit line voltage being 0V is estimated. The bit line voltage is a plurality of separate analysis values ​​from 0V to a predetermined value.

[0008] In one embodiment, for the method of determining a fast pass write operation, the operation region includes a triangle, and the base of the triangle is the range of the bit line voltage.

[0009] In one embodiment, for the method of determining a fast pass write operation, the reduction amount topography determines a first selected area based on the height of the bit line voltage, and the programming gun number topography determines a second selected area based on the height of the programming gun number, and at least a portion of the overlapping area between the first selected area and the second selected area is set as the operation area.

[0010] In one embodiment, for the method of determining a fast pass write operation, the estimation of the reduction amount of the threshold voltage distribution width includes comparing a model with experimental data based on the bit line voltage, the voltage difference and the step voltage of a predetermined sample to determine the correctness of the model.

[0011] In one embodiment, the present invention further provides a system for determining a fast-through write operation in a step programming pulse operation. The step programming pulse operation is first applied to a plurality of memory cells of a memory cell array, and the fast-through write operation is to start the fast-through write operation after the gate voltage reaches a pre-programming verification voltage that is smaller than a programming verification voltage. There is a voltage difference from the pre-programming verification voltage to the programming verification voltage. The fast-through write operation is to simultaneously apply a bit line voltage in the step programming pulse operation. The system for determining the fast-through write operation includes an analysis circuit and an analysis program storage unit, wherein the analysis circuit is configured to obtain an analysis program from the analysis program storage unit to operate the memory cell array to perform the following steps including estimating the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference according to the plurality of bit line voltages varying within a first range and the plurality of voltage differences varying within a second range, and obtaining a reduction amount topographic map. According to the plurality of bit line voltages and the plurality of voltage differences, estimating the number of programming guns required to apply the step programming pulse operation to reach the programming verification voltage, and obtaining a programming gun number topographic map. After the reduction amount map and the programming gun number map are superimposed, an operation region consisting of an application range of the bit line voltage and an application range of the voltage difference is determined.

[0012] In one embodiment, for the system for determining a fast pass write operation, the reduction amount of the threshold voltage distribution width is estimated for each bit line voltage at a step voltage, including estimating a change curve of the threshold voltage relative to the gate voltage at different voltage differences corresponding to the bit line voltage and the step voltage. According to the change curve, the slope of the programming verification voltage at the voltage difference is estimated. According to the slope and the step voltage, the reduction amount relative to the bit line voltage being 0V is estimated. The bit line voltage is a plurality of separate analysis values ​​from 0V to a predetermined value.

[0013] In one embodiment, for the system for determining a fast pass write operation, the operating region includes a triangle, the base of the triangle being the range of the bit line voltage.

[0014] In one embodiment, for the system for determining a fast pass write operation, the reduction amount topography determines a first selected area according to the height of the bit line voltage. The programming gun number topography determines a second selected area according to the height of the programming gun number. At least a portion of the overlapping area between the first selected area and the second selected area is set as the operation area.

[0015] In one embodiment, for the system for determining fast-through write operation, the estimation of the reduction amount of the threshold voltage distribution width includes comparing the bit line voltage, the voltage difference and the step voltage of a predetermined sample with experimental data to determine the correctness of the model.

[0016] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of threshold voltage distributions corresponding to multiple levels of MLC memory cells in a memory device according to an embodiment of the present invention is shown.

[0018] Figure 2 FIG. 1 is a schematic diagram of a change curve of a threshold voltage (Vt) of a memory cell relative to a gate voltage (Vg) according to an embodiment of the present invention.

[0019] Figure 3 According to an embodiment of the present invention, Figure 2 The data is converted into effective current density (J pgm ) relative to the effective gate voltage (Vg eff ) is a schematic diagram of the change curve of the inverse of .

[0020] Figure 4 FIG. 1 is a schematic diagram of a mechanism for performing an ISPP operation in conjunction with a QPW operation in the linear region of Vt versus Vg according to an embodiment of the present invention.

[0021] Figure 5 According to an embodiment of the present invention, according to the change of a voltage difference (ΔPV) from a pre-programming verification voltage to a programming verification voltage, according to Figure 2 Schematic diagram of the slope of the curve at the programming verification voltage.

[0022] Figure 6 The diagram is a schematic diagram of actually measuring the accumulation rate of a memory cell according to a change in a voltage difference (ΔPV) from a pre-programming verification voltage to a programming verification voltage according to an embodiment of the present invention.

[0023] Figure 7 The diagram is a comparison diagram of simulation data and measurement data for the reduction in the width of the threshold voltage packet distribution according to a change in a voltage difference (ΔPV) from a pre-programming verification voltage to a programming verification voltage according to an embodiment of the present invention.

[0024] Figure 8 It is a schematic diagram of a reduction amount map and a programming gun number map according to an embodiment of the present invention.

[0025] Fig. 9 FIG. 1 is a schematic diagram of an operation region of a quick pass write (QPW) operation determined by overlapping a reduction amount map with a programming gun count map according to an embodiment of the present invention.

[0026] Fig.10 FIG. 1 is a schematic diagram of the architecture of a system for determining a fast pass write operation according to an embodiment of the present invention.

[0027]

Explanation of symbols

[0028] 10: Reduction

[0029] 100: Reduced terrain map

[0030] 102, 104: Area

[0031] 110: Programming gun count map

[0032] 112, 114: Area

[0033] 200: Analyze the circuit

[0034] 202: memory cell array

[0035] 204: Storage unit DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0037] The present invention can determine the time point of introducing a quick pass write operation in a step programming pulse operation, wherein the bit line voltage of the quick pass write (QPW) operation can also be set accordingly, so that the optimal operation region formed by the bit line voltage and the time point of the quick pass write operation can be estimated. According to the model of the reduction amount topography and the programming gun number topography established by the present invention, the timing of introducing the quick pass write (QPW) operation and the range of the bit line voltage that can be applied can be determined after the two are interleaved and compared.

[0038] The present invention is described below with reference to some embodiments, but the present invention is not limited to the embodiments.

[0039] Figure 1 FIG. 1 is a schematic diagram of a threshold voltage distribution corresponding to multiple levels of multiple MLC memory cells in a memory device according to an embodiment of the present invention. Figure 1 , the threshold voltage distribution in the upper part is a general possible situation. For example, a two-bit memory cell has four threshold voltages for four storage states. The tail regions of the threshold voltage distribution corresponding to each level may overlap. For example, if the threshold voltage value read out of the memory cell falls in the overlapping region, it will be difficult to determine the packet to which it belongs, and may even cause data errors, which will require complicated error code correction processing.

[0040] Continue reading Figure 1In the lower part, if the width of the threshold voltage distribution can be appropriately reduced, the threshold voltages of each step can be clearly distinguished to reduce the probability of erroneous data.

[0041] The present invention adopts the method of appropriately introducing the QPW operation under the ISPP operation, so as to shrink the trailing edge of the threshold voltage distribution packet, thereby at least reducing the overlapping area with the next packet.

[0042] Before estimating the mode of QPW operation, the present invention first conducts detailed research and verification on the changes of some operation parameters corresponding to ISPP operation and QPW operation, and then determines the conditions of QPW operation.

[0043] Figure 2 FIG. 1 is a schematic diagram of a change curve of a threshold voltage (Vt) of a memory cell relative to a gate voltage (Vg) according to an embodiment of the present invention. Figure 2 , the threshold voltage of the memory cell of the memory cell array is actually measured. A gate voltage (Vg) is applied to the gate of the memory transistor. The gate voltage (Vg) varies from 10V to 20V, for example. The waveform of the gate voltage (Vg) is a pulse, and the pulse time width is, for example, 1 microsecond, 2 microseconds, and 3 microseconds. Under the ISPP operation, the threshold voltage can be measured as the gate voltage (Vg) changes.

[0044] Figure 3 According to an embodiment of the present invention, Figure 2 The data is converted into effective current density (J pgm ) relative to the effective gate voltage (Vg eff ) is a graph showing the change curve of the inverse of Figure 3 ,according to Figure 2 The data can be converted into the current density (J) by the following formula (1) and formula (2): pgm ) relative to the effective gate voltage (Vg eff ) changes, which is used to verify that the relationship is linear, and its slope is β. This ensures Figure 2 The gate voltage (Vg) can be used to obtain the current density.

[0045] Vg eff =Vg-V BL -Vt=Vg * -Vt (1)

[0046] J pgm =C pp ×ΔVt / t pgm (2)

[0047] Where V BL is the bit line voltage, C pp is the capacitance constant, tpgm is the pulse width.

[0048] go through Figure 3 Verification, during the ISPP operation, if the bit line voltage (V BL ), the current density is predictable in ISPP operation. ISPP operation is to gradually increase the gate voltage (Vg) pulse height in a step-by-step manner. At this time, if the bit line voltage (V BL ) is 0V, this operation is the general ISPP operation. QPW operation means that during the ISPP operation, the bit line voltage (V BL ), which will increase the voltage on the channel, resulting in a weakening of the write electric field strength, slowing down the programming speed, which is expected to reduce the width of the threshold voltage distribution.

[0049] According to the relationship between equation (1) and equation (2), the ISPP operation is further coordinated with the bit line voltage (V BL ) to predict the behavior of the threshold voltage. Equations (3) to (5) are obtained by adding ISPP operation and QPW operation (depending on the bit line voltage (V BL )), the voltage difference (ΔVt_i) corresponding to the programming gun number (i) under ISPP operation can be estimated.

[0050]

[0051]

[0052] ΔVt _i =J pgm_i ×t pgm / C pp (5)

[0053] Figure 4 FIG. 1 is a schematic diagram of a mechanism for performing an ISPP operation in conjunction with a QPW operation in the linear region of Vt versus Vg according to an embodiment of the present invention. Figure 4 ,Pick Figure 2 The linear region is the gate voltage (Vg) greater than 16V. In ISPP operation, the gate voltage (Vg) increases step by step. BL = 0, which means that the whole process is ISPP operation. When QPW operation is required, in this embodiment, for the target value of the programming verification voltage (PV), the voltage value for starting the QPW operation is selected, which is called the pre-programming verification voltage (V pre-PV ), which is the programming verification voltage relative to the target (V PV ) has a voltage difference (ΔPV). The voltage difference (ΔPV) is defined as:

[0054] ΔPV=V PV -V pre-PV (6)

[0055] After the gate voltage programming pulse reaches the pre-programming verification voltage (pre-PV), the bit line voltage (V BL Once a non-zero bit line voltage (V BL ), it enters the QPW operation mode, and its threshold voltage (Vt) will be affected by the bit line voltage (V BL ) deflects, that is, its slope decreases. When the gate voltage (Vg) reaches the programming verification voltage (PV), the slope (S) of the threshold voltage (Vt) relative to the gate voltage (Vg) QPW ) will also change with the bit line voltage (V BL ) value. Figure 4 The bit line voltage (V BL ) Taking 0V, 0.4V, 0.8V and 1.2V as examples, the effect of QPW operation can be observed.

[0056] Figure 5 According to an embodiment of the present invention, according to the change of a voltage difference (ΔPV) from a pre-programming verification voltage to a programming verification voltage, according to Figure 2 The slope of the curve at the programming verification voltage is shown in Figure 2. Figure 5 According to the above slope (S QPW ) in QPW operation, for each bit line voltage (V BL ), the slope (S QPW )The change curve of the relative voltage difference (ΔPV). Figure 5 For example, V BL =0.2V, and the step voltage of the gate voltage corresponding to ISPP is 0.4V. Similarly, other conditions such as different bit line voltages (V BL ) also has a corresponding slope curve. The voltage difference (ΔPV) at the lowest point of the slope is the voltage value corresponding to the QPW operation. Since the programming verification voltage (PV) is a fixed value, the voltage difference (ΔPV) corresponds to the pre-programming verification voltage (pre-PV). The pre-programming verification voltage (pre-PV) is the reference value for determining the QPW operation. QPW ) and the step voltage, which can be multiplied to estimate the shrinkage quantity of the threshold voltage distribution width. Figure 5 The behavior is the result simulated by the model of the present invention, which is convenient for rapid analysis by the system. However, the present invention also needs to confirm the correctness of the above model through experimental data.

[0057] Figure 6 According to an embodiment of the present invention, the accumulation rate of a memory cell is actually measured according to the change of a voltage difference (ΔPV) from a pre-programming verification voltage to a programming verification voltage. Figure 6 , according to the bit line voltage (V BL ) and step voltage (V ISPP ) is applied, and the threshold voltage Vt of multiple memory cells is measured and statistically analyzed, where for example V BL =0.2V and V ISPP =0.4V, and the voltage difference (ΔPV) is a change of multiple values. The square point is V BL =0V, that is, the case without QPW operation, which is used as a reference value. When QPW operation is applied, the threshold voltage Vt shrinks, and the measured shrinkage can be estimated by 10.

[0058] Figure 7 The diagram is a comparison diagram of simulation data and measurement data for the reduction in the width of the threshold voltage packet distribution according to a change in a voltage difference (ΔPV) from a pre-programming verification voltage to a programming verification voltage according to an embodiment of the present invention. Figure 7 ,according to Figure 5 The reduction in the width of the threshold voltage envelope distribution estimated by simulation is represented by dots. Figure 6 The width reduction of the threshold voltage envelope distribution estimated by measurement is represented by square points. The simulation and measurement results can be considered consistent to a certain extent. In this way, the simulation model of the present invention can reasonably reflect the width reduction of the threshold voltage envelope distribution.

[0059] Figure 8 Schematic diagram of a reduction map and a programming gun number map according to an embodiment of the present invention. Figure 8 , based on Figure 5 According to a plurality of bit line voltages (V BL ) and multiple voltage differences (ΔPV) varying in a range, for example, from 0.1V to 0.4V, to estimate the bit line voltage (V BL ) and the voltage difference (ΔPV) to obtain a reduction amount topographic map 100. The reduction amount is the height of the topographic map, such as grayscale. From the reduction amount topographic map 100, the desired area 102 and the other areas 104 can be distinguished and selected according to the height of the reduction amount.

[0060] In addition, similarly, according to a plurality of bit line voltages (V BL ) and multiple voltage difference maps (ΔPV) to estimate the step programming pulse (ISPP) operation to reach the programming verification voltage (V PV) The number of programming guns required is counted as height to obtain a programming gun number topographic map 110. The accepted area 112 and the outside area 114 are also determined based on the consideration of the operation time cost.

[0061] It can be noted here that since the model of the present invention has been confirmed to be correct, Figure 8 The data can be simulated in large quantities based on the model to facilitate estimation, which does not require actual measurement, or only requires simple measurement confirmation.

[0062] Fig. 9 FIG. 1 is a schematic diagram of an operation area of ​​a quick pass write (QPW) operation determined by overlapping a reduction amount map and a programming gun number map according to an embodiment of the present invention. Fig. 9 ,Will Figure 8 The reduction map 100 is superimposed on the programming gun number map 110. The overlapping area of ​​the area 102 and the area 112 can determine the bit line voltage (V BL ) and the voltage difference (ΔPV) constitute the operating region. The operating region may vary depending on the different types of memory cell structures, but the estimated mechanism is similar.

[0063] from Fig. 9 As a result, the present invention can reduce the bit line voltage (V BL ) and the voltage difference (ΔPV) for optimization estimation, the threshold voltage distribution width can be reduced and a reasonable operation time can be maintained.

[0064] From the perspective of the hardware system, Fig.10 FIG. 1 is a schematic diagram of a system for determining a fast pass write operation according to an embodiment of the present invention. Fig.10 , a system for determining a fast pass write operation, for example, includes an analysis circuit 200 and an analysis program storage unit 204, wherein the analysis circuit 200 is configured to obtain an analysis program from the analysis program storage unit 204 to operate on the storage cells of the storage cell array 202 to perform the steps of obtaining the reduction amount topography 100 and the programming gun number topography 110 as described above.

[0065] Specifically, the system for determining a fast pass write operation is configured to perform a plurality of steps including estimating the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference according to a plurality of the bit line voltages varying in a first range and a plurality of the voltage difference values ​​varying in a second range, thereby obtaining a reduction amount topographic map. According to a plurality of the bit line voltages and a plurality of the voltage difference values, estimating the number of programming guns required for applying the step programming pulse operation to reach the programming verification voltage, thereby obtaining a programming gun number topographic map. After superimposing the reduction amount topographic map and the programming gun number topographic map, an operation region formed by the application range of the bit line voltage and the application range of the voltage difference is determined.

[0066] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for determining a fast-through write operation in a step programming pulse operation, wherein the step programming pulse operation is first applied to a plurality of memory cells of a memory cell array, wherein the fast-through write operation is started after a gate voltage reaches a pre-programming verification voltage that is smaller than a programming verification voltage, wherein there is a voltage difference from the pre-programming verification voltage to the programming verification voltage, wherein the fast-through write operation is simultaneously applying a bit line voltage in the step programming pulse operation, wherein the method for determining the fast-through write operation comprises: According to the plurality of bit line voltages varying within the first range and the plurality of voltage differences varying within the second range, the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference is estimated to obtain a reduction amount topographic map; According to the plurality of bit line voltages and the plurality of voltage differences, the number of programming guns required to apply the step programming pulse operation to reach the programming verification voltage is estimated to obtain a programming gun number topography; and After the reduction amount map and the programming gun number map are superimposed, an operation region consisting of the application range of the bit line voltage and the application range of the voltage difference is determined.

2. The method for determining a fast-through write operation according to claim 1, wherein the reduction amount of the threshold voltage distribution width is estimated for each of the bit line voltages under a step voltage, comprising: Under the corresponding bit line voltage and the step voltage, estimate the change curve of the threshold voltage relative to the gate voltage for different voltage differences; According to the variation curve, estimating the slope of the programming verification voltage at the voltage difference; and The reduction amount relative to the bit line voltage being 0V is estimated according to the slope and the step voltage, The bit line voltage is a plurality of separate analysis values ​​ranging from 0V to a predetermined value. 3 . The method for determining a fast-through write operation according to claim 1 , wherein the operation region comprises a triangle, and a base of the triangle is a range of the bit line voltage.

4. The method for determining a fast pass write operation according to claim 1, wherein the reduction amount topography determines a first selected area according to the height of the bit line voltage, and the programming gun number topography determines a second selected area according to the height of the programming gun number, and at least a portion of the overlapping area between the first selected area and the second selected area is set as an operating area.

5. The method for determining a fast pass write operation according to claim 2, wherein the estimation of the reduction amount of the threshold voltage distribution width comprises comparing a model with experimental data based on the bit line voltage, the voltage difference and the step voltage of a predetermined sample to determine the correctness of the model.

6. A system for determining a fast-through write operation in a step programming pulse operation, wherein the step programming pulse operation is first applied to a plurality of memory cells of a memory cell array, wherein the fast-through write operation is initiated after a gate voltage reaches a pre-programming verification voltage that is smaller than a programming verification voltage, wherein there is a voltage difference from the pre-programming verification voltage to the programming verification voltage, wherein the fast-through write operation is performed by simultaneously applying a bit line voltage in the step programming pulse operation, The system for determining a fast-pass write operation includes an analysis circuit and an analysis program storage unit, wherein the analysis circuit is configured to obtain an analysis program from the analysis program storage unit to operate the storage cell array to perform the following steps: According to the plurality of bit line voltages varying within the first range and the plurality of voltage differences varying within the second range, the reduction amount of the threshold voltage distribution width obtained under the bit line voltage and the voltage difference is estimated to obtain a reduction amount topographic map; According to the plurality of bit line voltages and the plurality of voltage differences, the number of programming guns required to apply the step programming pulse operation to reach the programming verification voltage is estimated to obtain a programming gun number topography; and After the reduction amount map and the programming gun number map are superimposed, an operation region consisting of an application range of the bit line voltage and an application range of the voltage difference is determined.

7. The system for determining a fast-through write operation according to claim 6, wherein the reduction amount of the threshold voltage distribution width is estimated for each of the bit line voltages at a step voltage, comprising: Under the corresponding bit line voltage and the step voltage, estimate the change curve of the threshold voltage relative to the gate voltage for different voltage differences; According to the variation curve, estimating the slope of the programming verification voltage at the voltage difference; and The reduction amount relative to the bit line voltage being 0V is estimated according to the slope and the step voltage, The bit line voltage is a plurality of separate analysis values ​​ranging from 0V to a predetermined value. 8 . The system for determining a fast-through write operation according to claim 6 , wherein the operation region comprises a triangle, a base of the triangle being the range of the bit line voltage.

9. A system for determining a fast pass write operation according to claim 6, wherein the reduction amount topography determines a first selected area according to the height of the bit line voltage, and the programming gun number topography determines a second selected area according to the height of the programming gun number, and at least a portion of the overlapping area between the first selected area and the second selected area is set as an operating area.

10. The system for determining a fast-through write operation according to claim 7, wherein the estimation of the reduction amount of the threshold voltage distribution width comprises comparing a model with experimental data based on the bit line voltage, the voltage difference and the step voltage of a predetermined sample to determine the correctness of the model.

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