A method, device, equipment and storage medium for obtaining the number of RTL output stages

Abstract

The present application provides a method, apparatus, device, and storage medium for obtaining the number of RTL output stages. The method includes: generating a syntax constraint tree based on the output signals of the RTL text; simplifying the syntax constraint tree into a data flow tree according to a preset conversion rule; parallelizing the nodes in the data flow tree and updating the bit widths of the nodes; and analyzing the data flow tree after parallelization processing to obtain the number of output stages. The technical solution of the embodiments of the present application can accurately obtain the logic stages of the corresponding logic circuit through the analysis of the RTL text, which is convenient for optimizing the logic circuit, reducing the logic resources, and reducing the system power consumption in the process of logic circuit design.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and particularly to a method, device, equipment, and storage medium for obtaining the RTL output stage number. Background Art

[0002] The hardware description language register level (RTL) circuit is converted into a logic circuit by a synthesis tool. The synthesis process mainly includes translation and optimization. The translation process converts the RTL description into corresponding internal logic resources, and then optimizes it to meet the timing constraints while reducing the area and power consumption. Therefore, the RTL-level description is the basis for optimizing logic circuits and electronics design automation (EDA) tools.

[0003] Existing analysis tools generally optimize the logic circuit according to the timing constraint requirements based on the current RTL-level description. However, the optimization cannot cover all cases of resource waste, and there are differences in the optimization results of the logic circuit each time, resulting in the final output netlist being unable to truly reflect the logic circuit stage number of the RTL-level description, which is not conducive to the development of logic circuits. Summary of the Invention

[0004] This application provides a method, device, equipment, and storage medium for obtaining the RTL output stage number.

[0005] An embodiment of this application provides a method for obtaining the RTL output stage number, including:

[0006] Generating a syntax constraint tree according to the RTL text; simplifying the syntax constraint tree into a data flow tree according to a preset conversion rule; parallelizing the nodes in the data flow tree and updating the bit width of the nodes; analyzing the data flow tree after parallelization to obtain the output stage number.

[0007] An embodiment of this application provides an apparatus for obtaining the RTL output stage number, including:

[0008] A text analysis module for generating a syntax constraint tree according to the RTL text; a data flow module for simplifying the syntax constraint tree into a data flow tree according to a preset conversion rule; a parallel processing module for parallelizing the nodes in the data flow tree and updating the bit width of the nodes; a stage number determination module for analyzing the data flow tree to obtain the output stage number.

[0009] An embodiment of this application provides a device, which includes:

[0010] One or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the RTL output stage number acquisition method as described in any one of the embodiments of the present application.

[0011] The embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and characterized in that when the program is executed by a processor, it implements the RTL output stage number acquisition method as described in any one of the embodiments of the present application.

[0012] More descriptions about the above embodiments and other aspects of the present application and their implementation manners are provided in the drawings description, the specific implementation manner and the claims. Description of the Drawings

[0013] Figure 1a It is a flowchart of the steps of an RTL output stage number acquisition method provided in Embodiment 1 of the present application;

[0014] Figure 1b It is an example diagram of the output signal and the input signal of an RTL text provided in Embodiment 1 of the present application;

[0015] Figure 1c It is a schematic diagram of a syntax constraint tree provided in Embodiment 1 of the present application;

[0016] Figure 1d It is a schematic diagram of a data flow tree provided in Embodiment 1 of the present application;

[0017] Figure 2 It is a flowchart of the steps of an RTL output stage number acquisition method provided in Embodiment 2 of the present application;

[0018] Figure 3 It is a schematic structural diagram of an RTL output stage number acquisition device provided in Embodiment 3 of the present application;

[0019] Figure 4 It is a schematic structural diagram of a device provided in Embodiment 4 of the present application. Detailed Description of the Embodiment

[0020] To make the purpose, technical solution and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily.

[0021] The RTL logic level in the embodiments of the present application can be the minimum number of logic gates that an electrical signal needs to pass through between two flip - flops in a logic circuit. The RTL logic level is related to the signal delay of the logic circuit. By analyzing the RTL logic level, the signal delay of the corresponding logic circuit can be obtained, and then an optimization scheme can be provided. Removing redundant registers in the logic circuit can save logic resources and reduce system power consumption.

[0022] Embodiment 1

[0023] Figure 1a FIG. is a flowchart of the steps of a method for obtaining the RTL output level provided in Embodiment 1 of the present application. This embodiment is applicable to the situation of analyzing the RTL logic level. This method can be executed by a device for obtaining the RTL output level, and this device can be integrated in an intelligent device, and this device can be implemented in a hardware and / or software manner. Refer to Figure 1a , the method of the embodiments of the present application includes:

[0024] Step 101: Generate a syntax constraint tree according to the output signal of the RTL text.

[0025] Among them, the RTL text can be a circuit design program text data storing a register transfer level circuit, which can be used for digital circuit operations in an integrated circuit. The RTL text can include input information, output information numbers, and the operation relationship between input signals and output signals. Taking the RTL text as C = A + B as an example, Figure 1b FIG. is an example diagram of the output signal and input signal of an RTL text provided in Embodiment 1 of the present application. Refer to Figure 1b , A and B can be input signals 10, and C can be output signal 11; the syntax constraint tree can be an abstract representation form of the RTL text, which can show the syntax structure of the RTL text. The output signal in the RTL text can correspond to the syntax constraint tree, and each output signal can correspond to its own syntax constraint tree. Exemplarily, Figure 1c FIG. is a schematic diagram of a syntax constraint tree provided in Embodiment 1 of the present application. Taking the content of an output signal in the RTL text as 1+(2+(3 + 4))+5 as an example, the syntax constraint tree generated according to the RTL text can be as Figure 1c shown. The output signal in the RTL text can be the signal output from the register, which can represent the data generated after the operation in the RTL text.

[0026] Specifically, the RTL text can be processed to generate a syntax constraint tree. The output signals in the RTL text can be obtained. For each output signal, a syntax constraint tree can be generated. The input signal corresponding to the output signal can be used as the child node of the corresponding syntax constraint tree. Exemplarily, the process of generating the syntax constraint tree can include performing lexical analysis on the RTL text to obtain words, generating an abstract syntax tree according to the words and the generation syntax of the RTL text, traversing the abstract syntax tree to obtain the operator symbols in the nodes. For each output signal, the corresponding input signal can be obtained, and the syntax constraint tree can be constructed by the input signal according to the syntax rules for generating the output signal.

[0027] Step 102: Simplify the syntax constraint tree into a data flow tree according to a preset conversion rule.

[0028] Among them, the preset conversion rule can be a rule for forwarding the syntax constraint tree into a data flow tree. The preset conversion rule can be specifically converted according to the syntax in the RTL text. Different syntaxes can correspond to different conversion rules. The conversion targets corresponding to different syntaxes can be the same, that is, the description structures of different syntaxes of the data flow tree are the same. Exemplarily, when the syntax of a certain line of text in the RTL text is the execution syntax of addition, subtraction, multiplication, and division, all the nodes corresponding to this line of text in the syntax constraint tree can be converted into an object for description. The data flow tree can be a simplified syntax constraint tree. The nodes of the data flow tree can include all the information of the node, such as the bit width and the node value, etc. The data flow tree can be a syntax constraint tree with the same description structure. In the data flow tree, the description structures of the data flow trees corresponding to different syntax texts can be the same.

[0029] Specifically, the syntaxes appearing in the syntax constraint tree can be simplified. According to different syntaxes, the corresponding conversion rules can be determined, and the syntax constraint tree with the same syntax can be converted into a data flow tree according to the conversion rule. Exemplarily, Figure 1d is a schematic diagram of a data flow tree provided in Embodiment 1 of this application. Refer to Figure 1d , the syntax constraint tree of A + B can be converted into a data flow tree according to the conversion rule corresponding to the addition rule. The node values 11 of the child nodes of the syntax constraint tree can be obtained as A and B respectively. The node attribute 13 of the child node can also be obtained. The bit width of the node value can be 15 bits. The node value 11 and the node attribute 13 can be used as the child nodes of the data flow tree. The child nodes of the data flow tree can carry node attribute information, and the data flow tree can directly display the attribute information of the node.

[0030] Step 103: Parallelize the nodes in the data flow tree and update the bit width of the nodes.

[0031] Among them, parallel processing can process the nodes in the data flow tree, making the signal processing in the data flow tree conform to the processing rules of the hardware logic circuit. It can change the display of the levels with continuous identical operations in the data flow tree to the same-level display. Exemplarily, the operation symbol in the data flow tree with the syntax of consecutive addition syntax can be obtained. When the operation symbol is located at the child node, the child nodes of the operation symbol can be used to replace the operation symbol, and the child nodes in the data flow tree can be continuously traversed and replaced. After all the operation symbols that are child nodes in all the data flow trees are replaced, it can be considered that the parallel processing of the data flow tree is completed.

[0032] Specifically, since the syntax structure of the data flow tree is a traditional text syntax structure, which is different from the syntax structure of the hardware logic circuit and cannot intuitively reflect the parallel characteristics of the hardware logic circuit, the data flow tree can be parallelized so that the data flow tree for continuous operation operations such as consecutive multiplication, consecutive addition, consecutive division, and consecutive subtraction conforms to the syntax structure of the hardware logic circuit. The data flow tree can specifically be a binary tree. When a consecutive addition operation is represented using a binary tree, the depth of the data flow tree can be greater than one. For the child nodes of the root node, one of the child nodes is a black box, and the specific node value and node attributes cannot be known. The root node in the data flow tree of the hardware logic circuit cannot be directly calculated and needs to continue traversing downward to determine whether it is a consecutive addition. The parallel processing process of the data flow tree can be that when traversing the child nodes of the current node, it is judged whether the operation symbol of the child node is the same as that of the current node. If they are the same, the child nodes of this child node are used to replace this child node, and so on to complete the parallel processing of the data flow tree; the bit widths of the nodes in the data flow tree after parallel processing can also be updated. Since when there is multiplication, the bit widths of the child nodes will change. For example, when a node value A with a bit width of 3 is multiplied by a node value B with a bit width of 4, the bit width of the operation result can be 3 + 4 = 7. To prevent overflow errors caused by insufficient bit widths of the nodes, the bit widths of the child nodes of the data flow tree can be updated to expand the child nodes of each data flow tree. The way to update the node bit widths can include expanding using a fixed threshold bit width, or starting from the node at the third position from the rightmost side of the data flow tree, using the sum of the bit widths of two nodes as the bit width of this node.

[0033] Step 104: Analyze the data flow tree after parallel processing to obtain the output level.

[0034] Among them, the output level can be the logic level of the RTL text determined according to the data flow tree, which can reflect the signal delay of the hardware logic circuit corresponding to the RTL text.

[0035] In an embodiment of the present invention, the operation syntax of RTL text may be related to the logical levels of the hardware logic circuit. By analyzing the syntax rules and the number of child nodes as signal inputs in the data flow tree, the logical levels of the hardware logic circuit can be obtained as the output levels. For example, different operation syntaxes correspond to different logical level calculation formulas. The logical levels can be determined according to the logical formulas corresponding to different syntaxes through the child nodes of the data flow tree. The sum of the logical levels of each data flow tree can be used as the output level corresponding to the RTL text.

[0036] The technical solution of the embodiment of the present application generates a syntax constraint tree according to the RTL text, simplifies the syntax constraint tree into a data flow tree according to the preset conversion rules, parallelizes the processing of the internal nodes of the data flow tree and updates the bit widths of the nodes, and analyzes the data flow tree to obtain the output level of the RTL text. By accurately analyzing the RTL text to obtain the logical levels of the corresponding hardware logic circuit, it is convenient to optimize the hardware logic circuit, save logical resources and reduce system power consumption.

[0037] Embodiment 2

[0038] Figure 2 It is a step flowchart of a method for obtaining the RTL output level provided in Embodiment 2 of the present application. The embodiment of the present application is a specific implementation based on the above embodiment. Refer to Figure 2 The step flowchart of the method for obtaining the RTL output level provided in the embodiment of the present application includes:

[0039] Step 201: Parse the RTL text to obtain at least one of description tags, operators, keywords, and line number information as lexical information.

[0040] Among them, the description tag can be the text used for description in the RTL text, specifically a string composed of English letters, numbers, and underscores, used to describe the content of the RTL text. The operator can be the symbol used for operation in the RTL text, which can include plus, minus, multiplication, and division signs, etc. The keyword can be the predefined processing rules in the RTL text, and the keywords can include ABS, ACCESS, NOR, IF, and FOR, etc. The line number can be the statement line number mark in the RTL text, and the lexical information can be a set of word information appearing in the RTL text. The lexical information can specifically be one or more of description tags, operators, keywords, and line number information.

[0041] Specifically, lexical analysis can be performed on the RTL text to obtain words such as description tokens, operators, keywords, or line number information. The obtained number of occurrences can be used as the lexical information of the RTL text. It can be understood that the method of performing lexical analysis on the RTL text can be to input the RTL text into the lex lexical analysis tool to extract the lexical feature information of the RTL text, and the extracted feature information can be used as the lexical information. It can be understood that before obtaining the lexical information of the RTL text, preprocessing can be performed on the RTL text, and the iVerilog tool can be used to replace the header files and macro definitions in the RTL text.

[0042] Step 202: Arrange the lexical information in the order of their appearance to generate an abstract syntax tree.

[0043] Among them, the order of appearance can be the order in which each word in the lexical information appears in the RTL text. For example, if the RTL text is C = A + B, then the order of appearance of the words A, B, and C is 2, 3, and 1. The abstract syntax tree can specifically be a binary tree, and the nodes in the abstract syntax tree can be the words in the lexical information.

[0044] In the embodiments of the present invention, an abstract syntax tree can be constructed according to the syntax rules of the RTL text based on the order of appearance of the lexical information. The words that appear in the lexical information can be used as the root nodes of the abstract syntax tree, and the words of the subsequent lexical information can be used as the child nodes of the root nodes. The lexical information can be filled into the nodes of the binary tree in the order of appearance to generate an abstract syntax tree. All the lexical information of the RTL text can construct one abstract syntax tree, or multiple abstract syntax trees can also be constructed.

[0045] Step 203: Extract the symbol information in the abstract syntax tree and store the symbol information in a symbol table.

[0046] Among them, the symbol signal can be the operation symbols that appear in the RTL text, and the symbol table can be a data file that stores all the operation symbols in the RTL text.

[0047] Specifically, the nodes of the abstract syntax tree can be traversed to determine whether the information stored in the node is symbol information. If the information stored in the node is symbol information, the symbol information can be stored in the symbol table.

[0048] Step 204: Construct a syntax constraint tree according to the symbol table.

[0049] In an embodiment of the present invention, each symbol in the symbol table can correspond to an output signal in the hardware logic circuit. The output signal can be obtained according to the symbol information in the symbol table. For each output signal, the input signal related to the output signal can be used as a node of the syntax constraint tree, and different syntax constraint trees can be constructed for different output signals.

[0050] Step 205: When the syntax rule of the syntax constraint tree is a branch syntax rule, parse the syntax constraint tree to obtain node attributes, store the node attributes into a preset branch syntax tree according to the corresponding branches, and use the preset branch syntax tree as a data flow tree.

[0051] Among them, the branch syntax rule can be a syntax that generates branches, which can include IF syntax rules and SWITCH syntax rules, etc. The node attributes can be the attributes included in each node of the syntax constraint tree, which can include node values and bit widths, etc.

[0052] Specifically, the structure of the syntax constraint tree can be judged. If the syntax rule corresponding to the syntax constraint tree is a branch syntax rule, each node of the syntax constraint tree can be parsed to obtain the node value and bit width as node attributes. According to the branch to which the node belongs in the branch syntax, for example, if the node belongs to the success condition branch, the corresponding node attributes are stored in the success branch of the branch syntax tree; if the node belongs to the failure condition branch, the corresponding node attributes are stored in the failure branch of the branch syntax tree; if the node belongs to the conditional branch, the corresponding node attributes are stored in the conditional branch of the branch syntax tree. It can be understood that the preset branch syntax tree can include a failure branch, a success branch, and a conditional branch, and the branch syntax tree storing the node attributes can be used as a data flow tree.

[0053] Further, on the basis of the above application embodiment, a preset branch syntax tree includes: a conditional branch node, a first branch node, and a second branch node, and the branch symbol node is respectively connected to the first branch node and the second branch node.

[0054] In an embodiment of the present invention, the preset branch syntax tree can be divided into three storage areas according to the rules of the branch syntax. One storage area can be a conditional branch node for storing branch conditions; one storage area can be a first branch node for storing success branch information; and another storage area can be a second branch node for storing failure branch information.

[0055] Step 206: When the syntax rule of the syntax constraint tree is not a branch syntax rule, obtain the node attributes of the syntax constraint tree, and add the node attributes to the corresponding nodes as a data flow tree.

[0056] Specifically, the grammar rules in the grammar constraint tree that are not branch grammar rules may include grammar rules such as constants, endpoints, and operators. Since the structure of the grammar rules in the grammar constraint tree, such as constants, endpoints, and operators, is similar to the storage structure of the data flow tree, when the grammar rules of the grammar constraint tree are not branch grammar rules, the node attributes such as bit widths can be obtained by traversing the nodes of the grammar constraint tree, and the node attributes such as bit widths can be stored together with the node values. The grammar constraint tree storing the node attributes can be used as the data flow tree.

[0057] Step 207: Traverse the data flow tree. If the operation symbol of the current node is the same as that of the child node of the current node, then replace the current node with the child node of the current node.

[0058] Specifically, when there is a node in the data flow tree whose symbol is the same as that of its child node, it can indicate that there is a continuous operation in the data flow tree and parallelization processing is required. The process of parallelizing the data flow tree may include traversing the nodes in the data flow tree, obtaining the nodes whose operation symbols of the current node and its child node are the same, replacing the node with its child node, and recursively traversing the data flow tree in sequence to replace the nodes whose symbols of the nodes in the data flow tree are the same as those of their child nodes as the process of parallelizing the data flow tree.

[0059] Step 208: If the node in the data flow tree is a multiplication symbol, then replace the bit width of the node with the sum of the bit widths of the child nodes of the node.

[0060] In the embodiments of the present invention, when multiplication appears in the RTL text, there may be a situation where the bit width of the node is insufficient. For example, the bit width of A is 4. If A = B * C, since the bit widths of B and C are also 4, the bit width of B * C can be 8 = 4 + 4. After the multiplication operation, the bit width of A is not sufficient to accommodate B * C. Therefore, the bit width of A needs to be expanded. If the node of the data flow tree is a multiplication symbol, the sum of the bit widths of the child nodes of the node can be used as the bit width of the node to implement the update of the bit width of the nodes in the data flow tree.

[0061] Step 209: Obtain the leaf nodes of the data flow tree.

[0062] Among them, the leaf node can be a node in the data flow tree that has no child nodes. When the node is a leaf node, the information stored on the node can be the input signal in the hardware logic circuit.

[0063] Specifically, each data flow tree can be traversed, including depth-first traversal and breadth-first traversal, to obtain each leaf node in the data flow tree, and the logical levels of the RTL text can be obtained through the leaf nodes serving as output signals.

[0064] Step 210: Determine the logical levels from the leaf nodes to the root node of the data flow tree according to the operation rules corresponding to the leaf nodes.

[0065] Among them, the operation rules can be related to the structure of the data flow tree. The corresponding operation rules are obtained through the data flow tree. For example, if the data flow tree includes an addition symbol and the data flow tree only includes two child nodes, it can be determined that the operation rule corresponding to the data flow tree is the addition operation rule.

[0066] Specifically, for each data flow tree, the path lengths from each leaf node to the root node can be determined in the data flow tree. It can be determined that the path length from the leaf node to the root node can be the logical levels of the input signal to the output signal in the corresponding hardware logic circuit. The number of nodes passed by the leaf node to reach the root node can be the same as the number of logic gates of the input signal to the output signal in the corresponding hardware logic circuit. The logical levels of the hardware logic circuit can be determined through the path length from the leaf node to the root node.

[0067] Step 211: Use the sum of the logical levels corresponding to each leaf node as the output level.

[0068] In the embodiment of the present invention, the logical levels can correspond to the leaf nodes. The sum of the logical levels corresponding to all leaf nodes in the data flow tree can be determined, and the sum can be used as the output level of the RTL text or the output level of the hardware logic circuit corresponding to the RTL text. The output level can be obtained without obtaining the logic circuit through the analysis of the RTL text.

[0069] Further, on the basis of the above application embodiment, constructing a syntax constraint tree according to the symbol table includes: obtaining each output signal in the abstract syntax tree according to the symbol table; for each output signal, constructing an abstract syntax constraint tree for the corresponding input signal.

[0070] Among them, the output signal can be the output signal in the hardware logic circuit and can correspond to the non-leaf node in the abstract syntax tree. It can be understood that an output signal can be both an output signal and an input signal.

[0071] In the embodiment of the present application, non-symbol nodes in the syntax constraint tree can be determined through a symbol table, and it can be judged whether the node has child nodes. If the node has child nodes, the node can be used as an output signal. The corresponding child nodes can be obtained according to the output signal, and all child nodes of the output signal can be used as input signals of a logic circuit. An abstract syntax constraint tree can be constructed from the input signals and the corresponding operation symbols. It can be understood that the input signals can be direct or indirect child nodes of the node of the output signal. For example, if B is a child node of A, C is a child node of B, and D is a child node of C, when A is the output signal, B, C, and D can be input signals of A.

[0072] In the technical solution of the embodiment of the present application, lexical information is obtained by parsing RTL text, the lexical information is arranged according to the order of their appearance to generate an abstract syntax tree, all symbol information in the abstract syntax tree is obtained and stored as a symbol table, a syntax constraint tree is constructed according to the symbol table, the syntax constraint tree is processed with node attributes added to be a data flow tree, the data flow tree is processed in parallel and the node bit widths are updated, the corresponding logic levels are determined according to the path length from the leaf node to the root node of the data flow tree, and the sum of the logic levels of the leaf nodes is used as the output level, realizing the acquisition of the output level of the RTL text. The present application does not need to implement a hardware logic circuit, and obtains the logic level through the RTL text, which is convenient for optimizing the performance of the logic circuit, removing redundant registers in the logic circuit, saving logic resources, and reducing the system power consumption in the logic circuit design process.

[0073] Further, after obtaining the output level, the output level can be compared with a preset level threshold. If the output level is less than the set level threshold, the design system of the logic circuit can give a warning message to remind the logic developer that there is room for optimization in the RTL text, and a certain register in the hardware logic circuit can be removed for optimization. An automatic optimization module can also be added to analyze the output levels of the pre-stage register signal and the post-stage register signal of two register signals according to the data flow tree to determine whether it can be optimized. If it is still less than the threshold after merging, it can be optimized and an optimization suggestion is output.

[0074] Embodiment III

[0075] Figure 3 FIG. 13 is a schematic structural diagram of an RTL output level acquisition device provided in Embodiment III of the present application, which can execute the RTL output level acquisition method provided in any embodiment of the present application, and has corresponding functional modules and beneficial effects for executing the method. The device can be implemented by software and / or hardware, and specifically includes: a text analysis module 301, a data flow module 302, a parallel processing module 303, and a level determination module 304.

[0076] Among them, the text analysis module 301 is used to generate a syntax constraint tree according to the RTL text.

[0077] The data flow module 302 is used to simplify the syntax constraint tree into a data flow tree according to a preset conversion rule.

[0078] The parallel processing module 303 is used to parallelize the nodes in the data flow tree and update the bit width of the nodes.

[0079] The stage number determination module 304 is used to analyze the data flow tree after parallel processing to obtain the output stage number.

[0080] In the technical solution of the embodiment of the present application, the text analysis module 301 generates a syntax constraint tree according to the RTL text, the data flow module 302 simplifies the syntax constraint tree into a data flow tree according to a preset conversion rule, the parallel processing module 303 parallelizes the nodes in the data flow tree and updates the bit width of the nodes, and the stage number determination module 304 analyzes the data flow tree to obtain the output stage number of the RTL text. By accurately analyzing the RTL text to obtain the logic stage number of the corresponding hardware logic circuit, it is convenient to optimize the hardware logic circuit, save logic resources and reduce system power consumption.

[0081] Further, on the basis of the above application embodiment, the text analysis module 301 includes:

[0082] The lexical analysis unit is used to parse the RTL text to obtain at least one of description tags, operators, keywords, and line number information as lexical information.

[0083] The syntax analysis unit is used to arrange the lexical information in the order of appearance to generate an abstract syntax tree.

[0084] The symbol table unit is used to extract symbol information from the abstract syntax tree and store the symbol information in the symbol table.

[0085] The tree construction unit is used to construct a syntax constraint tree according to the symbol table.

[0086] Further, on the basis of the above application embodiment, the tree construction unit includes:

[0087] The output signal sub-unit is used to obtain each output signal in the abstract syntax tree according to the symbol table.

[0088] The construction execution unit is used to construct an abstract syntax constraint tree for the corresponding input signal for each of the output signals.

[0089] Further, on the basis of the above application embodiment, the data flow module 302 includes:

[0090] A branch processing unit, configured to parse the syntax constraint tree to obtain node attributes when the syntax rule of the syntax constraint tree is a branch syntax rule, store the node attributes into a preset branch syntax tree according to the corresponding branches, and use the preset branch syntax tree as a data flow tree.

[0091] A non-branch processing unit, configured to obtain the node attributes of the syntax constraint tree when the syntax rule of the syntax constraint tree is not a branch syntax rule, and add the node attributes to the corresponding nodes as a data flow tree.

[0092] Further, based on the above application embodiment, the preset branch syntax tree in the branch processing unit includes: a conditional branch node, a first branch node, and a second branch node, and the branch symbol node is respectively connected to the first branch node and the second branch node.

[0093] Further, based on the above application embodiment, the parallel processing module 303 includes:

[0094] A parallel processing unit, configured to traverse the data flow tree, and if the operation symbol of the current node is the same as that of the child node of the current node, replace the current node with the child node of the current node.

[0095] A bit width update unit, configured to use the sum of the bit widths of the child nodes of the node to replace the bit width of the node if the node in the data flow tree is a multiplication symbol.

[0096] Further, based on the above application embodiment, the stage determination module 304 includes:

[0097] A node acquisition unit, configured to acquire the leaf nodes of the data flow tree.

[0098] A logic stage unit, configured to determine the logic stage from the leaf node to the root node of the data flow tree according to the operation rule corresponding to the leaf node.

[0099] A stage determination unit, configured to use the sum of the logic stages corresponding to each leaf node as the output stage.

[0100] Embodiment 4

[0101] Figure 4 The structural schematic diagram of a device provided by Embodiment 4 of this application is shown as Figure 4 shown. The device includes a processor 40, a memory 41, an input device 42, and an output device 43; the number of processors 40 in the device can be one or more, Figure 4 taking one processor 40 as an example; the processor 40, the memory 41, the input device 42, and the output device 43 in the device can be connected through a bus or other means, Figure 4Take the bus connection as an example.

[0102] The memory 41, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program modules corresponding to the RTL output stage number acquisition method in the embodiments of the present invention (for example, the text analysis module 301, the data flow module 302, the parallel processing module 303, and the stage number determination module 304 in the RTL output stage number acquisition device). The processor 40 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 41, that is, implements the above-mentioned RTL output stage number acquisition method.

[0103] The memory 41 mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory 41 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some instances, the memory 41 may further include a memory remotely set relative to the processor 40, and these remote memories can be connected to the device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and their combinations.

[0104] The input device 42 can be used to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the device. The output device 43 may include display devices such as a display screen.

[0105] It should be noted that Figure 4 The structure shown is only schematic and does not limit the structure of the above device. For example, the device may further include more or fewer components than those shown Figure 4 in the figure, or have a different configuration from that shown Figure 4 in the figure.

[0106] Embodiment Five

[0107] Embodiment Five of the present invention further provides a storage medium containing computer-executable instructions, and the computer-executable instructions are used to execute an RTL output stage number acquisition method when executed by a computer processor. The method includes:

[0108] Generating a syntax constraint tree according to the output signal of the RTL text;

[0109] Simplifying the syntax constraint tree into a data flow tree according to a preset conversion rule;

[0110] Parallelizing the nodes in the data flow tree and updating the bit widths of the nodes;

[0111] Analyze the data stream tree after parallel processing to obtain the output series.

[0112] Certainly, for a storage medium containing computer-executable instructions provided in the embodiments of the present application, the computer-executable instructions are not limited to the method operations described above, and can also execute the related operations in the RTL output series acquisition method provided in any embodiment of the present invention.

[0113] From the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as a floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk, or optical disc of a computer, and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0114] It should be noted that in the embodiments of the above RTL output series acquisition device, the included units and modules are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be realized; in addition, the specific names of the functional units are only for the convenience of mutual distinction and do not limit the protection scope of the present application.

[0115] The above is only an exemplary embodiment of the present application and is not used to limit the protection scope of the present application.

[0116] Those skilled in the art should understand that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable network browser, or a vehicle-mounted mobile station.

[0117] Generally speaking, various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, a microprocessor, or other computing devices, although the present application is not limited thereto.

[0118] Embodiments of the present application can be implemented by a data processor of a mobile device executing computer program instructions, for example, in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages.

[0119] Any block diagram of a logical process in the accompanying drawings of the present application can represent program steps, or can represent interconnected logical circuits, modules, and functions, or can represent a combination of program steps and logical circuits, modules, and functions. The computer program can be stored in a memory. The memory can have any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical memory devices and systems (digital versatile disc DVD or CD optical disc), etc. The computer-readable medium can include non-transitory storage media. The data processor can be any type suitable for the local technical environment, such as but not limited to a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (FPGA), and a processor based on a multi-core processor architecture.

[0120] By way of illustrative and non-limiting examples, a detailed description of exemplary embodiments of the present application has been provided above. However, considering the accompanying drawings and the claims, various modifications and adjustments to the above embodiments will be obvious to those skilled in the art without departing from the scope of the present invention. Therefore, the proper scope of the present invention will be determined according to the claims.

Claims

1. A method for obtaining RTL output series, characterized in that: include: Generate a grammar constraint tree based on the output signal of the RTL text; Simplifying the grammatical constraint tree into a data flow tree according to preset conversion rules; Parallel processing of nodes in the data stream tree and updating the bit width of the nodes; Analyzing the data flow tree after parallel processing to obtain output levels; The parallel processing of the nodes in the data stream tree and updating the bit width of the nodes includes: Traversing the data flow tree, if the operation symbol of the current node is the same as that of the child node of the current node, replacing the current node with the child node of the current node; If a node in the data stream tree is a multiplication symbol, the bit width of the node is replaced by the sum of the bit widths of the child nodes of the node.

2. The method according to claim 1, characterized in that Generating a grammar constraint tree according to the RTL text includes: Parsing the RTL text to obtain at least one of a description tag, an operator, a keyword, and a line number as lexical information; Arranging the lexical information according to the order of appearance of the lexical information to generate an abstract syntax tree; Extracting symbol information from the abstract syntax tree and storing the symbol information in a symbol table; A grammar constraint tree is constructed according to the symbol table.

3. The method according to claim 2, characterized in that The step of constructing a grammar constraint tree according to the symbol table includes: Acquire each output signal in the abstract syntax tree according to the symbol table; For each of the output signals, an abstract syntax constraint tree is constructed for the corresponding input signal.

4. The method according to claim 1, wherein The step of simplifying the grammatical constraint tree into a data flow tree according to a preset conversion rule includes: When the grammatical rule of the grammatical constraint tree is a branch grammatical rule, parsing the grammatical constraint tree to obtain node attributes, storing the node attributes into a preset branch grammatical tree according to the corresponding branches, and using the preset branch grammatical tree as a data flow tree; When the grammatical rule of the grammatical constraint tree is not a branching grammatical rule, a node attribute of the grammatical constraint tree is obtained, and the node attribute is added to a corresponding node as a data flow tree.

5. The method according to claim 4, characterized in that The preset branch syntax tree includes: a conditional branch node, a first branch node, and a second branch node, and a branch symbol node is connected to the first branch node and the second branch node respectively.

6. The method according to claim 1, characterized in that The analyzing the parallelized data stream tree to obtain the output level includes: Obtaining a leaf node of the data stream tree; Determine the logical level from the leaf node to the root node of the data flow tree according to the operation rule corresponding to the leaf node; The sum of the logical levels corresponding to the leaf nodes is used as the output level.

7. An RTL output level acquisition device, characterized in that: include: Text analysis module, used to generate a grammar constraint tree based on RTL text; A data flow module, configured to simplify the grammatical constraint tree into a data flow tree according to preset conversion rules; A parallel processing module, used for parallel processing of nodes in the data stream tree and updating the bit width of the nodes; A series number determination module, configured to analyze the data flow tree after parallel processing to obtain an output series number; Wherein, the parallel processing module includes: a parallel processing unit, configured to traverse the data stream tree, and if an operation symbol of a current node is the same as that of a child node of the current node, replace the current node with the child node of the current node; The bit width updating unit is configured to replace the bit width of the node with the sum of the bit widths of the child nodes of the node if the node in the data stream tree is a multiplication symbol.

8. A device, characterized in that The device comprises: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the RTL output level acquisition method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method for obtaining the RTL output level as claimed in any one of claims 1 to 6 is implemented.

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