Pixel unit, image sensor and electronic device

Abstract

A pixel unit, an image sensor and an electronic device, wherein the pixel unit comprises: a photodiode, a transfer transistor, a floating diffusion point, a reset transistor, a conversion gain control transistor and a gain control capacitor; wherein the floating diffusion point is arranged close to the transfer transistor and connected to the transfer transistor; the conversion gain control transistor is connected between the floating diffusion point and the reset transistor; the first electrode of the gain control capacitor comprises a connecting portion and an extension portion, the connecting portion is a connecting point between the reset transistor and the conversion gain control transistor, and the extension portion protrudes from the connecting point to between two photodiodes adjacent in the column direction; the connecting portion and the extension portion are combined to form a gain control capacitor, thereby achieving a lower low gain value, so as to improve the gain ratio of the image sensor and the working performance in high-light scenes.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a pixel unit with a high gain ratio, an image sensor and an electronic device. Background Art

[0002] Image sensors are semiconductor devices that convert light signals into electrical signals. Existing image sensors include charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors. Compared with traditional CCD sensors, CMOS image sensors have the characteristics of low power consumption and low cost, and therefore are increasingly widely used.

[0003] Conventional CMOS image sensors use transfer transistors to transfer electrons generated by photosensitive elements such as photodiodes to floating diffusion nodes and output them through source follower amplifier transistors. Depending on the actual application, some sensors will design dual conversion gain modes to use different gains in different application environments. For example, in low-light scenes, the pixel circuit of the image sensor works in high conversion gain mode with higher sensitivity; in high-light scenes, the pixel circuit of the image sensor works in low conversion gain mode with relatively low sensitivity, but can read more signals.

[0004] However, due to the limitation of process level, small-sized image sensors cannot further reduce the low gain part for application in high-light environment. The parasitic capacitance value of the floating diffusion node affects the upper limit of the dynamic range, and the charge generated by the heat of the photodiode and other noise factors affect the lower limit of the pixel dynamic range. The dynamic range is the ratio of the maximum detectable illumination intensity to the minimum detectable illumination intensity of the pixel circuit. If the dynamic range of the scene to be imaged exceeds the dynamic range of the pixel circuit, it will cause the pixel circuit of the image sensor to saturate, which may affect the correct capture of the light signal in scenes with a large dynamic range, such as outdoor scenes.

[0005] Therefore, in order to improve the working performance of the image sensor in high-light scenes, it is necessary to reduce the low gain value of the pixel circuit. Figure 1 The schematic diagram of the layout structure of a pixel unit of an image sensor in the prior art is shown, wherein the reset transistor RST and the conversion gain control transistor DCG are arranged in the same direction between two adjacent columns of photodiodes PD, and the source follower transistor SF and the row selection transistor RS are arranged in the same direction between two adjacent rows of photodiodes PD. The parasitic capacitance value of the floating diffusion node of this layout structure is small, and the low gain value of the image sensor cannot be reduced. Summary of the invention

[0006] The purpose of the present invention is to provide a pixel unit, an image sensor and an electronic device to solve the problem that the low gain value in the existing image sensor is too high, resulting in a small dynamic range, and to improve the gain ratio of the image sensor and the working performance in high-light scenes.

[0007] The present invention provides a pixel unit, which comprises:

[0008] A photodiode and a transfer transistor connected to the photodiode, wherein the transfer transistor is tilted at an angle to a corner of the photodiode;

[0009] a floating diffusion point, the floating diffusion point being disposed adjacent to the transfer transistor and connected to the transfer transistor;

[0010] a reset transistor and a conversion gain control transistor, the conversion gain control transistor being connected between the floating diffusion and the reset transistor;

[0011] A gain control capacitor, wherein the first electrode of the gain control capacitor includes a connecting portion and an extending portion, wherein the connecting portion is a connecting point between the reset transistor and the conversion gain control transistor, and the extending portion protrudes from the connecting point to between two photodiodes adjacent in a column direction.

[0012] Optionally, the photodiode is provided with notches at the upper right, lower right and upper left of the connecting portion, so that the connecting portion of the gain control capacitor is formed into a polygon.

[0013] Optionally, the connecting portion protrudes upward to be connected to the reset transistor, and the connecting portion protrudes rightward to be connected to an extended portion of the gain control capacitor.

[0014] Optionally, the gate of the conversion gain control transistor is arranged in an irregular shape, the source thereof is connected to a floating diffusion point, and the drain thereof is connected to the gain control capacitor and the reset transistor.

[0015] Optionally, the floating diffusion point is tilted along a first tilt direction between the photodiode and the first pole, and the conversion gain control transistor is tilted along a second tilt direction between the floating diffusion point and the first pole, and the first tilt direction and the second tilt direction intersect.

[0016] Optionally, the length of the first electrode along the row direction is greater than 50% of the length of the pixel unit along the row direction.

[0017] Optionally, a width of the extended portion along the column direction is greater than 40% of a distance between two adjacent photodiodes along the column direction.

[0018] Optionally, an isolation structure is provided between the expansion portion and the photodiodes located on both sides thereof in the column direction, and the isolation structure is isolated by ion implantation or STI isolation.

[0019] Optionally, the reset transistor is located between two photodiodes adjacent to each other in the row direction in the previous row of pixel units.

[0020] Optionally, the image sensor further includes a source follower transistor and a row selection transistor; the source follower transistor is connected between the floating diffusion point and the row selection transistor, and the source follower transistor and the row selection transistor are located between two photodiodes adjacent to each other in the row direction in the pixel unit of the row.

[0021] Optionally, the reset transistor, the conversion gain control transistor, the source follower transistor and the row selection transistor are sequentially arranged between two adjacent columns of photodiodes on the left and right.

[0022] Optionally, the conversion gain control transistor is tilted at an angle, and the reset transistor, the source follower transistor and the row selection transistor are arranged in the same direction.

[0023] Optionally, the distance from the leftmost end of the connecting portion to the rightmost end of the extending portion connected thereto is the length of the first pole, and the length of the first pole is 3 to 3.65 μm.

[0024] Optionally, the width of the extended portion along the column direction is 0.4-0.5 μm.

[0025] Optionally, the extended portion is 0.1-0.25 μm away from the photodiodes on both sides thereof in the column direction.

[0026] Optionally, the second electrode of the gain control capacitor is formed of polysilicon, and the second electrode is arranged between two photodiodes adjacent to each other in the column direction.

[0027] Optionally, the second electrode of the gain control capacitor is connected to the gate of the conversion gain control transistor through a gain control signal line.

[0028] Optionally, a plurality of second contacts are arranged between the gain control signal line and the second electrode, and the plurality of second contacts are arranged at intervals in the row direction.

[0029] The present invention also provides an image sensor, which includes a plurality of pixel units of any one of the above types arranged in row and column directions.

[0030] The present invention also provides an electronic device, which comprises the above-mentioned image sensor.

[0031] The present invention provides a pixel unit, an image sensor and an electronic device, wherein the pixel unit adopts a connection portion and an extension portion protruding between two photodiodes adjacent to each other in a column direction to form a gain control capacitor, and the gain control capacitor is increased by the layout design of other components, thereby achieving a lower gain value to increase the gain ratio of the image sensor and improve the working performance of the image sensor in a high-light scene. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The schematic diagram is a layout structure diagram of a pixel unit of an image sensor in the prior art.

[0033] Figure 2 FIG. 1 is a circuit diagram of a pixel unit in an image sensor according to a first embodiment of the present invention.

[0034] Figure 3 FIG. 1 is a schematic diagram of the layout structure of a pixel unit in an image sensor according to the first embodiment of the present invention.

[0035] Figure 4 for Figure 3 A partial enlarged view of the layout structure of the pixel unit shown.

[0036] Figure 5 FIG. 1 is a timing diagram of a pixel unit circuit in an image sensor according to the first embodiment of the present invention.

[0037] Figure 6 FIG. 4 is a schematic diagram of the layout structure of a pixel unit in an image sensor according to a second embodiment of the present invention.

[0038] Figure 7 It is a schematic diagram of the layout structure of metal wiring arranged in a pixel unit of an image sensor according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0039] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0040] The term "connection" used in the present invention is defined as follows: "connection" is used to describe a direct connection or an indirect connection between two circuit elements. For example, two connection elements can be directly connected through a metal wire, or indirectly connected through an intermediate circuit element (e.g., a capacitor, a resistor, or a source or drain of a transistor).

[0041] The directions or positional relationships indicated by the terms "up", "down", "left", "right", "row direction", "column direction", etc. used in the present invention are based on the directions or positional relationships shown in the accompanying drawings and are only for the clarity of expressing the technical solution and the convenience of description. Therefore, they should not be understood as limitations on the present invention.

[0042] First embodiment

[0043] The first embodiment of the present invention provides a pixel unit and an image sensor, wherein the image sensor includes a pixel array composed of a plurality of pixel units arranged in a row direction X and a column direction Y. Figure 4 , Figure 2 Schematic diagram of the circuit of the pixel unit in this embodiment is shown. Figure 3 Schematic diagram of the layout structure of the pixel unit is shown. Figure 4 Shows Figure 3 A partial enlarged view of the A area in the middle. Each pixel unit includes: a photodiode PD, a transfer transistor TX connected to the photodiode PD, a floating diffusion point FD, a reset transistor RST, a conversion gain control transistor DCG, a gain control capacitor C, a source follower transistor SF, and a row selection transistor RS. The transfer transistor TX, the reset transistor RST, the conversion gain control transistor DCG, the source follower transistor SF, and the row selection transistor RS are all active elements. The following provides an example in which these active elements are all composed of MOS transistors with N-type carrier polarity, but is not limited to this.

[0044] The anode of the photodiode PD is grounded, and the photodiode PD converts incident light into electric charges of an amount corresponding to the amount of incident light.

[0045] The transfer transistor TX is tilted at an angle at the corner of the photodiode PD, the transfer transistor TX is connected between the floating diffusion point FD and the photodiode PD, and the source of the transfer transistor TX is connected to the cathode of the photodiode PD. The floating diffusion point FD is arranged close to the transfer transistor TX and connected to the drain of the transfer transistor TX. The gate of the transfer transistor TX is connected to the transmission signal line and responds to the transmission signal Vtx, and transfers the charge accumulated in the photodiode PD to the floating diffusion point FD after the integration process of the photodiode PD is completed.

[0046] The conversion gain control transistor DCG is connected between the reset transistor RST and the floating diffusion point FD, the drain of the conversion gain control transistor DCG is connected to the floating diffusion point FD, the source of the conversion gain control transistor DCG is connected to the reset transistor RST, and the gate of the conversion gain control transistor DCG is connected and responds to the gain control signal Vdcg. The gain control capacitor C is connected to the connection point between the conversion gain control transistor DCG and the reset transistor RST, that is, the first node Q1. The conversion gain control transistor DCG and the gain control capacitor C are used to realize the conversion of the pixel circuit between high and low gain, thereby improving the dynamic range of the image sensor.

[0047] The reset transistor RST is connected between the first voltage source VDD and the conversion gain control transistor DCG, the drain of the reset transistor RST is connected to the source of the conversion gain control transistor DCG, the source of the reset transistor RST is connected to the first voltage source VDD, and the gate of the reset transistor RST is connected and responds to the reset signal Vrst to reset the circuit within the pixel unit.

[0048] The source follower transistor SF is connected between the first voltage source VDD and the row selection transistor RS, the drain of the source follower transistor SF is connected to the row selection transistor RS, the source of the source follower transistor SF is connected to the first voltage source VDD, the gate of the source follower transistor SF is connected to the floating diffusion point FD and responds to the charge on the floating diffusion point FD. The source follower transistor SF is used to amplify the signal of the potential of the floating diffusion point FD and output the amplified signal to the row selection transistor RS.

[0049] The row selection transistor RS is connected between the source follower transistor SF and the vertical signal line Lout, the source of the row selection transistor RS is connected to the drain of the source follower transistor SF, the drain of the row selection transistor RS is connected to the vertical signal line line_out, the gate of the row selection transistor RS is connected to the row selection line and responds to the row selection signal Vrs. When the row selection line is a high-level signal, the gate of the row selection transistor RS is turned on due to the high-level signal input through the row selection line, and the pixel signal PIXOUT amplified by the follower transistor SF is output to the vertical signal line line_out.

[0050] Please refer to Figure 5 , taking the above active elements as N-type MOS transistors as an example, a timing diagram of the pixel unit circuit in this embodiment is shown. It should be noted that one or more active elements use P-type MOS transistors and change the signal level accordingly, which is still within the protection scope of the present invention.

[0051] During the operation, the reset stage T1 is first performed, and the gate voltage of the reset transistor RST and the gate voltage of the conversion gain control transistor DCG are both set to a high level. At this time, the reset transistor RST and the conversion gain control transistor DCG are both turned on, and the photodiode PD and the floating diffusion point FD are reset through the first voltage source VDD.

[0052] When exposure is performed, the photodiode PD responds to the incident light and generates charges.

[0053] Entering the low conversion gain reference voltage output stage T2, the gate voltage of the reset transistor RST is set to a low level, the reset transistor RST is turned off, the gate voltage of the conversion gain control transistor DCG is set to a high level, the conversion gain control transistor DCG is turned on, the capacitance value between the floating diffusion point FD and the first voltage source VDD increases due to the gain control capacitor C, the gate voltage of the row selection transistor RS is set to a high level, the row selection transistor RS is turned on, and the pixel circuit outputs the reference voltage VL0 when the conversion gain is low.

[0054] Entering the high conversion gain reference voltage output stage T3, the gate voltage of the reset transistor RST is set to a low level, the reset transistor RST is turned off, the gate voltage of the conversion gain control transistor DCG is set to a low level, the conversion gain control transistor DCG is turned off, the gate voltage of the row selection transistor RS is set to a high level, the row selection transistor RS is turned on, and the pixel circuit outputs the reference voltage VH0 when the conversion gain is high.

[0055] The integration process of the photodiode PD ends and enters the high conversion gain signal voltage VH1 output stage T4. The gate voltage of the conversion gain control transistor DCG is set to a low level, the conversion gain control transistor DCG is turned off, the gate voltage of the transmission transistor TX is set to a high level, the transmission transistor TX is turned on, the gate voltage of the row selection transistor RS is set to a high level, the row selection transistor RS is turned on, and the transmission transistor TX transfers the charge generated by the photodiode PD to the floating diffusion point FD, and outputs the high conversion gain signal voltage VH1 through the row selection transistor RS.

[0056] The gate voltage of the conversion gain control transistor DCG is set to a high level, the conversion gain control transistor DCG is turned on, the gate voltage of the row selection transistor RS is set to a low level, and the row selection transistor RS is turned off; then the signal voltage VL1 output stage T5 for low conversion gain is entered, the gate voltage of the row selection transistor RS is set to a high level, the row selection transistor RS is turned on, and since the capacitance value between the floating diffusion point FD and the first voltage source VDD increases due to the gain control capacitor C, the gate voltage of the source follower transistor SF decreases, and thus the output voltage of the source follower transistor SF decreases accordingly, and a lower low gain is obtained, and the row selection transistor RS is turned on and outputs the signal voltage VL1 for low conversion gain.

[0057] Therefore, the capacitance value of the gain control capacitor C affects the reference voltage VL0 at low conversion gain and the signal voltage VL1 at low conversion gain, thereby affecting the low gain value. The ratio of the high gain value to the low gain value determines the gain ratio. The higher the gain ratio, the larger the dynamic range of the image sensor. In the layout structure of the existing image sensor, the capacitance value at the floating diffusion point FD is limited by the connection point area of ​​the conversion gain control transistor DCG and the reset transistor RST, and is affected by the layout structure of the conversion gain control transistor DCG, the reset transistor RST, the source follower transistor SF, the row selection transistor RS and other components.

[0058] In this embodiment, please refer to Figure 3 and Figure 4 The first electrode 10 of the gain control capacitor C includes a connection portion 11 and an extension portion 12. The connection portion 11 is a connection point between the reset transistor RST and the conversion gain control transistor DCG, and the extension portion 12 protrudes from the connection point to between two photodiodes PD adjacent to each other in the column direction Y. The gain control capacitor C can be a device capacitor or a parasitic capacitor. The second electrode of the device capacitor can be grounded or connected to a fixed voltage source according to the application, such as the first voltage source VDD.

[0059] The floating diffusion point FD is tilted along a first tilt direction A1 between the photodiode PD and the gain control capacitor C, the conversion gain control transistor DCG is tilted along a second tilt direction A2 between the floating diffusion point FD and the gain control capacitor C, the gate of the conversion gain control transistor DCG is arranged in an irregular shape, the source thereof is connected to the floating diffusion point FD, and the drain thereof is connected to the gain control capacitor C and the reset transistor RST. The first tilt direction A1 and the second tilt direction A2 intersect. Preferably, the floating diffusion point FD is arranged between the photodiode PD and the first pole 10 at an tilt angle of 45°, the conversion gain control transistor DCG is arranged between the floating diffusion point FD and the first pole 10 at an tilt angle of 45°, and the floating diffusion point FD and the conversion gain control transistor DCG are arranged orthogonally.

[0060] For the layout structure of a certain pixel unit, the reset transistor RST is located between two photodiodes PD adjacent to each other in the row direction X in the pixel unit of the previous row, the source follower transistor SF is connected between the floating diffusion point FD and the row selection transistor RS, and the source follower transistor SF and the row selection transistor RS are located between two photodiodes PD adjacent to each other in the row direction X in the pixel unit of the current row.

[0061] In the layout structure of this embodiment, the reset transistor RST, the conversion gain control transistor DCG, the source follower transistor SF and the row selection transistor RS are sequentially arranged between two adjacent columns of photodiodes PD, wherein the conversion gain control transistor DCG is arranged at an angle, and the reset transistor RST, the source follower transistor SF and the row selection transistor RS are arranged in the same direction. The layout space between the two adjacent rows of photodiodes PD is reserved, so that the size of the gain control capacitor C can be increased.

[0062] For further information, see Figure 2 and Figure 4 , four pixel units arranged in a matrix form a pixel unit group, the connection portion 11 of the gain control capacitor C is located at the center of the pixel unit group, the gain control capacitor C corresponds to the photodiode PD located at the lower left of its connection portion 11, and is connected to the upper right corner of the photodiode PD. The photodiode PD is provided with notches at the upper right, lower right and upper left of the connection portion 11, so that the connection portion 11 of the gain control capacitor C is formed into a polygon, the connection portion 11 protrudes upward and / or downward to be connected to the reset transistor RST, and the connection portion 11 protrudes to the left and / or right to be connected to the extension portion 12 of the gain control capacitor C. In this embodiment, the connecting portion 11 protrudes upward to connect to the reset transistor RST, and the connecting portion 11 protrudes to the right to connect to the extended portion 12 of the gain control capacitor C. The conversion gain control transistor DCG is arranged at an angle at the center position of the pixel unit group, and one end is arranged close to the photodiode PD located in the upper left corner of the pixel unit group, and the other end is arranged close to the photodiode located in the lower right corner of the pixel unit group, which fully utilizes the center position space of the pixel array and the pixel unit gap space, which is beneficial to reducing the pixel size and improving the fill factor.

[0063] Since the layout structure of the active element leaves a layout space between two rows of photodiodes PD adjacent to each other, preferably, the length of the first electrode 10 of the gain control capacitor C along the row direction X is greater than 50% of the length of the pixel unit along the row direction X, and the width of the extension portion 12 along the column direction Y is greater than 40% of the spacing between two photodiodes PD adjacent to each other in the column direction Y. Specifically, the distance from the leftmost end of the connection portion 11 to the rightmost end of the extension portion 12 connected thereto is the length L1 of the first electrode 10 of the gain control capacitor C, the length L2 of the pixel unit along the row direction X is, for example, 3.8-4.5 μm, and the length L1 of the first electrode 10 is, for example, 3-3.65 μm; the width L3 of the extension portion 12 along the column direction Y is, for example, 0.4-0.5 μm, the spacing L4 between two photodiodes PD adjacent to each other in the column direction Y is, for example, 0.7-0.9 μm, the extension portion 12 is 0.1-0.25 μm away from the photodiodes PD on both sides of the extension portion 12 in the column direction Y, and the width of the connection portion 11 along the column direction Y is slightly larger than the extension portion 12. In one embodiment, the length L1 of the first electrode 10 is 3.57 μm; the width L3 of the extension portion 12 along the column direction Y is 0.45 μm, and an isolation structure 13 is provided between the extension portion 12 and the photodiodes PD on both sides thereof in the column direction Y and between other active areas. The isolation structure 13 is isolated by ion implantation or STI isolation.

[0064] This embodiment further provides an electronic device, which includes any one of the image sensors provided in this embodiment. The electronic device is, for example, a digital camera, a video camera, a computer, a portable terminal device, a copier, etc.

[0065] This embodiment combines a connecting portion 11 and an extension portion 12 protruding between two photodiodes PD adjacent to each other in the column direction Y to form a gain control capacitor C, and increases the gain control capacitor C through the layout design of other active components. The capacitance value of the gain control capacitor C is 3 to 5 times the capacitance value in the prior art, thereby achieving a lower gain value to increase the gain ratio of the image sensor and improve the working performance of the image sensor in high-light scenes.

[0066] Second embodiment

[0067] Please refer to Figure 6 The second embodiment of the present invention provides an image sensor, which is different from the first embodiment in that the second electrode 20 of the gain control capacitor C in the present embodiment is formed of polysilicon, the second electrode 20 is arranged between two photodiodes PD adjacent to each other in the column direction Y, the first electrode 10 and the second electrode 20 are arranged opposite to each other with an oxide insulating layer sandwiched therebetween. The gain control capacitor C is formed as a MOS capacitor, so that the gain control capacitor C has a larger capacitance value within the same area, further reducing the low gain value.

[0068] Please refer to Figure 7 , shows a schematic diagram of the layout structure of the metal wiring of the pixel unit in this embodiment, the second electrode 20 of the gain control capacitor C is connected to the gate of the conversion gain control transistor DCG through the gain control signal line 30, the gain control signal line 30 is located between two rows of photodiodes PD adjacent to each other in the column direction Y, extends along the row direction X and connects the second electrodes 20 of multiple gain control capacitors C and the gates of multiple conversion gain control transistors DCG.

[0069] In the reset phase T1, the gate of the reset transistor RST, the gate of the conversion gain control transistor DCG, and the second electrode 20 of the gain control capacitor C are all set to a high level, so the second electrode 20 of the gain control capacitor C and the gate of the conversion gain control transistor DCG respond to the same gain control signal Vdcg and will not affect the floating diffusion point FD from being reset to a high level. In the output phase T5 of the signal voltage VL1 at a low conversion gain, the gate of the conversion gain control transistor DCG and the second electrode 20 of the gain control capacitor C are all set to a high level, and the gain control capacitor C amplifies the capacitance value between the floating diffusion point FD and the first voltage source VDD. Therefore, in this embodiment, the second electrode 20 of the gain control capacitor C and the gate of the conversion gain control transistor DCG can respond to the same gain control signal Vdcg, and there is no need to set a separate signal line for the second electrode 20 of the gain control capacitor C, which simplifies the circuit design and circuit layout.

[0070] Furthermore, the first contact 41 between the gain control signal line 30 and the conversion gain control transistor DCG is located at the upper right corner of the conversion gain control transistor DCG. Since the gain control signal line 30 and the extension portion 12 of the gain control capacitor C extend along the row direction X, a plurality of second contacts 42 can be provided between the gain control signal line 30 and the second electrode 20 of the gain control capacitor C. The plurality of second contacts 42 are arranged at intervals in the row direction X, so that a more uniform signal is applied to the second electrode 20, further improving the charge capacity of the gain control capacitor C, so that the image sensor can achieve a lower low gain value.

[0071] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features is not contradictory, they should be considered to be within the scope of this specification.

[0072] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A pixel unit, characterized in that: include: A photodiode and a transfer transistor connected to the photodiode, wherein the transfer transistor is tilted at an angle to a corner of the photodiode; a floating diffusion point, the floating diffusion point being disposed adjacent to the transfer transistor and connected to the transfer transistor; a reset transistor and a conversion gain control transistor, the conversion gain control transistor being connected between the floating diffusion and the reset transistor; A gain control capacitor, wherein a first electrode of the gain control capacitor includes a connection portion and an extension portion, wherein the connection portion is a connection point between the reset transistor and the conversion gain control transistor, and the extension portion protrudes from the connection point to between two photodiodes adjacent to each other in a column direction; The floating diffusion point is tilted along a first tilt direction between the photodiode and the first electrode, and the conversion gain control transistor is tilted along a second tilt direction between the floating diffusion point and the first electrode, and the first tilt direction and the second tilt direction intersect; An isolation structure is disposed between the expansion portion and the photodiodes located on both sides of the expansion portion in the column direction, and the isolation structure is isolated by ion implantation or STI isolation.

2. The pixel unit according to claim 1, characterized in that: The photodiode is provided with notches at the upper right, lower right and upper left of the connecting portion, so that the connecting portion of the gain control capacitor is formed into a polygon.

3. The pixel unit according to claim 1, characterized in that: The connecting portion protrudes upward to be connected to the reset transistor, and the connecting portion protrudes rightward to be connected to the extended portion of the gain control capacitor.

4. The pixel unit according to claim 1, characterized in that: The gate of the conversion gain control transistor is arranged in an irregular shape, the source thereof is connected to a floating diffusion point, and the drain thereof is connected to the gain control capacitor and the reset transistor.

5. The pixel unit according to claim 1, characterized in that: The length of the first electrode along the row direction is greater than 50% of the length of the pixel unit along the row direction.

6. The pixel unit according to claim 1, characterized in that: The width of the extended portion along the column direction is greater than 40% of the distance between two adjacent photodiodes along the column direction.

7. The pixel unit according to claim 1, characterized in that: The reset transistor is located between two photodiodes adjacent to each other in the row direction in the pixel units of the previous row.

8. The pixel unit according to claim 1, characterized in that: The pixel unit also includes a source follower transistor and a row selection transistor; the source follower transistor is connected between the floating diffusion point and the row selection transistor, and the source follower transistor and the row selection transistor are located between two photodiodes adjacent to each other in the row direction in the pixel unit of this row.

9. The pixel unit according to claim 8, characterized in that: The reset transistor, the conversion gain control transistor, the source follower transistor and the row selection transistor are sequentially arranged between two adjacent left and right columns of photodiodes.

10. The pixel unit according to claim 9, characterized in that: The conversion gain control transistor is tilted at an angle, and the reset transistor, the source follower transistor and the row selection transistor are arranged in the same direction.

11. The pixel unit according to claim 1, characterized in that: The distance from the leftmost end of the connecting portion to the rightmost end of the extending portion connected thereto is the length of the first pole, and the length of the first pole is 3 to 3.65 μm.

12. The pixel unit according to claim 1, characterized in that: The width of the extended portion along the column direction is 0.4-0.5 μm.

13. The pixel unit according to claim 1, characterized in that: The distance between the extended portion and the photodiodes on both sides of the extended portion in the column direction is 0.1-0.25 μm respectively.

14. The pixel unit according to claim 1, characterized in that: The second electrode of the gain control capacitor is formed of polysilicon, and the second electrode is arranged between two photodiodes adjacent to each other in the column direction.

15. The pixel unit according to claim 14, characterized in that: The second electrode of the gain control capacitor is connected to the gate of the conversion gain control transistor through a gain control signal line.

16. The pixel unit according to claim 15, characterized in that: A plurality of second contacts are arranged between the gain control signal line and the second electrode, and the plurality of second contacts are arranged at intervals in the row direction.

17. An image sensor, characterized in that: The image sensor comprises a plurality of pixel units according to any one of claims 1 to 16 arranged in row and column directions.

18. An electronic device, characterized in that: Comprising the image sensor of claim 17.

Images