Display device and testing method thereof

Abstract

The present application discloses a display device and a test method thereof. The display device includes: a substrate in which a cutout portion is defined; and a first conductive layer, which is disposed on the substrate and includes a first signal line and a first test line, wherein the first test line intersects the cutout portion, and an end portion of the first test line includes an extended first pad area.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2019-0136865, filed on October 30, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Exemplary embodiments of the present invention relate to a display device and a test method thereof, and more particularly, to a retractable display device capable of expansion and contraction and a test method thereof. Background Art

[0003] The importance of display devices has increased with the development of multimedia. Accordingly, various types of display devices, such as organic light emitting display ("OLED") devices or liquid crystal display ("LCD") devices, are being used.

[0004] Recently, the demand for flexible display devices has increased. Among the flexible display devices, a retractable display device that can be expanded and contracted has a wide range of applications. The retractable display device can be utilized as a display device intended to be stretched, but can also be applied to other flexible display devices, foldable display devices, and rollable display devices for effective bending, folding, and rolling. Summary of the invention

[0005] When the display device is stretched, not only the substrate but also the wires arranged on the substrate may be subjected to stress. The stress of the substrate can be reduced by cutting off a portion of the substrate. In the case of a wire arranged on the substrate, the stress can be released by changing the constituent material or pattern, but the stress caused by stretching is concentrated in the portion of the wire passing through the cutout portion compared to other portions of the wire, and the wire may be disconnected in some cases. The disconnection of the wire causes a display defect of the display device. However, the display defect may occur due to various reasons and therefore it is difficult to find the exact cause only by confirming the display defect. In addition, the display device includes a plurality of transistors for driving a pixel circuit, and a display defect occurs when the characteristic values ​​of the corresponding transistors are uneven. However, it may be difficult to accurately identify which positions of the transistors in the display area have different characteristic values ​​using only the display defect.

[0006] Exemplary embodiments of the present invention provide a display device in which it is easy to confirm whether a conductive layer is disconnected.

[0007] Exemplary embodiments of the present invention also provide a display device in which characteristic values ​​of a transistor and a corresponding position in a display region are easily confirmed.

[0008] Exemplary embodiments of the present invention also provide a method of testing a display device, in which whether a conductive layer is disconnected can be easily identified.

[0009] It should be noted that the features and advantages of the present invention are not limited to the above-mentioned objects, and other features and advantages of the present invention will be apparent to those skilled in the art from the following description.

[0010] An exemplary embodiment of a display device includes: a substrate in which a cutout portion is defined; and a first conductive layer disposed on the substrate and including a first signal line and a first test line, wherein the first test line intersects the cutout portion, and one end portion of the first test line includes an expanded first pad area.

[0011] Another exemplary embodiment of the device includes: a substrate including a display area, the display area including a plurality of pixels; a plurality of pixel circuit transistors and a test transistor arranged on the substrate; and a pixel electrode connected to at least some of the plurality of pixel circuit transistors and provided to each of the plurality of pixels, wherein the test transistor is arranged in the display area, the test transistor has a layered structure that is the same as the layered structure of the pixel circuit transistor, and further includes a contact electrode of a material containing the pixel electrode, and the contact electrode includes a gate contact electrode connected to a gate electrode of the test transistor, a first source / drain contact electrode connected to a first source / drain electrode of the test transistor, and a second source / drain contact electrode connected to a second source / drain electrode of the test transistor.

[0012] An exemplary embodiment of a method for testing a display device includes: forming a first conductive layer including a first signal line and a first test line on a substrate, defining a cutout portion in the substrate so that the first test line intersects the cutout portion and includes an end portion including an extended first pad area; and measuring a resistance of the first test line.

[0013] In an exemplary embodiment, it is possible to easily confirm whether the conductive layer is disconnected. Further, it is possible to easily confirm the characteristic value of the transistor and the corresponding position in the display area.

[0014] The effects in the exemplary embodiments of the present invention are not limited to the above-exemplified contents, and more various effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other exemplary embodiments and features of the present invention will become more apparent by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 is a perspective view of an exemplary embodiment of a display device;

[0017] Figure 2 is a diagram showing a horizontal stretch Figure 1 A perspective view showing a state of the display device;

[0018] Figure 3 It shows that the local stretch Figure 1 A perspective view showing a state of the display device;

[0019] Figure 4 is a schematic diagram showing an exemplary embodiment of an arrangement of islands of a substrate in a partial region of a display device;

[0020] Figure 5 yes Figure 4 Schematic diagram of array repeating units in an island pattern;

[0021] Figure 6 is a circuit diagram of an exemplary embodiment of one pixel of a display device;

[0022] Figure 7 is a cross-sectional view of an exemplary embodiment of a display device;

[0023] Figure 8 is a plan view of an exemplary embodiment of a source / drain conductive layer in a repeating unit of an array;

[0024] Fig. 9 It is along Figure 8 A cross-sectional view taken along line IX-IX′;

[0025] Fig.10 yes Figure 8 A plan view of a first source / drain conductive layer;

[0026] Fig.11 yes Figure 8 A plan view of a second source / drain conductive layer;

[0027] Fig.12 yes Figure 8 A plan view of a third source / drain conductive layer;

[0028] Fig.13 is a plan view of an exemplary embodiment of a source / drain conductive layer in a repeating unit of an array;

[0029] Fig.14 It is along Fig.13 A cross-sectional view taken along line XIV-XIV′;

[0030] Fig.15 is a plan view of an exemplary embodiment of a source / drain conductive layer in a repeating unit of an array;

[0031] Fig.16 yes Fig.15 A magnified image of the test transistor;

[0032] Fig.17 It is along Fig.16A cross-sectional view taken along line XVII-XVII′ of ; and

[0033] Fig.18 It is along Fig.16 A cross-sectional view taken along line XVIII-XVIII′. DETAILED DESCRIPTION

[0034] The present invention will be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0035] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0036] For ease of description, spatially relative terms, such as "below," "below," "below," "above," and "on," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or another feature (or features) as shown in the accompanying drawings. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. In an exemplary embodiment, when the device in the accompanying drawings is turned over, the elements described as being "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Therefore, the exemplary term "below" can cover both orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0037] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this article, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as the second element, second component, second region, second layer or second part.

[0038] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, the singular forms "a", "an" and "said" are intended to include plural forms, including "at least one", unless the content clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related enumerated items. It should be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification specify the presence of narrated features, regions, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or their groups.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention belongs. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted in an ideal or overly formal sense unless explicitly defined as such herein.

[0040] Exemplary embodiments are described herein with reference to schematically illustrated cross-sectional illustrations as idealized embodiments. As such, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but rather include deviations in shapes caused by, for example, manufacturing. In exemplary embodiments, regions shown or described as flat may typically have rough and / or nonlinear features. Moreover, the sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the exact shapes of the regions and are not intended to limit the scope of the claims.

[0041] Like reference numerals refer to like components throughout the specification.

[0042] Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[0043] Figure 1is a perspective view of an exemplary embodiment of a display device. Throughout the specification, the first direction D1 and the second direction D2 refer to directions intersecting each other. The third direction D3 is a direction perpendicular to the plane in which the first direction D1 and the second direction D2 are placed and indicates a thickness direction. It is shown in the drawings that the first direction D1 indicates a longitudinal direction in a plan view, and the second direction D2 indicates a horizontal direction in a plan view, but the present invention is not limited thereto.

[0044] refer to Figure 1 , the display device 10 displays a video or a still image and includes a display panel. Examples of display panels include self-luminous display panels, such as organic light-emitting display ("OLED") panels, inorganic electroluminescent ("EL") display panels, quantum dot light-emitting display ("QLED") panels, micro-luminescent display ("micro-LED") panels, nano LED panels, plasma display panels ("PDP"), field emission display ("FED") panels, and cathode ray tube ("CRT") display panels; and light-receiving display panels, such as liquid crystal display ("LCD") panels and electrophoretic display ("EPD") panels. Hereinafter, an OLED panel will be described as an exemplary embodiment of a display panel, and unless a specific distinction is desired, the OLED panel applied to the exemplary embodiment will be referred to as a display panel. However, the present invention is not limited to OLED panels, and to the extent that technical viewpoints are shared, other display panels listed above or known in the art may be applied to the display panel.

[0045] The display device may further include a touch member. The touch member may be integral with the display panel or may be provided as a panel separate from the display panel.

[0046] In addition to the display panel and the touch member, the display device 10 may further include sensors, various controllers, housings, and other components. Any device including a display area DPA that displays an image or video may be interpreted as corresponding to the display device 10, regardless of the main purpose of the device, the added functions, the name, etc. In an exemplary embodiment, the display device 10 may include, but is not limited to, a smart phone, a mobile phone, a tablet personal computer ("PC"), a personal digital assistant ("PDA"), a portable multimedia player ("PMP"), a television, a game console, a wristwatch-type electronic device, a head-mounted (e.g., mounted) display, a monitor of a PC, a notebook computer, a car navigation system, a car dashboard, a digital camera, a camcorder, an external billboard, an electronic signboard, various medical devices, various inspection devices, various household appliances including a display component (such as a refrigerator or a washing machine, etc.) and an Internet of Things ("IoT") device, etc.

[0047] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an active area, which is an area in which an image is displayed, and the non-display area NDA may be an inactive area, which is an area in which no image is displayed. The display area DPA may have a rectangular planar shape, but the present invention is not limited thereto, and the display area DPA may have various planar shapes, such as a square shape, a diamond shape, a circular shape, and an elliptical shape. The non-display area NDA may be arranged around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. A signal line (through which a signal is applied to the display area DPA or a signal detected in the display area DPA is transmitted) may be arranged in the non-display area NDA. The non-display area NDA (which is an inactive area) may correspond to the border area of ​​the display device 10. Although the non-display area NDA is shown in the drawings as being disposed around all sides of the display area DPA having a rectangular shape, the present invention is not limited thereto, and the non-display area NDA may not be disposed around some sides of the display area DPA, or may be displayed in the following manner so as to be omitted in a plan view: the non-display area NDA is bent toward the rear surface of the display area DPA and overlaps with the display area DPA in the thickness direction.

[0048] The display area DPA includes a plurality of pixels PX. The pixels PX are arranged in a matrix form. The pixels PX may include a first color pixel, a second color pixel, and a third color pixel. In an exemplary embodiment, for example, the first color pixel may be a red pixel, the second color pixel may be a green pixel, and the third color pixel may be a blue pixel. In an exemplary embodiment, the arrangement of the pixels PX may be performed in a stripe arrangement, wherein pixels of the same color are arranged along a first direction D1 (which is a column extension direction), and red pixels, green pixels, and blue pixels are arranged alternately in the order of red pixels, green pixels, and blue pixels along a second direction D2 (which is a row extension direction), but the arrangement of the pixels PX is not limited to the example shown. In an exemplary embodiment, for example, the arrangement of the pixels PX may be performed in a pentile arrangement in which each of the pixels PX is provided in a rhombus shape, and the red pixels and the blue pixels are radially arranged around the green pixels. In addition, the pixels PX may further include white pixels in addition to the red pixels, the green pixels, and the blue pixels.

[0049] The display device 10 may be a flexible device. The display device 10 may be retractable, flexible, bendable, foldable or rollable. Such flexibility of the display device 10 may be implemented by a flexible substrate. The flexible substrate may include a flexible polymer. In an exemplary embodiment, for example, the flexible polymer may include a polymer comprising at least one of polyimide, polyester (e.g., polyethylene terephthalate, polybutylene phthalate, or polyethylene naphthalate, etc.), polystyrene, polycarbonate, polyether sulfone, polyarylate, polycycloolefin, norbornene resin, poly(chlorotrifluoroethylene) and polymethyl methacrylate.

[0050] As an example of a flexible display device, Figure 2 and Figure 3 An application example of a retractable display device is shown in FIG.

[0051] Figure 2 is a diagram showing that the horizontal direction is stretched Figure 1 A perspective view showing the status of the display device.

[0052] refer to Figure 2 , the display device 10 may expand in the horizontal direction. In an exemplary embodiment, for example, when the vicinity of the two edges of the display device 10 is grasped and stretched in a direction away from the two edges, the display device 10 may expand in the stretched direction. As the display device 10 expands, the area of ​​the display device 10 in the plan view may increase. In the accompanying drawings, although the display device 10 is shown as expanding in the second direction D2, the display device 10 may expand in the first direction D1, in both the first direction D1 and the second direction D2, or in another horizontal direction. The display device 10 may expand by an external force and may shrink to return to its original state when the external force is removed.

[0053] Figure 3 It shows that the local stretch Figure 1 A perspective view showing the state of the display device. Figure 3 , the display device 10 can be partially expanded while maintaining the total plane area. That is, as shown in the drawings, when the display device 10 is pressed in the third direction D3 (which is the thickness direction), the display device 10 can be partially expanded relative to the pressing point. In this case, the direction in which the display device 10 is expanded becomes a direction inclined relative to the horizontal direction, and the total plane area of ​​the display device 10 can be maintained to be equal to the total plane area before the expansion. Once the pressure is removed, the expanded part can be retracted again to return to the original state.

[0054] Figure 2 The expansion and Figure 3In the exemplary embodiment, for example, not only the plane area is locally increased in a direction inclined relative to the horizontal direction with respect to the pressure in the thickness direction, but also the total plane area can be further increased.

[0055] As described above, when the display device 10 is stretched or shrunk, the substrate of the display device 10 and the thin film disposed thereon are stressed. In order to release such tensile stress, the substrate of the display device 10 may include a cutout portion. Figure 4 for a detailed description.

[0056] Figure 4 is a schematic diagram showing an exemplary embodiment of an arrangement of islands of a substrate in a partial region of a display device. Figure 5 yes Figure 4 Schematic representation of the patterning of island ISLs in the array repeating unit APU.

[0057] refer to Figure 4 and Figure 5 , the substrate of the display device (reference Figure 7 The "SUB" in the figure may include a plurality of islands ISL. The islands ISL are separated from each other by a cutout portion SLT. The cutout portion SLT passes through the substrate in the thickness direction. The material constituting the substrate may not be in the cutout portion SLT. The cutout portion SLT, in which the material constituting the substrate is not present, can be deformed more freely with respect to stretching than a portion filled with the material constituting the substrate. Accordingly, when the substrate is locally stretched, the substrate is easily stretched due to the cutout portion SLT, thereby reducing the strain applied to the substrate.

[0058] The cutout portion SLT may be completely empty, and may also be completely or partially filled with other thin films on the substrate. In one exemplary embodiment, all edges of each of the islands ISL may be surrounded by the cutout portion SLT. In another exemplary embodiment, adjacent islands ISL may be connected to each other by a bridge including a material constituting the substrate.

[0059] In a pattern in which a plurality of islands ISL are arranged, substantially the same basic unit (hereinafter, referred to as "array repeating unit APU") is repeatedly arranged. The array repeating unit APU may have substantially the same arrangement of islands ISL, and likewise, lines and electrodes, etc., arranged in corresponding areas may have substantially the same pattern and the same arrangement. The array repeating unit APU may have a square shape or a rectangular shape.

[0060] The array repeating units APU are continuously arranged along the longitudinal direction D1 (first direction D1) and the transverse direction D2 (second direction D2), and adjacent array repeating units APU may have a symmetrical relationship with each other relative to a line perpendicular to the direction in which adjacent array repeating units APU are adjacent to each other. In an exemplary embodiment, for example, the array repeating units APU adjacent to each other in the longitudinal direction D1 may have a line-symmetrical shape relative to a boundary intersecting with the space between them in the transverse direction D2. In addition, the array repeating units APU adjacent to each other in the transverse direction D2 may have a line-symmetrical shape relative to a boundary intersecting with the space between them in the longitudinal direction D1.

[0061] An array repeating unit APU may include a plurality of islands ISL. Figure 5 The array repeating unit APU shown in FIG. 1 may have six islands ISL1 to ISL6.

[0062] The first island ISL1 (which is the main island) has the largest area in the island ISL and is disposed at the central portion of the array repeat unit APU. The first island ISL1 is disposed in one array repeat unit APU and may be an independent island separated from an adjacent array repeat unit APU. The first island ISL1 may have a substantially "+" shape in a plan view. That is, the first island ISL1 may have a shape that protrudes upward (on one side in the first direction D1), downward (on the other side in the first direction D1), rightward (on one side in the second direction D2), and leftward (on the other side in the second direction D2) from the central area CEN in a plan view. Each protrusion is connected to the central area CEN.

[0063] The left protrusion LPT may be arranged so that the center of its gravity is offset upward from the transverse centerline TVL, and the right protrusion RPT may be arranged so that the center of its gravity is offset downward from the transverse centerline TVL. The left protrusion LPT and the right protrusion RPT may have substantially similar areas and may have a substantially point-symmetrical relationship relative to the center of the array repeating unit APU.

[0064] The lower protrusion BPT may have an area substantially similar to that of the left protrusion LPT or the right protrusion RPT.The lower protrusion BPT may be disposed such that the center of gravity thereof is offset to the left from the longitudinal center line VTL.

[0065] The upper protrusion UPT may have an area smaller than that of the lower protrusion BPT.The center of gravity of the upper protrusion UPT may be substantially located on the longitudinal centerline VTL.

[0066] The second island ISL2 (which is a sub-island) may be disposed on one side (right side in the drawing) of the upper protrusion UPT. The second island ISL2 may have a rectangular shape elongated in the longitudinal direction D1. In an exemplary embodiment, at least one corner of the second island ISL2 may be inclined relative to an adjacent side connected to the corner. The second island ISL2 may be an independent island separated from an adjacent array repeating unit APU. The combined area of ​​the second island ISL2 and the upper protrusion UPT may be substantially similar to the area of ​​the lower protrusion BPT.

[0067] The third to sixth islands ISL3 to ISL6 are arranged at the corners of the array repeating unit APU. The third to sixth islands ISL3 to ISL6 may be connected islands arranged on adjacent array repeating units APU. The connected islands may each have a line-symmetric shape relative to the boundaries between the array repeating units APU.

[0068] The third island ISL3 is disposed at the upper left corner of the array repeating unit APU, and has a substantially quadrilateral shape elongated in the lateral direction D2. The third island ISL3 may be connected to the third island ISL3 of the adjacent array repeating unit APU on the left.

[0069] The fourth island ISL4 is disposed at the upper right corner of the array repeating unit APU, and has a substantially quadrilateral shape elongated in the longitudinal direction D1. The fourth island ISL4 may be connected to the fourth island ISL4 of the array repeating unit APU adjacent on the upper side.

[0070] The fifth island ISL5 is disposed at the lower right corner of the array repeating unit APU, and has a substantially quadrilateral shape elongated in the lateral direction D2. The fifth island ISL5 may be connected to the fifth island ISL5 of the right adjacent array repeating unit APU.

[0071] The sixth island ISL6 is disposed at the lower left corner of the array repeating unit APU, and has a substantially quadrilateral shape elongated in the longitudinal direction D1. The sixth island ISL6 may be connected to the sixth island ISL6 of the array repeating unit APU adjacent on the lower side.

[0072] One or more pixels PX may be arranged in the array repeat unit APU. In an exemplary embodiment, for example, a basic pixel group representing full color may be arranged in the array repeat unit APU. As shown in the accompanying drawings, three pixels PX1, PX2 and PX3 of red, green and blue (which are basic units representing full color) may be arranged in one array repeat unit APU. As another example, four pixels of red, green, blue and white may also be arranged in one array repeat unit APU. As yet another example, in one array repeat unit APU, two pixels of red and green may be arranged, two pixels of blue and green may be arranged, or four pixels of red, green, blue and green may be arranged. In addition, two or more basic pixel groups representing full color may be arranged in one array repeat unit APU, and various other modifications may be made thereto.

[0073] Each pixel PX in the array repetition unit APU includes a pixel electrode. The pixel electrode of the first pixel PX1, the pixel electrode of the second pixel PX2, and the pixel electrode of the third pixel PX3 may be connected to different driving transistors to receive separate voltages.

[0074] Each pixel electrode may be disposed in an island ISL of the substrate. Each pixel electrode may not be disposed in the cutout portion SLT of the substrate. In an exemplary embodiment, the pixel electrodes of the first pixel PX1, the second pixel PX2, and the third pixel PX3 disposed in one array repeat unit APU may all be disposed in the same island ISL. In an exemplary embodiment, for example, each pixel electrode may be disposed in the first island ISL1 (which is a main island disposed in the central portion of the array repeat unit APU).

[0075] In order to drive each pixel electrode of the pixel PX, a pixel circuit including multiple lines and multiple transistors is desired. For this purpose, multiple lines, multiple electrodes, multiple insulating layers, multiple semiconductor layers, etc. may be provided on the substrate. Unlike the pixel electrode, a portion of the line may intersect with the cutout portion SLT and the upper portion of the island ISL.

[0076] Hereinafter, a pixel circuit of one pixel of each display device will be described.

[0077] Figure 6 is a circuit diagram of an exemplary embodiment of one pixel of a display device.

[0078] The circuit of one pixel of the organic light emitting display device includes an organic light emitting diode OLED, a plurality of transistors T1 to T7, and a storage capacitor Cst. A data signal DATA, a first scan signal GW, a second scan signal GI, a light emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT are applied to the circuit of one pixel. The data signal DATA can be applied to the circuit of one pixel through a data line DL (reference Figure 7 ) is provided, and the first scan signal GW and the second scan signal GI can be respectively provided through the first scan line SL1 (reference Figure 7 ) and the second scanning line SL2 (reference Figure 7 ) is provided, and the light emission control signal EM can be provided through the light emission signal control line EML (reference Figure 7 Similarly, the first power supply voltage ELVDD, the second power supply voltage ELVSS and the initialization voltage VINT can be respectively provided through the first power supply voltage line ELVDDL (reference Figure 7 ), the second power supply voltage line ELVSSL (reference Figure 7 ) and the initialization voltage line VINTL (reference Figure 7 )supply.

[0079] The organic light emitting diode OLED includes: a pixel electrode PXL (reference Figure 7 ) anode, including the common electrode CME (reference Figure 7 ) cathode and an organic layer OML inserted between them (reference Figure 7 ).

[0080] The storage capacitor Cst includes a first electrode CE1 (reference Figure 7 ) and the second electrode CE2 (reference Figure 7 ).

[0081] The plurality of transistors may include first to seventh transistors T1 to T7. Each of the transistors includes a gate electrode, a first source / drain electrode, and a second source / drain electrode. One of the first source / drain electrode and the second source / drain electrode becomes a source electrode, and the other of the two becomes a drain electrode. Hereinafter, for ease of description, the first source / drain electrode will be referred to as a first electrode, and the second source / drain electrode will be referred to as a second electrode.

[0082] Each of the transistors T1 to T7 may be a thin film transistor ("TFT"). Each of the transistors T1 to T7 may be one of a p-type metal-oxide-semiconductor ("PMOS") transistor and an n-type metal-oxide-semiconductor ("NMOS") transistor. Although the seven transistors may all be transistors of the same type, some transistors may be PMOS transistors and the remaining transistors may be NMOS transistors. In the accompanying drawings, a case is shown in which all seven transistors are PMOS transistors.

[0083] The first transistor T1 is a driving transistor, a gate electrode of the first transistor T1 is connected to a first electrode of the storage capacitor Cst, a first electrode of the first transistor T1 is connected to a terminal of a first power supply voltage ELVDD via a fifth transistor T5, and a second electrode of the first transistor T1 is connected to an anode of the organic light emitting diode OLED via a sixth transistor T6. The first transistor T1 receives a data signal DATA through a data line according to a switching operation of the second transistor T2, and supplies a driving current Id to the organic light emitting diode OLED.

[0084] The second transistor T2 is a data transmission transistor, a gate electrode of the second transistor T2 is connected to a terminal of a first scanning signal GW, a first electrode of the second transistor T2 is connected to a terminal of a data signal DATA, and a second electrode of the second transistor T2 is connected to a terminal of a first power supply voltage ELVDD via a fifth transistor T5, and is connected to a first electrode of the first transistor T1. The second transistor T2 is turned on in response to the first scanning signal GW to perform a switching operation of transmitting the data signal DATA to the first electrode of the first transistor T1.

[0085] The third transistor T3 is a compensation transistor, the gate electrode of the third transistor T3 is connected to the terminal of the first scan signal GW, the first electrode of the third transistor T3 is connected to the anode of the organic light emitting diode OLED via the sixth transistor T6, and is connected to the second electrode of the first transistor T1, and the second electrode of the third transistor T3 is connected to the first electrode of the storage capacitor Cst, the first electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 is turned on in response to the first scan signal GW to connect the gate electrode and the second electrode of the first transistor T1 so that the first transistor T1 is diode-connected. Accordingly, a voltage difference corresponding to the threshold voltage of the first transistor T1 may occur between the first electrode and the gate electrode of the first transistor T1, and the threshold voltage variation of the first transistor T1 may be compensated by supplying the data signal DATA (whose threshold voltage is compensated) to the gate electrode of the first transistor T1.

[0086] The fourth transistor T4 is a first initialization transistor, a gate electrode of the fourth transistor T4 is connected to a terminal of a second scan signal GI, a second electrode of the fourth transistor T4 is connected to a terminal of an initialization voltage VINT, and a first electrode of the fourth transistor T4 is connected to a first electrode of a storage capacitor Cst, a second electrode of the third transistor T3, and a gate electrode of the first transistor T1. The fourth transistor T4 is turned on in response to the second scan signal GI to transmit the initialization voltage VINT to the gate electrode of the first transistor T1, thereby performing an operation of initializing the voltage of the gate electrode of the first transistor T1.

[0087] The fifth transistor T5 is a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to a terminal of a light emission control signal EM, a first electrode of the fifth transistor T5 is connected to a terminal of a first power supply voltage ELVDD, and a second electrode of the fifth transistor T5 is connected to a first electrode of the first transistor T1 and a second electrode of the second transistor T2.

[0088] The sixth transistor T6 is a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the terminal of the light emission control signal EM, a first electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 and the first electrode of the third transistor T3, and a second electrode of the sixth transistor T6 is connected to the anode of the organic light emitting diode OLED.

[0089] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the light emission control signal EM, and thus a driving current Id flows through the organic light emitting diode OLED.

[0090] The seventh transistor T7 is a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the terminal of the second scan signal GI, a first electrode of the seventh transistor T7 is connected to the anode of the organic light emitting diode OLED, and a second electrode of the seventh transistor T7 is connected to the terminal of the initialization voltage VINT. The seventh transistor T7 is turned on in response to the second scan signal GI to initialize the anode of the organic light emitting diode OLED.

[0091] A second electrode of the storage capacitor Cst is connected to a terminal of a first power supply voltage ELVDD. A first electrode of the storage capacitor Cst is connected to a gate electrode of the first transistor T1, a second electrode of the third transistor T3, and a first electrode of the fourth transistor T4. A cathode of the organic light emitting diode OLED is connected to a terminal of a second power supply voltage ELVSS. The organic light emitting diode OLED receives a driving current Id from the first transistor T1 and emits light to display an image.

[0092] The illustrated pixel circuit structure may be modified variously. In an exemplary embodiment, for example, a 2T1C structure including two transistors of a first transistor and a second transistor and one capacitor, or 3T1C, 3T2C, or 6T1C, etc. may be applied in various forms known in the art.

[0093] Figure 7 is a cross-sectional view of an exemplary embodiment of a display device. Figure 7 Show Figure 6 A cross section of a first transistor T1 and a second transistor T2 among a plurality of transistors in FIG. For ease of description, Figure 7 It is shown that the second source / drain electrode DE of the first transistor T1 is directly connected to the pixel electrode PXL without the sixth transistor T6. Figure 7 , a cross section of a cutout portion SLT of the substrate SUB is shown.

[0094] refer to Figure 7 , the display device includes a substrate SUB. The substrate SUB may include a flexible polymer. Since a description thereof has been given above, a repeated description will be omitted.

[0095] The buffer layer BUF is disposed on the substrate SUB and can prevent diffusion of impurity ions and penetration of moisture or external air, and can perform a surface planarization function.

[0096] The semiconductor layer PSL is disposed on the buffer layer BUF. The semiconductor layer PSL forms a channel of the TFT of the pixel PX. The semiconductor layer PSL may include polycrystalline silicon. However, the present invention is not limited thereto, and the semiconductor layer PSL may also include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. In an exemplary embodiment, the oxide semiconductor may include a binary compound (AB x ), ternary compounds (AB x C y ) and quaternary compounds (AB x C y D z ), including at least one of indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr) and / or magnesium (Mg), etc.

[0097] The gate insulating film GIL is disposed on the semiconductor layer PSL. The gate conductive layer GL is disposed on the gate insulating film GIL. The gate conductive layer GL may include a first electrode CE1 of a storage capacitor and a gate electrode GE of a TFT of a pixel PX. The gate conductive layer GL may include one or more metals including at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate conductive layer GL may be provided as a single layer film or a multilayer film.

[0098] The interlayer insulating film ILD is disposed on the gate conductive layer GL. The source / drain conductive layer SDL is disposed on the interlayer insulating film ILD. The source / drain conductive layer SDL may include a plurality of conductive layers separated from each other by an insulating film. In an exemplary embodiment, for example, the source / drain conductive layer SDL may include a first source / drain conductive layer SDL1, a second source / drain conductive layer SDL2, and a third source / drain conductive layer SDL3. A first passivation layer PAS1 as an insulating film may be disposed between the first source / drain conductive layer SDL1 and the second source / drain conductive layer SDL2, and a first through layer VIA1 as an insulating film may be disposed between the second source / drain conductive layer SDL2 and the third source / drain conductive layer SDL3. A second through layer VIA2 may be disposed on the third source / drain conductive layer SDL3, and a second passivation layer PAS2 may be disposed on the second through layer VIA2.

[0099] The source / drain conductive layer SDL may include one or more metals including at least one of Al, Mo, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The source / drain conductive layer SDL may be provided as a single-layer film or a multi-layer film. In an exemplary embodiment, for example, the source / drain conductive layer SDL may be provided in a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu, etc.

[0100] Various lines and electrodes constituting the pixel circuit may be formed of the source / drain conductive layer SDL.

[0101] In an exemplary embodiment, for example, the first source / drain conductive layer SDL1 may include a data line DL, and a first source / drain electrode SE and a second source / drain electrode DE of the TFT. In addition, portions of the first scan line SL1, the second scan line SL2, the light emission signal control line EML, etc. may also be formed by the first source / drain conductive layer SDL1. The first scan line SL1, the second scan line SL2, and the light emission signal control line EML may be electrically connected to the gate conductive layer GL thereunder through a contact hole passing through the interlayer insulating film ILD. In addition, the second electrode CE2 of the storage capacitor may also be formed by the first source / drain conductive layer SDL1. The second source / drain conductive layer SDL2 may include a first power supply voltage line ELVDDL, and the third source / drain conductive layer SDL3 may include a second power supply voltage line ELVSSL and an initialization voltage line VINTL. In addition, the source / drain conductive layer SDL may further include a test line TSL (reference Figure 8 ). A detailed description of the test line TSL will be given below.

[0102] The number of gate conductive layers GL and source / drain conductive layers SDL, or the lines included in each source / drain conductive layer SDL may be variously modified according to a plan, etc. In an exemplary embodiment, for example, a separate gate conductive layer forming the second electrode CE2 of the storage capacitor may be further provided between the gate conductive layer GL and the first source / drain conductive layer SDL1. In some cases, the gate conductive layer GL may be omitted, and the gate electrode GE, the scan line, the first electrode CE1 of the storage capacitor, etc. may be provided by the source / drain conductive layer SDL. An exemplary layout of the source / drain conductive layer SDL will be described below.

[0103] The second passivation layer PAS2 is disposed on the second through layer VIA2. The pixel electrode PXL is disposed on the second passivation layer PAS2. The pixel electrode PXL may be electrically connected to the second source / drain electrode DE of the TFT (first transistor T1). In an exemplary embodiment, the pixel electrode PXL may have a material having a high work function (such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), or indium oxide (In 2 O 3 The pixel electrode PXL may have a stacked film structure in which a layer of a reflective material (such as Ag, Mg, Al, Pt, lead (Pb), Au, Ni, Nd, Ir, Cr, Li, Ca or a combination thereof) is stacked. The layer of the material having a high work function may be disposed above the layer of the reflective material and disposed close to the organic layer OML. In an exemplary embodiment, the pixel electrode PXL may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO, but the present invention is not limited thereto.

[0104] The pixel defining film PDL may be disposed on the pixel electrode PXL. An opening exposing the pixel electrode PXL may be defined in the pixel defining film PDL.

[0105] The organic layer OML is disposed in the opening of the pixel definition layer PDL. The organic layer OML may include an organic light emitting layer, a hole injection / transport layer, and an electron injection / transport layer.

[0106] The common electrode CME is disposed on the organic layer OML and the pixel definition film PDL. The common electrode CME may be disposed on the entire surface of each pixel PX. The common electrode CME may include a layer of a material having a low work function, which includes at least one of Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, and a compound or combination thereof (e.g., a combination of Ag and Mg). The common electrode CME may further include a transparent metal oxide layer disposed on the layer of the material having a low work function. The common electrode CME may be connected to a second power supply voltage line ELVSSL formed by a third source / drain conductive layer SDL3 through a contact hole passing through the pixel definition film PDL, the second passivation layer PAS2, and the second through layer VIA2.

[0107] The thin film encapsulation layer TFE may be disposed on the common electrode CME. The thin film encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0108] In an exemplary embodiment, each of the above-mentioned buffer layer BUF, gate insulating film GIL, interlayer insulating film ILD, first passivation layer PAS1 and second passivation layer PAS2 may include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide or zinc oxide. In an exemplary embodiment, each of the first through layer VIA1, the second through layer VIA2 and the pixel definition film PDL may include an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene ("BCB"). However, it should be understood that the materials constituting the insulating film are not limited to those shown above, and various materials known in the art may be applied to the constituent materials of each insulating film.

[0109] Hereinafter, an exemplary layout of the source / drain conductive layer SDL and the test line TSL of each conductive layer will be described.

[0110] Figure 8 is a plan view of a source / drain conductive layer in a repeating unit of an array in an exemplary embodiment. Fig. 9 It is along Figure 8 A cross-sectional view taken along line IX-IX′. Fig.10 yes Figure 8 A plan view of a first source / drain conductive layer. Fig.11 yes Figure 8 A plan view of a second source / drain conductive layer. Fig.12 yes Figure 8 A plan view of a third source / drain conductive layer.

[0111] refer to Figures 8 to 12 The first source / drain conductive layer SDL1 may include a first data line DL1 (through which a data signal is transmitted to the first pixel PX1), a second data line DL2 (through which a data signal is transmitted to the second pixel PX2), and a third data line DL3 (through which a data signal is transmitted to the third pixel PX3). The data line DL is connected from the sixth island ISL6 (reference Figure 5 ) extends upward and passes through the cutout portion SLT to reach the first island ISL1 (reference Figure 5 ) of the left protrusion LPT (reference Figure 5 ) and then bends in the right direction to extend to the right protrusion RPT of the first island ISL1 (reference Figure 5 At the right protrusion RPT of the first island ISL1, the data line DL is bent and extended upward again to extend to the fourth island ISL4 by passing through the cutout portion SLT (refer to Figure 5 Although not shown in the drawings, the data line DL disposed at the lower boundary of the sixth island ISL6 may extend to the sixth island ISL6 of another array repeat unit APU disposed therebelow, and the data line DL disposed at the upper boundary of the fourth island ISL4 may extend to the fourth island ISL4 of another array repeat unit APU disposed thereover.

[0112] The first source / drain conductive layer SDL1 may further include a first scan line SL1, a second scan line SL2, and a light emission signal control line EML, through which a first scan signal GW, a second scan signal GI, and a light emission control signal EM are respectively provided to the first pixel PX1, the second pixel PX2, and the third pixel PX3. Portions of the first scan line SL1, the second scan line SL2, and the light emission signal control line EML extend rightward from the left boundary of the third island ISL3 and extend to the upper protrusion UPT of the first island ISL1 beyond the cutout portion SLT and terminate. Symmetrically, the other portions of the first scan line SL1, the second scan line SL2, and the light emission signal control line EML extend from the fifth island ISL5 (reference Figure 5) extends to the left and extends to the lower protrusion BPT of the first island ISL1 beyond the cutout portion SLT and terminates. In addition, segments of the first source / drain conductive layer SDL1 may be disposed in the first island ISL1 and the second island ISL2, and signal lines may be connected to the segments through another conductive layer.

[0113] The second source / drain conductive layer SDL2 includes a first power voltage line ELVDDL. A portion of the first power voltage line ELVDDL extending from the sixth island ISL6 to the fourth island ISL4 through the first island ISL1 and another portion of the first power voltage line ELVDDL extending from the third island ISL3 to the fifth island ISL5 through the first island ISL1 intersect each other at the first island ISL1. Some segments of the second source / drain conductive layer SDL2 extend from the upper protrusion UPT of the first island ISL1 to the second island ISL2. In addition, the second source / drain conductive layer SDL2 may further include a plurality of segments disposed in the first island ISL1.

[0114] The third source / drain conductive layer SDL3 includes an initialization voltage line VINTL and a second power supply voltage line ELVSSL. A portion of the initialization voltage line VINTL extends rightward from the left boundary of the third island ISL3 and extends to the upper protrusion UPT of the first island ISL1 beyond the cutout portion SLT and terminates. Symmetrically, another portion of the initialization voltage line VINTL extends leftward from the right boundary of the fifth island ISL5 and extends to the lower protrusion BPT of the first island ISL1 beyond the cutout portion SLT and terminates. The second power supply voltage line ELVSSL extends from the sixth island ISL6 to the right protrusion RPT of the first island ISL1 and branches at the right protrusion RPT of the first island ISL1, and a portion of the branched second power supply voltage line ELVSSL extends to the fourth island ISL4, and another portion of the branched second power supply voltage line ELVSSL extends to the second island ISL2, the upper protrusion UPT of the first island ISL1, and the third island ISL3. In addition, the third source / drain conductive layer SDL3 may further include a plurality of segments disposed in the first island ISL1.

[0115] As described above, the line formed by the source / drain conductive layer SDL may extend to intersect with the plurality of islands ISL of the substrate SUB. A portion of the line is also disposed on the cutout portion SLT of the substrate SUB. However, since the width of the cutout portion SLT is stretched relatively more in the process in which the substrate SUB is stretched, the line placed on the cutout portion SLT may be subjected to strong stress. In some cases, the line on the cutout portion SLT may be disconnected during the stretching process, which may result in a display defect. However, even when a display defect is confirmed, it is difficult to confirm whether it is due to the disconnection of the line on the cutout portion SLT or due to other reasons because of various reasons for the presence of display defects. Each source / drain conductive layer SDL may include a test line TSL to identify the exact cause of the display defect and / or the defect-causing factor at each process operation.

[0116] The test line TSL is formed by the corresponding source / drain conductive layer SDL. The test line TSL may include, for example, at least one of a first test line TSL1 formed by the first source / drain conductive layer SDL1, a second test line TSL2 formed by the second source / drain conductive layer SDL2, and a third test line TSL3 formed by the third source / drain conductive layer SDL3. Although the test line TSL is shown in the drawings as including all of the first to third test lines TSL1 to TSL3, some of the first to third test lines TSL1 to TSL3 may be omitted.

[0117] The first test line TSL1, the second test line TSL2, and the third test line TSL3 may not overlap with each other. However, the present invention is not limited thereto, and some or all may be disposed to overlap with each other.

[0118] The test line TSL intersects with the cutout portion SLT. In an exemplary embodiment, one end portion and the other end portion of the test line TSL may be disposed in different islands ISL. Specifically, as shown in the accompanying drawings, one end portion of some test lines TSL may be disposed in the left protrusion LPT of the first island ISL1, and the other end portion thereof may be disposed in the third island ISL3 adjacent to the left protrusion LPT. One end portion of some other test lines TSL may be disposed in the right protrusion RPT of the first island ISL1, and the other end portion thereof may be disposed in the fifth island ISL5 adjacent to the right protrusion RPT.

[0119] In another exemplary embodiment, both end portions of the test line TSL may be disposed in the same island ISL. In this case, the test line TSL may intersect the cutout portion SLT two or more times while changing its extension direction a plurality of times.

[0120] Both end portions of the test line TSL may include pad areas TSL1_PD, TSL2_PD, and TSL3_PD which are extended more in width than the extension portion. The extended pad areas TSL1_PD, TSL2_PD, and TSL3_PD may be used for a probe to directly apply a signal.

[0121] At least one of the two end portions of the test line TSL may be separated from other signal lines. In an exemplary embodiment, for example, one end portion of the test line TSL disposed in the first island ISL1 having sufficient space may be disposed to be spaced apart from other signal lines in its periphery. The other end portion of the test line TSL disposed in the third island ISL3 and the fifth island ISL5 (where the space is slightly insufficient) may be connected to an adjacent signal line. In an exemplary embodiment, for example, the other end portion of the first test line TSL1 may be connected to the first scan line SL1, the other end portion of the second test line TSL2 may be connected to the first power supply voltage line ELVDDL, and the other end portion of the third test line TSL3 may be connected to the second power supply voltage line ELVSSL or the initialization voltage line VINTL. As in the case of the first test line TSL1, when the width of the line of the extended pad area TSL1_PD connected to the first test line TSL1 is less than the width of the extended pad area TSL1_PD, a portion of the extended pad area TSL1_PD may protrude from the line connected to the pad area TSL1_PD. As in the case of the second test line TSL2, when the width of the line connected to the extended pad area TSL2_PD is sufficient, the extended pad area TSL2_PD may be disposed in the line connected to the extended pad area TSL2_PD, and thus its shape may not be observed.

[0122] The test line TSL can be used to confirm the disconnection of the corresponding line during the intermediate operation of the process. In an exemplary embodiment, for example, a first source / drain conductive layer SDL1 is provided. Thereafter, the probe directly contacts the extended pad area TSL1_PD of one end portion and the other end portion of the first test line TSL1, respectively, to measure the resistance of the first test line TSL1. Before measuring the resistance of the first test line TSL1, a plurality of tensile tests may be performed. Through the resistance measurement, it can be confirmed whether the first test line TSL1 intersecting the cutout portion SLT is disconnected. When the first test line TSL1 is disconnected, it is determined that the first source / drain conductive layer SDL1 is disconnected, and the corresponding intermediate structure can be regarded as a defective structure. Because the first test line TSL1 is set in the array repeating unit APU in the display area DPA, it is possible to directly test whether the disconnection occurs in the corresponding array repeating unit APU in which the actual pixel PX is set instead of the outside of the display area DPA, so that the location where the defect occurs can be specifically identified. In the same way, after providing the second source / drain conductive layer SDL2, it can be determined whether the second test line TSL2 is disconnected by measuring the resistance of the second test line TSL2. In addition, after providing the third source / drain conductive layer SDL3 , it may be determined whether the third test line TSL3 is disconnected by measuring the resistance of the third test line TSL3 .

[0123] The intermediate structure that has been tested by contacting the probe with the test line TSL may be discarded after being used only to determine whether a defect exists. When it is determined that a defect exists, it may be assumed that there is a problem with the position and width of the cutout portion SLT of the substrate SUB, and the formation process of the corresponding source / drain conductive layer SDL, and the process conditions, etc. may be checked again. When it is determined that no defect exists, the existing process conditions may be confirmed as good conditions.

[0124] The test using the test line TSL can be performed by sampling some of the intermediate structures that complete the same process. For this purpose, the test line TSL can be set only on the intermediate structure to be sampled among the various intermediate structures, but due to the characteristics of the mask process, such a method may be inefficient. Accordingly, forming the test line TSL in all products to be manufactured, and then evaluating whether the test line TSL is disconnected for some of all products can be more effective in process efficiency. When it is determined that there is a defect due to the test, the intermediate structure manufactured in the same process can be discarded or repaired, and when it is determined that there is no defect, the intermediate structure manufactured in the same process can be completed as a final product by the following process. Although the display device completed in this way may include the test line TSL, the intermediate structure of the corresponding display device may not be tested.

[0125] Fig.13 is a plan view of a source / drain conductive layer in a repeating unit of an array according to another exemplary embodiment. Fig.14 It is along Fig.13A cross-sectional view taken along line XIV-XIV′.

[0126] refer to Fig.13 and Fig.14 , the display device according to the exemplary embodiment shown and the reference Figure 8 and Fig. 9 The described exemplary embodiment is different in that each of the test lines TSL includes a contact electrode.

[0127] Specifically, the first to third test lines TSL1 to TSL3 are arranged on different layers. Because the first test line TSL1 is exposed to the outside when the first source / drain conductive layer SDL1 is provided, the resistance can be measured by making a probe contact, but at the time of this operation, the second test line TSL2 is not provided, and therefore the resistance of the second test line TSL2 may not be measured all at once. A subsequent process must be performed to measure the resistance of the second test line TSL2, and in this case, because the first passivation layer PAS1 covers the first source / drain conductive layer SDL1, the first test line TSL1 is not exposed to the outside and is therefore difficult to test by making a contact probe. In order to test the first test line TSL1 by making a probe contact even after the second test line TSL2 is provided, the second source / drain conductive layer SDL2 may include a first lower contact electrode CTE1_B that contacts the extended pad area TSL1_PD of the first test line TSL1 by passing through the first passivation layer PAS1. When the contact electrode of the first test line TSL1 is formed by the second source / drain conductive layer SDL2, the second test line TSL2 and the first test line TSL1 can be tested at once. That is, the resistance of each test line TSL can be measured by sequentially or simultaneously contacting the probe with the first lower contact electrode CTE1_B of the first test line TSL1 and the second test line TSL2.

[0128] The same method can also be applied to the third test line TSL3. That is, the first upper contact electrode CTE1_U (which is connected to the first lower contact electrode CTE1_B of the first test line TSL1 by passing through the first through layer VIA1) and the second contact electrode CTE2 connected to the second test line TSL2 can be formed by the third source / drain conductive layer SDL3. As a result, the first upper contact electrode CTE1_U of the first test line TSL1, the second contact electrode CTE2 of the second test line TSL2, and the third test line TSL3 are exposed to the outside, and the probe is contacted therewith sequentially or simultaneously to measure the resistance of each test line TSL.

[0129] Fig.13 and Fig.14The configuration of the contact electrode shown in is only an example, and various modifications are possible. In an exemplary embodiment, for example, the first contact electrode CTE1 for exposing the first test line TSL1 to the outside may be formed by the third source / drain conductive layer SDL3 without the second source / drain conductive layer SDL2. Further, a contact electrode that passes through another insulating layer disposed above the third source / drain conductive layer SDL3 may be provided using the material of the pixel electrode PXL.

[0130] Fig.15 is a plan view of an exemplary embodiment of a source / drain conductive layer in an array repeating unit according to another exemplary embodiment. Fig.15 The exemplary embodiment in FIG. 1 shows that a display device may include a test transistor capable of analyzing a characteristic value of a transistor in a pixel unit.

[0131] As reference Figure 6 As described, the display device includes a plurality of pixels PX, and each of the pixels PX includes a plurality of transistors (pixel circuit transistors). The transistors of each of the pixels PX can be provided simultaneously by the same process. Although a plurality of transistors are provided by the same process, each of the transistors may have different characteristic values ​​depending on its position. In an exemplary embodiment, for example, due to misalignment, the width or length of the channel at each position may be different, or a thickness difference may occur in the film due to the influence of the surrounding structure. In addition, a temperature difference may occur at each position in the process operation, and therefore the components of the deposited materials may be partially different from each other. For each position, such a slight difference in process conditions may cause the transistors provided to have different threshold voltages, cut-off currents, voltage-current curves, etc. When the substrate SUB or the mother substrate SUB becomes larger, the characteristic values ​​of the transistors at each position may be different. It is necessary to check the distribution of such transistors and analyze whether there are defects.

[0132] One method of determining whether a transistor is defective is to analyze the characteristic value of the transistor after forming a dummy transistor in the non-display area NDA. However, although the characteristic value of the transistor provided in the pixel PX can be indirectly evaluated only by the characteristic value of the dummy transistor in the non-display area NDA, it is difficult to reflect the variables depending on the position of each pixel PX. In particular, when the substrate SUB includes a cutout portion SLT, the characteristics of the transistor around the cutout portion SLT may vary according to stretching, and thus it is difficult to explain that the dummy transistor in the non-display area NDA outside the display area DPA shows the same state as the transistor around the cutout portion SLT.

[0133] By setting the test transistor TRT in the array repetition unit APU, the test transistor TRT can be in a micro-machining state and stress state substantially the same as the peripheral transistor. Accordingly, the characteristic value of the peripheral transistor (e.g., the driving transistor) can be more accurately identified by analyzing the characteristic value of the test transistor TRT. In addition, when the test transistor TRT is provided in various array repetition units APU, the distribution of transistors at each position can also be accurately analyzed. That is, the short-range uniformity characteristics can be accurately measured.

[0134] One test transistor TRT may be provided for each array repetition unit APU, but the present invention is not limited thereto, and two or more test transistors TRT may be provided for each array repetition unit APU, or a test transistor TRT may also be provided for each array repetition unit APU provided at regular intervals in a plurality of array repetition units APU.

[0135] The test transistor TRT may be provided not only to be separated from the transistor of the pixel circuit but also to be separated from other lines without being connected to the other lines. For this purpose, the test transistor TRT may be provided in the first island ISL1 having a relatively large area. In an exemplary embodiment, for example, the test transistor TRT may be provided on the left protrusion LPT of the first island ISL1, but the present invention is not limited thereto.

[0136] Fig.16 yes Fig.15 A magnified image of the test transistor. Fig.17 It is along Fig.16 A cross-sectional view taken along line XVII-XVII′. Fig.18 It is along Fig.16 A cross-sectional view taken along line XVIII-XVIII′.

[0137] refer to Figures 16 to 18 , the test transistor TRT includes a semiconductor layer PSL, a gate electrode TRT_GE, a first source / drain electrode TRT_SE, and a second source / drain electrode TRT_DE. The test transistor TRT has a layered structure that is the same as that of a transistor of a pixel. The gate electrode TRT_GE may be formed by the above-mentioned gate conductive layer GL, and the first source / drain electrode TRT_SE and the second source / drain electrode TRT_DE may be formed by the first source / drain conductive layer SDL1. Each of the gate electrode TRT_GE, the first source / drain electrode TRT_SE, and the second source / drain electrode TRT_DE may include a pad area extending in one direction and then extending in width. The areas of the pad areas may be the same, but the present invention is not limited thereto.

[0138] The test transistor TRT may further include a gate contact electrode GCT, a first source / drain contact electrode SCT, and a second source / drain contact electrode DCT. The gate contact electrode GCT, the first source / drain contact electrode SCT, and the second source / drain contact electrode DCT may include the material of the pixel electrode PXL. The gate contact electrode GCT may be electrically connected to the gate electrode TRT_GE through a contact hole passing through the second passivation layer PAS2, the second through layer VIA2, the first through layer VIA1, the first passivation layer PAS1, and the interlayer insulating film ILD. The first source / drain contact electrode SCT and the second source / drain contact electrode DCT may be electrically connected to the first source / drain electrode TRT_SE and the second source / drain electrode TRT_DE through contact holes passing through the second passivation layer PAS2, the second through layer VIA2, the first through layer VIA1, and the first passivation layer PAS1, respectively.

[0139] As described above, when the contact electrode of the test transistor TRT is disposed on the top layer and exposed to the outside, a test by contacting the probe can be easily performed. That is, through the probe, an on / off voltage can be applied to the gate contact electrode GCT and various test voltages can be applied to the first source / drain contact electrode SCT and the second source / drain contact electrode DCT to measure various characteristic values ​​of the test transistor TRT. As described above, because a signal can be directly applied to each terminal of the test transistor TRT, the characteristic value of the pure test transistor TRT itself can be accurately identified without being affected by the power supply voltage lines ELVDDL and ELVSSL or other transistors connected to the test transistor TRT. In addition, as a result, the characteristic values ​​of the transistors around the display area DPA can be accurately evaluated, which can be utilized to manage the distribution characteristics of the transistors in the entire display area DPA.

[0140] The above exemplary embodiments may be combined in various ways. In an exemplary embodiment, for example, the display device may include both the test transistor TRT and the test line TSL. Specifically, the test transistor TRT and the test line TSL may be provided in one array repeating unit APU, and only the test transistor TRT may be provided in some array repeating units APU, and only the test line TSL may be provided in some other array repeating units APU.

[0141] In summarizing the detailed description, those skilled in the art will recognize that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the invention. Therefore, the disclosed preferred embodiments of the present invention are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A display device, comprising: a substrate defining a cutout portion therein; as well as a first conductive layer, the first conductive layer being disposed on the substrate and comprising a first signal line and a first test line, wherein a portion of the first test line does not overlap with the substrate in the thickness direction, The portion of the first test line that does not overlap the substrate intersects the cutout portion and overlaps the cutout portion in the thickness direction, and One end portion of the first test line includes an extended first pad area. 2 . The display device according to claim 1 , wherein the substrate includes a plurality of islands divided by the cutout portion.

3. The display device according to claim 2, wherein: wherein the pattern in which the plurality of islands are arranged comprises a plurality of array repeating units, and The plurality of array repeating units are repeatedly arranged along a first direction and a second direction intersecting the first direction.

4. The display device according to claim 3, wherein the plurality of array repeating units comprises a first array repeating unit and a second array repeating unit adjacent to the first array repeating unit in the first direction or the second direction, and The second array repeating unit has a shape that is line symmetric with respect to the first array repeating unit. 5 . The display device according to claim 3 , wherein at least one first test line is provided for each of the plurality of array repeating units. 6 . The display device of claim 3 , wherein one or more pixels are disposed in at least one of the plurality of array repeating units. 7 . The display device according to claim 1 , wherein at least a portion of the first signal line intersects the cutout portion.

8. The display device according to claim 1, further comprising a first insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the first insulating layer and comprising a second signal line and a second test line, wherein the second test line intersects the cutout portion, and One end portion of the second test line includes an extended second pad area. 9 . The display device according to claim 8 , wherein the second conductive layer includes a portion of the first contact electrode connected to the first pad region of the first test line by passing through the first insulating layer.

10. The display device according to claim 8, further comprising a second insulating layer disposed on the second conductive layer, and a third conductive layer disposed on the second insulating layer and comprising a third signal line and a third test line, wherein the third test line intersects the cutout portion, and One end portion of the third test line includes an extended third pad area.

11. The display device according to claim 10, wherein the third conductive layer includes a portion of the first contact electrode connected to the first pad region by passing through the second insulating layer and the first insulating layer, and A second contact electrode is connected to the second pad region by passing through the second insulating layer.

12. The display device according to claim 10, further comprising: As a pixel circuit provided to each pixel: a data line through which a data signal is transmitted; a first power supply voltage line, through which a first power supply voltage signal is transmitted; and a second power supply voltage line, through which a second power supply voltage signal is transmitted, in, The first signal line includes the data line, The second signal line includes the first power supply voltage line, and The third signal line includes the second power supply voltage line.

13. The display device according to claim 1, wherein the display device is retractable to expand and contract.

14. The display device according to claim 1, wherein The substrate includes a display area, and the display area includes a plurality of pixels. The display device further comprises: a plurality of pixel circuit transistors and a test transistor disposed on the substrate; as well as a pixel electrode connected to at least some of the plurality of pixel circuit transistors and provided to each of the plurality of pixels, wherein the test transistor is arranged in the display area, The test transistor has a layered structure identical to that of the pixel circuit transistor, and further includes a contact electrode including a material of the pixel electrode, and The contact electrodes include a gate contact electrode connected to a gate electrode of the test transistor, a first source / drain contact electrode connected to a first source / drain electrode of the test transistor, and a second source / drain contact electrode connected to a second source / drain electrode of the test transistor. 15 . The display device of claim 14 , wherein the substrate comprises a plurality of islands divided by the cutout portions.

16. The display device according to claim 15, wherein: wherein the pattern in which the plurality of islands are arranged comprises a plurality of array repeating units, the plurality of array repeating units being repeatedly arranged in a first direction and in a second direction intersecting the first direction, and The test transistor is disposed in at least one of the plurality of array repeating units.

17. The display device of claim 15, wherein the display device is retractable to expand and contract.

18. A method for testing a display device, the method comprising: forming a first conductive layer including a first signal line and a first test line on a substrate, defining a cutout portion in the substrate so that a portion of the first test line does not overlap with the substrate in a thickness direction, the portion of the first test line that does not overlap with the substrate intersects with the cutout portion and overlaps with the cutout portion in the thickness direction, and the first test line includes one end portion including an extended first pad area; and The resistance of the first test line is measured. 19 . The testing method according to claim 18 , wherein the measuring of the resistance of the first test line is performed by a contact probe.

20. The testing method of claim 18, further comprising performing a pull test on the substrate on which the first conductive layer is provided before the measuring of the resistance of the first test line.

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