Method for forming a semiconductor device

Abstract

Semiconductor devices and methods of forming semiconductor devices are disclosed herein, and more particularly to semiconductor devices including wrap-around gate transistor structures and methods of manufacturing the same. Methods described herein can etch a complex shape (e.g., L-shaped) into a multi-layer stack to form a fin for an active region of a wrap-around gate nanowire transistor structure. In some embodiments, the active region can have a first source / drain region with a first channel width and a first width, and a second source / drain region with a second channel width and a second width that is less than the first width.

Description

Technical Field

[0001] This disclosure relates to the integration of horizontally fully wound gate nanostructures for use in the design and operation of integrated circuits at 3nm technology nodes or smaller. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The fabrication method of semiconductor devices typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the multiple material layers to form circuit components and units on the semiconductor substrate.

[0003] The semiconductor industry continues to reduce minimum structural dimensions to improve the density of various electronic components, such as transistors, diodes, resistors, capacitors, or the like, in order to integrate more components into a given area. However, as the minimum structural dimensions decrease, additional problems arise that need to be addressed. Summary of the Invention

[0004] In one embodiment, a method for forming a semiconductor device includes: depositing a first sheet on a semiconductor substrate; depositing a first semiconductor material on the first sheet; depositing a second sheet on the first semiconductor material; depositing a second semiconductor material on the second sheet; patterning the first sheet, the first semiconductor material, the second sheet, and the second semiconductor material into fins, the fins having a first width and a second width, wherein the first width is greater than the second width; removing the first sheet and the second sheet to form a first nanostructure from the first semiconductor material and a second nanostructure from the second semiconductor material; depositing a gate dielectric layer around the first nanostructure and the second nanostructure; and depositing a gate around the gate dielectric layer.

[0005] In one embodiment, a method of forming a semiconductor device includes: forming a multilayer stack on a semiconductor substrate, the multilayer stack including a first layer of a first material and a second layer of a second material, wherein the first material and the second material are different; etching a pattern into the multilayer stack, the remainder of the multilayer stack including an active region, the active region separating a retained first side of the multilayer stack and a retained second side of the multilayer stack, the first side having a first width and the second side having a second width, wherein the first width and the second width are different; performing a line release process to remove the first layer and form a stack of nanostructures, wherein the stack of nanostructures has a first width on the first side and a second width on the second side; depositing a gate dielectric layer around the stack of nanostructures; and depositing a gate to surround each nanostructure in the stack of nanostructures.

[0006] In one embodiment, the semiconductor device includes: a gate dielectric layer on a substrate; a gate surrounding the gate dielectric layer; and a vertical stack of nanostructures, each nanostructure of the vertical stack including an active region surrounded by the gate dielectric layer, wherein each active region has a first channel width on a first side of the gate dielectric layer and a second channel width on a second side of the gate dielectric layer, and the first channel width is greater than the second channel width. Attached Figure Description

[0007] Figures 1 to 12 These are accompanying drawings illustrating intermediate steps in forming a fully encircling active device in some embodiments.

[0008] Figure 13A This is a perspective view of a fully wound gate device in one embodiment.

[0009] Figure 13B In one embodiment, Figure 13A Top view of a cross-section of the fully wound gate device shown.

[0010] Figure 14A and 14B This is a top view of a cross-section of a fully wound gate device in another embodiment.

[0011] Figures 15A to 15E Showing a top view of various cell schemes containing multilayer active device arrays in some embodiments.

[0012] Explanation of reference numerals in the attached figures:

[0013] AA: Section

[0014] L1: First Length

[0015] OS-L deviates to the left

[0016] OS-R: Deviate to the right

[0017] SDH1: First source / drain height

[0018] Th1: First thickness

[0019] Th2: Second thickness

[0020] Th3: Third thickness

[0021] Th4: Fourth thickness

[0022] Th5: Fifth Thickness

[0023] Th6: Sixth Thickness

[0024] W dg dummy gate width

[0025] Wf1: Width of the first fin

[0026] Wf2: Width of the second fin

[0027] W1: First width

[0028] W2: Second width

[0029] W3: Third Width

[0030] W4: Fourth Width

[0031] W5: Fifth Width

[0032] W6: Sixth Width

[0033] W7: Seventh Width

[0034] W8: Eighth Width

[0035] W9: Ninth Width

[0036] W10: Tenth Width

[0037] W11: Eleventh Width

[0038] W12: Twelfth Width

[0039] W13: Thirteenth Width

[0040] W14: Fourteenth Width

[0041] 72: Dummy Gate

[0042] 87: Contact Etching Stop Layer

[0043] 101: Substrate

[0044] 106: First Device Area

[0045] 119: Dummy gate dielectric layer

[0046] 121: Dummy Gate

[0047] 122: Fin-like structures

[0048] 123: Third Hard Mask

[0049] 125: Fourth Hard Mask

[0050] 129: Dummy Gate Stack

[0051] 130: Compliant dielectric layer

[0052] 131: Gate spacer

[0053] 133: Trench

[0054] 135: Shallow trench isolation zone

[0055] 200,1501: Multi-layer active device

[0056] 203: Multi-layer stacking

[0057] 205: First Hard Mask

[0058] 207: Second Hard Mask

[0059] 250: Deposition process

[0060] 251: First Floor

[0061] 261: Second layer

[0062] 301: Active Zone

[0063] 303: Corner

[0064] 350: Patterning process

[0065] 501: First inner spacer

[0066] 601: Source / Drain Region

[0067] 701: Interlayer dielectric layer

[0068] 901: Nanostructure

[0069] 1033,1511: Opening

[0070] 1101: Gate dielectric layer

[0071] 1103: Gate

[0072] 1300: Fully wound gate transistor

[0073] 1500: First Unit Scheme

[0074] 1510: Second Unit Scheme

[0075] 1520: Third Unit Scheme

[0076] 1522: First fin

[0077] 1523: Second fin

[0078] 1525: Third fin

[0079] 1527: Fourth fin

[0080] 1529: Fifth fin

[0081] 1530: Scheme for Unit 4

[0082] 1531: Sixth fin

[0083] 1533: Seventh fin

[0084] 1535: Eighth fin

[0085] 1537: Ninth Fin

[0086] 1539: Tenth fin

[0087] 1540: Fifth Unit Scheme Detailed Implementation

[0088] The different embodiments or examples provided below can implement different structures of this disclosure. Embodiments of specific components and configurations are used to simplify the content of this disclosure and not to limit it. For example, a description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where the two are separated by other additional components and are not in direct contact. Furthermore, multiple embodiments of this disclosure may repeat the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or configurations do not necessarily have the same correspondence.

[0089] In addition, spatial relative terms such as "below," "under," "lower," "above," "above," or similar terms can be used to simplify the description of the relative relationship between one element and another in the illustration. Spatial relative terms can be extended to elements used in other directions, rather than being limited to the direction shown in the illustration. Elements can also be rotated 90° or other angles, so directional terms are only used to describe the direction shown in the illustration.

[0090] The embodiments described herein relate to the integration of horizontally wrapped gate nanostructures for integrated circuit design and operation at 3nm technology nodes or smaller. These embodiments can form composite shapes (such as L-shapes) within the active region of the wrapped gate nanostructure transistor. In the embodiments described herein, the wrapped gate nanostructure transistor may have a first source / drain region with a first channel width and a second source / drain region with a second channel width and a second width (smaller than the first width). In this way, the wrapped gate nanostructure transistor can have composite active regions (such as L-shapes), which are energy-efficient during operation and provide design flexibility with a variety of cell configurations available. However, the embodiments can be used in various ways and are not limited to those described herein.

[0091] Figure 1This is a perspective view of a deposition process 250 performed on substrate 101 to form a multilayer active device 200 during an intermediate stage in the fabrication of a fully wound gate transistor in some embodiments. In one embodiment, substrate 101 is a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, a III-V group material substrate (e.g., gallium arsenide, gallium phosphide, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium arsenide, gallium indium phosphide, indium antimonide, gallium arsenide phosphide, or combinations thereof), or a substrate formed of other semiconductor materials such as high-bandwidth to band-tunneling semiconductor materials. Substrate 101 may be doped or undoped. In some embodiments, substrate 101 may be a substrate semiconductor substrate such as a substrate silicon substrate (wafer), a semiconductor-on-insulator substrate, a multilayer or gradient substrate, or the like. Substrate 101 may be implanted with dopants to form well regions used in the active device.

[0092] Figure 1 The substrate 101 shown may include a first device region 106 for forming an n-type device such as an n-type metal-oxide-semiconductor transistor (e.g., an n-type fully wound gate transistor), but the first device region 106 may also be used to form a p-type device such as a p-type gold metal-oxide-semiconductor transistor (e.g., a p-type fully wound gate transistor). Although Figure 1 Only a single device region is shown, but it should be understood that the first device region 106 is only used to illustrate a single area in a semiconductor wafer, and a semiconductor wafer may contain many device regions. Many device regions such as the first device region 106 and / or multiple other device regions different from the first device region 106 can be formed.

[0093] like Figure 1 As shown, a series of depositions are performed to form a multilayer stack 203 of interleaved first layers 251 and second layers 261 on substrate 101. In some embodiments, the deposition process 250 includes forming a semiconductor layer with a first lattice constant as the first layer 251, such as silicon-germanium, germanium, silicon, gallium arsenide, indium antimonide, gallium antimonide, aluminum indium arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or the like. In some embodiments, the method of epitaxially growing the first layer 251 on substrate 101 may employ deposition techniques such as epitaxial growth, vapor phase epitaxy, or molecular beam epitaxy, but may also employ other deposition processes such as chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma chemical vapor deposition, combinations thereof, or similar processes. In some embodiments, the first layer 251 has a first thickness Th1, which is between about 4 nm and about 15 nm, for example, about 10 nm. However, any suitable thickness is still within the scope of the embodiments.

[0094] Once the first layer 251 is formed on the substrate 101, a second layer 261 can be formed on the first layer 251. In some embodiments, the second layer 261 may be a second semiconductor material with a lattice constant different from that of the first layer 251, such as silicon, silicon-germanium, germanium, gallium arsenide, indium antimonide, gallium antimonide, aluminum indium arsenide, gallium antimony phosphide, gallium antimony arsenide, combinations thereof, or the like. In a specific embodiment, the first layer 251 is silicon-germanium, while the second layer 261 is a material with a different lattice constant, such as silicon. However, any suitable combination of materials may be used.

[0095] In some embodiments, the method of epitaxially growing the second layer 261 on the first layer 251 may employ deposition techniques such as epitaxial growth, vapor phase epitaxy, or molecular beam epitaxy, but may also employ other deposition processes such as chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ultra-high vacuum chemical vapor deposition, far-end plasma chemical vapor deposition, combinations thereof, or similar processes. The second layer 261 has a first thickness Th2, which is between about 4 nm and about 10 nm, for example, about 7 nm. However, any suitable thickness is still within the scope of the embodiments.

[0096] Once the second layer 261 is formed on the first layer 251, the deposition process 250 can be repeated to form a series of additional material layers with the first layer 251 and the second layer 261 interleaved, until the top layer required to form the multilayer stack 203 is formed. In a specific embodiment, another first layer 251 has a third thickness Th3, another second layer 261 has a fourth thickness Th4, another first layer 251 has a fifth thickness Th5, and another second layer 261 has a sixth thickness Th6. Furthermore, the sheet-like spaces between the second layers 261 are substantially equal to the thickness of the first layer 251 (e.g., the first thickness Th1, the third thickness Th3, and the fifth thickness Th5). In this embodiment, the top layer of the multilayer stack 203 is the second layer 261. However, in other embodiments, the top layer of the multilayer stack 203 may be the first layer 251. Furthermore, although the embodiments described herein include three first layers 251 and three second layers 261, the multilayer stack 203 can aggregate any number of layers (e.g., nanosheets). For example, the multilayer stack 203 may contain multiple nanosheets, such as 2 to 10 nanosheets. In some embodiments, the multilayer stack 203 may include the same number of first layers 251 and second layers 261. However, in other embodiments, the number of first layers 251 may differ from the number of second layers 261.

[0097] In some embodiments, the first layer 251 of the multilayer stack 203 may have substantially the same thickness (e.g., the first thickness Th1, the third thickness Th3, and the fifth thickness Th5 are substantially the same), and the second layer 261 of the multilayer stack 203 may have substantially the same thickness (e.g., the second thickness Th2, the fourth thickness Th4, and the sixth thickness Th6 are substantially the same). However, the thicknesses of the first layer 251 may differ from each other, and / or the thicknesses of the second layer 261 may differ from each other. Any suitable thickness may be used.

[0098] like Figure 2 Some of the embodiments shown are patterning processes 350 of multilayer active devices 200 in an intermediate stage of manufacturing a fully wound gate transistor. The patterning process may employ an oxide definition step to transfer the desired shape (such as an L-shaped pattern) into the multilayer stack 203 and the substrate 101.

[0099] In some embodiments, once the multilayer stack 203 is formed on the substrate 101, the multilayer stack 203 and the substrate 101 can be patterned to a desired shape (e.g., L-shape). The patterning process may first form a first hard mask 205 and a second hard mask 207 on the first hard mask 205. The first hard mask 205 includes a dielectric material such as silicon oxide, silicon nitride, titanium nitride, silicon oxynitride, combinations thereof, or the like. The formation process of the first hard mask 205 may be chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar processes. However, any other suitable materials and formation methods may be used. The thickness of the first hard mask 205 may be between approximately to approximately Between, for example, about

[0100] The second hard mask 207 comprises various dielectric materials such as silicon nitride, silicon oxide, titanium nitride, silicon oxynitride, combinations thereof, or similar materials. The formation process of the second hard mask 207 can be chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or similar processes. However, any other suitable materials and formation methods can be used. The thickness of the second hard mask 207 can be approximately [missing information - likely related to thickness]. to approximately Between, for example, about

[0101] Once the first hard mask 205 and the second hard mask 207 are formed, they can be patterned. In one embodiment, the patterning method for the first hard mask 205 and the second hard mask 207 may involve first placing a photoresist (not shown) on the second hard mask and exposing the photoresist with a patterning energy source (such as light, e.g., extreme ultraviolet light) to initiate a chemical reaction, which can adjust the physical properties of the exposed portion of the first photoresist. Then, a first developer (not shown) is applied, which can develop the first photoresist and utilize the difference in physical properties between the exposed and unexposed areas to selectively remove the exposed or unexposed areas.

[0102] Once the photoresist is patterned, it can be used as a mask to pattern the underlying second hard mask 207 and the first hard mask 205. In one embodiment, the method for patterning the second hard mask 207 and the first hard mask 205 may employ photoresist as a mask and one or more reactive ion etching processes. The patterning process can continue until the multilayer stack 203 beneath the first hard mask 205 is exposed.

[0103] Once the first hard mask 205 and the second hard mask 207 are patterned, the photoresist can be removed from the second hard mask 207. In one embodiment, the photoresist can be removed using an ashing process, i.e., raising the photoresist temperature until the photoresist thermally decomposes, and the thermally decomposed photoresist can be easily removed using one or more cleaning processes. However, any other suitable removal process can be used.

[0104] In the oxide definition step, a first hard mask 205 and a second hard mask 207 are used as masks, and one or more etching processes, such as anisotropic etching processes (e.g., reactive ion etching), can be performed to transfer the mask pattern (e.g., an L-shaped pattern) to the underlying layer to form fins 122 in the multilayer stack 203 and the substrate 101. Although the embodiment here uses an L-shaped pattern to transfer the multilayer stack 203 and the substrate 101 to form fins 122, any suitable pattern shape can be used, as detailed below. Furthermore, the oxide definition step can employ any suitable etching process and any suitable number of etching processes to form fins 122 in the multilayer stack 203 and the substrate 101.

[0105] Furthermore, although the steps for forming fins 122 are described as a single masking process, this description is illustrative only and not intended to limit the embodiments. The patterning method for the fully wrapped gate transistor structure can be any suitable method, and any suitable number of fins can be formed in the multilayer stack 203 and the substrate 101. For example, one or more photolithography processes (including dual patterning or multi-patterning processes) can be used to pattern the structure to form a plurality of fins 122 in the same L-shape or any other suitable shape. Generally, dual patterning or multi-patterning processes combine photolithography with self-alignment processes, resulting in a pattern spacing smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers can be formed along the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fins 122 are patterned in the multilayer stack 203 and the substrate 101 using the remaining spacers.

[0106] like Figure 3 As shown, after the fin 122 is formed, a shallow trench isolation region 135 may be formed. In one embodiment, the shallow trench isolation region 135 may be formed by depositing a dielectric material such as an oxide material (e.g., a flowable oxide), a high-density plasma oxide, or the like. After cleaning and padding steps, a dielectric material may be formed to fill or overfill the area around the fin 122, and this can be achieved using chemical vapor deposition (e.g., high aspect ratio process), high-density plasma chemical vapor deposition, or other suitable methods.

[0107] Once deposited, excess dielectric material in the shallow trench isolation region 135 can be removed by a suitable process, such as chemical mechanical polishing, etching, a combination of the above, or similar processes. In one embodiment, the removal process can remove any dielectric material on the fin 122 and expose the surface of the fin 122 for subsequent processing steps.

[0108] After removing excess dielectric material from the shallow trench isolation region 135, the dielectric material can then be recessed from the surface of the fin 122 to form the shallow trench isolation region 135. The recessing step can be performed to expose at least a portion of the sidewalls of the fin 122 adjacent to the upper surface of the fin 122. The method for recessing the dielectric material of the shallow trench isolation region 135 can employ wet etching, such as immersing the upper surface of the fin 122 in an etchant selective for the dielectric material. Other methods such as reactive ion etching, dry etching, chemical oxide removal, or dry chemical cleaning can also be used. In some embodiments, the dielectric material can be recessed below the bottom layer of the first layer 251 to expose some of the substrate 101.

[0109] Figure 3The active region 301 of the fin 122 is also shown, and the fin 122 has a first length L1 between the L-shaped corners 303. In some embodiments, the first length L1 may be between about 8 nm and about 30 nm, such as about 10 nm. However, any suitable length may be used.

[0110] At the distal end of the active region 301, the fin 122 has a different first width W1 and a second width W2. In some embodiments, the second width W2 is smaller than the first width W1, but the second width W2 may also be larger than the first width W1. The first width W1 may be between about 8 nm and about 50 nm, for example, about 30 nm. The second width W2 may be between about 8 nm and about 50 nm, for example, about 10 nm. In some embodiments, the difference between the first width W1 and the second width W2 may be between about 2 nm and about 16 nm, for example, about 10 nm. The first ratio R1 of the first width W1 to the second width W2 may be between about 4:1 and about 1.5:1, for example, about 3:1. However, any suitable width and any suitable ratio may be used.

[0111] like Figure 4 As shown, a dummy gate stack 129 is formed on the active region 301 and between the L-shaped corners 303 in the fin 122. In some embodiments, the dummy gate stack 129 includes a dummy gate dielectric layer 119, a dummy gate 121 on the dummy gate dielectric layer 119, a third hard mask 123 on the dummy gate 121, and a fourth hard mask 125 on the third hard mask 123. Figure 4 It is also shown that the left interface between the dummy gate stack 129 and the active region 301 has a third width W3, and the right interface between the dummy gate stack 129 and the active region 301 has a fourth width W4.

[0112] In one embodiment, the dummy gate dielectric layer 119 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art for forming a gate dielectric layer. The thickness of the dummy gate dielectric layer 119 on the top of the fin 122 may differ from the thickness of the dummy gate dielectric layer 119 on the sidewalls of the fin 122, depending on the technique used to form the gate dielectric layer. The material of the dummy gate dielectric layer 119 may comprise silicon oxide or silicon oxynitride, and its thickness may be approximately [missing information]. to approximately For example, about In one embodiment, the dummy gate dielectric layer 119 may be formed by first depositing a sacrificial layer material, such as silicon, to provide sidewall protection. Once the sacrificial layer is formed, it may be oxidized or nitrided and consumed to form a dielectric layer, such as silicon oxide or silicon oxynitride. However, any suitable process may be used.

[0113] In other embodiments, the dummy gate dielectric layer 119 may also be a material with a high dielectric constant (greater than about 5), such as lanthanum oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, or a combination thereof, and its equivalent oxide thickness may be about [missing information]. to approximately For example, less than or equal to approximately In addition, any combination of silicon oxide, silicon oxynitride, and / or high dielectric constant materials may be used as the dummy gate dielectric layer 119.

[0114] The dummy gate 121 may comprise a conductive material such as polysilicon, tungsten, aluminum, copper, aluminum-copper, titanium, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or similar materials. The deposition method for the dummy gate 121 may be chemical vapor deposition, sputtering deposition, or other techniques known in the art for depositing conductive materials. The thickness of the dummy gate 121 may be approximately [missing information - likely a number]. to approximately The dummy gate 121 may have a non-flat upper surface, and the upper surface of the dummy gate 121 may be planarized before patterning or etching the gate. Ions can then be introduced into the dummy gate 121. For example, the method for introducing ions may be ion implantation technology.

[0115] Once the dummy gate dielectric layer 119 and the dummy gate 121 are formed, they can be patterned. In one embodiment, the patterning step first forms a third hard mask 123 and a fourth hard mask 125 on the third hard mask 123. The methods for forming the third hard mask 123 and the fourth hard mask 125 can employ any materials and processes suitable for forming the first hard mask 205 and the second hard mask 207, respectively. In some embodiments, the third hard mask 123 is a silicon oxide layer with a thickness between approximately to approximately Between, for example, about In some embodiments, the fourth hard mask 125 may be a silicon nitride layer with a thickness of approximately to approximately Between, for example, about However, any suitable material and thickness can be used.

[0116] Once the third hard mask 123 and the fourth hard mask 125 are formed, the fourth hard mask 125 can be patterned using any material (such as photoresist) and process (such as exposure and development of photoresist, reactive ion etching, or similar processes) suitable for patterning the first hard mask 205 and the second hard mask 207, as described above. The patterning process can continue until the dummy gate 121 under the third hard mask 123 is exposed.

[0117] Once the third hard mask 123 and the fourth hard mask 125 are patterned, the photoresist can be removed from them using an ashing process. However, any other suitable removal process can be used. Using the third hard mask 123 and the fourth hard mask 125 as masks, and employing an anisotropic etching process (such as reactive ion etching), the pattern of the third hard mask 123 and the fourth hard mask 125 can be transferred to the dummy gate 121 and the dummy gate dielectric layer 119 to form a dummy gate stack 129 on the fin 122. However, any suitable process can be used to transfer the pattern onto the dielectric layer, such as the aforementioned method using the first hard mask 205 and the second hard mask 207.

[0118] Once the dummy gate stack 129 is formed, the upper surface and sidewalls of the unprotected multilayer stack 203 and the upper surface of the shallow trench isolation region 135 are exposed. In one embodiment, the dummy gate stack 129 may cover a dummy gate width W. dg A portion of the multilayer stack 203 (less than the first length L1), and the dummy gate width W dg The width is between approximately 8 nm and approximately 16 nm (e.g., approximately 10 nm). In this way, the dummy gate can form a left interface and a right interface with the multilayer stack 203. In some embodiments, the third width W3 of the active region 301 at the left interface can be between approximately 28 nm and approximately 34 nm (e.g., 30 nm), while the fourth width W4 of the active region 301 at the right interface can be between approximately 8 nm and approximately 12 nm (e.g., approximately 10 nm). However, any suitable width can be used.

[0119] like Figure 5 In some embodiments shown, a compliant dielectric layer 130 is formed. In the initial step of forming the gate spacer 131 used for the gate 1103, the compliant dielectric layer 130 is deposited on the dummy gate stack 129, the fin 122, and the shallow trench isolation region 135. Thus, the compliant dielectric layer 130 is formed on both sides of the dummy gate stack 129 along the sidewalls of the dummy gate dielectric layer 119, the dummy gate 121, the third hard mask 123, and the fourth hard mask 125. The compliant dielectric layer 130 is also formed on both sides of the fin 122 along the sidewalls of the first layer 251 and the second layer 261, and on any exposed portion of the substrate 101. The L-shaped corners 303 and portions of the active region 301 in the fin 122 are located below the compliant dielectric layer 130 and are therefore not shown. Figure 5 .

[0120] In some embodiments, a compliant dielectric layer 130 may be deposited on the multilayer active device 200 in a blanket manner. The compliant dielectric layer 130 may comprise silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, or silicon carbonitride, but may also employ any suitable material such as a low dielectric constant material with a dielectric constant less than about 4.0, even an air gap, or a combination thereof. The compliant dielectric layer 130 may be formed by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering, or any other suitable method.

[0121] Figure 6 The horizontal surface of the compliant dielectric layer 130 is etched to form a gate spacer 131 on the dummy gate stack 129. In one embodiment, the gate spacer 131 may be formed using an anisotropic etching process such as reactive ion etching. While the gate spacer 131 described may be a single layer such as the compliant dielectric layer 130, this is merely illustrative and not limiting to the embodiments disclosed herein. Instead, any number of layers and any combination of deposition and removal processes may be used, and all of these processes are entirely within the scope of the embodiments. Once the horizontal surface of the compliant dielectric layer 130 is removed, the gate spacer 131 and the unprotected fourth hard mask 125, fins 122, and the top surface of the shallow trench isolation region 135 of the dummy gate stack 129 are exposed.

[0122] Once the gate spacer 131 is formed, a trench 133 can be etched through the fin 122. The etching process used removes material from the fin 122 exposed on both sides of the dummy gate stack 129 and not protected by the sidewalls of the gate spacer 131. In some embodiments, one or more anisotropic etching passes, such as reactive ion etching, can be used to etch the trench 133 through the fin 122, and its size can be the size of the etched portion of the fin 122.

[0123] In some embodiments, a first trench is formed on the left side of the dummy gate stack 129, having a first width W1 at the distal end of the trench 133 extending from the exposed sidewall of the fin 122, and a fifth width W5 at the exposed sidewall of the fin 122. The fifth width W5 is less than or equal to the first width W1 (e.g., between about 8 nm and about 50 nm, such as about 30 nm), and greater than the third width W3 (e.g., between about 8 nm and about 50 nm, such as about 28 nm). However, any suitable width may be used.

[0124] In some embodiments, a second trench is formed on the right side of the dummy gate stack 129, having a second width W2 at the distal end of the trench 133 extending from the exposed sidewall of the fin 122, and a sixth width W6 at the exposed sidewall of the fin 122. The sixth width W6 is greater than or equal to the second width W2 (e.g., between about 8 nm and about 50 nm, such as about 10 nm) and less than the fourth width W4 (e.g., between about 8 nm and about 50 nm, such as about 20 nm). However, any suitable width may be used.

[0125] like Figure 7 As shown, a first inner spacer 501 is formed in the first layer 251 of the first device region 106 (see...). Figure 6 In the first device region 106, a first inner spacer 501 is formed in a recess of the first layer 251. In some embodiments, the first inner spacer 501 is formed by wet etching to pattern the recess, and the etchant used in the wet etching is selective for the material of the first layer 251 (such as silicon-germanium) without significantly removing the material of the second layer 261 or the substrate 101 (such as silicon). For example, in an embodiment where the first layer 251 is silicon-germanium and the second layer 261 is silicon, the etchant used in the wet etching may be hydrogen chloride.

[0126] In one embodiment, the wet etching process can be an immersion process, a spray process, a spin process, or a similar process. Furthermore, the temperature of the wet etching process can be between about 400°C and about 600°C, and the duration can be between about 100 seconds and about 1000 seconds (e.g., about 300 seconds). However, any suitable process conditions and parameters can be used. A continuous etching process is used, such that the length of the recess with a crystal plane-constrained surface formed in each of the first layers 251 is between about 4 nm and about 8 nm, e.g., about 6 nm. However, any suitable length can be used.

[0127] However, wet etching is not the only process that can be used. For example, another embodiment of the method for patterning the first layer 251 may be an isotropic dry etching process or a combination of dry etching and wet etching processes. Any suitable process can be used to pattern the first layer 251, and all of these processes are entirely within the scope of the embodiments.

[0128] Once formed in each of the first layers 251 recessed in the first device region 106, spacer material can be formed on the first device region 106. In some embodiments, the spacer material may differ from the gate spacer 131 material, and the spacer may be a silicon-containing dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, or silicon carbonitride, or any suitable material such as a low dielectric constant material (even an air gap) with a dielectric constant less than about 4.0, or a combination thereof. The deposition process of the spacer material may be chemical vapor deposition, physical vapor deposition, or atomic layer deposition to achieve a thickness of about 3 nm to about 10 nm, such as about 5 nm. However, any suitable thickness or deposition process may be used.

[0129] By depositing spacer material onto the first device region 106, the spacer material can line the sidewalls of the trench 133 and fill the recesses in the first layer 251 of the first device region 106. Once the spacer material has filled the recesses, a removal process is then performed to remove excess spacer material from the trench 133 in the first device region 106, leaving the first inner spacer 501 in the first device region 106. In one embodiment, the method for removing excess spacer material may employ an etching process such as an anisotropic dry etching process, such as a reactive ion etching process. However, any suitable etching process may be used to remove excess spacer material from the trench 133 and leave the first inner spacer 501 and other inner spacers.

[0130] In this way, the first inner spacer 501 will adopt a first recessed shape. Furthermore, although the first inner spacer formed in the described embodiment has a crystal plane shape, this is illustrative and not limiting. Instead, any shape can be adopted, such as a recessed or protruding shape, or even formed within the first inner spacer 501. These shapes are entirely within the scope of the embodiments.

[0131] like Figure 8As shown, a source / drain region 601 is formed in the first device region 106. Based on the different widths (e.g., a first width W1, a second width W2, a third width W3, a fourth width W4, a fifth width W5, and a sixth width W6) of the right and left sides of the active region 301, the source / drain region 601 has an unbalanced width. For example, in some embodiments, the source / drain region 601 located on the left side of the dummy gate stack 129 may have a seventh width W7, and the source / drain region 601 located on the right side of the dummy gate stack 129 may have an eighth width W8, with the seventh width W7 being greater than the eighth width W8. In some embodiments, the seventh width W7 of the source / drain region 601 located on the left side of the dummy gate stack 129 may be between about 8 nm and about 50 nm (e.g., about 30 nm), and the eighth width W8 of the source / drain region 601 located on the right side of the dummy gate stack 129 may be between about 8 nm and about 50 nm (e.g., about 10 nm).

[0132] In one embodiment, the source / drain region 601 may be formed by first protecting other device regions with photoresist or other masking materials. Once the other device regions are protected, a growth process such as selective epitaxy can be used to form the semiconductor material required for the device, thereby forming the source / drain region 601. For example, one embodiment uses the source / drain region 601 to form an n-type metal-oxide-semiconductor device, and the source / drain region 601 may be a semiconductor material such as silicon, silicon phosphide, silicon carbide, a combination thereof, or the like. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, or the like, and may last from about 5 minutes to about 120 minutes (e.g., about 30 minutes). In some embodiments, the first source / drain height SDH1 of the source / drain region 601 is between about 30 nm and about 90 nm, for example, about 60 nm. However, any suitable height and / or suitable depth may be used.

[0133] Once the source / drain region 601 is formed, suitable dopants are planted to supplement the dopant in the remaining portion of the first device region 106, i.e., dopants are planted into the source / drain region 601. For example, n-type dopants such as phosphorus, carbon, arsenic, silicon, antimony, tungsten-like substances, or combinations thereof (such as silicon phosphide, silicon carbide, silicon carbide phosphide, silicon arsenide, silicon, antimony, or similar substances) can be planted to form an n-type metal-oxide-semiconductor device. These dopants can be planted using a dummy gate stack 129 and gate spacers 131 as a mask.

[0134] In another embodiment, the source / drain region 601 may be doped with a dopant during the growth of the source / drain region 601. For example, phosphorus may be doped in situ during the formation of the source / drain region 601. Any suitable process may be used to place the dopant into the source / drain region, and all such processes are fully encompassed within the scope of this embodiment. Furthermore, an annealing process may be performed to activate the dopant in the source / drain region.

[0135] exist Figure 9 In the middle, the contact etch stop layer 87 is deposited. Figure 8 The structure shown. The contact etch stop layer 87 may comprise a dielectric material containing silicon, nitrogen, and additional elements such as carbon, such as silicon carbonitride. In some embodiments, the contact etch stop layer 87 comprises a dielectric material such as silicon oxide, silicon nitride, any other suitable dielectric material, or the like. However, any suitable material may be used.

[0136] The dielectric material (such as silicon carbonitride) of the conformally deposited contact etch stop layer 87 is in Figure 8 The source / drain region 601, the fourth hard mask 125, and the gate spacer 131 of the structure shown are illustrated. In some embodiments, the contact etch stop layer 87 may be formed using a chemical vapor deposition process, but any suitable deposition process may also be used.

[0137] Figure 9 It is also shown that the interlayer dielectric layer 701 is deposited on the contact etch stop layer 87. The interlayer dielectric layer 701 may be composed of a dielectric material, and its deposition method may be any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. Other insulating materials formed using any acceptable process may also be used.

[0138] like Figure 9 As shown, a planarization process, such as chemical mechanical polishing, can be performed to make the upper surface of the interlayer dielectric layer 701 flush with the upper surfaces of the dummy gate 121, the gate spacer 131, and the contact etch stop layer 87. In this way, the planarization process also removes the third hard mask 123 and the fourth hard mask 125, exposing the upper surface of the dummy gate 121 between the gate spacers 131. After the planarization process, the dummy gate 72, the gate spacer 131, and the upper surface of the interlayer dielectric layer 701 are flush. In some embodiments, the third hard mask 123 (or a portion of the third hard mask 123) may remain on the upper surface of the gate 121 to be placed, and in this example, the planarization process makes the upper surfaces of the interlayer dielectric layer 701, the gate spacer 131, and the contact etch stop layer 87 flush with the upper surface of the third hard mask 123.

[0139] like Figure 10 As shown, remove any remaining portions (if any) of the dummy gate 121, dummy gate dielectric layer 119, and third hard mask 123. This exposes the central portion of the active region 301 in the opening 1033 between the gate spacers 131, while the gate spacers 131 retain coverage of the L-shaped corner 303 in the fin 122 and the rest of the active region 301. Figure 10 The phantom of the gate spacer 131 is also shown to show that the distal end of the second layer 261 and the first inner spacer 501 are embedded in the gate spacer 131, and to show that the first inner spacer 501 separates the distal ends of the second layer 261 from each other.

[0140] In one embodiment, the material of the third hard mask 123 may be removed using an etching process or a planarization process (such as continuing the aforementioned chemical mechanical polishing process) to remove the remainder of the third hard mask 123. However, any suitable method may be used to remove the third hard mask 123. Once the third hard mask 123 is removed, the dummy gate 121 is exposed and can then be removed. In one embodiment, the removal of the dummy gate 121 may employ one or more wet etching processes or dry etching processes, using etchants that are selective to the material of the dummy gate 121. However, any suitable removal process may be used. Once the dummy gate 121 is removed, the dummy gate dielectric layer 119 is exposed and can also be removed. In one embodiment, the dummy gate dielectric layer 119 may be removed using one or more dry etching processes or wet etching processes, using etchants that are selective to the dummy gate dielectric layer 119. In this way, the upper surface of the shallow trench isolation region 135, the upper surface of the top layer of the second layer 261, the side of the first layer 251, the side of the second layer 261, the side of the substrate 101 (above the shallow trench isolation region 135), and the side of the gate spacer 131 are exposed in the central part of the active region 301.

[0141] Figure 11 The circuit release process steps are shown. The circuit release process steps can also be considered as sheet release process steps, sheet formation process steps, nanosheet formation process steps, or circuit formation process steps. Once the dummy gate dielectric layer 119 is removed and the sides of the first layer 251 are exposed, the first layer 251 can be removed from between the substrate 101 and the second layer 261 in the first device region 106. In one embodiment, the removal method of the first layer 251 can be a wet etching process, which selectively removes the material of the first layer 251 (such as silicon-germanium) and substantially does not remove the material of the substrate 101 and the second layer 261 (such as silicon). However, any suitable removal process can be used. In one embodiment, the etchant can be high-temperature hydrogen chloride. Furthermore, the temperature of the wet etching process can be between about 400°C and about 600°C (e.g., about 560°C), and the time can be between about 100 seconds and about 600 seconds (e.g., about 300 seconds). However, any suitable etchant, process parameters, and time can be used.

[0142] By removing the material of the first layer 251, the material of the second layer 261 (e.g., nanosheets) will form nanostructures 901 in the first device region 106, and the nanostructures 901 are spaced apart by first inner spacers 501. The nanostructures 901 are stretched between the source / drain regions 601 on both sides (e.g., ...). Figure 8 (as shown), and together they form a channel region stack for the fully wrapped gate transistor in region 106. In one embodiment, the thickness of nanostructure 901 is the same as the original thickness of the second layer 261.

[0143] However, in other embodiments, the etching process can be used to reduce the thickness of a portion of the nanostructure 901, so that the thickness of the nanostructure 901 varies with its width. Specifically, the thickness of the nanostructure 901 may be about 0.3 nm to about 2 nm thinner than the original thickness of the second layer 261 (e.g., silicon). For example, during the line release step and the formation of the gate dielectric layer 1101, the thickness of each second layer 261 may undergo some silicon loss and / or oxidation. As a result, the thickness of each nanostructure 901 (and the central portion of the active region 301) is between about 4 nm and about 8 nm (e.g., about 5 nm), separated from the original space (e.g., the first thickness Th1, the second thickness Th2, and the third thickness Th3) plus additional space (e.g., about 0.3 nm to about 2 nm), and the additional space comes from the silicon loss and / or oxidation that occur during the line release process and the formation of the gate dielectric layer 1101. However, during the line release step and the formation of the gate dielectric layer 1101, the gate spacer 131 maintains the protection of the L-shaped corner 303 and other parts of the active region 301 in the fin 122. In summary, the L-shaped corner 303 and other parts of the active region 301 in the fin 122 protected by the gate spacer 131 can maintain their original thickness.

[0144] In addition, although Figure 11 Three nanostructures 901 are shown, but any suitable number of nanostructures 901 can be formed from the nanosheets provided by the multilayer stack 203. For example, the multilayer stack 203 (see...) Figure 1 The multilayer stack 203 may contain any suitable number of first layers 251 (such as first nanosheets) and any suitable number of second layers 261 (such as second nanosheets). In this way, a multilayer stack 203 containing fewer first layers 251 and fewer second layers 261, after removing the first layer 251, forms one or two nanostructures 901, such as a channel region stack of a fully wound gate transistor to be formed in the first device region 106. In this way, a multilayer stack 203 containing many first layers 251 and many second layers 261, after removing the first layer 251, may form four or more nanostructures 901, such as a channel region stack of a fully wound gate transistor to be formed in the first device region 106. Figure 11 It also shows the central region of the active region 301 that will be exposed, while the gate spacer 131 maintains the protection of the L-shaped corner 303 in the fin 122 and the other parts of the active region 301.

[0145] like Figure 12In some embodiments shown, a gate dielectric layer 1101 is formed in the first device region 106. The gate dielectric layer 1101 is formed around the nanostructure 901 once a release process step is performed and the nanostructure 901 is exposed. In some embodiments, prior to forming the gate dielectric layer 1101, a first interface layer (not shown) may be formed to surround the gate spacers 131, nanostructure 901, substrate 101, and exposed surfaces of the shallow trench isolation region 135 in the opening 1033 between the gate spacers 131, and to cover the gate spacers 131, the contact etch stop layer 87, and the upper surface of the interlayer dielectric layer 701. In some embodiments, the first interface layer may comprise a buffer material such as silicon oxide, but any suitable material may also be used. The first interface layer may be formed around the nanostructure 901 in the first device region 106, and the formation process may employ chemical vapor deposition, physical vapor deposition, or oxidation to achieve approximately to approximately The thickness, for example, about However, any suitable process or thickness can be used.

[0146] In one embodiment, the gate dielectric layer 1101 is a high-dielectric-constant dielectric material such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, aluminum oxide, combinations thereof, or the like, and its deposition process can be atomic layer deposition, chemical vapor deposition, or similar processes. The thickness of the gate dielectric layer 1101 can be between about 1 nm and about 3 nm, but any suitable material and thickness can be used. As shown, the gate dielectric layer 1101 covers the nanostructure 901, thus isolating the channel region stack of the fully wound gate transistor in the first device region 106. In some embodiments, a nitrogen-doped dielectric material (not shown) may be formed first, as detailed below, before the metal contact material forming the gate is applied to the gate dielectric layer 1101.

[0147] Figure 13A In some embodiments shown, the gate 1103 used to form the L-shaped fully wound gate transistor 1300 is located in the first device region 106. Figure 13A The diagram uses a phantom image to represent the gate 1103, gate spacer 131, contact etch stop layer 87, and interlayer dielectric layer 701 to illustrate these structures embedded in an L-shaped fully wound gate transistor 1300. For example, portions of the active region 301, source / drain region 601, nanostructure 901, first inner spacer 501, and gate dielectric layer 1101 embedded in the gate 1103, gate spacer 131, contact etch stop layer 87, and interlayer dielectric layer 701 can be considered as an L-shaped fully wound gate transistor 1300, as... Figure 13A As shown. Figure 13AThe seventh width W7 of the source / drain region 601 on the left side of the L-shaped fully wound gate transistor 1300 and the eighth width W8 of the source / drain region 601 on the right side of the L-shaped fully wound gate transistor 1300 are also shown.

[0148] Once the gate dielectric layer 1101 is formed around the nanostructure 901, the gate 1103 can be formed on the gate dielectric layer 1101 and fill the remaining space of the opening 1033 between the gate spacers 131. In one embodiment, the gate 1103 is multilayered, and the method of sequentially depositing each layer can employ a highly compliant deposition process such as atomic layer deposition, but any suitable deposition process can be used. In this way, the multilayer used to form the gate 1103 fills the reserved open regions between the channel regions stacked between the gate dielectric layers 1101 and fills other reserved open regions in the opening 1033. In some embodiments, the gate 1103 may include a capping layer, a barrier layer, an n-type metal work function layer, a p-type metal work function layer, and a filler material (not shown separately).

[0149] A capping layer may be formed adjacent to the gate dielectric layer 1101, and the capping layer may be composed of metallization materials such as tantalum nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicates, zirconium aluminate, combinations thereof, or similar materials. The deposition process of the metallization material may employ atomic layer deposition, chemical vapor deposition, or similar processes, but any suitable deposition process may also be used.

[0150] A barrier layer may be formed adjacent to the capping layer, and the materials of the barrier layer and the capping layer may be different. For example, the barrier layer may be one or more metallized materials such as titanium nitride, tantalum nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar materials. The barrier layer may be deposited using atomic layer deposition, chemical vapor deposition, or similar processes, but any suitable deposition process may be used.

[0151] In some embodiments, the fully wound gate transistor formed in the first device region 106 may be a first-type fully wound gate transistor (e.g., an n-type metal-oxide-semiconductor transistor). In this way, an n-type metal work function layer can be formed adjacent to the barrier layer. In one embodiment, the material of the n-type metal work function layer may be tungsten, copper, aluminum copper, titanium aluminum carbide, titanium aluminum nitride, titanium aluminum, platinum, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, silver, aluminum, tantalum aluminum, tantalum aluminum carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type work function materials, or combinations thereof. For example, the deposition method of the first n-type metal work function layer may employ atomic layer deposition, chemical vapor deposition, or similar processes. However, any suitable materials and processes can be used to form the n-type metal work function layer.

[0152] A p-type metal work function layer can be formed adjacent to an n-type metal work function layer. In one embodiment, the composition of the first p-type metal work function layer may be a metallization material such as tungsten, aluminum, copper, titanium nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum, tantalum nitride, cobalt, nickel, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, tantalum silicide, nickel silicide, manganese, zirconium, zirconium silicide, ruthenium, aluminum copper, molybdenum, molybdenum silicide, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar. Furthermore, the deposition method of the p-type metal work function layer may be a deposition process such as atomic layer deposition, chemical vapor deposition, or similar processes, but any suitable deposition process may be used.

[0153] Once the p-type metal work function layer is formed, a filler material can be deposited to fill the remaining portion of opening 1033. In one embodiment, the filler material may be tungsten, aluminum, copper, aluminum-copper, tungsten, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or similar materials, and its formation method may employ deposition processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, plating, combinations thereof, or similar processes. However, any suitable material may be used.

[0154] Once the opening 1033 left by removing the dummy gate 121 is filled, the material of the gate 1103 in the first device region 106 can be planarized so that any material outside the opening left by removing the dummy gate 121 is removed. In a specific embodiment, the removal can be performed using a planarization process such as chemical mechanical polishing. However, any suitable planarization and removal process can be used.

[0155] Figure 13B Some embodiments are shown. Figure 13AA top view of the cross-section AA of the L-shaped fully wound gate transistor 1300. Specifically, Figure 13B The L-shaped fully wound gate transistor 1300 shows the gate 1103, gate spacer 131, and active region 301 in the channel region. Figure 13B The structure of the active region 301 in some embodiments is also shown, including corner 303, a seventh width W7 of the left source / drain region 601, an eighth width W8 of the right source / drain region 601, and a first length L1. For ease of illustration, the gate dielectric layer 1101 and the contact etch stop layer 87 are not shown.

[0156] like Figure 13B In some embodiments shown, the L-shaped fully wound gate transistor 1300 has a gate 1103 aligned with and directly located on the L-shaped active region 301, such that the corner 303 of the L-shape in the fin 122 is located below the gate 1103 at the interface between the stack of nanostructures 901 and the source / drain regions 601. Furthermore, Figure 13B The left side of the active area 301 (e.g., the width of the left channel) has a third width W3, while the right side of the active area 301 (e.g., the width of the right channel) has a fourth width W4, and the third width W3 is greater than the fourth width W4. Figure 13B It also shows the fifth width W5 of the left channel interface between the left distal end of the nanostructure 901 and the source / drain region 601, and the sixth width W6 of the right channel interface between the right distal end of the nanostructure 901 and the source / drain region 601.

[0157] These multilayer active devices 200 include L-shaped active regions, with one side of the active region 301 wider than the other side to provide energy-saving advantages (compared to an active region 301 with no difference in width on both sides). For example, the left channel width of the active region 301 of the L-shaped fully wound gate transistor 1300 is greater than the right channel width (e.g., the third width W3 > the fourth width W4) to provide energy-saving advantages (between about 6% and about 8%). Furthermore, the channel interfaces of the multilayer active devices 200 containing the L-shaped active regions 301 may be approximately the same as the channel widths of the active regions 301, for example, the fifth width W5 is approximately the same as the third width W3, and / or the sixth width W6 is approximately the same as the fourth width W4. In this way, the interface between the source / drain regions 601 and the stack of nanostructures 901 in the active regions 301 may have slight distortion or no distortion.

[0158] Figure 14A In another embodiment, Figure 13A A top view of the cross-section AA of the L-shaped fully wound gate transistor 1300. In some embodiments, Figure 14A and Figure 13BSimilar and displaying the same structure, the difference lies in Figure 14A The gate 1103, gate dielectric layer 1101 (not shown), and gate spacer 131 formed on the active region 301 are offset to the left by OS-L. For ease of illustration, the gate dielectric layer 1101 and the contact etch stop layer are not shown.

[0159] In some embodiments, the left offset OS-L is between about 0 nm and about 8 nm, which may be derived from the design of the offset photoresist mask or by employing measured stack offset. The left and right channel widths of the active region 301 are offset relative to each corner 303 to the left of the L-shaped corner 303 in the fin 122, and the offset distance is the left offset OS-L. In this way, the left corner 303 of the multilayer active device 200 is located below the gate 1103, while the right corner 303 of the multilayer active device 200 is located below the gate spacer 131 to the right of the right side of the active region 301.

[0160] In this way, the interface between the epitaxially grown source / drain region 601 on the right side of the multilayer active device 200 and the active region 301 can have a ninth width W9 (between about 8 nm and about 50 nm, for example, about 10 nm), while the interface between the gate 1103 and the right side of the active region 301 can have a tenth width W10 (between about 8 nm and about 50 nm, for example, about 12 nm). Similarly, on the opposite side of the active region 301, the interface between the epitaxially grown source / drain region 601 on the left side of the multilayer active device 200 and the active region 301 has a seventh width W7, while the interface between the gate 1103 and the left side of the active region 301 can have an eleventh width W11 (between about 8 nm and about 50 nm, for example, about 30 nm). However, any suitable dimensions can be used.

[0161] Figure 14B In another embodiment, Figure 13A A top view of a cross-section AA of the L-shaped fully wound gate transistor 1300. In some embodiments, Figure 14B and Figure 13B Similar and displaying the same structure, however Figure 14B The gate 1103, gate dielectric layer 1101 (not shown), and gate spacer 131 are formed on the active region 301 and offset to the right from OS-R. For simplicity, the gate dielectric layer 1101 and the contact etch stop layer 87 are not shown.

[0162] In some embodiments, the rightward offset from OS-R is between about 0 nm and about 8 nm, which may be derived from the design of the offset photoresist mask or by employing measured stack offset. The left and right channel widths of the active region 301 are offset to the right of the L-shaped corner 303 in the fin 122, and the offset distance is the rightward offset from OS-R. In this way, the left corner 303 of the multilayer active device 200 is located below the interlayer dielectric layer 701 or gate spacer 131 to the left of the active region 301, while the right corner 303 of the multilayer active device 200 is located below the gate 1103 to the left of the gate spacer 131 on the right side of the gate 1103.

[0163] In this way, the interface between the epitaxially grown source / drain region 601 on the right side of the multilayer active device 200 and the active region 301 can have an eighth width W8 (between about 8 nm and about 50 nm, for example, about 10 nm), while the interface between the gate 1103 and the right side of the active region 301 can have a twelfth width W12 (between about 8 nm and about 50 nm, for example, about 12 nm). Similarly, on the other side of the active region 301, the interface between the epitaxially grown source / drain region 601 on the left side of the multilayer active device 200 and the active region 301 can have a thirteenth width W13, while the interface between the gate 1103 and the left side of the active region 301 can have a fourteenth width W14 (between about 8 nm and about 50 nm, for example, about 28 nm). However, any suitable dimensions can be used.

[0164] Figures 15A to 15E The illustrations show various cell schemes containing multilayer active device arrays in some embodiments. Each cell scheme includes an array of multilayer active devices 1501 incorporating one or more L-shaped fully wound gate transistors 1300. The design flexibility and energy-saving advantages of the L-shaped fully wound gate transistors 1300 can be used in a large number of cell schemes to further achieve design flexibility and energy saving in different cell schemes.

[0165] like Figure 15A In some embodiments shown, a first cell configuration 1500 is formed using six L-shaped fully wound gate transistors 1300. In some embodiments, the first cell configuration 1500 includes a first fin 1522 (whose first composite shape includes three L-shaped active regions 301) and a second fin 1523 (whose second composite shape includes three L-shaped active regions 301), and the second composite shape is a mirror image of the first composite shape. The first fin 1522 and the second fin 1523 are formed in a multilayer stack 203 (not shown) and a substrate 101 (not shown) using the materials and processes described above for forming the fin 122. Furthermore, if one or more of the required gates 1103 can be replaced with dummy gates, this includes one or more of the gates 1103 located on the L-shaped active regions 301.

[0166] Figure 15B In some embodiments shown, a second cell configuration 1510 is formed using four L-shaped fully wound gate transistors 1300. The second cell configuration 1510 includes a third fin 1525 having a third composite shape including an L-shaped active region 301, and the third composite shape including an opening 1511 in a first fin 1522. The second cell configuration 1510 also includes a fourth fin 1527 having a second composite shape including three L-shaped active regions 301. In one embodiment, the first of the three L-shaped active regions 301 of the second fin 1523 has the same first active width as the L-shaped active region 301 of the first fin 1522. Furthermore, the other two of the three L-shaped active regions 301 of the fourth fin 1527 may have the same second active width (which is smaller than the first active width). In some embodiments, the first active width may be between about 8 nm and about 50 nm (e.g., about 30 nm), while the second active width may be between about 8 nm and about 50 nm (e.g., about 10 nm). The third fin 1525, the fourth fin 1527, the L-shaped active region 301, and the gate 1103 can be formed using any of the materials and processes described herein.

[0167] like Figure 15C In some embodiments shown, a third cell configuration 1520 is formed using four L-shaped fully wound gate transistors 1300. The third cell configuration 1520 includes a fifth fin 1529 having a fifth composite shape (including four L-shaped active regions 301), and a sixth fin 1531 having a sixth composite shape (including four L-shaped active regions 301). In some embodiments, the sixth composite shape may be a mirror image of the fifth composite shape, and the fin widths of the four L-shaped active regions 301 gradually decrease from the left to the right side of the fin. For example, the first fin width Wf1 of the L-shaped active regions 301 may be between about 8 nm and about 50 nm (e.g., about 40 nm), and the second fin width Wf2 may be between about 8 nm and about 50 nm (e.g., about 10 nm). The interval of fin width reduction may be between about 72 nm and about 102 nm, e.g., about 90 nm. The fifth fin 1529, the sixth fin 1531, the L-shaped active region 301, and the gate 1103 can be formed using any of the materials and processes described herein.

[0168] Figure 15DThis illustration shows a fourth cell configuration 1530 formed using five L-shaped fully wound gate transistors 1300. The fourth cell configuration 1530 includes a seventh fin 1533 (whose seventh composite shape includes two L-shaped active regions 301) and an eighth fin 1535 (whose eighth composite shape includes three L-shaped active regions 301). In this embodiment, the composite shapes may be offset from each other, so the seventh fin 1533 and the eighth fin 1535 are not mirror images of each other. The seventh fin 1533, the eighth fin 1535, the L-shaped active regions 301, and the gate 1103 can be formed using any of the materials and processes described herein.

[0169] Figure 15E In some embodiments, a fifth cell configuration 1540 is shown, formed using eight L-shaped fully wound gate transistors 1300. The fifth cell configuration 1540 includes a ninth fin 1537 of a ninth composite shape and a tenth fin 1539 of a tenth composite shape. The ninth composite shape includes four L-shaped active regions 301, and the tenth composite shape includes four L-shaped active regions 301. In some embodiments, the tenth composite shape may be a mirror image of the ninth composite shape, with adjacent gates 1103 each located on an L-shaped active region 301. The ninth fin 1537, the tenth fin 1539, the L-shaped active regions 301, and the gates 1103 may be formed using any of the materials and processes described herein.

[0170] In each embodiment described herein, the L-shaped fully wound gate transistor 1300 may be an n-type (n-type metal-oxide-semiconductor) fully wound gate transistor or a p-type (p-type metal-oxide-semiconductor) fully wound gate transistor. Furthermore, the embodiments described herein can be used with L-shaped fully wound gate transistors in both n-type and p-type field-effect transistor devices. In this way, the embodiments described herein can be used in many energy-efficient applications requiring high design flexibility.

[0171] The embodiments described herein relate to a multilayer active device 200 and its method of formation, which contains an active region 301 with a composite shape (such as an L-shape) in a nanostructure 901. In the embodiments, the active regions 301 have a nanostructure active length, such as a first length L1, between corners 303 of the active regions 301. The corners 303 are located below the gate spacers 131 of the active device. At the distal ends of the active regions 301, the nanostructure 901 has a different width. In some embodiments, the multilayer active device 200 has the advantage of energy saving of approximately 6% to 8% compared to an active device with an active region 301 having a non-composite shape. Furthermore, the design flexibility provided by the multilayer active device 200 can be used for many different configurations of the active device.

[0172] By forming and employing nanostructure 901 with an L-shaped active region 301 in the nanostructure of the multilayer active device 200, the short-channel device can achieve both high efficiency and energy saving. Furthermore, in different embodiments using design flexibility for different cell types, the L-shaped corner 303 of the fully wrapped gate device is located below the gate spacer 131 and / or the gate, as described herein.

[0173] In one embodiment, a method of forming a semiconductor device includes: depositing a first sheet on a semiconductor substrate; depositing a first semiconductor material on the first sheet; depositing a second sheet on the first semiconductor material; depositing a second semiconductor material on the second sheet; patterning the first sheet, the first semiconductor material, the second sheet, and the second semiconductor material into fins, the fins having a first width and a second width, wherein the first width is greater than the second width; removing the first sheet and the second sheet to form a first nanostructure from the first semiconductor material and a second nanostructure from the second semiconductor material; depositing a gate dielectric layer to surround the first nanostructure and the second nanostructure; and depositing a gate around the gate dielectric layer. In one embodiment, the step of depositing the gate includes at least partially forming the gate at a first corner of the first nanostructure. In one embodiment, after depositing the gate dielectric layer, a gate spacer is adjacent to the gate dielectric layer and at least partially located at a second corner of the first nanostructure, and the second corner is adjacent to a portion of a fin having a second width. In one embodiment, the step of depositing the gate includes at least partially forming the gate at a second corner of the first nanostructure. In one embodiment, after depositing the gate dielectric layer, a gate spacer is adjacent to the gate dielectric layer and at least partially located at a second corner of the first nanostructure, and the second corner is adjacent to a portion of a fin having a first width. In one embodiment, the method further includes epitaxially growing a first source / drain region adjacent to the first nanostructure, the first source / drain region having a third width; and epitaxially growing a second source / drain region adjacent to the first nanostructure, the second source / drain region having a fourth width, the fourth width being different from the third width. In one embodiment, the first width is between about 8 nm and about 30 nm.

[0174] In one embodiment, a method of forming a semiconductor device includes: forming a multilayer stack on a semiconductor substrate, the multilayer stack including a first layer of a first material and a second layer of a second material, wherein the first material and the second material are different; etching a pattern into the multilayer stack, the remainder of the multilayer stack including an active region, the active region separating a retained first side of the multilayer stack and a retained second side of the multilayer stack, the first side having a first width and the second side having a second width, wherein the first width and the second width are different; performing a line release process to remove the first layer and form a stack of nanostructures, wherein the stack of nanostructures has a first width on the first side and a second width on the second side; depositing a gate dielectric layer around the stack of nanostructures; and depositing a gate to surround each nanostructure in the stack of nanostructures. In one embodiment, the method further includes forming a first source / drain region adjacent to the first side of the stack of nanostructures, and forming a second source / drain region adjacent to the second side of the stack of nanostructures, wherein the width of the first source / drain region is greater than the width of the second source / drain region. In one embodiment, the difference between the first width and the second width is at most 8 nm. In one embodiment, a nanostructure in a stack of nanostructures includes a first corner on a first side, and the first corner is at least partially located under a gate. In one embodiment, a nanostructure includes a second corner on a second side, and the second corner is at least partially located under a gate. In one embodiment, a nanostructure includes a second corner on a second side, and the second corner is at least partially located under an interlayer dielectric layer, wherein a first width is greater than a second width. In one embodiment, a nanostructure includes a second corner on a second side, and the second corner is at least partially located under an interlayer dielectric layer, wherein a first width is less than a second width.

[0175] In one embodiment, the semiconductor device includes: a gate dielectric layer located on a substrate; a gate located around the gate dielectric layer; and a vertical stack of nanostructures, each nanostructure of the vertical stack including an active region surrounded by the gate dielectric layer, wherein each active region has a first channel width on a first side of the gate dielectric layer and a second channel width on a second side of the gate dielectric layer, and the first channel width is greater than the second channel width. In one embodiment, the difference between the first channel width and the second channel width does not exceed 16 nm. In one embodiment, the first nanostructure of the vertical stack includes a first corner on the first side of the gate dielectric layer and a second corner on the second side of the gate dielectric layer. In one embodiment, the semiconductor device further includes: a first gate spacer adjacent to the gate on the first side of the gate dielectric layer; and a second gate spacer adjacent to the gate on the second side of the gate dielectric layer. In one embodiment, the first corner is at least partially located under the first gate spacer, and the second corner is at least partially located under the gate. In one embodiment, the first corner is at least partially located under the gate, and the second corner is at least partially located under the second gate spacer.

[0176] The features of the above embodiments are beneficial to those skilled in the art in understanding this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the concept and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A first sheet-like material is deposited on a semiconductor substrate; A first semiconductor material is deposited on the first sheet; A second sheet is deposited on the first semiconductor material; A second semiconductor material is deposited on the second sheet; The first sheet, the first semiconductor material, the second sheet, and the second semiconductor material are patterned to form a fin. The fin includes an active separation between a first side and a second side of the fin. The upper surface of the fin has a first width and a second width in a top view, and the first width is greater than the second width. The first width is measured along a first direction, and the second width is measured along a second direction. The first direction is parallel to the second direction. The first width corresponds to the first side of the fin, and the second width corresponds to the second side of the fin. Remove the first sheet and the second sheet to form a first nanostructure from the first semiconductor material and a second nanostructure from the second semiconductor material, wherein the first nanostructure has the first width on the first side and the second width on the second side; Deposit a gate dielectric layer to surround the first nanostructure and the second nanostructure; and A gate is deposited around the gate dielectric layer.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the step of depositing the gate includes at least partially forming the gate at a first corner of the first nanostructure.

3. The method of forming a semiconductor device as claimed in claim 2, wherein after depositing the gate dielectric layer, a gate spacer is adjacent to the gate dielectric layer and at least partially located at a second corner of the first nanostructure, and the second corner is adjacent to a portion of the fin having the second width.

4. The method of forming a semiconductor device as claimed in claim 2, wherein the step of depositing the gate includes at least partially forming the gate on a second corner of the first nanostructure.

5. The method of forming a semiconductor device as claimed in claim 4, wherein after depositing the gate dielectric layer, a gate spacer is adjacent to the gate dielectric layer and at least partially located at a second corner of the first nanostructure, and the second corner is adjacent to a portion of the fin having the first width.

6. The method for forming a semiconductor device as claimed in claim 1, further comprising: A first source / drain region is epitaxially grown adjacent to the first nanostructure, and the first source / drain region has a third width; as well as A second source / drain region is epitaxially grown adjacent to the first nanostructure. The second source / drain region has a fourth width, which is different from the third width.

7. The method of forming a semiconductor device as claimed in claim 1, wherein the first width is between 8 nm and 30 nm.

8. A method for forming a semiconductor device, comprising: A multilayer stack is formed on a semiconductor substrate, the multilayer stack including a plurality of first layers of a first material and a plurality of second layers of a second material, wherein the first material and the second material are different; A pattern is etched into the multilayer stack, the retained multilayer stack including an active region that separates a first side and a second side of the retained multilayer stack, wherein the topmost surface of the retained multilayer stack has a first width and a second width in a top view, wherein the first width and the second width are different, wherein the first width is measured along a first direction and the second width is measured along a second direction, and the first direction is parallel to the second direction, wherein the first width corresponds to the first side of the retained multilayer stack and the second width corresponds to the second side of the retained multilayer stack; A linear release process is performed to remove the first layers and form a stack of multiple nanostructures, wherein the stack of nanostructures has the first width on the first side and the second width on the second side; A gate dielectric layer is deposited around the stack of these nanostructures; as well as A gate is deposited around each of the nanostructures in the stack.

9. The method of forming a semiconductor device as claimed in claim 8, further comprising forming a first source / drain region adjacent to the stack of the nanostructures on the first side, and forming a second source / drain region adjacent to the stack of the nanostructures on the second side, wherein the width of the first source / drain region is greater than the width of the second source / drain region.

10. The method of forming a semiconductor device as claimed in claim 8, wherein the difference between the first width and the second width is at most 8 nm.

11. The method of forming a semiconductor device as claimed in claim 8, wherein one of the nanostructures in the stack includes a first corner on the first side, and the first corner is at least partially located under the gate.

12. The method of forming a semiconductor device as claimed in claim 11, wherein the nanostructure includes a second corner on the second side, and the second corner is at least partially located below the gate.

13. The method of forming a semiconductor device as claimed in claim 11, wherein the nanostructure includes a second corner on the second side, and the second corner is at least partially located under an inter-dielectric layer, wherein the first width is greater than the second width.

14. The method of forming a semiconductor device as claimed in claim 11, wherein the nanostructure includes a second corner on the second side, and the second corner is at least partially located under an inter-dielectric layer, wherein the first width is smaller than the second width.

15. A semiconductor device, comprising: A gate dielectric layer is located on a substrate; A gate is located around the gate dielectric layer; A vertical stack of multiple nanostructures, each of the nanostructures in the vertical stack including an active region surrounded by the gate dielectric layer, wherein the topmost surface of each active region includes: The gate dielectric layer has a first channel width on a first side; as well as The gate dielectric layer has a second channel width on a second side, and the first channel width is greater than the second channel width, wherein the measurement direction of the first channel width is parallel to the measurement direction of the second channel width.

16. The semiconductor device of claim 15, wherein the difference between the width of the first channel and the width of the second channel is no more than 16 nm.

17. The semiconductor device of claim 15, wherein the vertically stacked first nanostructure of the nanostructures includes a first corner on the first side of the gate dielectric layer and a second corner on the second side of the gate dielectric layer.

18. The semiconductor device of claim 17, further comprising: A first gate spacer is adjacent to the gate on the first side of the gate dielectric layer; as well as A second gate spacer is adjacent to the gate on the second side of the gate dielectric layer.

19. The semiconductor device of claim 18, wherein the first corner is at least partially located under the first gate spacer, and the second corner is at least partially located under the gate.

20. The semiconductor device of claim 18, wherein the first corner is at least partially located under the gate, and the second corner is at least partially located under the second gate spacer.

21. A method for forming a semiconductor device, comprising: A first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are sequentially deposited on a semiconductor substrate; The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the semiconductor substrate are etched to form a fin, the upper surface of which is L-shaped in the top view; The first semiconductor layer and the second semiconductor layer are etched to form a first nanostructure from the second semiconductor layer; A gate dielectric layer is formed around the first nanostructure; and A gate is formed around the gate dielectric layer.

22. The method of forming a semiconductor device as claimed in claim 21, wherein the fin has a first width and a second width in a top view, wherein the measurement direction of the first width is parallel to the measurement direction of the second width, and wherein the difference between the first width and the second width is 2 nm to 16 nm.

23. The method of forming a semiconductor device as claimed in claim 22, wherein the ratio between the first width and the second width is 4:1 to 15:

1.

24. The method of forming a semiconductor device as claimed in claim 22, further comprising: A first source / drain region is formed to be adjacent to a first side of an active region of the fin, and the first side of the fin corresponds to the first width; as well as A second source / drain region is formed to be adjacent to a second side of an active region of the fin, and the second side of the fin corresponds to the second width.

25. The method of forming a semiconductor device as claimed in claim 24, wherein a third width of the first source / drain region is different from a fourth width of the second source / drain region, wherein the measurement direction of the third width is parallel to the measurement direction of the fourth width.

26. The method of forming a semiconductor device as claimed in claim 24, wherein the step of forming the gate includes forming the gate to overlap with a first corner portion of the first nanostructure, and the first corner of the first nanostructure is adjacent to a portion of the fin having the first width.

27. The method of forming a semiconductor device as claimed in claim 24, wherein the step of forming the gate includes forming the gate to overlap with a second corner portion of the first nanostructure, and the second corner of the first nanostructure is adjacent to a portion of the fin having the second width.

28. A method for forming a semiconductor device, comprising: A multilayer stack is deposited on a semiconductor substrate, the multilayer stack including a plurality of interleaved first layers and a plurality of second layers, wherein the materials of the first layers are different from the materials of the second layers; The multi-layered stack is patterned to form a fin, wherein the fin in the top view includes: One active zone; A first portion of the fin is adjacent to a first end of the active region; and A second portion of the fin is adjacent to a second end of the active region, wherein the active region is located between the first portion of the fin and the second portion of the fin, the first end of the active region has a first width, the second end of the active region has a second width, and the first width is different from the second width. Remove the first layers to form multiple nanostructures from the second layers; and A gate is deposited around each of these nanostructures.

29. The method of forming a semiconductor device as claimed in claim 28, further comprising: A first source / drain region is formed adjacent to the first end of the active region; as well as A second source / drain region is formed adjacent to the second end of the active region, and a third width of the first source / drain region is different from a fourth width of the second source / drain region, wherein the measurement direction of the third width is parallel to the measurement direction of the fourth width.

30. The method of forming a semiconductor device as claimed in claim 28, wherein the difference between the first width and the second width is 2 nm to 16 nm.

31. The method of forming a semiconductor device as claimed in claim 28, wherein a first nanostructure of the nanostructures includes a first corner at the first end of the active region, and the first corner is at least partially located below the gate, wherein the first width is greater than the second width.

32. The method of forming a semiconductor device as claimed in claim 31, wherein the first nanostructure includes a second corner at the second end of the active region, and the second corner is at least partially located under a first gate spacer.

33. The method of forming a semiconductor device as claimed in claim 28, wherein a second nanostructure of the nanostructures includes a third corner at the first end of the active region, the third corner being at least partially located under a second gate spacer, wherein the first width is greater than the second width.

34. The method of forming a semiconductor device as claimed in claim 33, wherein the second nanostructure includes a fourth corner at the second end of the active region, and the fourth corner is located only partially below the gate.

35. A semiconductor device, comprising: Multiple channel areas are located on a single substrate; A gate dielectric layer surrounds each of the channel regions, wherein the channel regions are stacked vertically. A gate is located around the gate dielectric layer; A first source / drain region is located on a first side of the gate; and A second source / drain region is located on a second side of the gate, wherein a first channel width of each of the channel regions on the first side is greater than a second channel width of each of the channel regions on the second side, wherein the measurement direction of the first channel width is parallel to the measurement direction of the second channel width.

36. The semiconductor device of claim 35, wherein the ratio between the first channel width and the second channel width is 4:1 to 15:

1.

37. The semiconductor device of claim 35, wherein a third width of the first source / drain region is greater than a fourth width of the second source / drain region, wherein the measurement directions of the third width and the fourth width are parallel to the measurement directions of the first channel width and the second channel width.

38. The semiconductor device of claim 35, wherein the difference between the first channel width and the second channel width is 2 nm to 16 nm.

39. The semiconductor device of claim 35, further comprising: A first gate spacer is adjacent to the first side of the gate; as well as A second gate spacer is adjacent to the second side of the gate, wherein the thickness of a portion of each of the channel regions between the first gate spacer and the second gate spacer varies in the direction from the first gate spacer toward the second gate spacer.

40. The semiconductor device of claim 35, wherein the width of the first channel and the width of the second channel are 8 nm to 50 nm.

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