Functional blocks implemented by 3D stacked integrated circuits

Abstract

The present invention provides a three-dimensional stacked integrated circuit (3D SIC), which has: a non-volatile memory die having a non-volatile memory partition array; a volatile memory die having a volatile memory partition array; and a processing logic die having a processing logic partition array. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form a functional block array, and at least two functional blocks can each include different data processing functions that reduce the amount of calculation of a controller.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. patent application serial number 16 / 169,910, filed on October 24, 2018, and entitled “Functional Blocks Implemented by 3D Stacked Integrated Circuit,” which is hereby incorporated herein by reference. Technical Field

[0003] At least some embodiments disclosed herein relate generally to three-dimensional integrated circuits (3D ICs), and more particularly, but not limited to, to three-dimensional stacked integrated circuits (3D SICs). Background Art

[0004] A 3D IC is an integrated circuit built by stacking silicon dies and interconnecting them vertically so that the combination of the dies is a single device. For a 3D IC, the electrical path through the device can be shortened by its vertical layout, which produces a device that can be faster and has a smaller footprint than similar ICs arranged side by side. 3D ICs can generally be grouped into 3D SICs, which refer to stacked ICs with through silicon via interconnects (TSVs), and monolithic 3D ICs, which are produced using a manufacturing process to implement 3D interconnects at the local level of the on-chip wiring hierarchy as stated by the International Technology Roadmap for Semiconductors (ITRS). Using a manufacturing process to implement 3D interconnects can produce direct vertical interconnects between device layers. Monolithic 3D ICs are built in layers on a single wafer that is cut into separate 3D ICs.

[0005] 3D SICs can be produced by three known general methods: a die-to-die method, a die-to-wafer method, or a wafer-to-wafer method. In the die-to-die method, electronic components are produced on multiple dies. Then, the dies are aligned and bonded. The benefit of the die-to-die method is that each die can be tested before being aligned and bonded to another die. In the die-to-wafer method, electronic components are produced on multiple wafers. Accordingly, one of the wafers can be cut and then aligned and bonded to the die sites of another wafer. In the wafer-to-wafer method, electronic components are produced on multiple wafers, then the multiple wafers are aligned, bonded, and cut into individual 3D ICs.

[0006] TSVs are vertical electrical connections that can pass through a die. TSVs can be a central part used to increase performance in 3D packaging and 3D ICs. Using TSVs, interconnect and device density can be substantially higher and the length of the connection can be shorter than alternatives for connecting stacked chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0008] Figure 1 An elevation view illustrating an example 3D SIC having multiple non-volatile memory dies, volatile memory dies, and processing logic dies according to some embodiments of the invention.

[0009] Figure 2 A top view of an example nonvolatile memory die having multiple nonvolatile memory partitions, each partition having multiple nonvolatile memory elements, is illustrated in accordance with some embodiments of the present invention.

[0010] Figure 3 A top view of an example volatile memory die having multiple volatile memory partitions, each partition having multiple volatile memory elements, is illustrated in accordance with some embodiments of the present invention.

[0011] Figure 4 A top view of an example processing logic die with multiple processing logic partitions, each partition having a separate field programmable gate array, is illustrated in accordance with some embodiments of the present invention.

[0012] Figure 5 A system having multiple non-volatile memory dies, volatile memory dies, and processing logic dies according to some embodiments of the present invention is described. Figure 1 A perspective view of the example 3D SIC illustrated in FIG.

[0013] Figure 6 A block diagram illustrating an example computer system in which embodiments of the invention may operate.

[0014] Figure 7 A flow chart illustrating an example method in which embodiments of the present invention may be performed in conjunction with a controller. DETAILED DESCRIPTION

[0015] At least some aspects of the invention relate to functional blocks implemented by a 3D SIC.Furthermore, aspects of the invention generally relate to functional blocks implemented by a 3D IC.

[0016] Generally speaking, a 3D IC is an integrated circuit manufactured by stacking silicon wafers or dies and interconnecting them in a first direction (e.g., vertically) using, for example, TSV or Cu-Cu connections so that they appear as a single device to achieve performance improvements with reduced power and a smaller footprint compared to conventional two-dimensional devices.

[0017] In some embodiments, TSVs may be used, which allows 3D IC embodiments to be considered 3D SICs. Embodiments that are 3D ICs or 3D SICs may be produced as heterogeneous, for example combining different memory type layers and / or one or more processing layers into a single IC stack. Alternative embodiments of 3D SICs may include monolithic 3D ICs.

[0018] Embodiments using monolithic 3D ICs are created in layers on a single semiconductor wafer, which is then cut into 3D ICs. These embodiments have the advantage that no alignment, thinning, bonding, or TSVs are required. Although the present invention focuses primarily on 3D SIC embodiments, it should be understood that the embodiments disclosed herein are not limited to 3D SIC embodiments. Some embodiments may be monolithic 3D ICs rather than 3D SICs. In such example embodiments, the overall structure of the 3D IC may be similar. However, the interconnects of the monolithic 3D IC include fabricated vias rather than TSVs.

[0019] With regard to producing 3D SIC embodiments, such embodiments may be produced by a die-to-die production method, a die-to-wafer production method, or a wafer-to-wafer production method. In the die-to-die method, thinning and TSV generation may be performed before or after bonding in the production method. An example advantage of the die-to-die method is that each component die may be tested before stacking each component die with other die. In addition, each die may be individually boxed for production. In the die-to-wafer method, thinning and TSV generation may be performed before or after bonding, similar to the wafer-to-wafer method. However, the advantage of die-to-wafer over wafer-to-wafer is that additional wafers may be added to the stack before cutting, and the die may be tested before adding the die to the wafer. In wafer-to-wafer, each wafer may be thinned before or after bonding, and connectors may be built into the wafer before bonding, or may be generated in the stack after bonding. For the wafer-to-wafer method, TSV may pass through the silicon substrate between the active layers and / or between the active layers and the external bonding pads. The disadvantage of the wafer-to-wafer method is that a defect in one chip causes a defect in the entire stack output of the method.

[0020] The chip scaling process has been slow to improve due in part to power density constraints, and interconnects are not getting faster, while transistors are generally getting faster. 3D ICs address two such example scaling issues by stacking two-dimensional dies and connecting them in the third dimension. This stacking may enable faster communication between chips compared to a horizontal arrangement of ICs. In addition, 3D ICs may offer other possible benefits compared to horizontally arranged chips, including: smaller footprint, shorter interconnects, reduced power consumption, circuit security through hiding, and increased bandwidth.

[0021] 3D ICs provide greater functionality into a smaller two-dimensional space by adding functionality in layers in the third dimension, and can save costs by dividing a large chip into multiple smaller dies with 3D stacking. In other words, 3D IC manufacturing can be more modular than the conventional process of producing chips with IC arrays. In addition, 3D ICs can be produced using layers produced by different processes or different types of wafers, which increases design options. In addition, the increased connectivity expands design options.

[0022] Another advantage is that 3D ICs reduce power consumption by keeping signals within the device. Shorter electrical connections in two different directions (eg, horizontally and vertically) also reduce power consumption by, for example, creating less parasitic capacitance. Reducing the power budget also results in less heat generation.

[0023] Furthermore, 3D ICs can achieve security through obscurity because the stacked die structure complicates attempts to reverse engineer the overall circuit. Furthermore, sensitive or critical functions can be divided among the layers of the 3D IC to further hide such functions. Some embodiments may even have layers or dies dedicated to monitoring or security of other layers. This is similar to a firewall layer, where the individual dies of the 3D IC provide a hardware firewall for the die to be monitored at runtime. Doing so can protect part of the chip or the entire stack from attack.

[0024] The basic structural arrangement of 3D ICs increases bandwidth by allowing a large number of vias between dies or layers, the combination of which can provide a bandwidth far greater than that of a conventional bus. In addition, a set of functional blocks of a 3D SIC can act as a group of networked or clustered individual computers. Different functional blocks can have different types of processing units. Moreover, different types of functional blocks can be complementary. Moreover, the more related a functional block is to another block, the more advantageous it is to position the two functional blocks adjacent to each other. For example, in a common multi-operation data processing method, a first block can provide a first data processing operation and an adjacent second block can provide a second data processing operation. Such features can greatly reduce the load on the controller of a computerized system. For example, such features can reduce the load on a central processing unit (CPU).

[0025] In embodiments where the blocks are implemented by 3D SICs, the use of TSVs can advantageously reduce each functional block to one function so that the benefits of TSVs are fully realized. In such embodiments, the functionality of the 3D IC can be increased by increasing the number of functional blocks in the 3D IC rather than the number of functions that a single functional block can perform. Thus, the TSVs or another type of interconnect of the 3D SIC can be fully utilized.

[0026] TSVs are electrical connections that can pass completely through a silicon wafer or die. Using TSVs, the interconnect and device density is substantially higher than conventional interconnects between dies. Also, the length of the connections between dies is shorter than conventional interconnects.

[0027] Some embodiments may have TSVs added to 3D IC structures with through-first TSV fabrication. This is a process where TSVs are fabricated before components such as transistors, capacitors, and resistors are patterned onto the wafer. Some embodiments use through-mid TSV fabrication, where TSVs are fabricated after patterning individual devices but before metal layers are added to the die or die stack. Also, some embodiments use through-last TSV fabrication, where TSVs are fabricated after or during the addition of metal layers.

[0028] In addition to the manner in which TSVs are added to 3D ICs, the layout and design of TSVs may also vary between the embodiments described herein. For example, differences in the granularity of partitioning of the functional elements of the die of the 3D IC may cause variations in the design and layout of the TSVs. Some embodiments have gate-level partitioning using TSVs and other embodiments have block-level partitioning. Gate-level partitioning using TSVs is less practical than block-level partitioning; therefore, to increase the benefit of having more TSVs, the functional sub-elements partitioned within the functional blocks may be connected via TSVs. This may be a middle ground solution.

[0029] In some embodiments, in addition to memory ICs (e.g., 3D XPoint memory (3DXP) and dynamic random access memory (DRAM) ICs), the chip stack or die may also have a processing logic integrated circuit (IC). The units of processing logic, 3DXP, and DRAM may be connected, for example, by TSVs to form functional blocks. In one 3D SIC or in general in one 3D IC, different functional blocks may be configured differently as needed and / or operate substantially independently of each other. The processing logic implements commonly used functions and / or data-intensive functions, so that even though the processing logic IC may not have the processing power of a CPU, its advantages in better data access may still provide better overall performance when implementing selected functions. Multiple functional blocks (e.g., multiple rows of functional blocks within a 3D SIC or 3DIC) may run in parallel and reduce the amount of computation on the CPU.

[0030] As described, in some embodiments, the processing logic IC or die does not have a complete array of processing cores that a typical CPU would have. However, in such embodiments, the processing logic implements commonly used functions and / or data-intensive functions; therefore, it is possible to reduce the significant processing burden of the CPU and enhance the performance of the CPU. In such embodiments, the functional block cannot execute a complete multifunctional instruction set on its own. Therefore, the functional block and the remainder of the 3D IC can be connected to the CPU, and the CPU can instruct the functional block to complete the task it is configured to complete. For example, the functional block of the example embodiment can be configured to decrypt data stored in its non-volatile memory IC through its processing logic IC, and insert the decrypted data into its volatile memory to be transmitted to the CPU for further processing by the CPU. In addition, the CPU can provide a request to the volatile memory of the functional block to request the block to produce the result of a specific function, and the CPU can also provide subsequent requests to retrieve the result from the functional block. For example, a request to produce a result can be provided from the CPU to the functional block in the form of a write command, and a request to retrieve the result can be provided from the CPU to the functional block in the form of a read command.

[0031] Figure 1 1 illustrates a front view of a 3D SIC 100 having a plurality of non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 according to some embodiments of the present invention. As shown, the dies are parallel to each other. The 3D SIC 100 also has functional blocks 110, 112, and 114 (eg, Figure 1 ) and functional blocks 210, 212, 214, 220, 222 and 224 (as shown in Figures 2 to 5 106, which crosses and is perpendicular to a plurality of nonvolatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106. 3D SIC 100 also has TSVs 116, 118, and 120 that connect the dies, respectively. TSVs 116 are shown between nonvolatile memory die 102 and nonvolatile memory die 104 and connect the nonvolatile memory die 102 to the nonvolatile memory die 104. TSVs 118 are shown between nonvolatile memory die 104 and processing logic die 106 and connect the nonvolatile memory die 104 to the processing logic die 106. TSVs 120 are shown between processing logic die 106 and volatile memory die 108 and connect the processing logic die 106 to the volatile memory die 108. It should be understood that all TSVs described herein also pass through the die described herein, even if this is not clear from the drawings. For example, TSV 116, TSV 118, and TSV 120 are parts of a single TSV passing through the die of 3DSIC 100.

[0032] 3D SIC 100 also has interconnects 122, 124, 126, and 128 shown as being embedded in the dies, respectively. Interconnect 122 is shown as being embedded in non-volatile memory die 102. Interconnect 124 is shown as being embedded in non-volatile memory die 104. Interconnect 126 is shown as being embedded in processing logic die 106. Also, interconnect 128 is shown as being embedded in volatile memory die 108. Interconnects 122, 124, 126, and 128 may be perpendicular to TSVs 116, 118, and 120 (e.g., Figure 1 As shown in Figure 5 (partial display).

[0033] It should be understood that the interconnects described herein, such as interconnects 122, 124, 126, and 128, refer to interconnects between components of a chip or die, such as copper or metal interconnects, interconnect traces, etc. The interconnects may include interconnects in metallization layers of a die or chip.

[0034] As depicted, in some embodiments, a 3D SIC may have multiple nonvolatile memory dies. In some embodiments, the nonvolatile memory die is slower than the volatile memory die. Specifically, the nonvolatile memory die has a bandwidth (e.g., the maximum amount of data that the die can transfer per second) that is less than the volatile memory die. The nonvolatile memory die may include a 3DXP die or any other type of electrically addressed memory system die, such as an EPROM die, a flash die, a ferroelectric RAM, and a magnetoresistive RAM. Each nonvolatile memory die may have a nonvolatile memory partition array. Each partition of the nonvolatile memory partition array may include an array of nonvolatile memory cells and each memory cell may have a corresponding address.

[0035] Figure 2 A top view of a nonvolatile memory die 102 having multiple nonvolatile memory partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i is illustrated in accordance with some embodiments of the present invention. The partitions may be arranged along a second direction (i.e., perpendicular to the stacking direction of the die of the 3D IC). Each of the partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i has multiple nonvolatile memory elements. Figure 2 Each of the partitions illustrated in FIG. 2 shows nine non-volatile memory element clusters 206. Also, each of the non-volatile memory element clusters 206 shows nine non-volatile memory elements 208. Thus, Figure 2Each of the partitions illustrated in FIG. 1 has eighty-one memory elements 208. However, it should be understood that the depiction of eighty-one memory elements is for convenience and that in some embodiments each partition may have at least one billion memory elements. In other words, the number of memory elements per non-volatile memory partition may be extremely large and vary widely. Furthermore, it should be understood that non-volatile memory die 102 and non-volatile memory die 104 are similar or identical in structure and design.

[0036] 3DXP ICs (also known as 3D XPoint memory ICs) use transistor-free memory elements, each with a memory cell and a corresponding address (and optionally a selector, which can be stacked together as a column). In an example with memory elements, the memory elements can be connected via two vertical layers of interconnects (e.g. Figure 2 , where one layer is above the memory element and the other layer is below the memory element. At each of the two layers of interconnects, a crossover point of an interconnect (e.g., see Figure 2 Each memory element is individually selected at the cross point 209 shown in FIG. Each cross point has an address or can be addressed or selected, for example, by an address decoder of a 3DXP IC, a 3D IC, or a group of ICs of 3D ICs. 3DXP devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

[0037] As described, nonvolatile memory dies 102 and 104 may be 3DXP dies. Some advantages of using 3DXP dies as the nonvolatile memory dies for 3D SIC 100 include that they are bit addressable by an address decoder. An address decoder (not shown in the drawings) used with the embodiments described herein may be a binary decoder having two or more inputs for address bits and one or more outputs for device select signals. When the address of a particular device or IC appears on the address input, the decoder asserts the select output of that device or IC. A dedicated single-output address decoder may be incorporated into each device or IC on the address bus, or a single address decoder may serve multiple devices or ICs.

[0038] Furthermore, a 3D SIC may have a volatile memory die (eg, a DRAM die or a static random access memory (SRAM) die) that includes an array of volatile memory partitions. Each partition of the volatile memory partition array may include an array of volatile memory cells and each memory cell may have a corresponding address.

[0039] Figure 3A top view of a volatile memory die 108 having multiple volatile memory partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i is illustrated according to some embodiments of the present invention. The partitions may be arranged along a second direction (i.e., perpendicular to the stacking direction of the dies of the 3D IC). Each of the partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i has multiple volatile memory elements. Figure 3 Each of the partitions illustrated in FIG. 3 shows nine volatile memory element clusters 306. Also, each of the volatile memory element clusters 306 shows nine volatile memory elements 308. Thus, Figure 3 Each of the partitions illustrated in FIG. 3 has eighty-one memory elements 308. However, it should be understood that the depiction of eighty-one memory elements is for convenience, and in some embodiments each partition may have at least one billion memory elements. In other words, the number of memory elements in each volatile memory partition may be extremely large and vary widely.

[0040] 3D SICs may also have a processing logic die with an array of processing logic partitions. Each partition may have a separate field programmable gate array (FPGA) or another type of processing logic device. The processing logic die may include a controller unit and an arithmetic / logic unit. For example, the arithmetic / logic unit may include an FPGA.

[0041] Figure 4 A top view of processing logic die 106 having multiple processing logic partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i is illustrated in accordance with some embodiments of the present invention. Figure 4 Each of the partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i is shown with a separate FPGA 406. As shown, Figure 4 Each of the nine FPGAs 406 illustrated in FIG. 4 has thirty-two input / output blocks 408 and sixteen logic blocks 410. In addition, Figure 4 Programmable or non-programmable interconnects 412 between the input / output blocks 408 and logic blocks 410 of each of the nine FPGAs 406 are shown. It should be understood that the depiction of the number of input / output cells and logic cells of the FPGA 406 is for convenience, and in some embodiments, each FPGA of the partition may have more or fewer input / output cells and logic cells depending on the embodiment of the corresponding functional block. In addition, even if Figure 4One FPGA per partition is shown, but it should be understood that in other embodiments of 3DSIC or processing logic die, each processing logic partition may have multiple FPGAs. In other words, the number of specific portions of the processing logic die may vary greatly.

[0042] Figure 2 , 3 4 also show functional blocks 110 , 112 , 114 , 210 , 212 , 214 , 220 , 222 , and 224 of 3D SIC 100 . Figure 2 A top view of the respective sections of the functional blocks at the non-volatile memory die 102 is shown. Figure 3 A top view of the respective sections of the functional blocks at the volatile memory die 108 is shown. Figure 4 A top view of corresponding sections of functional blocks at processing logic die 106 is shown.

[0043] Figure 2 , 3 4 also show interconnects 122, 128, and 126, respectively, interconnecting the non-volatile memory partitions, the volatile memory partitions, and the processing logic partitions. Thus, interconnects 122, 128, and 126 are also shown interconnecting the functional blocks of 3D SIC 100 at each layer of the 3D SIC. Specifically, as shown in FIG. Figure 2 As shown in FIG. 1 , interconnect 122 interconnects nonvolatile memory partitions 204a, 204b, 204c, 204d, 204e, 204f, 204g, 204h, and 204i of nonvolatile memory die 102. Figure 3 As shown in , interconnect 128 interconnects volatile memory partitions 304a, 304b, 304c, 304d, 304e, 304f, 304g, 304h, and 304i of volatile memory die 108. Also, as shown in FIG. Figure 4 , interconnect 126 interconnects processing logic partitions 404a, 404b, 404c, 404d, 404e, 404f, 404g, 404h, and 404i of processing logic die 106.

[0044] In a 3D SIC, a nonvolatile memory die, a volatile memory die, and a processing logic die are stacked along a first direction (e.g., vertically), and the processing logic die may be stacked between the nonvolatile memory die and the volatile memory die. The 3D SIC may also have a functional block array composed of the dies of the 3D SIC. In other words, the nonvolatile memory die, the volatile memory die, and the processing logic die are arranged to form a functional block array. At least two functional blocks of the functional block array may each include different data processing functions that reduce the amount of calculation of the controller (and thus reduce the amount of calculation of the CPU). Each functional block of the functional block array may include a corresponding column of the 3D SIC. The corresponding column of the 3D SIC may include a corresponding nonvolatile memory partition of the nonvolatile memory partition array, a corresponding volatile memory partition of the volatile memory partition array, and a corresponding processing logic partition of the processing logic partition array. The corresponding processing logic partition may be stacked between the corresponding nonvolatile memory partition and the corresponding volatile memory partition along the first direction.

[0045] Figure 5 A system having a plurality of non-volatile memory dies 102 and 104, a volatile memory die 108, and a processing logic die 106 is illustrated in accordance with some embodiments of the present invention. Figure 1 1. A perspective view of the 3D SIC 100 illustrated in FIG. Figure 5 A perspective view of nonvolatile memory dies 102 and 104, volatile memory die 108, and processing logic die 106 is shown, and shows how the dies are stacked in a first direction (eg, vertically) and how a processing logic die can be stacked between the nonvolatile memory dies and the volatile memory dies. Figure 5 The functional block array is also shown in its entirety, wherein all functional blocks 110 , 112 , 114 , 210 , 212 , 214 , 220 , 222 , and 224 of the 3D SIC 100 are depicted.

[0046] It should be understood that the number of functional blocks of the 3D SIC may vary depending on the embodiment of the 3D SIC. Figures 1 to 5 Each functional block of the functional block array described in can include a corresponding column of the 3D SIC 100. Figures 1 to 5 As shown by the combination of such figures, a column of a 3D SIC having a single functional block may include a respective nonvolatile memory partition of the nonvolatile memory partition array, a respective volatile memory partition of the volatile memory partition array, and a respective processing logic partition of the processing logic partition array. Furthermore, as shown by the combination of such figures, a respective processing logic partition may be stacked between a respective nonvolatile memory partition and a respective volatile memory partition along a first direction (e.g., vertically).

[0047] In some embodiments, each of two adjacent function blocks of the function block array may have different specific data processing functions that are usually used together for a larger specific data processing function. The specific data processing function may include a basic process of the CPU, such as a decode process of a decode operation of the CPU.

[0048] Some embodiments of the 3D IC or at least one functional block group may be used as an instruction decoder for a CPU. Thus, when connected to such an embodiment of a 3D IC, the CPU may retain resources for fetching and executing operations.

[0049] Certain data processing functions may also include functions of the arithmetic logic unit of the CPU, such as integer arithmetic and bitwise logic operations. Thus, the CPU may conserve resources by delegating arithmetic logic unit operations to such embodiments of the 3D IC.

[0050] In addition, embodiments of the 3D IC or at least one functional block group of some embodiments can be used as encoders and / or decoders of a type different from encoders and / or decoders that are usually hardwired or programmed into a CPU. For example, embodiments of the 3D IC or at least one functional block group of some embodiments can be used as an encryption block, wherein the 3D IC or at least one functional block group has a password that can generate a ciphertext. In addition, embodiments can be used as decryption blocks. In one embodiment, one or more blocks of the 3D IC can be dedicated to encryption and one or more other blocks of the same 3D IC can be dedicated to decryption. In addition, embodiments of the 3D IC or at least one functional block group of some embodiments can be used as one or more data processing intensive operations, such as data intensive operations of a type of machine learning.

[0051] The 3D SIC may also include: a first set of TSVs (eg, Figure 1 and 5 118) that connects the corresponding non-volatile memory partitions and the corresponding processing logic partitions in the corresponding columns of the 3D SIC; and a second set of TSVs (e.g., as Figure 1 and 5 ), which connects the corresponding volatile memory partitions and the corresponding processing logic partitions in the corresponding columns of the 3D SIC.

[0052] In some embodiments, the processing logic die may include a control unit and an arithmetic / logic unit, and each of the memory ICs may include a storage portion that is addressable by an address decoder and / or has a predefined address. In such embodiments, the control unit is connected to the storage portion of the memory IC and the arithmetic / logic unit is connected to the storage portion of the memory IC and / or portions of the IC are connected to the storage portion of the memory IC via an address decoder.

[0053] In some embodiments including a control unit and an arithmetic / logic unit, the control unit is configured to fetch instructions from a volatile memory IC of the 3D IC during instruction time and direct data to move from the volatile memory IC to the arithmetic / logic unit according to at least a portion of the instructions. Furthermore, the arithmetic / logic unit may be configured to execute at least a portion of the instructions during run time and store at least a portion of the execution results of the instructions in a non-volatile memory of the 3D IC.

[0054] In such embodiments, the arithmetic / logic unit is given control and performs actual operations on the data. The combination of instruction time and run time may be a machine cycle of the 3D IC, and in some embodiments, the control unit may direct the volatile memory IC and / or non-volatile memory IC to release the result to an output device or storage device outside the device during the run time. In some embodiments, the connection between the control and arithmetic / logic unit and the memory cell of the memory IC is a connection that may be a TSV. In other words, the control unit may be connected to the memory element of the memory IC along a first direction (e.g., vertically) through a plurality of electrical connections, and the arithmetic / logic unit may be connected to the memory element of the memory IC along a first direction through a plurality of electrical connections.

[0055] The memory cells and logic units of each IC or the die of the 3D IC may be connected to each other through a plurality of electrical connections along a second direction (e.g., a horizontal direction) orthogonal to the first direction. For example, the 3D SIC may also include: a first set of interconnects (e.g., Figure 1 and 2 ) that connects the nonvolatile memory partitions of the nonvolatile memory partition array along a second direction; a second set of interconnects (e.g., Figure 1 and 3 ) which connects the volatile memory partitions of the volatile memory partition array along a second direction; and a third set of interconnects (e.g., Figure 1 and 4 ) that connects the processing logic partitions of the processing logic partition array along the second direction. In some embodiments having three sets of interconnects, the interconnects of the first set of interconnects only connect the non-volatile memory partition of the non-volatile memory partition array to another non-volatile memory partition immediately adjacent to the non-volatile memory partition (e.g., see Figure 1 and 2 ). Furthermore, in such embodiments, the interconnects of the second set of interconnects only connect a volatile memory partition of the volatile memory partition array to another volatile memory partition that is immediately adjacent to the volatile memory partition (e.g., see Figure 1 and 2). Furthermore, the interconnects of the third set of interconnects only connect a processing logic partition of the processing logic partition array to another processing logic partition that is immediately adjacent to the processing logic partition (e.g., see Figure 1 and 4 The interconnect 126 shown in FIG.

[0056] Some exemplary embodiments of 3D SIC include a processing logic die, a 3DXP die, and a DRAM die, wherein the processing logic die is stacked between the 3DXP die and the DRAM die. In such exemplary embodiments, a set of TSVs interconnects the processing logic die, the 3DXP die, and the DRAM die. In such exemplary embodiments or some other exemplary embodiments, the 3D SIC includes a 3DXP die having a non-volatile memory partition array, wherein each partition of the non-volatile memory partition array has a non-volatile memory cell array. In such embodiments, the volatile memory die has a volatile memory partition array, wherein each partition of the volatile memory partition array has a volatile memory cell array. In addition, in such embodiments, a processing logic die is included and has a processing logic partition array. Moreover, the 3DXP die, the volatile memory die, and the processing logic die are stacked along a first direction (e.g., vertically), wherein the processing logic die is stacked between the 3DXP die and the volatile memory die. Furthermore, such embodiments of the 3D SIP may include a first set of TSVs connecting respective non-volatile memory partitions and respective processing logic partitions in respective columns of the 3D SIC. Moreover, such embodiments may include a second set of TSVs connecting respective volatile memory partitions and respective processing logic partitions in respective columns of the 3D SIC.

[0057] 3D SICs can also have multiple non-volatile memory dies (such as Figure 1 and 5 ). For example, the 3D SIC may include a second nonvolatile memory die that may include a second nonvolatile memory partition array. Moreover, each partition of the second nonvolatile memory partition array may have a nonvolatile memory cell array. In embodiments where the 3D SIC has multiple nonvolatile memory dies, the nonvolatile memory dies (e.g., a first nonvolatile memory die and a second nonvolatile memory die) may be concentrated so that the processing logic die is between the volatile memory die and the nonvolatile memory die group (e.g., Figure 1 and 5 ).

[0058] In some embodiments of the 3D SIC, each functional block of the 3D SIC may have a respective communication interface (i.e., a respective port) configured to communicatively couple the block to a bus so that each block can operate in parallel and independently of each other. Additionally or alternatively, groups of at least two functional blocks of the 3D SIC each share a respective communication interface configured to communicatively couple the at least two functional blocks to a bus so that each group of at least two functional blocks can operate in parallel and independently of another group of at least two functional blocks. Additionally or alternatively, the 3D SIC may have one or more general communication interfaces (i.e., one or more general ports) configured to communicatively couple any one or all functional blocks of the 3DSIC to a bus.

[0059] Figure 6 A block diagram illustrating an example computer system 600 in which embodiments of the present invention may operate is shown. Figure 6 As shown in FIG. 6 , computer system 600 includes 3D SIC 100 including communication interface 602 (or also referred to as port 602). Communication interface 602 is communicatively coupled to bus 604 of computer system 600. Bus 604 is communicatively coupled to a controller of computer system 600 (e.g., a CPU of system 600) as well as main memory 608 and network interface 610 of computer system 600. Figure 6 As shown in , network interface 610 communicatively couples computer system 600 to a computer network 612 .

[0060] Computer system 600 may be or include a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network facility, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specifies the actions to be taken by the computerized system. In addition, although a single computer system 600 is described, the term "computer system" should also be considered to include any collection of computer systems. Bus 604 may be or include multiple buses. Controller 606 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Controller 606 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), an FPGA, a digital signal processor (DSP), a network processor, or the like. The main memory 608 may be a read-only memory (ROM), flash memory, DRAM (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), and / or SRAM.

[0061] refer to Figure 1 and 6 , in some embodiments, port 602 may be configured to communicatively couple volatile memory die 108 to bus 604. In this arrangement, controller 606 may delegate data processing functions to 3D SIC 100 via bus 604 and volatile memory die 108. The delegated data processing functions may be data intensive functions or frequently used functions of controller 606. As described above, in some embodiments, the processing logic IC or die does not have a complete array of processing cores that a typical CPU would have. However, in such embodiments, the processing logic may implement frequently used functions and / or data intensive functions; therefore, it is possible to reduce the significant processing burden of the CPU and enhance the performance of the CPU. Furthermore, in the depicted embodiment, the functional blocks are unable to execute a full multi-function instruction set on their own. Therefore, the functional blocks and the rest of the 3D SIC 100 may be connected to a controller (e.g., a CPU) and the controller may instruct the functional blocks to complete the tasks they are configured to complete.

[0062] For example, a functional block of an example embodiment may be configured to decrypt data stored in its corresponding non-volatile memory partition through its processing logic partition and insert the decrypted data into its corresponding volatile partition for transmission to a controller for further processing by the controller.

[0063] In addition, in general, the controller may provide a request to the volatile memory partition of the functional block to request that the block produce a result of a particular function, and the controller may also provide a second or subsequent request to retrieve the result from the functional block. For example, the request to produce the result may be provided from the controller to the functional block in the form of a write command, and the request to retrieve the result may be provided from the controller to the functional block in the form of a read command.

[0064] Figure 7 A flowchart illustrating an example method 700 in which an embodiment of a 3D SIC (eg, Figures 1 to 6 3D SIC100) can be connected via a bus (e.g., Figure 6 bus 604) and a controller (e.g., Figure 6 Controller 606) interacts.

[0065] In general, method 700 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit, a dedicated logic, a programmable logic, a microprocess code, hardware of a device, an integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. Although shown in a particular sequence or order and performed by specific hardware / software, the order of the processes and the hardware / software may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders and / or by different hardware / software, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0066] Specifically, method 700 may be performed by at least nonvolatile memory die 102 and / or nonvolatile memory die 104, processing logic die 106, volatile memory die 108, and controller 606 (eg, Figure 7 ). At block 701, the controller 606 transmits a request via the bus. The request of the controller 606 is configured to instruct the 3D SIC to produce a result of a specific data processing function. This request may be communicated to the 3D SIC via a write command of the controller 606. For example, if the controller 606 makes the request using a write command, the request is sent to a selected volatile memory partition of the volatile memory die 108. Alternatively, the controller 606 may make the request using an execute command, and in such an example the request may be sent directly to a selected processing logic partition of the processing logic die 106.

[0067] At block 702, the volatile memory die 108 receives a request via a bus. The volatile memory die 108 may be configured to receive the request from the controller via port 602 from the bus. In addition to being configured to instruct the 3D SIC to produce a result of a specific data processing function, the request may also include at least one input parameter for the specific data processing function. At block 704, the volatile memory die 108 stores the request and transmits the request to the processing logic die 106. The volatile memory die 108 may be configured to store the request in at least one volatile partition of the volatile memory die.

[0068] The stored request is received by the processing logic die at block 706. Also, at block 706, at least one input parameter of a specific data processing function may be received by at least one processing logic partition via a TSV connecting at least one volatile partition of the volatile memory die and at least one processing logic partition.

[0069] At block 708, the processing logic die generates a result based on the stored request. At least one processing logic partition of the processing logic die 106 may include a specific data processing function, and the specific data processing function may generate a result based on the stored request and at least one input parameter of the specific data processing function. The specific data processing function may be hardwired into at least one processing logic partition of the processing logic die. Alternatively, the specific data processing function may be temporarily configured in at least one processing logic partition of the processing logic die by the controller 606 or another controller. For example, the specific data processing function may be implemented by an FPGA that may be configured by the controller 606 or another controller.

[0070] At block 710, processing logic die 106 communicates the results to nonvolatile memory die 102 and / or nonvolatile memory die 104. Processing logic die 106 may be configured to communicate the generated results of a particular data processing function to a nonvolatile memory die via a TSV connecting at least one nonvolatile partition of the nonvolatile memory die and at least one processing logic partition.

[0071] At block 712, non-volatile memory die 102 and / or non-volatile memory die 104 receive and store the results transferred from processing logic die 106. Non-volatile memory die 102 and / or non-volatile memory die 104 may be configured to store the generated results in at least one non-volatile partition and transfer the stored results to processing logic die 106 after the stored results are requested by the processing logic die 106. The request by processing logic die 106 for the stored results may be in response to the request by volatile memory die 108 for the stored results, and the request by volatile memory die 108 for the stored results may be in response to the request by controller 606 for the stored results via bus 604.

[0072] The processing logic die 106 may be configured to retrieve the stored results from the non-volatile memory die via the TSVs connecting the at least one non-volatile partition and the at least one processing logic partition. Moreover, the 3D SIC may be configured to transmit the retrieved results to the volatile memory die via the TSVs connecting the at least one volatile partition and the at least one processing logic partition. The volatile memory die may be configured to receive the retrieved results and store the retrieved results in the at least one volatile partition, and when the second request of the controller is configured to instruct the 3D SIC to retrieve the results generated by the specific data processing function, transmit the stored retrieved results to the bus via the port according to the second request of the controller. In some examples where the controller 606 uses a read command to make the second request, the second request is sent to the selected volatile memory partition of the volatile memory die 108.

[0073] about Figure 7 At block 714a, the controller transmits a second request configured to instruct the 3D SIC to retrieve a result generated by a specific data processing function. At block 714b, the second request is received, stored, and sent to the processing logic die 106 by the volatile memory die 108. At block 714c, the second request is received, stored, and forwarded to the non-volatile memory die 102 and / or the non-volatile memory die 104 by the processing logic die 106.

[0074] At block 716, in response to block 714c, non-volatile memory die 102 and / or non-volatile memory die 104 transmit the stored results to processing logic die 106. At block 718, processing logic die 106 receives the retrieved results, and at block 720, processing logic die 106 transmits the retrieved results to volatile memory die 108. Processing logic die 106 may be configured to retrieve the stored results from the non-volatile memory die via the TSVs connecting at least one non-volatile partition and at least one processing logic partition. Also, processing logic die 106 may be configured to transmit the retrieved results to the volatile memory die via the TSVs connecting at least one volatile partition and at least one processing logic partition.

[0075] At block 722, the volatile memory die 108 receives and stores the retrieved results sent from the processing logic die 106. At block 724, the retrieved results are then transmitted by the volatile memory die 108 to the controller 606. The volatile memory die may be configured to receive and store the retrieved results in at least one volatile partition, and to transmit the stored retrieved results to the bus via a port according to a second instruction of the controller configured to instruct the 3D SIC to retrieve results generated by a specific data processing function.

[0076] At block 726, the controller 606 receives the retrieved results. The retrieved results may be used by the controller 606 for another processing step or output by the controller to another device.

[0077] In such embodiments, at least two of the volatile partition, the non-volatile partition, and the processing logic partition may be in the same one or more columns of the 3D SIC. For example, the volatile partition, the non-volatile partition, and the processing logic partition used together may be in the same one or more columns of the 3D SIC. Furthermore, in some embodiments, each of two adjacent functional blocks of the functional block array may have different sub-specific data processing functions of the specific data processing function.

[0078] A specific data processing function, such as that described using method 700, may comprise a basic process of controller 606. For example, if controller 606 is a CPU, the basic process may be a decode process of a decode operation of the CPU. Processing logic die 106 may be programmed or hardwired as a decoder of the CPU or at least a common or data intensive portion of a decoder of the CPU. Thus, when connected to 3D SIC 100, the CPU may retain resources for fetching and executing operations.

[0079] The specific data processing functions may also include processing logic that provides at least part of the functionality of the arithmetic logic unit of the CPU, and this functionality may be programmed or hardwired into the processing logic die 106. Moreover, contiguous partitions of the processing logic die 106 may provide sub-operations of the arithmetic logic unit, such as different integer arithmetic and bitwise logic operations. Thus, the CPU may conserve resources by delegating arithmetic logic unit operations to the 3D SIC 100.

[0080] Furthermore, the processing logic die 106 may function as an encoder and / or decoder of a different type than that which is typically hardwired or programmed into a CPU. For example, for some embodiments of the 3D SIC 100 or at least one functional block group, the 3D SIC 100 may provide encryption functionality, where the 3D IC or at least one functional block group has a password hardwired or programmed into the processing logic die 106 so that the die can generate ciphertext and then can immediately store the ciphertext in the non-volatile memory die 102 and / or non-volatile memory die 104 of the 3DSIC 100 for subsequent retrieval by the controller 606. Also, the processing logic die 106 or partition of the die may function as a decryption algorithm. In one embodiment, one or more blocks of the 3D SIC 100 may be dedicated to encryption and other one or more blocks of the 3D IC may be dedicated to decryption.

[0081] In addition, the 3D SIC 100 or at least a group of functional blocks of some embodiments can be used for one or more specific data processing intensive operations, such as selected data intensive operations of a type of machine learning. Moreover, data intensive operations that immediately precede or follow each other in a machine learning algorithm or another type of complex computerized algorithm can be implemented by blocks of the 3DSIC 100 that are adjacent to each other. Thus, the transition time between operations of the algorithm is accelerated and other benefits are provided, such as reduced power consumption.

[0082] In some embodiments, when the device is powered on, the first memory IC of the 3D IC may provide a non-volatile storage portion. Each non-volatile storage portion of the non-volatile storage portion stores a bit when receiving power or when not receiving power. In addition, when the device is powered on, the second memory IC of the 3D IC may provide a volatile storage portion. Each volatile storage portion of the volatile storage portion stores a bit only when receiving power. In such embodiments, when the device is powered on, the electrical connector of the 3D IC along a second direction (e.g., horizontal direction) orthogonal to the first direction may communicatively couple the first storage portion of the first memory IC to each other and the second storage portion of the second memory IC to each other. Moreover, when the device is powered on, the electrical connector along the first direction (e.g., vertically) of the 3D IC may communicatively couple the control unit and the arithmetic / logic unit of the processing logic IC of the 3D IC to the storage portions of the first memory IC and the second memory IC to control the use of the storage portions.

[0083] In such embodiments, during a machine cycle of the 3D IC, the control unit may fetch instructions from the first memory IC and / or the second memory IC during an instruction time of the machine cycle. Furthermore, during a machine cycle of the 3D IC, the control unit or a decoder controlled by the control unit may decode the instructions and direct data to be moved from the first memory IC and / or the second memory IC to the arithmetic / logic unit according to at least a portion of the instructions during the instruction time. Furthermore, during the machine cycle, the arithmetic / logic unit may execute at least a portion of the instructions during a run time of the machine cycle, and store at least a portion of the execution results of the instructions in the first memory IC and / or the second memory IC during the run time. Furthermore, during the machine cycle, the control unit may direct the first memory IC and / or the second memory IC to release the results to an output device or a storage device outside the device during the run time.

[0084] In an example system of some embodiments, the system may include a first functional block, the first functional block including a first processing logic IC, a first memory IC, and a second memory IC. The first processing logic IC, the first memory IC, and the second memory IC may be arranged as an IC stack along a first direction (e.g., vertically) to form the first functional block. The system may also include a second functional block, the second functional block may include a second processing logic IC, a third memory IC, and a fourth memory IC. The second processing logic IC, the third memory IC, and the fourth memory IC may be arranged as an IC stack along the first direction to form the second functional block. The system may also include at least one bus or interconnect communicatively coupling the first functional block and the second functional block.

[0085] In this example system, the first function block and the second function block are configured differently from each other for different corresponding data processing functions. The data processing functions may be different commonly used functions and / or data-intensive functions, so that even if each processing logic IC of the block may not have the processing power of a CPU, its advantages in improved (e.g., tighter) data access to non-volatile memory and volatile memory enable it to provide better overall performance when implementing selected functions. Each of the first function block and the second function block can be configured as needed by a controller (e.g., a CPU) connected to the function block via a wired and / or wireless bus. Each of the first function block and the second function block can be configured to reduce the amount of calculation of the controller. The configuration of each of the first function block and the second function block can include the configuration of the corresponding processing logic IC of the function block as needed. Each of the first function block and the second function block can be configured to operate independently of each other. Each of the first function block and the second function block is configured to operate in parallel to provide parallel data processing.

[0086] In an example method of some embodiments implemented by multiple functional blocks of one or more 3D ICs, a functional block of the multiple functional blocks may perform a first data processing function including a processing logic IC that controls storage and retrieval of data to and from a first memory IC and a second memory IC. The functional block may also be changed as needed (e.g., by a CPU) so that the functional block is configured to perform a second data processing function. The functional block may also perform a second data processing function that includes the processing logic IC controlling storage and retrieval of data to and from a first memory IC and a second memory IC in a manner different from that in which the processing logic IC controls storage and retrieval of data to and from the first memory IC and the second memory IC during the first data processing function. In this example method, each functional block of the multiple functional blocks includes a respective processing logic IC, a respective first memory IC, and a respective second memory IC, and the respective processing logic IC, the respective first memory IC, and the respective second memory IC are arranged as an IC stack along a first direction (e.g., vertically) to form a functional block.

[0087] In the foregoing specification, embodiments of the present invention have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the embodiments of the present invention without departing from the broader spirit and scope of the embodiments of the present invention as set forth in the appended claims. Accordingly, the description and drawings should be regarded as intended to be illustrative rather than restrictive.

Claims

1. A three-dimensional stacked integrated circuit 3D SIC, comprising: a nonvolatile memory die comprising a nonvolatile memory partition array, wherein each partition of the nonvolatile memory partition array comprises an array of nonvolatile memory cells; a volatile memory die comprising a volatile memory partition array, wherein each partition of the volatile memory partition array comprises an array of volatile memory cells; and a processing logic die including an array of processing logic partitions, wherein the non-volatile memory die, the volatile memory die, and the processing logic die are stacked along a first direction, wherein the non-volatile memory die, the volatile memory die, and the processing logic die are arranged to form an array of functional blocks, wherein each of at least two functional blocks of the functional block array comprises a different data processing function, wherein each functional block in the functional block array comprises a respective column of the 3D SIC; and The corresponding columns include: a corresponding non-volatile memory partition of the non-volatile memory partition array; a corresponding volatile memory partition of the volatile memory partition array; and A corresponding processing logical partition of the processing logical partition array. 2 . The 3D SIC of claim 1 , further comprising through silicon vias (TSVs) connecting the corresponding non-volatile memory partition, the corresponding processing logic partition, and the corresponding volatile memory partition in the corresponding column of the 3D SIC.

3. The 3D SIC of claim 1 , further comprising: a first plurality of interconnects connecting nonvolatile memory partitions of the array of nonvolatile memory partitions along a second direction orthogonal to the first direction; a second plurality of interconnects connecting volatile memory partitions of the volatile memory partition array along the second direction; and A third plurality of interconnects connects the processing logic partitions of the processing logic partition array along the second direction.

4. The 3D SIC of claim 3, wherein: interconnects of the first plurality of interconnects connect a nonvolatile memory partition of the array of nonvolatile memory partitions only to another nonvolatile memory partition immediately adjacent to the nonvolatile memory partition; interconnects of the second plurality of interconnects connect a volatile memory partition of the array of volatile memory partitions only to another volatile memory partition that is immediately adjacent to the volatile memory partition; The interconnects of the third plurality of interconnects connect a processing logic partition of the processing logic partition array only to another processing logic partition immediately adjacent to the processing logic partition.

5. The 3D SIC of claim 1 , further comprising a second nonvolatile memory die, the second nonvolatile memory die comprising a second nonvolatile memory partition array, wherein each partition of the second nonvolatile memory partition array comprises an array of nonvolatile memory cells, and wherein the second nonvolatile memory die is grouped with the nonvolatile memory die.

6. The 3D SIC of claim 1, wherein the non-volatile memory die is a 3D XPoint 3DXP die.

7. The 3D SIC of claim 1, wherein the volatile memory die is a dynamic random access memory (DRAM) die.

8. The 3D SIC of claim 1, further comprising: a port configured to communicatively couple the volatile memory die to a bus, wherein the volatile memory die is configured to: receiving a request from a controller via the port from the bus, the request being configured to instruct the 3D SIC to generate a result of a specific data processing function, wherein the request includes at least one input parameter of the specific data processing function; and storing the request in at least one volatile partition of the volatile memory die, wherein at least one processing logic partition of the processing logic die includes the specific data processing function, and the specific data processing function generates the result according to the stored request, The at least one input parameter in the specific data processing function is received by the at least one processing logic partition through a through silicon via (TSV), and the TSV connects the at least one volatile partition of the volatile memory die and the at least one processing logic partition.

9. The 3D SIC of claim 8, wherein the specific data processing functionality is hardwired into the at least one processing logic partition of the processing logic die.

10. The 3D SIC of claim 8, wherein the specific data processing function is temporarily configured by the controller or another controller in the at least one processing logic partition of the processing logic die. The 3D SIC according to claim 10 , wherein the specific data processing function is implemented by a field programmable gate array (FPGA).

12. The 3D SIC of claim 8, wherein the processing logic die of the 3D SIC is configured to transfer the generated results of the specific data processing function to the non-volatile memory die by the TSV, the TSV also connecting at least one non-volatile partition of the non-volatile memory die and the at least one processing logic partition, and wherein the non-volatile memory die is configured to: storing the generated results in the at least one non-volatile partition; and In response to the volatile memory die requesting the stored results, the stored results are communicated to the processing logic die after the processing logic die requests the stored results, the volatile memory die requesting the stored results being in response to the controller requesting the stored results via the bus.

13. The 3D SIC of claim 12, wherein: The processing logic die of the 3D SIC is configured to: retrieving the stored results from the nonvolatile memory die via the TSV; and transferring the retrieved results to the volatile memory die via the TSV, and wherein the volatile memory die is configured to: receiving the retrieved results and storing the retrieved results in the at least one volatile partition; and The stored retrieval result is transmitted to the bus via the port according to a second request of the controller, the second request being configured to instruct the 3D SIC to retrieve a result generated by the specific data processing function.

14. The 3D SIC of claim 13, wherein at least two of the at least one volatile partition, the at least one non-volatile partition, and the at least one processing logic partition are in the same one or more columns of the 3D SIC.

15. The 3D SIC of claim 1, wherein each functional block in the 3D SIC includes a respective port configured to communicatively couple the block to a bus so that each block can operate in parallel and independently of the other blocks.

16. The 3D SIC of claim 1, wherein each group of at least two functional blocks of the 3D SIC shares a respective port configured to communicatively couple the at least two functional blocks to a bus so that each group of at least two functional blocks can operate in parallel and independently of another group of at least two functional blocks.

17. The 3D SIC of claim 1, further comprising one or more general purpose ports configured to communicatively couple any of the functional blocks to a bus.

18. The 3D SIC of claim 1, wherein each of two adjacent functional blocks of the functional block array comprises a different sub-partitioned data processing function that is commonly used together for a specific data processing function.

19. A three-dimensional stacked integrated circuit 3D SIC, comprising: Processing logic die; 3D XPoint 3DXP die; a dynamic random access memory DRAM die, wherein the processing logic die is stacked between the 3DXP die and the DRAM die to provide at least one data processing function; and A plurality of through silicon vias (TSVs) interconnect and pass through the processing logic die, the 3DXP die, and the DRAM die.

20. A three-dimensional stacked integrated circuit 3D SIC, comprising: a 3D XPoint 3DXP die comprising a non-volatile memory partition array, wherein each partition of the non-volatile memory partition array comprises an array of non-volatile memory cells; a volatile memory die comprising a volatile memory partition array, wherein each partition of the volatile memory partition array comprises an array of volatile memory cells; a processing logic die comprising a processing logic partition array, wherein the 3DXP die, the volatile memory die, and the processing logic die are stacked, and wherein the processing logic die provides at least one data processing function; Through silicon vias (TSVs) connect corresponding non-volatile memory partitions, corresponding processing logic partitions, and corresponding volatile memory partitions in corresponding columns of the 3D SIC.

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