Organic light-emitting diode display device

Abstract

An organic light-emitting diode (OLED) display device is disclosed. The OLED display device includes a substrate, a pixel structure, a first circuit transistor, a first lower electrode, a first upper electrode, and a planarization layer. The substrate has a display area and a peripheral area. The peripheral area includes a first circuit area, a second circuit area, and a blocking area located between the first circuit area and the second circuit area. The pixel structure is on the substrate in the display area. The first circuit transistor is on the substrate in the first circuit area. The first lower electrode is on the substrate in the blocking area. The first upper electrode is on the first lower electrode, and the first upper electrode and the first lower electrode constitute a first capacitor. The planarization layer is on the substrate and has a first opening, which is superimposed on the first capacitor in the blocking area.

Description

Technical Field

[0001] The exemplary embodiments generally relate to an organic light-emitting diode (OLED) display device. More specifically, embodiments of this disclosure relate to an OLED display device including a circuit structure. Background Technology

[0002] Due to their lightweight and thin characteristics, flat panel displays are used as alternatives to cathode ray tube (CRT) displays. Liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays are representative examples of such flat panel displays.

[0003] Organic light-emitting diode (OLED) display devices may include a display area for displaying images and a peripheral area that serves as a non-display area (such as invalid space). For example, multiple pixel structures may be disposed in the display area, and gate drivers, light-emitting control drivers, etc., comprising multiple circuit structures may be disposed in the peripheral area. The circuit structures may include multiple transistors and multiple capacitors. Meanwhile, when organic layers (e.g., planarization layers, pixel defining layers, etc.) are continuously disposed in the peripheral area, residual gases based on organic materials generated during the manufacturing process may permeate from the peripheral area through the organic layers into the display area, thereby damaging the pixel structures. To prevent or reduce such damage to the pixel structures, the organic layers may be discontinuously disposed in the peripheral area. For example, spaces formed by completely removing the organic layers (e.g., openings in the organic layers) may exist in the peripheral area. When openings in the organic layers are formed in the peripheral area, the area of ​​the peripheral area is relatively increased. Summary of the Invention

[0004] Some aspects of example embodiments relate to an organic light-emitting diode display device including a circuit structure.

[0005] According to some example embodiments, an organic light-emitting diode (OLED) display device includes a substrate, a pixel structure, a first circuit transistor, a first lower electrode, a first upper electrode, and a planarization layer. The substrate has a display area and a peripheral area, the peripheral area including a first circuit area, a second circuit area, and a blocking area located between the first and second circuit areas. The pixel structure is on the substrate in the display area. The first circuit transistor is on the substrate in the first circuit area. The first lower electrode is on the substrate in the blocking area. The first upper electrode is on the first lower electrode, and the first upper electrode and the first lower electrode constitute a first capacitor. The planarization layer is on the substrate and has a first opening overlapping the first capacitor in the blocking area.

[0006] In an example embodiment, the first capacitor and the first circuit transistor may define a first circuit structure, and the first circuit structure may be located in a first portion of the blocking region and in the first circuit region.

[0007] In an example embodiment, the first circuit transistor and the first capacitor may be electrically connected to each other.

[0008] In an example embodiment, the organic light-emitting diode display device may further include a pixel defining layer. The pixel defining layer may be on a planarization layer and may have a second opening superimposed on the first opening in a blocking region. A first capacitor may be superimposed on the second opening.

[0009] In an example embodiment, the organic light-emitting diode display device may further include: a first gate insulating layer between a substrate and a planarization layer; a second gate insulating layer on the first gate insulating layer, which also covers a first lower electrode; and an insulating intermediate layer on the second gate insulating layer, which also covers a first upper electrode.

[0010] In an example embodiment, the first opening may be configured to expose the top surface of the insulating intermediate layer located in the blocking region, and the width of the first opening may be smaller than the width of the second opening.

[0011] In an example embodiment, the pixel structure may include a first electrode on a planarization layer, a light-emitting layer on the first electrode, and a second electrode on the light-emitting layer.

[0012] In an example embodiment, the second electrode can extend from the display area to the peripheral area to overlap with the first opening and the second opening.

[0013] In an example embodiment, the organic light-emitting diode display device may further include a connection electrode on an insulating intermediate layer in a blocking region, and the connection electrode may contact the second electrode and the insulating intermediate layer through a first opening and a second opening.

[0014] In an example embodiment, the organic light-emitting diode display device may further include a pixel transistor. The pixel transistor may be located between the substrate and the pixel structure and may be electrically connected to the pixel structure. The pixel transistor may include: an active layer on the substrate in the display region; a gate electrode on a first gate insulating layer in the display region; and a source electrode and a drain electrode on an insulating intermediate layer in the display region.

[0015] In an example embodiment, the first lower electrode may be located on the same layer as the gate electrode.

[0016] In an example embodiment, the organic light-emitting diode display device may further include a storage capacitor spaced apart from the pixel transistors, and the storage capacitor may include: a lower gate pattern on a first gate insulating layer in the display area; and an upper gate pattern on a second gate insulating layer in the display area and superimposed on the lower gate pattern. A first upper electrode may be located on the same layer as the upper gate pattern.

[0017] In an example embodiment, the organic light-emitting diode display device may further include a second circuit transistor, a second lower electrode, and a second upper electrode. The second circuit transistor may be located on a substrate in a second circuit region. The second lower electrode may be located on the substrate in a blocking region and spaced apart from the first lower electrode. The second upper electrode may be located on the second lower electrode, and the second upper electrode and the second lower electrode may constitute a second capacitor.

[0018] In an example embodiment, the second capacitor and the second circuit transistor may define a second circuit structure, and the second circuit structure may be located in the second portion of the blocking region and the second circuit region.

[0019] In the example embodiment, the second circuit transistor and the second capacitor may be electrically connected to each other.

[0020] In an example embodiment, the first upper electrode may be integrally formed with the second upper electrode.

[0021] In an example embodiment, the organic light-emitting diode display device may further include a first pixel transistor and a second pixel transistor. The second pixel transistor may be spaced between the substrate and the pixel structure and from the first pixel transistor, and may be electrically connected to the pixel structure.

[0022] In an example embodiment, the first circuit structure may be configured to generate a gate signal provided to the first pixel transistor, and the second circuit structure may be configured to generate a light emission control signal provided to the second pixel transistor.

[0023] In the example embodiment, the peripheral area may be located on one side of the display area, and the first circuit area may be adjacent to the display area.

[0024] In an example embodiment, the organic light-emitting diode display device may further include a thin-film encapsulation structure on the pixel structure, and the thin-film encapsulation structure may include: a first inorganic thin-film encapsulation layer extending from the display area to the peripheral area; an organic thin-film encapsulation layer on the first inorganic thin-film encapsulation layer; and a second inorganic thin-film encapsulation layer extending from the display area to the peripheral area on the organic thin-film encapsulation layer.

[0025] In an organic light-emitting diode (OLED) display device according to an exemplary embodiment of the present disclosure, a first circuit structure may be located in a first portion of the blocking region and in a first circuit region, and a second circuit structure may be located in a second portion of the blocking region and in a second circuit region. When a first capacitor included in the first circuit structure is located in the blocking region, the area of ​​the first circuit region can be relatively reduced. Similarly, when a second capacitor included in the second circuit structure is located in the blocking region, the area of ​​the second circuit region can be relatively reduced. Therefore, the OLED display device can have a relatively smaller peripheral area, thus reducing the unused space of the OLED display device. Attached Figure Description

[0026] The exemplary embodiments will be understood in more detail from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 This is a plan view illustrating an organic light-emitting diode display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 2A It is shown Figure 1 An enlarged plan view of region "A" of the organic light-emitting diode display device;

[0029] Figure 2B It is shown Figure 2A An enlarged plan view of region "B";

[0030] Figure 3 This is an enlarged plan view showing an example of a first capacitor and a second capacitor included in an organic light-emitting diode display device;

[0031] Figure 4 It shows the electrical connection. Figure 1 A block diagram of the external components of an organic light-emitting diode display device;

[0032] Figure 5 It is shown Figure 2A The circuit diagram of the first circuit structure;

[0033] Figure 6 It is shown Figure 2A The circuit diagram of the second circuit structure;

[0034] Figure 7 It shows the setting Figure 1 The circuit diagram of the pixel circuit and organic light-emitting diode in the pixel area;

[0035] Figure 8 It is along Figure 1 A cross-sectional view taken along line I-I' of an organic light-emitting diode display device;

[0036] Figure 9 It is along Figure 2B A cross-sectional view taken along line II-II' of an organic light-emitting diode display device; and

[0037] Figure 10 , Figure 11 and Figures 13 to 22 This is a cross-sectional view illustrating a method of manufacturing an organic light-emitting diode display device according to an exemplary embodiment of the present disclosure. Figure 12 This is an enlarged plan view illustrating a method for manufacturing an organic light-emitting diode display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0038] In the following description, an organic light-emitting diode (OLED) display device and a method of manufacturing an OLED display device according to exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0039] As used herein, the term “may” is used to mean “one or more embodiments of the invention” when describing embodiments of the invention. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, the terms “basically,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measurements or calculations that will be recognized by one of ordinary skill in the art.

[0040] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to", "bonded to", or "adjacent to" another element or layer, the element or layer may be directly on, connected to, bonded to, or adjacent to the other element or layer, or one or more intermediate elements or layers may be present. Conversely, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to", "directly bonded to", or "immediately adjacent to" another element or layer, no intermediate elements or layers are present.

[0041] Figure 1 This is a plan view illustrating an organic light-emitting diode display device according to an exemplary embodiment of the present disclosure. Figure 2A It is shown Figure 1 An enlarged plan view of region "A" of the organic light-emitting diode display device. Figure 2B It is shown Figure 2A An enlarged plan view of region "B". Figure 3 This is an enlarged plan view showing an example of a first capacitor and a second capacitor included in an organic light-emitting diode display device. Figure 4 It shows the electrical connection. Figure 1 Block diagram of the external components of an organic light-emitting diode display device.

[0042] Reference Figure 1 , Figure 2A and Figure 2B The organic light-emitting diode (OLED) display device 100 may include a gate driver, a light-emitting signal controller, a pad electrode 470, etc., and the OLED display device 100 may have a display area 10 and a peripheral area 20 located at the periphery of the display area 10. For example, the peripheral area 20 may substantially surround the display area 10. In addition, the peripheral area 20 may include a first circuit area 21, a second circuit area 22, and a blocking area 23. The blocking area 23 may be located between the first circuit area 21 and the second circuit area 22, and the first circuit area 21 may be positioned adjacent to the display area 10.

[0043] Display area 10 may include a plurality of pixel areas 30. The pixel areas 30 may be arranged in a matrix (e.g., a matrix pattern) over the entire area of ​​display area 10. For example, Figure 7 The pixel circuit PC shown (e.g., Figure 8 The first pixel transistor 250 and the second pixel transistor 255 shown can be disposed in each of the pixel regions 30, and the organic light-emitting diode OLED (e.g., Figure 8 The pixel structure 200 shown can be disposed on the pixel circuit PC. The image can be displayed in the display area 10 via the pixel circuit PC and the organic light-emitting diode OLED.

[0044] For example, a first pixel circuit, a second pixel circuit, and a third pixel circuit can be disposed in pixel region 30. The first pixel circuit can be connected to a first organic light-emitting diode that emits red light, the second pixel circuit can be connected to a second organic light-emitting diode that emits green light, and the third pixel circuit can be connected to a third organic light-emitting diode that emits blue light.

[0045] In an example embodiment, a first organic light-emitting diode (OLED) may be stacked with a first pixel circuit, a second OLED may be stacked with a second pixel circuit, and a third OLED may be stacked with a third pixel circuit. In some embodiments, a first OLED may be stacked with a portion of the first pixel circuit and a portion of a pixel circuit different from the first pixel circuit, a second OLED may be stacked with a portion of the second pixel circuit and a portion of a pixel circuit different from the second pixel circuit, and a third OLED may be stacked with a portion of the third pixel circuit and a portion of a pixel circuit different from the third pixel circuit. For example, the first to third OLEDs may be arranged using schemes such as RGB stripes (e.g., RGB stripe patterns) in which rectangles of the same size are arranged sequentially, S-stripes (e.g., S-strip patterns) including blue OLEDs with relatively large areas, WRGB (e.g., WRGB patterns) including white OLEDs, and PenTile arrangements with an RG-GB repeating pattern (e.g., arrangements such as RGB stripes, S-stripes, WRGB, and PenTile patterns).

[0046] Additionally, at least one driving transistor, at least one switching transistor, at least one capacitor, etc., may be disposed in each of the pixel regions 30. In the example embodiment, a driving transistor (e.g., Figure 7 The first transistor TR1), and six switching transistors (e.g., Figure 7 The second to seventh transistors TR2, TR3, TR4, TR5, TR6 and TR7) and a storage capacitor (e.g., Figure 7 Storage capacitors (CSTs) can be set in each of the pixel areas 30.

[0047] Although when viewed from top, the display area 10, pixel area 30, and peripheral area 20 of the present invention are... Figure 1 The shapes shown are rectangular, but their shapes are not limited to this. For example, each of the display area 10, pixel area 30, and peripheral area 20 may have a triangular planar shape, a rhombus planar shape, a polygonal planar shape, a circular planar shape, a track (also known as a runway) planar shape, or an elliptical planar shape. For example, when viewed from a plan view, the display area 10, pixel area 30, and / or peripheral area 20 may have a triangular shape, a rhombus shape, a polygonal shape, a circular shape, a track shape, or an elliptical shape.

[0048] Multiple wirings can be provided in the peripheral area 20. For example, the wirings may include data signal wirings, gate signal wirings, light emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, power supply voltage wirings, etc. The wirings can extend from the peripheral area 20 to the display area 10 (e.g., into the display area 10) to electrically connect to the pixel circuit PC and / or electrically connect to the organic light-emitting diode OLED.

[0049] Additionally, multiple pad electrodes 470 may be disposed in the peripheral region 20 (e.g., in a portion of the peripheral region 20 below the display region 10). Figure 4 As shown, the external device 101 can be electrically connected to the organic light-emitting diode display device 100 via a flexible printed circuit board or a printed circuit board. For example, one side of the flexible printed circuit board can contact the pad electrode 470 (e.g., direct contact), and the other side of the flexible printed circuit board can contact the external device 101 (e.g., direct contact). The external device 101 can generate data signals, gate signals, light emission control signals, gate initialization signals, initialization voltages, power supply voltages, etc., and these signals can be provided to the pixel circuit PC and / or to the organic light-emitting diode OLED via the pad electrode 470 and the flexible printed circuit board. Additionally, a driver integrated circuit can be mounted on the flexible printed circuit board. In other example embodiments, the driver integrated circuit can be mounted on the organic light-emitting diode display device 100 adjacent to the pad electrode 470.

[0050] Additionally, the gate driver and the light-emitting control driver may be disposed within a portion of the peripheral region 20 (e.g., in the portion of the peripheral region 20 located to the left of the display region 10). For example, the gate driver may be positioned closer to the display region 10 than the light-emitting control driver. In other example embodiments, the gate driver and the light-emitting control driver may be disposed on the right or upper (e.g., the top side) of the display region 10 (e.g., in the portion of the peripheral region 20 located to the right or top of the display region 10), and the light-emitting control driver may be positioned closer to the display region 10 than the gate driver.

[0051] In an example embodiment, the gate driver may be disposed in a portion of the first circuit region 21 and the blocking region 23 included in the peripheral region 20, and the light emission control driver may be disposed in a portion of the second circuit region 22 and the blocking region 23 included in the peripheral region 20.

[0052] The gate driver may include multiple first circuit structures 800, and the light emission control driver may include multiple second circuit structures 600. The gate driver may receive a gate signal from the external device 101, and the gate signal may be provided to the pixel circuit PC through the first circuit structure 800 of the gate driver. In addition, the light emission control driver may receive a light emission control signal from the external device 101, and the light emission control signal may be provided to the pixel circuit PC through the second circuit structure 600.

[0053] Return to reference Figure 2A and Figure 2B The first circuit structure 800 may be disposed in the first circuit region 21 and in the first portion of the blocking region 23. The first circuit structure 800 may include at least one circuit transistor and at least one capacitor. For example, the first circuit structure 800 may have... Figure 5 The circuit structure shown includes the first to eighth transistors M1, M2, M3, M4, M5, M6, M7, and M8, as well as the first capacitor C1 and the second capacitor C2. However, the circuit construction of the first circuit structure 800 of this disclosure is not limited thereto. The first circuit structure 800 may include various suitable circuit components for generating gate signals.

[0054] In the example embodiment, Figure 5 The first capacitor C1 and / or the second capacitor C2 may be disposed in the blocking region 23. In some embodiments, Figure 5 The first to eighth transistors M1, M2, M3, M4, M5, M6, M7, and M8 can be disposed in the first circuit region 21, and Figure 5 The first capacitor C1 and / or the second capacitor C2 may be disposed in the first part of the blocking region 23. Figure 5 The first to eighth transistors M1, M2, M3, M4, M5, M6, M7, and M8 can be defined as a first circuit transistor (e.g., one of the first to eighth transistors M1, M2, M3, M4, M5, M6, M7, and M8 can be defined as...). Figure 9 The first circuit transistor 850), and Figure 5 The first capacitor C1 or the second capacitor C2 can be defined as follows: Figure 2B The first capacitor 500 is disposed in the first circuit region 21. The first circuit transistor may be disposed in the first circuit region 21, and the first capacitor 500 may be disposed in the blocking region 23 (e.g., in the first portion of the blocking region 23). In some embodiments, the first capacitor 500 may be electrically connected to the first circuit transistor, and the first capacitor 500 may be connected (e.g., directly connected) to... Figure 5Some of the first to eighth transistors M1, M2, M3, M4, M5, M6, M7, and M8. For example... Figure 2B As shown, the first capacitor 500 may include a first lower electrode 510 and a first upper electrode 520 disposed on the first lower electrode 510. The first lower electrode 510 may extend in a first direction D1 (from the first circuit region 21 to the blocking region 23) to be disposed in the blocking region 23. For example, in some embodiments, the first lower electrode 510 may extend from the first circuit region 21 in the first direction D1 to be disposed in the blocking region 23. The first upper electrode 520 may extend from the second circuit region 22 in a second direction D2 (e.g., from the second circuit region 22 to the blocking region 23) to overlap with the first lower electrode 510 in the blocking region 23. For example, a first driving power supply VGH may be provided to the first upper electrode 520, and the first driving power supply VGH wiring may be disposed in the second circuit region 22 such that the first upper electrode 520 may extend from the second circuit region 22. In other example embodiments, when the first driving power supply VGH wiring is disposed in the first circuit region 21, the first upper electrode 520 may extend from the first circuit region 21 in the first direction D1.

[0055] Additionally, the second circuit structure 600 may be disposed in the second circuit region 22 and in the second portion of the blocking region 23. The second circuit structure 600 may include at least one circuit transistor and at least one capacitor. For example, the second circuit structure 600 may have… Figure 6 The circuit structure shown may include eleventh to twentieth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20, and eleventh to thirteenth capacitors C11, C12, and C13. However, the construction of the second circuit structure 600 of this disclosure is not limited thereto. The second circuit structure 600 may include various suitable circuit components for generating light emission control signals.

[0056] In an exemplary embodiment, Figure 6 The eleventh capacitor C11, the twelfth capacitor C12, and / or the thirteenth capacitor C13 may be disposed in the blocking region 23 (e.g., in the second portion of the blocking region 23). In some embodiments, Figure 6 The eleventh to twentieth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20 can be disposed in the second circuit region 22, and Figure 6 The eleventh capacitor C11, the twelfth capacitor C12 and / or the thirteenth capacitor C13 may be disposed in the second part of the blocking area 23. Figure 6The eleventh to twentieth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20 can be defined as second circuit transistors (for example, one of the eleventh to twentieth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20 can be defined as...). Figure 9 The second circuit transistor 650); Figure 6 The eleventh capacitor C11, the twelfth capacitor C12, and / or the thirteenth capacitor C13 can be defined as follows: Figure 2B The second capacitor 700 is located in the blocking region 23; and the second capacitor 700 may be spaced apart from the first capacitor 500 in the blocking region 23 on a third direction D3 intersecting the first direction D1 and the second direction D2. For example, the second capacitor 700 may be located in the second portion of the blocking region 23, and the first capacitor 500 may be located in the first portion of the blocking region 23. In some embodiments, the second capacitor 700 may be electrically connected to the second circuit transistor and may be connected (e.g., directly connected) to... Figure 6 Some of the eleventh to twentieth transistors, M11, M12, M13, M14, M15, M16, M17, M18, M19, and M20. For example... Figure 2B As shown, the second capacitor 700 may include a second lower electrode 710 and a second upper electrode 720 disposed on the second lower electrode 710. The second lower electrode 710 may extend from the second circuit region 22 in a second direction D2 to be spaced apart from the first lower electrode 510 in a blocking region 23. The second upper electrode 720 may extend from the second circuit region 22 in the second direction D2 to overlap with the second lower electrode 710 in the blocking region 23, and the second upper electrode 720 may be spaced apart from the first upper electrode 520. For example, a first driving power supply VGH may be provided to the second upper electrode 720, and the first driving power supply VGH wiring may be disposed in the second circuit region 22 such that the second upper electrode 720 may extend from the second circuit region 22. In other example embodiments, when the first driving power supply VGH wiring is disposed in the first circuit region 21, the second upper electrode 720 may extend from the first circuit region 21 in a first direction D1.

[0057] In other example embodiments, such as Figure 3 As shown, the upper electrode 550 may be disposed on the first lower electrode 510 and on the second lower electrode 710. The upper electrode 550 may extend from the second circuit region 22 in the second direction D2 to overlap with the first lower electrode 510 and the second lower electrode 710. In some embodiments, the upper electrode 550 may have wherein... Figure 2B The first upper electrode 520 and the second upper electrode 720 are integrally formed together.

[0058] According to existing organic light-emitting diode (OLED) display devices, the gate driver can be disposed only in the first circuit region 21, and the light-emitting signal controller can be disposed only in the second circuit region 22. Simultaneously, the organic layer can be discontinuously disposed in the blocking region 23 to prevent or block residual gases based on organic materials generated during the manufacturing process of existing OLED display devices from passing through the organic layer from the peripheral region 20 (e.g., Figure 8 and Figure 9 The planarization layer 270 and the pixel definition layer 310) penetrate into the display area 10, and thus affect the pixels (e.g., Figure 8 The pixel structure 200 is damaged. In other words, the space formed by completely removing the organic layer (e.g., an opening in the organic layer) can exist in the blocking region 23. When an opening in the organic layer is formed in the blocking region 23, the area of ​​the peripheral region 20 can be relatively increased.

[0059] In an organic light-emitting diode (OLED) display device 100 according to an exemplary embodiment of the present disclosure, a first circuit structure 800 may be disposed in a first portion of a blocking region 23 and a first circuit region 21, and a second circuit structure 600 may be disposed in a second portion of a blocking region 23 and a second circuit region 22. When a first capacitor 500 included in the first circuit structure 800 is disposed in the blocking region 23, the area of ​​the first circuit region 21 may be relatively reduced (e.g., compared to when the first capacitor 500 is disposed in the first circuit region 21). Furthermore, when a second capacitor 700 included in the second circuit structure 600 is disposed in the blocking region 23, the area of ​​the second circuit region 22 may be relatively reduced (e.g., compared to when the second capacitor 700 is disposed in the second circuit region 22). Therefore, the OLED display device 100 may have a peripheral region 20 with a relatively reduced area, thereby reducing the unused space of the OLED display device 100.

[0060] Although Figure 2A A first circuit structure 800 and a second circuit structure 600 are shown corresponding in the first direction D1, but the construction of this disclosure is not limited thereto. For example, depending on the dimensions or circuit design of each of the first circuit structure 800 and the second circuit structure 600, a second circuit structure 600 may be configured to correspond to at least two first circuit structures 800 in the first direction D1, or a first circuit structure 800 may be configured to correspond to at least two second circuit structures 600 in the first direction D1. In this case, it is possible to... Figure 2B At least three capacitors should be installed.

[0061] Figure 5 It is shown Figure 2AThe circuit diagram of the first circuit structure.

[0062] Reference Figure 5 The first circuit structure 800 may include a first driver 1210, a second driver 1220, an output unit 1230, and a first transistor M1.

[0063] Output unit 1230 may include a fifth transistor M5 and a sixth transistor M6. Output unit 1230 may control the voltage supplied to output terminal 1004 based on the voltages of the first node N1 and the second node N2. The fifth transistor M5 may be connected between the first drive power supply VGH wiring (e.g., a high-power voltage wiring) and output terminal 1004, and the gate electrode of the fifth transistor M5 may be connected to the first node N1. The fifth transistor M5 may control the connection between the first drive power supply VGH wiring and output terminal 1004 based on the voltage applied to the first node N1. The sixth transistor M6 may be connected between output terminal 1004 and fourth input terminal 1005, and the gate electrode of the sixth transistor M6 may be connected to the second node N2. The sixth transistor M6 may control the connection between output terminal 1004 and fourth input terminal 1005 based on the voltage applied to the second node N2. Output unit 1230 may be driven as a buffer. In some embodiments, the fifth transistor M5 and / or the sixth transistor M6 may have a configuration in which multiple transistors are connected in parallel.

[0064] The first driver 1210 may include a second transistor M2, a third transistor M3, and a fourth transistor M4. The first driver 1210 can control the voltage of the third node N3 based on clock signals supplied to the first input terminal 1001, the second input terminal 1002, and the third input terminal 1003. The second transistor M2 may be connected between the first input terminal 1001 and the third node N3, and the gate electrode of the second transistor M2 may be connected to the second input terminal 1002. The second transistor M2 can control the connection between the first input terminal 1001 and the third node N3 based on the clock signal supplied to the second input terminal 1002. The third transistor M3 and the fourth transistor M4 may be connected in series between the third node N3 and the first drive power supply VGH wiring. The third transistor M3 may be connected between the fourth transistor M4 and the third node N3, and the gate electrode of the third transistor M3 may be connected to the third input terminal 1003. The third transistor M3 can control the connection between the fourth transistor M4 and the third node N3 based on the clock signal supplied to the third input terminal 1003. A fourth transistor M4 can be connected between the third transistor M3 and the first drive power supply VGH wiring, and the gate electrode of the fourth transistor M4 can be connected to the first node N1. The fourth transistor M4 can control the connection between the third transistor M3 and the first drive power supply VGH wiring based on the voltage of the first node N1.

[0065] The second driver 1220 may include a seventh transistor M7, an eighth transistor M8, a first capacitor C1, and a second capacitor C2. The second driver 1220 can control the voltage of the first node N1 based on the voltage at the second input terminal 1002 and the third node N3. The first capacitor C1 may be connected between the second node N2 and the output terminal 1004. The first capacitor C1 may be charged based on the on / off state of the sixth transistor M6. The second capacitor C2 may be connected between the first node N1 and the first drive power supply VGH wiring. The second capacitor C2 may be charged with the voltage applied to the first node N1. The seventh transistor M7 may be connected between the first node N1 and the second input terminal 1002, and the gate electrode of the seventh transistor M7 may be connected to the third node N3. The seventh transistor M7 can control the connection between the first node N1 and the second input terminal 1002 based on the voltage at the third node N3. The eighth transistor M8 may be connected between the first node N1 and the second drive power supply VGL wiring (e.g., a low-power voltage wiring), and the gate electrode of the eighth transistor M8 may be connected to the second input terminal 1002. The eighth transistor M8 can control the connection between the first node N1 and the second drive power supply VGL wiring based on the clock signal at the second input terminal 1002. The first transistor M1 can be connected between the third node N3 and the second node N2, and the gate electrode of the first transistor M1 can be connected to the second drive power supply VGL wiring. The first transistor M1 can maintain the electrical connection between the third node N3 and the second node N2 while remaining in an on state. In some embodiments, the first transistor M1 can limit the voltage drop of the third node N3 based on the voltage of the second node N2. In some embodiments, even when the voltage of the second node N2 drops below the voltage of the second drive power supply VGL, the voltage of the third node N3 can be no lower than the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the second drive power supply VGL.

[0066] Therefore, the first circuit structure 800 can transmit the gate signal (e.g., Figure 7 The gate signal GW is output to the output terminal 1004.

[0067] As described above, in the example embodiment, the first to eighth transistors M1, M2, M3, M4, M5, M6, M7 and M8 can be disposed in the first circuit region 21, and the first capacitor C1 and / or the second capacitor C2 can be disposed in the first part of the blocking region 23.

[0068] Although the first circuit structure 800 has been described as including eight transistors and two capacitors, the construction of the first circuit structure 800 of this disclosure is not limited thereto. For example, the first circuit structure 800 may be constructed to have at least one transistor and at least one capacitor.

[0069] Figure 6 It is shown Figure 2A The circuit diagram of the second circuit structure.

[0070] Reference Figure 6 The second circuit structure 600 may include a first signal processor 2100, a second signal processor 2200, a third signal processor 2300, and an output unit 2400.

[0071] The first signal processor 2100 may include an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The first signal processor 2100 can control the voltages of the twenty-second node N22 and the twenty-first node N21 based on signals supplied to the first input terminal 2001 and the second input terminal 2002. The eleventh transistor M11 may be connected between the first input terminal 2001 and the twenty-first node N21, and the gate electrode of the eleventh transistor M11 may be connected to the second input terminal 2002. The eleventh transistor M11 may be turned on when a clock signal is supplied to the second input terminal 2002. The twelfth transistor M12 may be connected between the second input terminal 2002 and the twenty-second node N22, and the gate electrode of the twelfth transistor M12 may be connected to the twenty-first node N21. The twelfth transistor M12 may be turned on or off based on the voltage of the twenty-first node N21. The thirteenth transistor M13 may be connected between the second drive power supply VGL wiring and the twenty-second node N22, and the gate electrode of the thirteenth transistor M13 may be connected to the second input terminal 2002. The thirteenth transistor M13 can be turned on when the clock signal is supplied to the second input terminal 2002.

[0072] The second signal processor 2200 may include a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eleventh capacitor C11, and a twelfth capacitor C12. The second signal processor 2200 can control the voltages of the twenty-first node N21 and the twenty-third node N23 based on a clock signal supplied to the third input terminal 2003 and the voltage of the twenty-first node N22. The fourteenth transistor M14 may be connected between the fifteenth transistor M15 and the twenty-first node N21, and the gate electrode of the fourteenth transistor M14 may be connected to the third input terminal 2003. The fourteenth transistor M14 may be turned on when a clock signal is supplied to the third input terminal 2003. The fifteenth transistor M15 may be connected between the first drive power supply VGH wiring and the fourteenth transistor M14, and the gate electrode of the fifteenth transistor M15 may be connected to the twenty-second node N22. The fifteenth transistor M15 may be turned on or off based on the voltage of the twenty-second node N22. The sixteenth transistor M16 can be connected between the first electrode of the seventeenth transistor M17 and the third input terminal 2003, and the gate electrode of the sixteenth transistor M16 can be connected to the twenty-second node N22. The sixteenth transistor M16 can be turned on or off based on the voltage of the twenty-second node N22. The seventeenth transistor M17 can be connected between the first electrode of the sixteenth transistor M16 and the twenty-third node N23, and the gate electrode of the seventeenth transistor M17 can be connected to the third input terminal 2003. The seventeenth transistor M17 can be turned on when a clock signal is supplied to the third input terminal 2003. The eleventh capacitor C11 can be connected between the twenty-first node N21 and the third input terminal 2003. The twelfth capacitor C12 can be connected between the twenty-second node N22 and the first electrode of the seventeenth transistor M17.

[0073] The third signal processor 2300 may include an eighteenth transistor M18 and a thirteenth capacitor C13. The third signal processor 2300 can control the voltage of the twenty-third node N23 based on the voltage of the twenty-first node N21. The eighteenth transistor M18 may be connected between the first drive power supply VGH wiring and the twenty-third node N23, and the gate electrode of the eighteenth transistor M18 may be connected to the twenty-first node N21. The eighteenth transistor M18 may be turned on or off based on the voltage of the twenty-first node N21. The thirteenth capacitor C13 may be connected between the first drive power supply VGH wiring and the twenty-third node N23.

[0074] Output unit 2400 may include a nineteenth transistor M19 and a twentieth transistor M20. Output unit 2400 may control the voltage supplied to output terminal 2004 based on the voltages of the twenty-first node N21 and the twenty-third node N23. Nineteenth transistor M19 may be connected between the first drive power supply VGH wiring and output terminal 2004, and the gate electrode of nineteenth transistor M19 may be connected to the twenty-third node N23. Nineteenth transistor M19 may be turned on or off based on the voltage of the twenty-third node N23. Twentieth transistor M20 may be connected between output terminal 2004 and the second drive power supply VGL wiring, and the gate electrode of twenty-tenth transistor M20 may be connected to the twenty-first node N21. Twentieth transistor M20 may be turned on or off based on the voltage of the twenty-first node N21. Output unit 2400 may be driven as a buffer. In some embodiments, nineteenth transistor M19 and / or twentieth transistor M20 may have a configuration in which multiple transistors are connected in parallel. For example, in some embodiments, each of the nineteenth transistor M19 and the twentieth transistor M20 may be provided as a plurality of transistors connected in parallel.

[0075] Therefore, the second circuit structure 600 can transmit the light emission control signal (e.g., Figure 7 The light emission control signal (EM) is output to the output terminal 2004.

[0076] As described above, in the example embodiment, the eleventh to twentieth transistors M11, M12, M13, M14, M15, M16, M17, M18, M19 and M20 can be disposed in the second circuit region 22, and the eleventh capacitor C11, the twelfth capacitor C12 and / or the thirteenth capacitor C13 can be disposed in the second part of the blocking region 23.

[0077] Although the second circuit structure 600 has been described as including ten transistors and three capacitors, the construction of the second circuit structure 600 of this disclosure is not limited thereto. For example, the second circuit structure 600 may be constructed to have at least one transistor and at least one capacitor.

[0078] Figure 7 It shows the setting Figure 1 The circuit diagram of the pixel circuit and organic light-emitting diode in the pixel area.

[0079] Reference Figure 7The pixel circuit PC and the organic light-emitting diode (OLED) can be disposed in each of the pixel regions 30 of the organic light-emitting diode display device 100. In each of the pixel regions 30, a pixel circuit PC may include first transistors to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6 and TR7, and a storage capacitor CST (e.g., Figure 8 The transistors include a storage capacitor 180), high supply voltage ELVDD wiring, low supply voltage ELVSS wiring, initialization voltage VINT wiring, data signal DATA wiring, gate signal GW wiring, gate initialization signal GI wiring, light emission control signal EM wiring, diode initialization signal GB wiring, etc. The first transistor TR1 can correspond to a driving transistor, and each of the second to seventh transistors TR2, TR3, TR4, TR5, TR6, and TR7 can correspond to a switching transistor. Each of the first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7 may include a first terminal, a second terminal, a channel, and a gate terminal. In an example embodiment, the first terminal may be a source terminal, and the second terminal may be a drain terminal. In some embodiments, the first terminal may be a drain terminal, and the second terminal may be a source terminal.

[0080] Organic light-emitting diodes (OLEDs) can output light based on a drive current ID. An OLED may include a first terminal and a second terminal. In an example embodiment, the second terminal of the OLED may be supplied with a low supply voltage ELVSS, and the first terminal may be supplied with a high supply voltage ELVDD. For example, the first terminal of the OLED may be an anode terminal, and the second terminal may be a cathode terminal. In some embodiments, the first terminal of the OLED may be a cathode terminal, and the second terminal may be an anode terminal. In an example embodiment, the anode terminal of the OLED may correspond to... Figure 8 The first electrode 290, the cathode terminal of the organic light-emitting diode OLED, can correspond to Figure 8 and Figure 9 The second electrode 340.

[0081] The first transistor TR1 can generate a drive current ID. In an example embodiment, the first transistor TR1 can operate in the saturation region. In this case, the first transistor TR1 can generate the drive current ID based on the voltage difference between the gate terminal and the source terminal. Alternatively, the hue wedge (or gray level) can be expressed based on the magnitude of the drive current ID supplied to the OLED. In some embodiments, the first transistor TR1 can operate in the linear region. In this case, the hue wedge (or gray level) can be expressed based on the sum of the times the drive current is supplied to the OLED within a frame.

[0082] The gate terminal of the second transistor TR2 can be supplied with a gate signal GW. For example, it can be supplied from the gate driver. Figure 2A The first circuit structure 800 provides a gate signal GW, which can be applied to the gate terminal of the second transistor TR2 via gate signal GW wiring. A data signal DATA can be supplied to the first terminal of the second transistor TR2. A second terminal of the second transistor TR2 can be connected to the first terminal of the first transistor TR1. For example, the gate signal GW can be provided from a gate drive unit and applied to the gate terminal of the second transistor TR2 via gate signal GW wiring. The second transistor TR2 can supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the gate signal GW (e.g., when the gate signal GW is applied to the gate signal GW wiring period). In this case, the second transistor TR2 can operate in the linear region.

[0083] The third transistor TR3 (for example, Figure 8 The gate terminal of the first pixel transistor 250 can receive the gate signal GW. For example, it can be received from the gate driver included in the first pixel transistor 250. Figure 2A The first circuit structure 800 provides a gate signal GW, which can be applied to the gate terminal of a third transistor TR3 via gate signal GW wiring. The first terminal of the third transistor TR3 can be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 can be connected to the second terminal of the first transistor TR1. During the active period of the gate signal GW, the third transistor TR3 can connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1. In this case, the third transistor TR3 can operate in the linear region. Therefore, the third transistor TR3 can diode-connect the first transistor TR1 during the active period of the gate signal GW.

[0084] The initialization voltage VINT wiring, which is provided with the initialization voltage VINT, can be connected to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7.

[0085] The gate terminal of the fourth transistor TR4 can be supplied with a gate initialization signal GI. The first terminal of the fourth transistor TR4 can be supplied with an initialization voltage VINT. The second terminal of the fourth transistor TR4 can be connected to the gate terminal of the first transistor TR1.

[0086] The fourth transistor TR4 can supply an initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI (e.g., when the gate initialization signal GI is applied to the wiring of the gate initialization signal GI). In this case, the fourth transistor TR4 can operate in the linear region. Therefore, the fourth transistor TR4 can initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an example embodiment, the initialization voltage VINT can have a voltage level sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT can be supplied to the gate terminal of the first transistor TR1. In other example embodiments, the initialization voltage can have a voltage level sufficiently higher than the voltage level of the data signal held by the storage capacitor in the previous frame, and the initialization voltage can be supplied to the gate terminal of the first transistor.

[0087] The gate terminal of the fifth transistor TR5 can be supplied with a light-emitting control signal EM. For example, this signal can be supplied from a driver included in the light-emitting control circuit. Figure 2AThe second circuit structure 600 provides a light-emitting control signal EM, which can be applied to the gate terminal of a fifth transistor TR5 via a light-emitting control signal EM wiring. The first terminal of the fifth transistor TR5 can be connected to a high supply voltage ELVDD wiring. The second terminal of the fifth transistor TR5 can be connected to the first terminal of the first transistor TR1. The fifth transistor TR5 can supply the high supply voltage ELVDD to the first terminal of the first transistor TR1 during the active period of the light-emitting control signal EM (e.g., when the light-emitting control signal EM is applied to the light-emitting control signal EM wiring). The fifth transistor TR5 can block the supply of the high supply voltage ELVDD during the inactive period of the light-emitting control signal EM (e.g., when the light-emitting control signal EM is not applied to the light-emitting control signal EM wiring). In this case, the fifth transistor TR5 can operate in the linear region. The fifth transistor TR5 can supply the high supply voltage ELVDD to the first terminal of the first transistor TR1 during the active period of the light-emitting control signal EM, allowing the first transistor TR1 to generate a drive current ID. In addition, the fifth transistor TR5 can block the supply of high power supply voltage ELVDD during the inactive period of the light emission control signal EM, so that the data signal DATA supplied to the first terminal of the first transistor TR1 can be supplied to the gate terminal of the first transistor TR1.

[0088] The sixth transistor TR6 (for example, Figure 8 The gate terminal of the second pixel transistor 255 can receive the light emission control signal EM. For example, it can be received from the light emission control driver. Figure 2AThe second circuit structure 600 provides a light emission control signal EM, which can be applied to the gate terminal of a sixth transistor TR6 via wiring. The first terminal of the sixth transistor TR6 can be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 can be connected to the first terminal of an organic light-emitting diode (OLED). During the active period of the light emission control signal EM, the sixth transistor TR6 can supply the drive current ID generated by the first transistor TR1 to the OLED. In this case, the sixth transistor TR6 can operate in the linear region. In some embodiments, the sixth transistor TR6 can supply the drive current ID generated by the first transistor TR1 to the OLED during the active period of the light emission control signal EM, allowing the OLED to output light. Additionally, during the inactive period of the light emission control signal EM, the sixth transistor TR6 electrically isolates the first transistor TR1 and the OLED from each other, allowing the data signal DATA (more precisely, a data signal compensated for the threshold voltage) supplied to the second terminal of the first transistor TR1 to be supplied to the gate terminal of the first transistor TR1.

[0089] The gate terminal of the seventh transistor TR7 can be supplied with a diode initialization signal GB. The first terminal of the seventh transistor TR7 can be supplied with an initialization voltage VINT. The second terminal of the seventh transistor TR7 can be connected to the first terminal of the organic light-emitting diode (OLED). The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the OLED during the activation period of the diode initialization signal GB (e.g., when the diode initialization signal GB is applied to the wiring of the diode initialization signal GB). In this case, the seventh transistor TR7 can operate in the linear region. In some embodiments, the seventh transistor TR7 can initialize the first terminal of the OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0090] Storage capacitors CST (e.g., Figure 8The storage capacitor 180 may include a first terminal and a second terminal. The storage capacitor CST may be connected between the high supply voltage ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high supply voltage ELVDD wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the inactive period of the gate signal GW (e.g., when the gate signal GW is not applied to the gate signal GW wiring). The inactive period of the gate signal GW may include the active period of the light emission control signal EM (e.g., may overlap with the active period of the light emission control signal EM in time), and the drive current ID generated by the first transistor TR1 during the active period of the light emission control signal EM may be supplied to the organic light-emitting diode OLED. Therefore, the drive current ID generated by the first transistor TR1 may be supplied to the organic light-emitting diode OLED based on the voltage level maintained by the storage capacitor CST.

[0091] Although the pixel circuit PC of this disclosure has been described as including seven transistors and a storage capacitor, the construction of the pixel circuit PC of this disclosure is not limited thereto. For example, the pixel circuit PC may be constructed to include at least one transistor and at least one storage capacitor.

[0092] Figure 8 It is along Figure 1 A cross-sectional view taken along line I-I' of an organic light-emitting diode display device. Figure 9 It is along Figure 2B A cross-sectional view taken along line II-II' of the organic light-emitting diode display device.

[0093] Reference Figure 8 and Figure 9The organic light-emitting diode (OLED) display device 100 may include a substrate 110, a buffer layer 115, a first pixel transistor 250, a second pixel transistor 255, a storage capacitor 180, a first circuit transistor 850, a second circuit transistor 650, a first capacitor 500, a first gate insulating layer 150, a second gate insulating layer 155, an insulating intermediate layer 190, a planarization layer 270, a pixel defining layer 310, a connecting electrode 295, a pixel structure 200, a thin-film encapsulation structure 450, etc. The first pixel transistor 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230. The second pixel transistor 255 may include a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. Additionally, the first circuit transistor 850 may include a first active pattern 730, a first gate pattern 770, a first source pattern 810, and a first drain pattern 830; the second circuit transistor 650 may include a second active pattern 530, a second gate pattern 570, a second source pattern 610, and a second drain pattern 630. Furthermore, the storage capacitor 180 may include a lower gate pattern 177 and an upper gate pattern 179; the first capacitor 500 may include a first lower electrode 510 and a first upper electrode 520. Additionally, the pixel structure 200 may include a first electrode 290, a light-emitting layer 330, and a second electrode 340; and the thin-film encapsulation structure 450 may include a first inorganic thin-film encapsulation layer 451, an organic thin-film encapsulation layer 452, and a second inorganic thin-film encapsulation layer 453.

[0094] A substrate 110 comprising, for example, a transparent or opaque material may be provided. The substrate 110 may be formed from a flexible transparent resin substrate. For example, the substrate 110 may be configured such that a first organic layer, a first barrier layer, a second organic layer, and a second barrier layer are sequentially laminated. The first and second barrier layers may comprise, for example, inorganic materials such as silicon oxide, and may prevent moisture and / or water from penetrating or permeating through the first and second organic layers. Additionally, the first and second organic layers may comprise, for example, organic materials such as polyimide resin, and may be flexible.

[0095] The organic light-emitting diode (OLED) display device 100 includes a display area 10 and a peripheral area 20 (the peripheral area 20 includes a first circuit area 21, a second circuit area 22, and a blocking area 23), such that the substrate 110 can also be divided into the display area 10 and the peripheral area 20 (e.g., it may have portions corresponding to the display area 10 and the peripheral area 20), such as... Figure 8 and Figure 9 As shown in the image.

[0096] In some embodiments, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc.

[0097] Although substrate 110 has been described as having four layers, the construction of substrate 110 in this disclosure is not limited thereto. For example, in other example embodiments, substrate 110 may consist of a single layer or multiple layers.

[0098] A buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may be disposed on the substrate 110 over the entire area of ​​the display area 10 and the peripheral area 20. Depending on the type or kind of the substrate 110, two or more buffer layers 115 may be disposed on the substrate 110, or no buffer layer 115 may be disposed on the substrate 110. For example, in some embodiments, depending on the type or kind of the substrate 110, the buffer layer 115 may be omitted. The buffer layer 115 may include (e.g., it may be) silicides, metal oxides, etc. For example, the buffer layer 115 may include (e.g., it may be) silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), etc.

[0099] The first active layer 130 and the second active layer 135 may be disposed on the buffer layer 115 in the display area 10, and the first active pattern 730 and the second active pattern 530 may be disposed on the buffer layer 115 in the peripheral area 20. In some embodiments, the first active layer 130 and the second active layer 135 may be spaced apart from each other in the display area 10, the first active pattern 730 may be located in the first circuit area 21, and the second active pattern 530 may be located in the second circuit area 22. Each of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 may include (e.g., may be) an oxide semiconductor, an inorganic semiconductor (such as amorphous silicon and / or polycrystalline silicon), an organic semiconductor, etc. Each of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 may have a source region, a drain region, and a channel region located between the source region and the drain region.

[0100] A first gate insulating layer 150 may be disposed on a first active layer 130, a second active layer 135, a first active pattern 730, and a second active pattern 530. The first gate insulating layer 150 may cover the first active layer 130 and the second active layer 135 in the display area 10 on a buffer layer 115, and may extend from the display area 10 to a peripheral area 20 (e.g., into the peripheral area 20) to cover the first active pattern 730 in the first circuit area 21 and the second active pattern 530 in the second circuit area 22. For example, the first gate insulating layer 150 may sufficiently cover the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 on the buffer layer 115, and may have a substantially flat surface (e.g., a substantially flat top surface) without creating steps around the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530. In some embodiments, the first gate insulating layer 150, while covering the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 on the buffer layer 115, may be configured to have a uniform thickness along the contours of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 (e.g., above and / or around the top surfaces of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530). The first gate insulating layer 150 may include (e.g., may be) silicide, metal oxide, etc. In other example embodiments, the first gate insulating layer 150 may have a multilayer structure comprising multiple insulating layers. The insulating layers may have different materials and different thicknesses.

[0101] The first gate electrode 170 and the second gate electrode 175 can be disposed on the first gate insulating layer 150 in the display area 10, and the first gate pattern 770 and the second gate pattern 570 can be disposed in the peripheral area 20. In some embodiments, the first gate electrode 170 may be disposed on a portion of the first gate insulating layer 150 below which the first active layer 130 is positioned (e.g., it may be configured to be superimposed on the channel region of the first active layer 130); the second gate electrode 175 may be disposed on a portion of the first gate insulating layer 150 below which the second active layer 135 is positioned (e.g., it may be superimposed on the channel region of the second active layer 135); the first gate pattern 770 may be disposed on a portion of the first gate insulating layer 150 below which the first active pattern 730 is positioned (e.g., it may be superimposed on the channel region of the first active pattern 730); and the second gate pattern 570 may be disposed on a portion of the first gate insulating layer 150 below which the second active pattern 530 is positioned (e.g., it may be superimposed on the channel region of the second active pattern 530). Each of the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, and the second gate pattern 570 may include (for example,) a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In other example embodiments, each of the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, and the second gate pattern 570 may have a multilayer structure comprising multiple metal layers. The metal layers may have different materials and different thicknesses.

[0102] A lower gate pattern 177 may be disposed on the first gate insulating layer 150 in the display area 10, and a first lower electrode 510 may be disposed on the first gate insulating layer 150 in the blocking area 23. In some embodiments, the lower gate pattern 177 may be spaced apart from the first gate electrode 170 and the second gate electrode 175, and the first lower electrode 510 may be spaced apart from the first gate pattern 770 and the second gate pattern 570. In an example embodiment, the lower gate pattern 177 and the first lower electrode 510 may be positioned on the same layer as the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, and the second gate pattern 570. Each of the lower gate pattern 177 and the first lower electrode 510 may include (e.g., a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.). For example, each of the lower gate pattern 177 and the first lower electrode 510 may include (e.g., may be) gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), aluminum-containing alloys, aluminum nitride (AlN).x ), alloys containing silver, tungsten nitride (WN) x ), alloys containing copper, alloys containing molybdenum, titanium nitride (TiN) x ), Chromium nitride (CrN) x ), Tantalum nitride (TaN) x ), SrRuO x O y ), zinc oxide (ZnO) x Indium tin oxide (ITO), tin oxide (SnO) x Indium oxide (InO) x Gallium oxide (GaO) x Indium zinc oxide (IZO), etc. In other example embodiments, each of the lower gate pattern 177 and the first lower electrode 510 may have a multilayer structure comprising multiple metal layers. The metal layers may have different materials and different thicknesses.

[0103] The second gate insulating layer 155 may be disposed on the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510. The second gate insulating layer 155 may cover the first gate electrode 170, the second gate electrode 175, and the lower gate pattern 177 in the display area 10 on the first gate insulating layer 150, and may extend from the display area 10 to the peripheral area 20 (e.g., into the peripheral area 20) to cover the first gate pattern 770 in the first circuit area 21, the second gate pattern 570 in the second circuit area 22, and the first lower electrode 510 in the blocking area 23. For example, the second gate insulating layer 155 may sufficiently cover the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510 on the first gate insulating layer 150, and may have a substantially flat surface (e.g., a substantially flat top surface) without creating steps around the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510. In some embodiments, while the second gate insulating layer 155 covers the first gate insulating layer 150, the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510, it may be configured to have a uniform thickness along the contours of the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510 (e.g., above and / or around the top surfaces of the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510). The second gate insulating layer 155 may include (e.g., may be) one or more silicides, one or more metal oxides, etc. In other example embodiments, the second gate insulating layer 155 may have a multilayer structure comprising multiple insulating layers. The insulating layers may have different materials and different thicknesses.

[0104] An upper gate pattern 179 may be disposed on the second gate insulating layer 155 in the display area 10, and a first upper electrode 520 may be disposed on the second gate insulating layer 155 in the blocking area 23. In some embodiments, the upper gate pattern 179 may be disposed on a portion of the second gate insulating layer 155 below which a lower gate pattern 177 is positioned (e.g., the upper gate pattern 179 may be superimposed on the lower gate pattern 177), and the first upper electrode 520 may be disposed on a portion of the second gate insulating layer 155 below which a first lower electrode 510 is positioned (e.g., the first upper electrode 520 may be superimposed on the first lower electrode 510). In an example embodiment, the first upper electrode 520 may be positioned on the same layer as the upper gate pattern 179. Each of the upper gate pattern 179 and the first upper electrode 520 may include (e.g., may be) a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In other example embodiments, each of the upper gate pattern 179 and the first upper electrode 520 may have a multilayer structure including multiple metal layers. The metal layers can have different materials and different thicknesses. Therefore, a storage capacitor 180 including a lower gate pattern 177 and an upper gate pattern 179 can be provided, and a first capacitor 500 including a first lower electrode 510 and a first upper electrode 520 can be provided.

[0105] An insulating intermediate layer 190 may be disposed on the upper gate pattern 179 and the first upper electrode 520. The insulating intermediate layer 190 may cover the upper gate pattern 179 in the display region 10 on the second gate insulating layer 155 and may extend from the display region 10 to the peripheral region 20 (e.g., into the peripheral region 20) to cover the first upper electrode 520 in the blocking region 23. For example, the insulating intermediate layer 190 may sufficiently cover the upper gate pattern 179 and the first upper electrode 520 on the second gate insulating layer 155 and may have a substantially flat surface (e.g., a substantially flat top surface) without creating steps around the upper gate pattern 179 and the first upper electrode 520. In some embodiments, while covering the upper gate pattern 179 and the first upper electrode 520 on the second gate insulating layer 155, the insulating intermediate layer 190 may be configured to have a uniform thickness along the contours of the upper gate pattern 179 and the first upper electrode 520 (e.g., above and / or around the top surfaces of the upper gate pattern 179 and the first upper electrode 520). The insulating interlayer 190 may include (for example,) one or more silicides, one or more metal oxides, etc. In other example embodiments, the insulating interlayer 190 may have a multilayer structure comprising multiple insulating layers. The insulating layers may have different materials and different thicknesses.

[0106] The first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 can be disposed on the insulating intermediate layer 190 in the display area 10, and the first source pattern 810, the first drain pattern 830, the second source pattern 610, and the second drain pattern 630 can be disposed on the insulating intermediate layer 190 in the peripheral area 20. The first source electrode 210 can be connected to the source region of the first active layer 130 through a contact hole (e.g., a contact hole formed by removing a first portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190), and the first drain electrode 230 can be connected to the drain region of the first active layer 130 through a contact hole (e.g., a contact hole formed by removing a second portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190). The second source electrode 215 can be connected to the source region of the second active layer 135 through a contact hole (e.g., a contact hole formed by removing a third portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190), and the second drain electrode 235 can be connected to the drain region of the second active layer 135 through a contact hole (e.g., a contact hole formed by removing a fourth portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190). The first source pattern 810 can be connected to the source region of the first active pattern 730 through a contact hole (e.g., a contact hole formed by removing a fifth portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190), and the first drain pattern 830 can be connected to the drain region of the first active pattern 730 through a contact hole (e.g., a contact hole formed by removing a sixth portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190). The second source pattern 610 can be connected to the source region of the second active pattern 530 through a contact hole (e.g., a contact hole formed by removing the seventh portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190), and the second drain pattern 630 can be connected to the drain region of the second active pattern 530 through a contact hole (e.g., a contact hole formed by removing the eighth portion of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190).

[0107] Each of the first source electrode 210, first drain electrode 230, second source electrode 215, second drain electrode 235, first source pattern 810, first drain pattern 830, second source pattern 610, and second drain pattern 630 may include (e.g., may be) a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In other example embodiments, each of the first source electrode 210, first drain electrode 230, second source electrode 215, second drain electrode 235, first source pattern 810, first drain pattern 830, second source pattern 610, and second drain pattern 630 may have a multilayer structure including multiple layers (e.g., multiple metal layers). The metal layers may have different materials and different thicknesses.

[0108] Therefore, a first pixel transistor 250 including a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230 can be provided; a second pixel transistor 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235 can be provided; a first circuit transistor 850 including a first active pattern 730, a first gate pattern 770, a first source pattern 810, and a first drain pattern 830 can be provided; and a second circuit transistor 650 including a second active pattern 530, a second gate pattern 570, a second source pattern 610, and a second drain pattern 630 can be provided.

[0109] A planarization layer 270 may be disposed on the first source electrode 210, the first drain electrode 230, the second source electrode 215, the second drain electrode 235, the first source pattern 810, the first drain pattern 830, the second source pattern 610, and the second drain pattern 630. The planarization layer 270 may cover the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 in the display area 10 on the insulating interlayer 190, and may extend into the peripheral area 20 (e.g., into the peripheral area 20) to cover the first source pattern 810 and the first drain pattern 830 in the first circuit area 21 and the second source pattern 610 and the second drain pattern 630 in the second circuit area 22. In an example embodiment, the planarization layer 270 may have a first opening 271 in the blocking area 23 exposing the top surface of the insulating interlayer 190 (see...). Figure 16 Therefore, the planarization layer 270 may not be provided in the blocking region 23. The first opening 271 may be positioned to overlap with the first capacitor 500, and may be positioned to... Figure 2B The second capacitor 700 is stacked. The connecting electrode 295 can contact the insulating intermediate layer 190 through the first opening 271.

[0110] The planarization layer 270 may have a relatively thick (e.g., large) thickness in the display area 10 and the peripheral area 20. In this case, the planarization layer 270 may have a substantially flat upper surface (e.g., a substantially flat top surface), and a planarization process may be applied to the planarization layer 270 to achieve the substantially flat upper surface of the planarization layer 270. In some embodiments, the planarization layer 270 may be configured on the insulating intermediate layer 190 to have a uniform thickness in the display region 10 and the peripheral region 20 along the contours of the first source electrode 210, the first drain electrode 230, the second source electrode 215, the second drain electrode 235, the first source pattern 810, the first drain pattern 830, the second source pattern 610, and the second drain pattern 630 (e.g., above and / or around the top surfaces of the first source electrode 210, the first drain electrode 230, the second source electrode 215, the second drain electrode 235, the first source pattern 810, the first drain pattern 830, the second source pattern 610, and the second drain pattern 630). The planarization layer 270 may be formed of an organic or inorganic material. In an example embodiment, the planarization layer 270 may include (e.g., may be) an organic material. For example, the planarization layer 270 may include (for example, it may be) a photoresist, a polyacrylamide resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylamide resin, an epoxy resin, etc.

[0111] A first electrode 290 may be disposed on the planarization layer 270 in the display area 10. The first electrode 290 may be connected to a second drain electrode 235 via a contact hole (e.g., a contact hole formed by removing a portion of the planarization layer 270), and the first electrode 290 may be electrically connected to a second pixel transistor 255. The first electrode 290 may include (e.g., a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc.). In other example embodiments, the first electrode 290 may have a multilayer structure comprising multiple layers (e.g., multiple metal layers). The metal layers may have different materials and different thicknesses.

[0112] The connecting electrode 295 can be disposed on the planarization layer 270 in the peripheral region 20. The connecting electrode 295 can contact the insulating intermediate layer 190 through the first opening 271, and can also contact the insulating intermediate layer 190 through the second opening 311 (see...). Figure 18The connection electrode 295 is in contact with the second electrode 340. The connection electrode 295 may contact the low-power supply voltage ELVSS wiring in the peripheral region 20 and may receive the low-power supply voltage ELVSS from the low-power supply voltage ELVSS wiring. The connection electrode 295 contacts the second electrode 340 in the blocking region 23, such that the low-power supply voltage ELVSS applied to the connection electrode 295 can be transmitted to the second electrode 340. The connection electrode 295 may include (e.g., may be) a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In other example embodiments, the connection electrode 295 may have a multilayer structure comprising multiple layers (e.g., multiple metal layers). The metal layers may have different materials and different thicknesses.

[0113] The pixel defining layer 310 may expose a portion (e.g., a central portion) of the first electrode 290 in the display region 10 on the planarization layer 270, and may extend from the display region 10 to the peripheral region 20 (e.g., into the peripheral region 20) to be disposed in the first circuit region 21 and the second circuit region 22. In an example embodiment, the pixel defining layer 310 may have a second opening 311 in the blocking region 23 that overlaps with the first opening 271 (see...). Figure 18 Therefore, the pixel defining layer 310 may not be disposed in the blocking region 23. The second electrode 340 can contact the connecting electrode 295 through the second opening 311. Additionally, the width of the first opening 271 may be smaller than the width of the second opening 311. The pixel defining layer 310 may be formed of organic or inorganic materials. In an example embodiment, the pixel defining layer 310 may include (e.g., may be) an organic material.

[0114] A light-emitting layer 330 may be disposed in the display area 10 on a first electrode 290 partially exposed by a pixel-defining layer 310. The light-emitting layer 330 may be formed using at least one of light-emitting materials capable of emitting different colors of light (such as red, green, and blue light) depending on the pixel (e.g., it may be formed from at least one of light-emitting materials capable of emitting different colors of light (such as red, green, and blue light) depending on the pixel). In some embodiments, the light-emitting layer 330 may be formed by laminating multiple light-emitting materials capable of producing different colors of light, such as red, green, and blue light, so that white light can be emitted overall. In this case, a color filter may be disposed on the light-emitting layer 330. The color filter may include at least one selected from a red color filter, a green color filter, and a blue color filter. In some embodiments, the color filter may also include a yellow color filter, a cyan color filter, and / or a magenta color filter. The color filter may include (e.g., it may be) a photosensitive resin and / or a colored photoresist.

[0115] The second electrode 340 may be disposed on the pixel defining layer 310 and the light-emitting layer 330 in the display area 10, and may extend into the peripheral area 20 (e.g., into the peripheral area 20) to overlap with the first opening 271 and the second opening 311 in the peripheral area 20. In an example embodiment, the second electrode 340 may contact the connecting electrode 295 through the second opening 311. The second electrode 340 may include (e.g.) a metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In other example embodiments, the second electrode 340 may have a multilayer structure comprising multiple metal layers. The metal layers may have different materials and different thicknesses.

[0116] Therefore, a pixel structure 200 including a first electrode 290, a light-emitting layer 330, and a second electrode 340 can be configured.

[0117] A first inorganic thin-film encapsulation layer 451 may be disposed on the second electrode 340 in the display area 10 and the peripheral area 20. While covering the second electrode 340, the first inorganic thin-film encapsulation layer 451 may be configured to have a uniform thickness along the contour of the second electrode 340 (e.g., above and / or around the top surface of the second electrode 340). The first inorganic thin-film encapsulation layer 451 can prevent or reduce the degradation of the pixel structure 200 due to penetration and / or permeation of moisture, oxygen, etc. Additionally, the first inorganic thin-film encapsulation layer 451 can also protect the pixel structure 200 from external impacts. The first inorganic thin-film encapsulation layer 451 may include (e.g., may be) a flexible inorganic material.

[0118] An organic thin-film encapsulation layer 452 may be disposed on the first inorganic thin-film encapsulation layer 451 in the display area 10 and the peripheral area 20. The organic thin-film encapsulation layer 452 can improve the flatness of the organic light-emitting diode display device 100 and can protect the pixel structure 200. For example, the organic thin-film encapsulation layer 452 may have a substantially flat top surface. The organic thin-film encapsulation layer 452 may include (e.g., may be) a flexible organic material.

[0119] A second inorganic thin-film encapsulation layer 453 may be disposed on the organic thin-film encapsulation layer 452 in the display area 10 and the peripheral area 20. While covering the organic thin-film encapsulation layer 452, the second inorganic thin-film encapsulation layer 453 may be configured to have a uniform thickness along the contour of the organic thin-film encapsulation layer 452 (e.g., above and / or around the top surface of the organic thin-film encapsulation layer 452). The second inorganic thin-film encapsulation layer 453, together with the first inorganic thin-film encapsulation layer 451, may prevent or reduce the degradation of the pixel structure 200 due to penetration and / or permeation of moisture, oxygen, etc. Additionally, the second inorganic thin-film encapsulation layer 453, together with the first inorganic thin-film encapsulation layer 451 and the organic thin-film encapsulation layer 452, may also protect the pixel structure 200 from external impacts. The second inorganic thin-film encapsulation layer 453 may include (e.g., may be) a flexible inorganic material. In some embodiments, the thin-film encapsulation structure 450 may have a five-layer structure with the first to fifth thin-film encapsulation layers laminated on it, or a seven-layer structure with the first to seventh thin-film encapsulation layers laminated on it.

[0120] Therefore, a thin-film encapsulation structure 450 can be provided, which includes a first inorganic thin-film encapsulation layer 451, an organic thin-film encapsulation layer 452, and a second inorganic thin-film encapsulation layer 453.

[0121] Therefore, it can provide Figures 1 to 9 The organic light-emitting diode display device 100 shown is illustrated.

[0122] In the organic light-emitting diode (OLED) display device 100 according to an exemplary embodiment of the present disclosure, when the first capacitor 500 included in the first circuit structure 800 and the second capacitor 700 included in the second circuit structure 600 are disposed in the blocking region 23, the area of ​​each of the first circuit region 21 and the second circuit region 22 of the OLED display device 100 can be relatively reduced. Therefore, the unused space of the OLED display device 100 can be reduced.

[0123] Figure 10 , Figure 11 and Figures 13 to 22 This is a cross-sectional view illustrating a method of manufacturing an organic light-emitting diode display device according to an exemplary embodiment of the present disclosure. Figure 12 This is an enlarged plan view illustrating a method for manufacturing an organic light-emitting diode display device according to an exemplary embodiment of the present disclosure.

[0124] Reference Figure 10 , Figure 11 and Figure 12A rigid glass substrate 105 can be provided. A substrate 110 comprising (e.g., is) a transparent or opaque material can be formed on the glass substrate 105. The substrate 110 can be formed using a flexible transparent resin substrate (e.g., it can be formed from a flexible transparent resin substrate). The substrate 110 can be divided into a display area 10 and a peripheral area 20 (e.g., it can have portions corresponding to the display area 10 and the peripheral area 20), the peripheral area 20 including a first circuit area 21, a second circuit area 22, and a blocking area 23.

[0125] A buffer layer 115 can be formed on the substrate 110. The buffer layer 115 can be formed on the substrate 110 over the entire area of ​​the display region 10 and the peripheral region 20. The buffer layer 115 can be formed using silicides, metal oxides, etc. (e.g., it can be formed from silicides, metal oxides, etc.). For example, the buffer layer 115 can include (e.g., it can be) SiO, SiN, SiON, SiOC, SiCN, AlO, AlN, TaO, HfO, ZrO, TiO, etc.

[0126] A first active layer 130 and a second active layer 135 can be formed on the buffer layer 115 in the display region 10, and a first active pattern 730 and a second active pattern 530 can be formed on the buffer layer 115 in the peripheral region 20. For example, after forming an initial active layer over the entire area of ​​the buffer layer 115, the initial active layer is partially etched so that the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 can be formed (e.g., simultaneously formed or formed from the same layer). In some embodiments, each of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 may include (e.g., may be) the same material. For example, each of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 can be formed using oxide semiconductors, inorganic semiconductors, or organic semiconductors (e.g., can be formed from oxide semiconductors, inorganic semiconductors, or organic semiconductors). Each of the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530 may have a source region, a drain region, and a channel region located between the source region and the drain region.

[0127] A first gate insulating layer 150 may be formed on the first active layer 130, the second active layer 135, the first active pattern 730, and the second active pattern 530. The first gate insulating layer 150 may cover the first active layer 130 and the second active layer 135 in the display area 10 on the buffer layer 115, and may extend from the display area 10 to the peripheral area 20 (e.g., into the peripheral area 20) to cover the first active pattern 730 in the first circuit area 21 and the second active pattern 530 in the second circuit area 22. The first gate insulating layer 150 may be formed using silicides, metal oxides, etc. (e.g., it may be formed from silicides, metal oxides, etc.).

[0128] A first gate electrode 170, a second gate electrode 175, and a lower gate pattern 177 can be formed on the first gate insulating layer 150 in the display region 10, and a first gate pattern 770, a second gate pattern 570, and a first lower electrode 510 can be formed in the peripheral region 20. For example, after forming an initial first electrode layer over the entire region of the first gate insulating layer 150, the initial first electrode layer is partially etched so that the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510 can be formed (e.g., simultaneously formed or formed from the same layer). In some embodiments, each of the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510 may include (e.g., may be) the same material and may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. (e.g., may be formed from metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials). For example, each of the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510 may include (for example, may be) Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, aluminum-containing alloys, AlN, silver-containing alloys, WN, copper-containing alloys, molybdenum-containing alloys, TiN, CrN, TaN, SrRuO, ZnO, ITO, SnO, InO, GaO, IZO, etc.

[0129] Reference Figure 13 , Figure 14 and Figure 2BA second gate insulating layer 155 can be formed on the first gate electrode 170, the second gate electrode 175, the first gate pattern 770, the second gate pattern 570, the lower gate pattern 177, and the first lower electrode 510. The second gate insulating layer 155 can cover the first gate electrode 170, the second gate electrode 175, and the lower gate pattern 177 in the display area 10 on the first gate insulating layer 150, and can extend from the display area 10 to the peripheral area 20 (e.g., into the peripheral area 20) to cover the first gate pattern 770 in the first circuit area 21, the second gate pattern 570 in the second circuit area 22, and the first lower electrode 510 in the blocking area 23. The second gate insulating layer 155 can be formed using silicides, metal oxides, etc. (e.g., it can be formed from silicides, metal oxides, etc.).

[0130] An upper gate pattern 179 may be formed on the second gate insulating layer 155 in the display region 10, and a first upper electrode 520 may be formed on the second gate insulating layer 155 in the blocking region 23. For example, after forming an initial second electrode layer over the entire area of ​​the second gate insulating layer 155, the initial second electrode layer is partially etched so that the upper gate pattern 179, the first upper electrode 520, and the second upper electrode 720 can be formed (e.g., simultaneously formed or formed from the same layer). In some embodiments, each of the upper gate pattern 179, the first upper electrode 520, and the second upper electrode 720 may include (e.g., may be) the same material and may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. (e.g., may be formed from metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc.).

[0131] Therefore, a storage capacitor 180 including a lower gate pattern 177 and an upper gate pattern 179, a first capacitor 500 including a first lower electrode 510 and a first upper electrode 520, and a second capacitor 700 including a second lower electrode 710 and a second upper electrode 720 can be formed (e.g., formed simultaneously or formed from the same layer).

[0132] Reference Figure 15 and Figure 16 An insulating intermediate layer 190 can be formed on the upper gate pattern 179, the first upper electrode 520, and the second upper electrode 720. The insulating intermediate layer 190 can cover the upper gate pattern 179 in the display area 10 on the second gate insulating layer 155, and can extend from the display area 10 to the peripheral area 20 (e.g., into the peripheral area 20) to cover the first upper electrode 520 and the second upper electrode 720 in the blocking area 23. The insulating intermediate layer 190 can be formed using silicides, metal oxides, etc. (e.g., it can be formed from silicides, metal oxides, etc.).

[0133] A first source electrode 210, a first drain electrode 230, a second source electrode 215, and a second drain electrode 235 can be formed on the insulating intermediate layer 190 in the display area 10. A first source pattern 810, a first drain pattern 830, a second source pattern 610, and a second drain pattern 630 can be formed on the insulating intermediate layer 190 in the peripheral area 20. The first source electrode 210 and the first drain electrode 230 can be connected to the source and drain regions of the first active layer 130 via contact holes (e.g., contact holes formed by removing the first and second portions of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190, respectively). The second source electrode 215 and the second drain electrode 235 can be connected to the source and drain regions of the second active layer 135 via contact holes (e.g., contact holes formed by removing the third and fourth portions of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190, respectively). The first source pattern 810 and the first drain pattern 830 can be connected to the source and drain regions of the first active pattern 730 via contact holes (e.g., contact holes formed by removing the fifth and sixth portions of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190, respectively). The second source pattern 610 and the second drain pattern 630 can be connected to the source and drain regions of the second active pattern 530 via contact holes (e.g., contact holes formed by removing the seventh and eighth portions of the first gate insulating layer 150, the second gate insulating layer 155, and the insulating intermediate layer 190, respectively).

[0134] For example, after forming an initial third electrode layer over the entire area of ​​the insulating intermediate layer 190, the initial third electrode layer is partially etched to allow the formation (e.g., simultaneously formed or formed from the same layer) of a first source electrode 210, a first drain electrode 230, a second source electrode 215, a second drain electrode 235, a first source pattern 810, a first drain pattern 830, a second source pattern 610, and a second drain pattern 630. In some embodiments, each of the first source electrode 210, the first drain electrode 230, the second source electrode 215, the second drain electrode 235, the first source pattern 810, the first drain pattern 830, the second source pattern 610, and the second drain pattern 630 may include (e.g., may be) the same material and may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. (e.g., may be formed from metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc.).

[0135] Therefore, a first pixel transistor 250, a second pixel transistor 255, a first circuit transistor 850, and a second circuit transistor 650 can be formed (e.g., simultaneously formed or formed from the same layer). The first pixel transistor 250 includes a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230. The second pixel transistor 255 includes a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. The first circuit transistor 850 includes a first active pattern 730, a first gate pattern 770, a first source pattern 810, and a first drain pattern 830. The second circuit transistor 650 includes a second active pattern 530, a second gate pattern 570, a second source pattern 610, and a second drain pattern 630.

[0136] A planarization layer 270 can be formed on the first source electrode 210, the first drain electrode 230, the second source electrode 215, the second drain electrode 235, the first source pattern 810, the first drain pattern 830, the second source pattern 610, and the second drain pattern 630. The planarization layer 270 can cover the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 in the display region 10 on the insulating intermediate layer 190, and can extend into the peripheral region 20 (e.g., into the peripheral region 20) to cover the first source pattern 810 and the first drain pattern 830 in the first circuit region 21 and the second source pattern 610 and the second drain pattern 630 in the second circuit region 22. In an example embodiment, the planarization layer 270 may have a first opening 271 exposing the top surface of the insulating intermediate layer 190 in the blocking region 23 and a contact hole exposing a portion of the second drain electrode 235 of the second pixel transistor 255. Therefore, the planarization layer 270 may not be formed in the blocking region 23. In some embodiments, the first opening 271 may be positioned to overlap with the first capacitor 500 and the second capacitor 700. The planarization layer 270 may include (e.g., may be) an organic material. For example, the planarization layer 270 may be formed using photoresist, polyacrylamide resin, polyimide resin, polyamide resin, siloxane resin, acrylamide resin, epoxy resin, etc. (e.g., it may be formed from photoresist, polyacrylamide resin, polyimide resin, polyamide resin, siloxane resin, acrylamide resin, epoxy resin, etc.).

[0137] Reference Figure 17 and Figure 18A first electrode 290 can be formed in the display area 10 on the planarization layer 270, and a connection electrode 295 can be formed in the peripheral area 20 on the planarization layer 270. The first electrode 290 can be connected to the second drain electrode 235 through a contact hole (e.g., a contact hole formed by removing a portion of the planarization layer 270), and the connection electrode 295 can contact the insulating intermediate layer 190 through a first opening 271. For example, after forming an initial fourth electrode layer over the entire area of ​​the planarization layer 270, the initial fourth electrode layer is partially etched so that the first electrode 290 and the connection electrode 295 can be formed (e.g., simultaneously formed or formed from the same layer). In some embodiments, each of the first electrode 290 and the connection electrode 295 may include (e.g., may be) the same material and can be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. (e.g., may be formed from metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc.).

[0138] The pixel defining layer 310 may expose a portion of the first electrode 290 in the display region 10 on the planarization layer 270, and may extend from the display region 10 to the peripheral region 20 (e.g., into the peripheral region 20) to be formed in the first circuit region 21 and the second circuit region 22. In an example embodiment, the pixel defining layer 310 may have a second opening 311 overlapping the first opening 271 in the blocking region 23. Therefore, the pixel defining layer 310 may not be formed in the blocking region 23. The pixel defining layer 310 may be formed using an organic material (e.g., it may be formed from an organic material).

[0139] Reference Figure 19 and Figure 20 A light-emitting layer 330 may be formed on a first electrode 290 partially exposed by a pixel-defined layer 310 in the display area 10. The light-emitting layer 330 may be formed using at least one of light-emitting materials capable of emitting different colors of light (such as red, green, and blue light) depending on the pixel (e.g., it may be formed from at least one of light-emitting materials capable of emitting different colors of light (such as red, green, and blue light) depending on the pixel). In some embodiments, the light-emitting layer 330 may be formed by laminating multiple light-emitting materials capable of producing different colors of light, such as red, green, and blue light, so that white light can be emitted overall.

[0140] The second electrode 340 may be formed on the pixel defining layer 310 and the light-emitting layer 330 in the display area 10, and may extend into the peripheral area 20 (e.g., into the peripheral area 20) to overlap with the first opening 271 and the second opening 311 in the peripheral area 20. In an example embodiment, the second electrode 340 may contact the connecting electrode 295 through the second opening 311. The second electrode 340 may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. (e.g., it may be formed from metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc.).

[0141] Therefore, a pixel structure 200 including a first electrode 290, a light-emitting layer 330, and a second electrode 340 can be formed.

[0142] Reference Figure 21 and Figure 22 A first inorganic thin-film encapsulation layer 451 can be formed on the second electrode 340 in the display area 10 and the peripheral area 20. The first inorganic thin-film encapsulation layer 451 can be formed using a flexible inorganic material (e.g., it can be formed from a flexible inorganic material).

[0143] An organic thin-film encapsulation layer 452 can be formed on the first inorganic thin-film encapsulation layer 451 in the display area 10 and the peripheral area 20. The organic thin-film encapsulation layer 452 can be formed using a flexible organic material (e.g., it can be formed from a flexible organic material).

[0144] A second inorganic thin-film encapsulation layer 453 can be formed on the organic thin-film encapsulation layer 452 in the display area 10 and the peripheral area 20. The second inorganic thin-film encapsulation layer 453 can be formed using a flexible inorganic material (e.g., it can be formed from a flexible inorganic material).

[0145] Therefore, a thin-film encapsulation structure 450 comprising a first inorganic thin-film encapsulation layer 451, an organic thin-film encapsulation layer 452, and a second inorganic thin-film encapsulation layer 453 can be formed.

[0146] After the thin-film encapsulation structure 450 is formed, the glass substrate 105 can be removed from the substrate 110. Therefore, it is possible to manufacture... Figures 1 to 9 The organic light-emitting diode display device 100 shown is illustrated.

[0147] This disclosure can be applied to a variety of suitable electronic devices, including organic light-emitting diode (OLED) display devices. For example, this disclosure can be applied to vehicle display devices, marine display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0148] The foregoing is a description of exemplary embodiments and should not be construed as limiting this disclosure. While some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without departing substantially from the spirit and scope of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined by the claims and their equivalents. It should therefore be understood that the foregoing is a description of some exemplary embodiments, and this disclosure should not be construed as limiting itself to the disclosed exemplary embodiments, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of this disclosure as defined by the appended claims and their equivalents.

Claims

1. An organic light-emitting diode (OLED) display device, the OLED display device comprising: A substrate having a display area and a peripheral area, the peripheral area including a first circuit area, a second circuit area, and a blocking area located between the first circuit area and the second circuit area; Pixel structure, on the substrate in the display area; A first circuit transistor is located on the substrate in the first circuit region; The first lower electrode is on the substrate in the blocking region; The first upper electrode is on the first lower electrode, and the first upper electrode and the first lower electrode constitute a first capacitor; as well as A planarization layer on the substrate, the planarization layer having a first opening that overlaps with the first capacitor in the blocking region.

2. The organic light-emitting diode display device according to claim 1, wherein, The first capacitor and the first circuit transistor define the first circuit structure. Wherein, the first circuit structure is located in the first portion of the blocking region and the first circuit region, and The first circuit transistor and the first capacitor are electrically connected to each other.

3. The organic light-emitting diode display device according to claim 1, further comprising: A pixel defining layer, on the planarization layer, has a second opening overlapping the first opening in the blocking region. The first capacitor is stacked with the second opening.

4. The organic light-emitting diode display device according to claim 3, further comprising: A first gate insulating layer is located between the substrate and the planarization layer; A second gate insulating layer is formed on the first gate insulating layer and simultaneously covers the first lower electrode; as well as An insulating intermediate layer is formed on the second gate insulating layer, simultaneously covering the first upper electrode. The first opening is configured to expose the top surface of the insulating intermediate layer located in the blocking region, and The width of the first opening is smaller than the width of the second opening.

5. The organic light-emitting diode display device according to claim 4, wherein, The pixel structure includes: The first electrode is on the planarization layer; A light-emitting layer is formed on the first electrode; and The second electrode is located on the light-emitting layer, and The second electrode extends from the display area to the peripheral area to overlap with the first opening and the second opening.

6. The organic light-emitting diode display device according to claim 5, further comprising: Connecting electrodes, in the blocking region on the insulating intermediate layer, The connecting electrode is in contact with the second electrode and the insulating intermediate layer through the first opening and the second opening.

7. The organic light-emitting diode display device according to claim 4, further comprising: A pixel transistor is located between the substrate and the pixel structure, and the pixel transistor is electrically connected to the pixel structure. The pixel transistor includes: an active layer on the substrate in the display area; a gate electrode on the first gate insulating layer in the display area; and a source electrode and a drain electrode, both on the insulating intermediate layer in the display area. The first lower electrode and the gate electrode are located on the same layer.

8. The organic light-emitting diode display device according to claim 7, further comprising: Storage capacitors, spaced apart from the pixel transistors. The storage capacitor includes: a lower gate pattern on the first gate insulating layer in the display area; and an upper gate pattern on the second gate insulating layer in the display area and superimposed on the lower gate pattern. The first upper electrode and the upper gate pattern are located on the same layer.

9. The organic light-emitting diode display device according to claim 2, further comprising: A second circuit transistor is located on the substrate in the second circuit region; A second lower electrode is located on the substrate in the blocking region and spaced apart from the first lower electrode; as well as The second upper electrode is located on the second lower electrode, and the second upper electrode and the second lower electrode together constitute a second capacitor. The second capacitor and the second circuit transistor define the second circuit structure. The second circuit structure is located in the second part of the blocking region and the second circuit region. In this circuit, the transistor and the capacitor are electrically connected to each other, and The first upper electrode and the second upper electrode are integrally formed.

10. The organic light-emitting diode display device according to claim 9, further comprising: First pixel transistor; as well as A second pixel transistor is located between the substrate and the pixel structure and spaced apart from the first pixel transistor; the second pixel transistor is electrically connected to the pixel structure. The first circuit structure is configured to generate a gate signal provided to the first pixel transistor, and The second circuit structure is configured to generate a light-emitting control signal provided to the second pixel transistor.

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