A method of measuring the ionization charge size of high-energy particles

Abstract

The application belongs to the technical field of integrated circuits, and discloses a method for measuring high-energy particle ionization charge particle size, which comprises the following steps: performing irradiation experiments by adopting a mode in which a single high-energy particle is vertically incident on a static random memory circuit provided with multiple pages; in the irradiation experiments, a single event upset threshold of the multiple pages of the static random memory circuit is acquired; and based on the single event upset threshold of the static random memory circuit and a series inter-device spacing of the multiple pages, the high-energy particle ionization charge particle size is determined. The method for measuring high-energy particle ionization charge particle size provided by the application can realize reliable evaluation of the high-energy particle ionization charge particle size.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for measuring the particle size of ionized charge in high-energy particles. Background Technology

[0002] Multiple bit flips refer to the situation where a single particle incident on a device causes multiple memory cells at the corresponding physical address to flip. With the advancement of semiconductor manufacturing processes, device sizes are continuously shrinking, and critical charges are decreasing, leading to a gradual increase in the proportion of multiple bit flips caused by high-energy particle vertical incidence devices. To suppress multiple bit flips caused by high-energy particle vertical incidence circuits, special layout topology designs are required for error correction coding and other circuits. This necessitates obtaining the influence range of ionization charges generated by high-energy particle incidence; however, reliable measurement methods are lacking in current technologies. Summary of the Invention

[0003] This invention provides a method for measuring the particle size of ionized charge of high-energy particles, solving the technical problem that the particle size of ionized charge of high-energy particles cannot be reliably measured in the prior art.

[0004] To solve the above-mentioned technical problems, the present invention provides a method for measuring the particle size of ionized charge of high-energy particles, comprising:

[0005] Irradiation experiments were conducted by vertically incidenting a single high-energy particle onto a static random access memory circuit with multiple pages.

[0006] In the irradiation experiment, the single-event flip threshold of the selected multiple pages of static random access memory circuit is obtained;

[0007] The high-energy particle ionization charge particle size is determined based on the single-particle flip threshold of the static random access memory circuit and the spacing between the multiple pages of the cascaded devices.

[0008] Furthermore, the static random access memory circuit includes: four pages;

[0009] The four pages are respectively equipped with a 6-tube static memory unit circuit, a first 10-tube static memory unit circuit, a second 10-tube static memory unit circuit, and a third 10-tube static memory unit circuit.

[0010] Wherein, the series device spacing d1 of the first 10-transistor static memory cell circuit, the series device spacing d2 of the second 10-transistor static memory cell circuit, and the series device spacing d3 of the third 10-transistor static memory cell circuit, and d1 <d2<d3。

[0011] Further, the single-event flip threshold for the selected multiple pages of the static random access memory circuit includes:

[0012] Selectively activate the four pages respectively, and obtain the single-event effect thresholds LET0, LET1, LET2, and LET3 of the 6T static memory cell circuit, the first 10T static memory cell circuit, the second 10T static memory cell circuit, and the third 10T static memory cell circuit.

[0013] Further, determining the ionization charge particle size of the high-energy particle based on the single-event upset threshold of the static random access memory circuit and the series device spacing of the multiple pages includes:

[0014] When LET0≈LET1≈LET2≈LET3, the ionization charge particle size D of the high-energy particle satisfies D≥d3;

[0015] When LET0≈LET1≈LET2<<LET3, the ionization charge particle size D of the high-energy particle satisfies d2≤D<d3;

[0016] When LET0≈LET1<<LET2≈LET3, the ionization charge particle size D of the high-energy particle satisfies d1≤D<d2;

[0017] When LET0<<LET1≈LET2≈LET3, the heavy ion particle size D satisfies D<d1.

[0018] Further, the static random access memory circuit is fabricated using the SOI process.

[0019] Further, the 6T static memory cell circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

[0020] The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage VDD. The drain of the first PMOS transistor and the gate of the second PMOS transistor are connected to the second storage node. The gate of the first PMOS transistor and the drain of the second PMOS transistor are connected to the first storage node;

[0021] The drain of the first NMOS transistor and the gate of the second NMOS transistor are connected to the first storage node. The gate of the first NMOS transistor and the drain of the second NMOS transistor are connected to the second storage node. The source of the first NMOS transistor and the source of the second NMOS transistor are grounded;

[0022] The source of the third NMOS transistor is connected to the first storage node. The gate of the third NMOS transistor is connected to the word line. The drain of the third NMOS transistor is connected to the first bit line;

[0023] The source of the fourth NMOS transistor is connected to the second memory node, the gate of the fourth NMOS transistor is connected to the word line, and the drain of the fourth NMOS transistor is connected to the second bit line.

[0024] Furthermore, the first 10-transistor static memory cell circuit includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor;

[0025] The source of the third PMOS transistor is connected to the power supply voltage VDD, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the third memory node, and the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the fourth memory node.

[0026] The source of the fifth PMOS transistor is connected to the power supply voltage VDD, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, the drain of the sixth PMOS transistor is connected to the fourth memory node, and the gates of the fifth PMOS transistor and the sixth PMOS transistor are connected to the third memory node.

[0027] The drain of the fifth NMOS transistor is connected to the third memory node, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the sixth NMOS transistor is grounded, and the gates of the fifth NMOS transistor and the sixth NMOS transistor are connected to the fourth memory node.

[0028] The drain of the seventh NMOS transistor is connected to the fourth memory node, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, and the gates of the seventh NMOS transistor and the eighth NMOS transistor are connected to the third memory node.

[0029] The source of the ninth NMOS transistor is connected to the third memory node, the drain of the ninth NMOS transistor is connected to the first bit line, and the gate of the ninth NMOS transistor is connected to the word line.

[0030] The source of the tenth NMOS transistor is connected to the fourth memory node, the drain of the tenth NMOS transistor is connected to the second bit line, and the gate of the tenth NMOS transistor is connected to the word line.

[0031] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0032] The method for measuring the particle size of ionized charge of high-energy particles provided in this application embodiment is based on the phenomenon of single-event flip caused by high-energy particles incident on SRAM circuits. By comparing the single-event flip threshold of memory cells with different series spacing, the range of values ​​of the ionized charge radius of high-energy particles can be obtained; the whole process is convenient and reliable. Attached Figure Description

[0033] Figure 1 This is a flowchart of a method for measuring the particle size of ionized charge of high-energy particles provided in an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the structure of a 6-transistor static memory cell circuit provided in an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of the structure of the first 10-transistor static memory cell circuit provided in an embodiment of the present invention;

[0036] Figure 4 The circuit layout of the first 10-tube static storage cell and the schematic diagram of the heavy ion particle size are provided for embodiments of the present invention. Detailed Implementation

[0037] This application provides a method for measuring the particle size of ionized charge of high-energy particles, thereby solving the technical problem in the prior art that the particle size of ionized charge of high-energy particles cannot be reliably measured.

[0038] To better understand the above technical solutions, the following will describe the above technical solutions in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0039] In devices where high-energy particles are incident perpendicularly, the generated charges, due to drift, diffusion, and bipolar effects, may be collected by multiple sensitive nodes in the memory cells, causing multi-bit flips. The influence range of the ionized charges generated after high-energy particles are incident on the device can be tested based on this multi-bit flip mechanism.

[0040] See Figure 1 A method for measuring the particle size of ionized charge of high-energy particles, comprising:

[0041] Irradiation experiments were conducted by vertically incidenting a single high-energy particle onto a static random access memory circuit with multiple pages.

[0042] In the irradiation experiment, the single-event flip threshold of the selected multiple pages of static random access memory circuit is obtained;

[0043] The high-energy particle ionization charge particle size is determined based on the single-particle flip threshold of the static random access memory circuit and the spacing between the multiple pages of the cascaded devices.

[0044] It is worth noting that the static random access memory circuit includes four pages;

[0045] The four pages are respectively equipped with a 6-tube static memory unit circuit, a first 10-tube static memory unit circuit, a second 10-tube static memory unit circuit, and a third 10-tube static memory unit circuit.

[0046] Wherein, the series device spacing d1 of the first 10-transistor static memory cell circuit, the series device spacing d2 of the second 10-transistor static memory cell circuit, and the series device spacing d3 of the third 10-transistor static memory cell circuit, and d1 <d2<d3。

[0047] The 6-transistor static random access memory (SRAM) cell, being the smallest circuit module in terms of design size, has the most circuit units and occupies the largest area. Therefore, it is most susceptible to the effects of radiation and process variations, resulting in the most significant deviations in its electrical characteristics. Based on this, this study combines three 10-transistor SRAM cell circuits with different series distances. Using the principle of multi-bit flipping, the single-event flip threshold of SRAMs with different structures is tested and compared to evaluate the heavy ionized charge particle size.

[0048] Specifically, the single-event flip threshold for the selected multiple pages of the static random access memory circuit includes:

[0049] Select the four pages respectively, and obtain the single-event thresholds LET0, LET1, LET2 and LET3 of the 6-tube static memory unit circuit, the first 10-tube static memory unit circuit, the second 10-tube static memory unit circuit and the third 10-tube static memory unit circuit.

[0050] In this embodiment, the device achieves full dielectric isolation based on silicon-on-insulator (SiI) technology. The static random access memory (SRAM) circuit adopts a four-page structure, with each page being identical except for its internal storage cells; the decoders, read / write driver circuits, etc., are completely the same.

[0051] See Figure 2 When a high-energy particle enters the 6-tube static memory cell circuit, if any of the first PMOS transistor P31, the second PMOS transistor P41, the first NMOS transistor N41, or the second NMOS transistor N51 in the latch structure experiences a single-event effect, it will cause the potential of the first memory node Q or the second memory node Qn to flip, i.e., from 0 to 1 or from 1 to 0.

[0052] Reference Figure 3, a first 10 - transistor static memory cell circuit is disclosed. That is, based on the 6 - transistor static memory cell circuit, the number of series devices is increased, introducing redundant storage nodes. Only when two series devices in the 10 - transistor static memory cell circuit, namely the third PMOS transistor P11 and the fourth PMOS transistor P12, the fifth PMOS transistor P21 and the sixth PMOS transistor P22, the fifth NMOS transistor N11 and the sixth NMOS transistor N12, or the seventh NMOS transistor N21 and the eighth NMOS transistor N22 are turned on due to single - event effect, will the potential of the third storage node Q or the fourth storage node Qn flip.

[0053] See Figure 4 , a layout schematic diagram of the first 10 - transistor static memory cell circuit. If the ionization charge particle size D1 of the high - energy particle can cover two series devices in the layout, taking N11 and N12 as an example, then the potential of the storage node flips, and the single - event effect flip threshold of the first 10 - transistor static memory cell circuit is comparable to that of the 6 - transistor static memory cell circuit. Conversely, if the ionization charge particle size D2 of the high - energy particle can only cover one device in the layout, taking N11 as an example, then the potential of the storage node will not flip. Therefore, the single - event effect flip threshold of the first 10 - transistor static memory cell circuit is greater than that of the 6 - transistor static memory cell circuit. The radius of the heavy - ion ionization charge can be evaluated from the different page - flip situations of the static random access memory circuit.

[0054] Determining the ionization charge particle size of the high - energy particle based on the single - event flip threshold of the static random access memory circuit and the series device spacing of the multiple pages includes:

[0055] When LET0≈LET1≈LET2≈LET3, the ionization charge particle size D of the high - energy particle satisfies D≥d3;

[0056] When LET0≈LET1≈LET2<<LET3, the ionization charge particle size D of the high - energy particle satisfies d2≤D<d3;

[0057] When LET0≈LET1<<LET2≈LET3, the ionization charge particle size D of the high - energy particle satisfies d1≤D<d2;

[0058] When LET0<<LET1≈LET2≈LET3, the heavy - ion particle size D satisfies D<d1.

[0059] That is,

[0060]

[0061] Furthermore, the static random access memory circuit is fabricated using SOI technology with all - dielectric isolation.

[0062] See Figure 2The 6-transistor static memory cell circuit includes: a first PMOS transistor P31, a second PMOS transistor P41, a first NMOS transistor N41, a second NMOS transistor N51, a third NMOS transistor N61, and a fourth NMOS transistor N62.

[0063] The source of the first PMOS transistor P31 and the source of the second PMOS transistor P41 are connected to the power supply voltage VDD. The drain of the first PMOS transistor P31 and the gate of the second PMOS transistor P41 are connected to the second memory node. The gate of the first PMOS transistor P31 and the drain of the second PMOS transistor P41 are connected to the first memory node.

[0064] The drain of the first NMOS transistor N41 and the gate of the second NMOS transistor N51 are connected to the first memory node Q, the gate of the first NMOS transistor N41 and the drain of the second NMOS transistor N51 are connected to the second memory node Qn, and the source of the first NMOS transistor N41 and the source of the second NMOS transistor N51 are grounded.

[0065] The source of the third NMOS transistor N61 is connected to the first memory node Q, the gate of the third NMOS transistor N62 is connected to the word line WL, and the drain of the third NMOS transistor N61 is connected to the first bit line BL.

[0066] The source of the fourth NMOS transistor N62 is connected to the second memory node Qn, the gate of the fourth NMOS transistor N62 is connected to the word line WL, and the drain of the fourth NMOS transistor N62 is connected to the second bit line BLB.

[0067] See Figure 3 The first 10-transistor static memory cell circuit includes: a third PMOS transistor P11, a fourth PMOS transistor P12, a fifth PMOS transistor P21, a sixth PMOS transistor P22, a fifth NMOS transistor N11, a sixth NMOS transistor N12, a seventh NMOS transistor N21, an eighth NMOS transistor N22, a ninth NMOS transistor N31, and a tenth NMOS transistor N32.

[0068] The source of the third PMOS transistor P11 is connected to the power supply voltage VDD, the drain of the third PMOS transistor P11 is connected to the source of the fourth PMOS transistor P12, the drain of the fourth PMOS transistor P12 is connected to the third memory node Q, and the gates of the third PMOS transistor P11 and the fourth PMOS transistor P12 are connected to the fourth memory node Qn.

[0069] The source of the fifth PMOS transistor P21 is connected to the power supply voltage VDD, the drain of the fifth PMOS transistor P21 is connected to the source of the sixth PMOS transistor P22, the drain of the sixth PMOS transistor P22 is connected to the fourth memory node Qn, and the gates of the fifth PMOS transistor P21 and the sixth PMOS transistor P22 are connected to the third memory node Q.

[0070] The drain of the fifth NMOS transistor N11 is connected to the third memory node Q, the source of the fifth NMOS transistor N11 is connected to the drain of the sixth NMOS transistor N12, the source of the sixth NMOS transistor N12 is grounded, and the gates of the fifth NMOS transistor N11 and the sixth NMOS transistor N12 are connected to the fourth memory node Qn.

[0071] The drain of the seventh NMOS transistor N21 is connected to the fourth memory node Qn, the source of the seventh NMOS transistor N21 is connected to the drain of the eighth NMOS transistor N22, the source of the eighth NMOS transistor N22 is grounded, and the gates of the seventh NMOS transistor N21 and the eighth NMOS transistor N22 are connected to the third memory node Q.

[0072] The source of the ninth NMOS transistor N31 is connected to the third memory node Q, the drain of the ninth NMOS transistor N31 is connected to the first bit line WL, and the gate of the ninth NMOS transistor N31 is connected to the word line BL.

[0073] The source of the tenth NMOS transistor N32 is connected to the fourth memory node Qn, the drain of the tenth NMOS transistor N32 is connected to the second bit line BLB, and the gate of the tenth NMOS transistor N32 is connected to the word line WL.

[0074] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0075] The method for measuring the particle size of ionized charge of high-energy particles provided in this application embodiment is based on the phenomenon of single-event flip caused by high-energy particles incident on SRAM circuits. By comparing the single-event flip threshold of memory cells with different series spacing, the range of values ​​of the ionized charge radius of high-energy particles can be obtained; the whole process is convenient and reliable.

[0076] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method of measuring the ionization charge diameter of high-energy particles, characterized in that, Comprising: Performing an irradiation experiment by means of vertically irradiating a static random access memory circuit with multiple pages using a single high-energy particle; In the irradiation experiment, obtaining the single-event upset threshold of the selected multiple pages of the static random access memory circuit; Determining the ionization charge particle size of the high-energy particle based on the single-event upset threshold of the static random access memory circuit and the series device pitch of the multiple pages; The static random access memory circuit includes: four pages; A 6-transistor static storage cell circuit, a first 10-transistor static storage cell circuit, a second 10-transistor static storage cell circuit, and a third 10-transistor static storage cell circuit are respectively provided in the four pages; Among them, the series device pitch d1 of the first 10-transistor static storage cell circuit, the series device pitch d2 of the second 10-transistor static storage cell circuit, and the series device pitch d3 of the third 10-transistor static storage cell circuit, and d1 < d2 < d3; Among them, the obtaining the single-event upset threshold of the selected multiple pages of the static random access memory circuit includes: Respectively selecting the four pages and obtaining the single-event effect thresholds LET0, LET1, LET2, and LET3 of the 6-transistor static storage cell circuit, the first 10-transistor static storage cell circuit, the second 10-transistor static storage cell circuit, and the third 10-transistor static storage cell circuit; The determining the ionization charge particle size of the high-energy particle based on the single-event upset threshold of the static random access memory circuit and the series device pitch of the multiple pages includes: When LET0 ≈ LET1 ≈ LET2 ≈ LET3, the ionization charge particle size D of the high-energy particle satisfies D ≥ d3; When LET0 ≈ LET1 ≈ LET2 << LET3, the ionization charge particle size D of the high-energy particle satisfies d2 ≤ D < d3; When LET0 ≈ LET1 << LET2 ≈ LET3, the ionization charge particle size D of the high-energy particle satisfies d1 ≤ D < d2; When LET0 << LET1 ≈ LET2 ≈ LET3, the heavy ion particle size D satisfies D < d1.

2. The method for measuring the particle size of ionized charge high-energy particles as described in claim 1, characterized in that, The static random access memory circuit is fabricated using SOI technology.

3. The method for measuring the particle size of ionized charge of high-energy particles as described in claim 1, characterized in that, The 6-transistor static storage cell circuit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage VDD, the drain of the first PMOS transistor and the gate of the second PMOS transistor are connected to the second storage node, and the gate of the first PMOS transistor and the drain of the second PMOS transistor are connected to the first storage node; The drain of the first NMOS transistor and the gate of the second NMOS transistor are connected to the first storage node, the gate of the first NMOS transistor and the drain of the second NMOS transistor are connected to the second storage node, and the source of the first NMOS transistor and the source of the second NMOS transistor are grounded; The source of the third NMOS transistor is connected to the first memory node, the gate of the third NMOS transistor is connected to the word line, and the drain of the third NMOS transistor is connected to the first bit line. The source of the fourth NMOS transistor is connected to the second memory node, the gate of the fourth NMOS transistor is connected to the word line, and the drain of the fourth NMOS transistor is connected to the second bit line.

4. The method for measuring the particle size of ionized charge of high-energy particles as described in claim 1, characterized in that, The first 10-transistor static memory cell circuit includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; The source of the third PMOS transistor is connected to the power supply voltage VDD, the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor, the drain of the fourth PMOS transistor is connected to the third memory node, and the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the fourth memory node. The source of the fifth PMOS transistor is connected to the power supply voltage VDD, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, the drain of the sixth PMOS transistor is connected to the fourth memory node, and the gates of the fifth PMOS transistor and the sixth PMOS transistor are connected to the third memory node. The drain of the fifth NMOS transistor is connected to the third memory node, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the sixth NMOS transistor is grounded, and the gates of the fifth NMOS transistor and the sixth NMOS transistor are connected to the fourth memory node. The drain of the seventh NMOS transistor is connected to the fourth memory node, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the source of the eighth NMOS transistor is grounded, and the gates of the seventh NMOS transistor and the eighth NMOS transistor are connected to the third memory node. The source of the ninth NMOS transistor is connected to the third memory node, the drain of the ninth NMOS transistor is connected to the first bit line, and the gate of the ninth NMOS transistor is connected to the word line. The source of the tenth NMOS transistor is connected to the fourth memory node, the drain of the tenth NMOS transistor is connected to the second bit line, and the gate of the tenth NMOS transistor is connected to the word line.

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