Pixel, display device having the pixel, and driving method of the display device

Abstract

A pixel according to an embodiment of the present invention includes: a first light source unit, including at least one first light-emitting element connected between a first separation electrode and a second power source; a second light source unit, including at least one second light-emitting element connected between a second separation electrode and the second power source; a driving current generator, including a first transistor, the first transistor being connected between the first power source and the first light source unit and the second light source unit, and generating a driving current corresponding to a first data signal supplied to a first data line; a first switching unit, including a first switching element connected between the driving current generator and the first light source unit; and a second switching unit, including a second switching element connected between the driving current generator and the second light source unit, and controlling the connection between the first transistor and the second light source unit in response to a second data signal supplied to a second data line.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a pixel, a display device including the pixel, and a driving method of the display device. Background Art

[0002] Recently, a technology for manufacturing an ultra-small light-emitting element using a material having a reliable inorganic crystal structure and manufacturing a display device using the light-emitting element has been developed. For example, a technology for manufacturing an ultra-small light-emitting element having a small size corresponding to a range from a nanometer size to a micrometer size and using the ultra-small light-emitting element to form a light source of a pixel has been developed. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure relate to a pixel including a plurality of light emitting elements, a display device including the pixel, and a driving method of the display device.

[0005] Technical Solution

[0006] According to one aspect of the present disclosure, a pixel may include: a first light source unit, including at least one first light-emitting element connected between a first separation electrode and a second power source; a second light source unit, including at least one second light-emitting element connected between a second separation electrode and a second power source; a driving current generator, including a first transistor connected between the first power source and the first light source unit and the second light source unit, and generating a driving current corresponding to a first data signal supplied to a first data line; a first switching unit, including a first switching element connected between the driving current generator and the first light source unit; and a second switching unit, including a second switching element connected between the driving current generator and the second light source unit, and controlling the connection between the first transistor and the second light source unit in response to a second data signal supplied to a second data line.

[0007] The first transistor may include a first electrode connected to the first power source, a second electrode commonly connected to the first switching element and the second switching element, and a gate electrode connected to the first node.

[0008] The driving current generator may also include at least one of: a second transistor, connected between the first data line and the first electrode of the first transistor, and including a gate electrode connected to the scan line; a third transistor, connected between the second electrode of the first transistor and the first node, and including a gate electrode connected to the scan line; a fourth transistor, connected between the first node and the initialization power supply, and including a gate electrode connected to the initialization control line; a fifth transistor, connected between the first power supply and the first electrode of the first transistor, and including a gate electrode connected to the emission control line; and a first capacitor, connected between the first power supply and the first node.

[0009] The first switching unit may include a sixth transistor as a first switching element. The sixth transistor may be connected between the first transistor and the first separation electrode, and may include a gate electrode connected to the emission control line.

[0010] The second switching unit may include: a seventh transistor, which is connected between the first transistor and the second separation electrode as a second switching element; an eighth transistor, which is connected between the gate electrode of the seventh transistor and the second node and includes a gate electrode connected to the emission control line; a ninth transistor, which is connected between the second data line and the second node and includes a gate electrode connected to the scan line; and a second capacitor, which is connected between the first power supply and the second node.

[0011] The first light source unit may include: a first separation electrode; a second pixel electrode spaced apart from the first separation electrode; and a plurality of first light emitting elements including the at least one first light emitting element and connected in parallel between the first separation electrode and the second pixel electrode.

[0012] The second light source unit may include: a second separation electrode; a second pixel electrode spaced apart from the second separation electrode; and a plurality of second light emitting elements including the at least one second light emitting element and connected in parallel between the second separation electrode and the second pixel electrode.

[0013] The first and second separation electrodes may be disposed in a predetermined emission region to be spaced apart from each other. The first and second light source units may further include a second pixel electrode commonly connected between a first end of each of the first and second light emitting elements and a second power source.

[0014] According to one aspect of the present disclosure, a display device may include: a timing controller configured to output first data corresponding to image data and second data corresponding to a grayscale of the image data; a data driver configured to generate first data signals and second data signals corresponding to the first data and the second data, respectively, and output the first data signals and the second data signals to first data lines and second data lines, respectively; and a pixel connected to the first data lines and the second data lines. The pixel may include: a first light source unit including at least one first light emitting element connected between a first separation electrode and a second power source; a second light source unit including at least one second light emitting element connected between a second separation electrode and a second power source; a driving current generator including a first transistor connected between the first power source and the first light source unit and the second light source unit, and generating a driving current corresponding to the first data signal; a first switching unit including a first switching element connected between the driving current generator and the first light source unit; and a second switching unit including a second switching element connected between the driving current generator and the second light source unit, and controlling the connection between the first transistor and the second light source unit in response to a second data signal.

[0015] The timing controller may include: a data processor configured to process the image data to generate first data; and a grayscale determiner configured to compare the grayscale value of each pixel included in the image data with a predetermined reference grayscale value and generate second data corresponding to the comparison result.

[0016] When the grayscale value of each pixel is greater than the reference grayscale value, the grayscale determiner can output second data having a predetermined first grayscale value corresponding to the gate-on voltage, and when the grayscale value of each pixel is equal to or less than the reference grayscale value, the grayscale determiner can output second data having a predetermined second grayscale value corresponding to the gate-off voltage.

[0017] The display device may include a pixel unit, the pixel unit including: a plurality of pixels arranged on n (n is a natural number of 2 or greater) horizontal lines and m (m is a natural number of 2 or greater) vertical lines; at least n scan lines connected to the pixels of each horizontal line; and m first data lines and m second data lines connected to the pixels of each vertical line. The data driver may include 2m data channels connected to different data lines among the first data lines and the second data lines.

[0018] The first transistor may include a first electrode connected to the first power source, a second electrode commonly connected to the first switching element and the second switching element, and a gate electrode connected to the first node.

[0019] The driving current generator may also include at least one of the following: a second transistor, connected between the first data line and the first electrode of the first transistor, and including a gate electrode connected to the scan line of the corresponding horizontal line; a third transistor, connected between the second electrode of the first transistor and the first node, and including a gate electrode connected to the scan line; a fourth transistor, connected between the first node and the initialization power supply, and including a gate electrode connected to the initialization control line of the corresponding horizontal line; a fifth transistor, connected between the first power supply and the first electrode of the first transistor, and including a gate electrode connected to the emission control line of the corresponding horizontal line; and a first capacitor, connected between the first power supply and the first node.

[0020] The first switching unit may include a sixth transistor as a first switching element, and the sixth transistor may be connected between the first transistor and the first separation electrode, and may include a gate electrode connected to an emission control line of a corresponding horizontal line.

[0021] The second switching unit may include: a seventh transistor, which is connected between the first transistor and the second separation electrode as a second switching element; an eighth transistor, which is connected between the gate electrode of the seventh transistor and the second node and includes a gate electrode connected to an emission control line of a corresponding horizontal line; a ninth transistor, which is connected between the second data line and the second node and includes a gate electrode connected to a scan line of the corresponding horizontal line; and a second capacitor, which is connected between the first power supply and the second node.

[0022] The first and second separation electrodes may be disposed in the emission region of the pixel to be spaced apart from each other, and the first and second light source units may further include a second pixel electrode commonly connected between the first end of each of the first and second light emitting elements and the second power source.

[0023] According to one aspect of the present disclosure, a method for driving a display device may include: generating first data corresponding to image data; comparing the image data with a predetermined reference grayscale value, and generating second data corresponding to the comparison result; generating a first data signal and a second data signal corresponding to the first data and the second data, respectively, and supplying the first data signal and the second data signal to a pixel; and generating a driving current corresponding to the first data signal, and driving a light source unit of the pixel by the driving current. In response to the second data signal, at least some of the plurality of light emitting elements forming the light source unit of the pixel may be selectively driven.

[0024] Generating the second data may include: when the grayscale value of the image data corresponding to the pixel is greater than the reference grayscale value, outputting the second data having a predetermined first grayscale value corresponding to the gate-on voltage; and when the grayscale value of the image data corresponding to the pixel is equal to or less than the reference grayscale value, outputting the second data having a predetermined second grayscale value corresponding to the gate-off voltage.

[0025] When a grayscale value of image data corresponding to a pixel is equal to or less than a reference grayscale value, a connection between some of the plurality of light emitting elements and a driving transistor of the pixel may be interrupted.

[0026] Beneficial Effects

[0027] According to an embodiment of the present disclosure, a pixel, a display device including the pixel, and a driving method of the display device can selectively drive at least some of the multiple light-emitting elements arranged in each pixel. According to an embodiment of the present disclosure, grayscale can be more accurately represented even in a low grayscale area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b A light emitting element according to an embodiment of the present disclosure is shown.

[0029] Figure 2a and Figure 2b A light emitting element according to an embodiment of the present disclosure is shown.

[0030] Figure 3a and Figure 3b A light emitting element according to an embodiment of the present disclosure is shown.

[0031] Figure 4 A display device according to an embodiment of the present disclosure is shown.

[0032] Figure 5 A pixel according to an embodiment of the present disclosure is shown.

[0033] Figure 6a and Figure 6b Both show that Figure 5 An embodiment of a light source unit of a pixel is shown in FIG.

[0034] Figure 7 Shows the drive Figure 5 An embodiment of the pixel method is shown in FIG.

[0035] Figure 8 A timing controller according to an embodiment of the present disclosure is shown.

[0036] Fig. 9 A data driver according to an embodiment of the present disclosure is shown.

[0037] Fig.10 A data driver according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to various embodiments of the present disclosure, and specific examples of the present disclosure are shown in the accompanying drawings and described below. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0039] Some elements that are not directly related to the features of the present disclosure may be omitted in the accompanying drawings to clearly explain the present disclosure. In addition, the sizes, proportions, etc. of some elements in the accompanying drawings may be slightly exaggerated. It should be noted that throughout the accompanying drawings, the same reference numerals are used to indicate the same or similar elements, and repeated descriptions will be omitted.

[0040] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It will also be understood that when the terms "comprise", "include", "have", etc. are used in this specification, the description indicates the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. In addition, when the first component or first part is disposed on the second component or second part, the first component or the first part may not only be directly on the second component or the second part, but also the third component or the third part may be between the first component or the first part and the second component or the second part. In addition, when the first component or the first part is connected or connected to the second component or the second part, the first component or the first part may not only be directly connected or connected to the second component or the second part, but also the third component or the third part may be between the first component or the first part and the second component or the second part.

[0041] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings in order to describe the present disclosure in detail so that a person skilled in the art with ordinary knowledge in the technical field to which the present disclosure belongs can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not particularly mentioned in a sentence.

[0042] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 2 and 3 show a light emitting element LD according to an embodiment of the present disclosure. In detail, Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 and 2 show a perspective view and a cross-sectional view of a light emitting element LD according to other embodiments of the present disclosure. Figures 1a to 3b It is illustrated that each light emitting element LD is a cylindrical rod-type light emitting diode, but the kind and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0043] First, refer to Figure 1a and Figure 1b , the light emitting element LD (e.g., light emitting diode) according to an embodiment of the present disclosure includes a first conductive type semiconductor layer 11 (also referred to as a "first semiconductor layer"), a second conductive type semiconductor layer 13 (also referred to as a "second semiconductor layer"), and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting element LD may be configured as a stack formed by continuously stacking the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13 in a longitudinal direction.

[0044] In the embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end in the longitudinal direction.

[0045] In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a first end of the light emitting element LD, and the other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a second end of the light emitting element LD.

[0046] In the embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type" includes a rod-like shape and a strip-like shape (such as a cylindrical shape and a prismatic shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1)), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0047] In an embodiment, the light emitting element LD may have a small size corresponding to the nanometer level to the micrometer level (e.g., a diameter D and / or a length L corresponding to the nanometer level to the micrometer level range). However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., a display device using a light emitting device using the light emitting element LD as a light source).

[0048] The first conductive semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant (such as Si, Ge, or Sn). However, the material forming the first conductive semiconductor layer 11 is not limited thereto, and the first conductive semiconductor layer 11 may be formed of various other materials.

[0049] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed above and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0050] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by combining electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0051] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant (such as Mg). However, the material forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0052] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer circumferential surface of the active layer 12. In addition, the insulating film INF may also surround a region of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. The insulating film INF may allow the opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the respective opposite ends in the longitudinal direction of the light emitting element LD (for example, each of the top surface and the bottom surface of the cylinder may be exposed instead of covering it).

[0053] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0054] In an embodiment, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF, the light emitting element LD may further include other additional components. For example, the light emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer and / or at least one electrode layer disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0055] For example, Figure 2a and Figure 2b As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on the first end of the second conductive type semiconductor layer 13. Figure 3a and Figure 3b As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on the first end of the first conductive type semiconductor layer 11 .

[0056] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO, and oxides or alloys thereof may be used alone or in combination with one another. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside of the light emitting element LD after passing through the electrode layers 14 and 15.

[0057] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround them. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, and, for example, may expose at least one region of each of the electrode layers 14 and 15. Alternatively, in another embodiment, the insulating film INF may not be provided.

[0058] If the insulating film INF is provided on the surface of the light emitting element LD, specifically, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode (not shown) (for example, at least one of the contact electrodes connected to the opposite ends of the light emitting element LD, etc.). Therefore, the electrical stability of the light emitting element LD can be ensured.

[0059] In addition, due to the insulating film INF formed on the surface of the light emitting element LD, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on each light emitting element LD, even when a plurality of light emitting elements LD are disposed adjacent to each other, an undesired short circuit of the light emitting element LD can be prevented.

[0060] In an embodiment, the light emitting element LD may be manufactured by a surface treatment process. For example, the light emitting element LD may be surface treated (e.g., by a coating process) so that when a plurality of light emitting elements LD are mixed with a fluid solution and then supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly distributed in the solution instead of being unevenly aggregated.

[0061] The light-emitting device including the above-mentioned light-emitting element LD can be used in various devices including display devices that require light sources. For example, at least one ultra-small light-emitting element LD (for example, multiple ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in various devices (such as lighting devices) that require light sources.

[0062] Figure 4 A display device according to an embodiment of the present disclosure is shown.

[0063] Reference Figure 4 , a display device according to an embodiment of the present disclosure includes a pixel unit 100 , a scan driver 110 , an emission control driver 120 , a data driver 130 , a timing controller 140 , and a host system 150 .

[0064] The pixel unit 100 includes a scan line S, an emission control line E, a data line D, and a plurality of pixels PXL connected to the scan line S, the emission control line E, and the data line D. Here, the term "connection" may comprehensively refer to physical connection and / or electrical connection. For example, the pixel PXL may be electrically connected to the scan line S, the emission control line E, and the data line D.

[0065] In an embodiment, in addition to at least one scan line S and an emission control line E, each pixel PXL may be connected to a plurality of data lines D to which different types of data signals are supplied. For example, a pixel PXL disposed on the i-th (i is a natural number greater than 0) horizontal line (i.e., the i-th horizontal pixel row) of the pixel unit 100 and the j-th (i.e., j is a natural number greater than 0) vertical line (i.e., the j-th vertical pixel column) of the pixel unit 100 may be connected to the i-th scan line S[i], the i-th emission control line E[i], the j-th first data line D1[j], and the j-th second data line D2[j]. In addition, each pixel PXL may be connected to at least one control line (e.g., an initialization control line). In an embodiment, the initialization control line may be any one of the scan lines S of the previous horizontal line, but the present disclosure is not limited thereto.

[0066] In an embodiment, the pixel PXL may include a plurality of light source units for self-emission. In an embodiment, each light source unit may include at least one light emitting element (eg, Figures 1a to 3bIn other words, each pixel PXL according to an embodiment of the present disclosure may include a plurality of light emitting elements LD divided into at least two groups. In an embodiment, the light emitting elements LD provided in each pixel PXL may be rod-shaped light emitting diodes each having a size corresponding to a range from a nanometer-scale size to a micrometer-scale size, but the present disclosure is not limited thereto.

[0067] When a scan signal is supplied to the scan line S of the corresponding horizontal line, each pixel PXL receives a first data signal from each first data line D1 and emits light having a brightness corresponding to the first data signal. In addition, in an embodiment of the present disclosure, each pixel PXL may receive a second data signal from each second data line D2 when supplied with a scan signal, and selectively drive at least some of the plurality of light source units in response to the second data signal. For example, when a low grayscale equal to or less than a predetermined reference grayscale value is expressed, each pixel PXL may interrupt the connection between some of the light source units and the driving transistor in response to the second data signal, and only supply a driving current to the remaining light source units, thereby expressing the corresponding grayscale. In this case, a larger driving current flows through each light emitting element LD compared to a comparative example in which all of the plurality of light source units are driven at the same grayscale. According to an embodiment of the present disclosure, grayscales may be expressed more accurately even in low grayscale regions.

[0068] The scan driver 110 supplies a scan signal to the scan line S in response to a first gate control signal supplied from the timing controller 140. For example, the scan driver 110 may receive a first gate start pulse GSP1 and a first gate shift clock GSC1 from the timing controller 140, and sequentially output the scan signal to the scan line S in response to the first gate start pulse GSP1 and the first gate shift clock GSC1. The pixel PXL is selected in units of horizontal lines by the scan signal, and the selected pixel PXL receives a first data signal and a second data signal from a first data line D1 and a second data line D2, respectively. In an embodiment, the scan driver 110 may be formed or installed in a display panel including the pixel unit 100, or installed on a separate circuit board to be connected to the display panel via a pad (or "pad") component.

[0069] The emission control driver 120 supplies the emission control signal to the emission control line E in response to the second gate control signal supplied from the timing controller 140. For example, the emission control driver 120 may receive the second gate start pulse GSP2 and the second gate shift clock GSC2 from the timing controller 140, and sequentially output the emission control signal to the emission control line E in response to the second gate start pulse GSP2 and the second gate shift clock GSC2.

[0070] In an embodiment, the emission control signal may have a predetermined gate-off voltage. The pixels PXL receiving the emission control signal may be controlled so that they do not emit light in units of horizontal lines, and are set to be in the following state: they can emit light during the remaining period of stopping the supply of the emission control signal (i.e., the period in which the emission control signal has a predetermined gate-on voltage). In an embodiment, the emission control driver 120 may be formed or installed in a display panel, or installed in a separate circuit board to be connected to the display panel via a pad assembly. In addition, in an embodiment, the emission control driver 120 may be integrated with the scan driver 110, or formed or installed separately from the scan driver 110.

[0071] The data driver 130 supplies each first data signal to each first data line D1, and supplies each second data signal to each second data line D2 in response to the data control signal and the first data DATA1 and the second data DATA2 supplied from the timing controller 140. For example, the data driver 130 may receive the first data DATA1, the second data DATA2, the source start pulse SSP, the source sampling clock SSC, and the source output enable signal SOE from the timing controller 140, and may output each of the first data signal and the second data signal to each of the first data line D1 and the second data line D2 in response to the first data DATA1, the second data DATA2, the source start pulse SSP, the source sampling clock SSC, and the source output enable signal SOE.

[0072] The timing controller 140 controls the scan driver 110, the emission control driver 120, and the data driver 130 in response to the image data RGB and the timing signal supplied from the host system 150. For example, based on the timing signals such as the image data RGB, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the clock signal CLK, the timing controller 140 may supply the first gate control signal and the second gate control signal to the scan driver 110 and the emission control driver 120, respectively, and may supply the first data DATA1 and the second data DATA2 and the data control signal to the data driver 130.

[0073] The first gate control signal may include a first gate start pulse GSP1 and one or more first gate shift clocks GSC1. The first gate start pulse GSP1 controls the supply timing of the first scan signal. The first gate shift clock GSC1 represents one or more clock signals for shifting the first gate start pulse GSP1.

[0074] The second gate control signal includes a second gate start pulse GSP2 and one or more second gate shift clocks GSC2. The second gate start pulse GSP2 controls the supply timing of the first emission control signal. The second gate shift clock GSC2 represents one or more clock signals for shifting the second gate start pulse GSP2.

[0075] The data control signal may include a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, etc. The source start pulse SSP controls the data sampling start timing of the data driver 130. The source sampling clock SSC controls the sampling operation of the data driver 130 based on a rising edge or a falling edge. The source output enable signal SOE controls the output timing of the data driver 130.

[0076] In addition, the timing controller 140 may generate first data DATA1 and second data DATA2 using the image data RGB, and may supply the first data DATA1 and second data DATA2 to the data driver 130. For example, the timing controller 140 may process the image data RGB to generate the first data DATA1, and may compare the image data RGB with a predetermined reference gray value to generate the second data DATA2.

[0077] The host system 150 supplies the image data RGB to the timing controller 140 through a predetermined interface. The host system 150 may supply various timing signals such as Vsync, Hsync, DE, and CLK to the timing controller 140.

[0078] In the display device according to the above-described embodiment, each pixel PXL is connected to a pair of first data lines D1 and second data lines D2. Therefore, the pixel unit 100 may include data lines D twice as many as vertical lines, and the data driver 130 may be provided with data channels corresponding to the data lines D, respectively. For example, assuming that the pixel unit 100 includes a plurality of pixels PXL arranged on n (n is a natural number equal to or greater than two) horizontal lines and m (m is a natural number equal to or greater than two) vertical lines, at least n scanning lines S connected to the pixels PXL arranged on each horizontal line and m first data lines D1 and m second data lines D2 each connected to the pixels PXL arranged on each vertical line may be provided in the pixel unit 100.

[0079] In this case, the data driver 130 may be provided with 2m data channels connected to different data lines D among the m first data lines D1 and the m second data lines D2. Such a data driver 130 supplies a first data signal to each first data line D1 to drive a pixel PXL having brightness corresponding to the image data RGB, and supplies a second data signal to each second data line D2 to selectively drive at least some of the plurality of light source units provided in each of the pixels PXL.

[0080] According to an embodiment of the present disclosure, grayscale can be more accurately represented even in a low grayscale area, and thus, the low grayscale representation of the pixel PXL and the display device including the pixel PXL can be improved. The structure and driving method of each pixel PXL, the data driver 130 and the timing controller 140 will be described in detail later.

[0081] Figure 5 Pixel PXL according to an embodiment of the present disclosure is shown. For example, Figure 5 It shows that it can be set in Figure 4 For convenience, Figure 5 Shows the settings Figure 4 Pixels PXL on the i-th row and j-th column of the pixel unit 100 are shown in FIG. In an embodiment, the pixels PXL disposed in the pixel unit 100 may have substantially the same structure, but the present disclosure is not limited thereto.

[0082] Reference Figure 4 and Figure 5 According to an embodiment of the present disclosure, the pixel PXL includes a plurality of light source units LSU (eg, a first light source unit LSU1 and a second light source unit LSU2). In addition, the pixel PXL includes a first switching unit 102, a second switching unit 103, and a driving current generator 101 for controlling driving of the light source unit LSU.

[0083] The first light source unit LSU1 includes at least one first light emitting element LD1 connected between the first separation electrode ELT11 and the second power source VSS. For example, the first light source unit LSU1 may include the first separation electrode ELT11, the second pixel electrode ELT2 spaced apart from the first separation electrode ELT11, and a plurality of first light emitting elements LD1 connected in parallel between the first separation electrode ELT11 and the second pixel electrode ELT2.

[0084] In an embodiment, the first separation electrode ELT11 and the second separation electrode ELT12 provided in the second light source unit LSU2 may constitute the first pixel electrode ELT1 of each pixel PXL. The first separation electrode ELT11 and the second separation electrode ELT12 may be separated and spaced apart from each other in the emission region of the corresponding pixel PXL, and may be connected to different switching elements. For example, the first separation electrode ELT11 may be connected to the drive current generator 101 via the sixth transistor T6 of the first switching unit 102, and the second separation electrode ELT12 may be connected to the drive current generator 101 via the seventh transistor T7 of the second switching unit 103.

[0085] In an embodiment, the second pixel electrode ELT2 may be connected to a second power source VSS via a second power line PL2. In an embodiment, the second power source VSS may be a low potential pixel power source. In an embodiment, the second pixel electrode ELT2 may be commonly connected between a first end of each of the first light emitting element LD1 and the second light emitting element LD2 and the second power source VSS.

[0086] In an embodiment, at least one first light emitting element LD1 provided in the first light source unit LSU1 may be connected between the first separation electrode ELT11 and the second pixel electrode ELT2 (broadly, between the first power source VDD and the second power source VSS) in the forward direction. In an embodiment, the first power source VDD may be a high potential pixel power source, and may have a potential equal to or higher than a threshold voltage of each light emitting element LD (e.g., each first light emitting element LD1 or each second light emitting element LD2) compared to the potential of the second power source VSS. When a driving current is supplied from the driving current generator 101, the at least one first light emitting element LD1 connected in the forward direction emits light having a brightness corresponding to the driving current.

[0087] In an embodiment, each first light emitting element LD1 may be an ultra-small light emitting diode. For example, each first light emitting element LD1 may be a rod-shaped light emitting diode having a size corresponding to a range from a nanometer size to a micrometer size. In the present disclosure, the type and / or shape of the first light emitting element LD1 is not particularly limited, and each of the first light emitting elements LD1 may be a self-emitting element of various types and / or shapes.

[0088] The second light source unit LSU2 includes at least one second light emitting element LD2 connected between the second separation electrode ELT12 and the second power source VSS. For example, the second light source unit LSU2 may include a second separation electrode ELT12, a second pixel electrode ELT2 spaced apart from the second separation electrode ELT12, and a plurality of second light emitting elements LD2 connected in parallel between the second separation electrode ELT12 and the second pixel electrode ELT2.

[0089] In an embodiment, at least one second light emitting element LD2 provided in the second light source unit LSU2 may be connected between the second separation electrode ELT12 and the second pixel electrode ELT2 in the forward direction (broadly, between the first power source VDD and the second power source VSS). When a driving current is supplied from the driving current generator 101, the at least one second light emitting element LD2 connected in the forward direction emits light having a brightness corresponding to the driving current.

[0090] In an embodiment, each second light emitting element LD2 may be an ultra-small light emitting diode. For example, each second light emitting element LD2 may be a rod-shaped light emitting diode having a size corresponding to a range from a nanometer size to a micrometer size. In the present disclosure, the type and / or shape of the second light emitting element LD2 is not particularly limited, and each of the second light emitting elements LD2 may be a self-emitting element of various types and / or shapes.

[0091] In an embodiment, the second light emitting element LD2 may be of the same type as the first light emitting element LD1, but the disclosure is not limited thereto. In addition, the first light emitting element LD1 and the second light emitting element LD2 may have substantially the same or similar size and / or shape, but the disclosure is not limited thereto.

[0092] The driving current generator 101 is connected between the first power source VDD and the first light source unit LSU1 and the second light source unit LSU2. In addition, the driving current generator 101 is connected to at least one scan line and a first data line D1 of a corresponding vertical line (e.g., the j-th first data line D1[j] (hereinafter, referred to as the "first data line")), wherein the at least one scan line includes a scan line S of a corresponding horizontal line (e.g., the i-th scan line S[i] (hereinafter, referred to as the "scan line" or the "current scan line")). Such a driving current generator 101 generates a driving current corresponding to a first data signal supplied to the first data line D1[j].

[0093] In an embodiment, the driving current generator 101 may include a first transistor T1 to a fifth transistor T5 and a first capacitor C1. In an embodiment, the first transistor T1 to the fifth transistor T5 may be of the same type. For example, all of the first transistor T1 to the fifth transistor T5 may be P-type transistors. However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, all of the first transistor T1 to the fifth transistor T5 may be N-type transistors. Alternatively, some of the first transistor T1 to the fifth transistor T5 may be P-type transistors, and the remaining transistors may be N-type transistors.

[0094] The first transistor T1 is a driving transistor of each pixel PXL and is connected between the first power source VDD and the first light source unit LSU1 and the second light source unit LSU2. For example, the first transistor T1 may include a first electrode (e.g., a source electrode) connected to the first power source VDD via a fifth transistor T5 and a first power line PL1, a second electrode (e.g., a drain electrode) connected to the first light source unit LSU1 and the second light source unit LSU2 via a sixth transistor T6 and a seventh transistor T7, and a gate electrode connected to the first node N1. In an embodiment, the second electrode of the first transistor T1 may be commonly connected to the sixth transistor T6 and the seventh transistor T7. Such a first transistor T1 generates a driving current corresponding to a first data signal supplied to the first node N1 via the first data line D1[j].

[0095] The second transistor T2 is connected between the first data line D1[j] and the first electrode of the first transistor T1, and the gate electrode of the second transistor T2 is connected to the scan line S[i]. When a scan signal (hereinafter, also referred to as a "current scan signal") of a gate-on voltage is supplied from the scan line S[i], such a second transistor T2 is turned on. When the second transistor T2 is turned on, the first data signal supplied to the first data line D1[j] is transmitted to the first electrode of the first transistor T1.

[0096] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1, and the gate electrode of the third transistor T3 is connected to the scan line S[i]. When a scan signal of a gate-on voltage is supplied from the scan line S[i], such a third transistor T3 is turned on. When the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0097] The fourth transistor T4 is connected between the first node N1 and the initialization power supply VINIT, and the gate electrode of the fourth transistor T4 is connected to the initialization control line of the corresponding horizontal line (for example, the i-th initialization control line CL[i] (hereinafter, referred to as the "initialization control line")). In an embodiment, the initialization control line CL[i] may be any one of the scan lines S of the previous horizontal line. For example, the i-th initialization control line CL[i] may be the immediately preceding horizontal line of the current scan line (i.e., the i-1-th scan line S[i-1] (also referred to as the "previous scan line")). However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the initialization control line CL[i] may be set separately from the scan line S. When an initialization control signal of a gate-on voltage (for example, a previous scan signal having a gate-on voltage) is supplied to the initialization control line CL[i], such a fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, the first node N1 is initialized to the voltage of the initialization power supply VINT. In an embodiment, the voltage of the initialization power supply VINT may be equal to or less than the lowest voltage of the first data signal. For example, the voltage of the initialization power supply VINT can be lower than the lowest voltage of the first data signal by the threshold voltage of the first transistor T1 or more. Therefore, during each frame period, regardless of the voltage of the first data signal supplied in the previous frame period, the first data signal can be stably supplied to the first node N1.

[0098] The fifth transistor T5 is connected between the first power supply VDD and the first electrode of the first transistor T1, and the gate electrode of the fifth transistor T5 is connected to the emission control line of the corresponding horizontal line (for example, the i-th emission control line E[i] (hereinafter, referred to as "emission control line")). Such a fifth transistor T5 is turned off when the emission control signal of the gate-off voltage is supplied to the emission control line E[i], and is turned on in other cases (that is, when the voltage of the emission control signal is the gate-on voltage). When the fifth transistor T5 is turned off, the connection between the first power supply VDD and the first transistor T1 is interrupted. When the fifth transistor T5 is turned on, the first transistor T1 is connected to the first power supply VDD.

[0099] The first capacitor C1 is connected between the first power source VDD and the first node N1. Such a first capacitor C1 charges a voltage corresponding to a first data signal transmitted to the first node N1 in each frame period (specifically, a data programming period of each frame) and a threshold voltage of the first transistor T1, and maintains the charged voltage until the first data signal of the next frame is supplied.

[0100] Meanwhile, the configuration of the driving current generator 101 is not limited to Figure 5 For example, the driving current generator 101 may have a configuration corresponding to a pixel circuit of various known structures.

[0101] The first switching unit 102 includes at least one switching element (e.g., a sixth transistor T6 (also referred to as a "first switching element")) connected between the driving current generator 101 and the first light source unit LSU1. The sixth transistor T6 is connected between the first transistor T1 and the first separation electrode ELT11, and the gate electrode of the sixth transistor T6 is connected to the emission control line E[i]. The sixth transistor T6 is turned off when an emission control signal of a gate-off voltage is supplied to the emission control line E[i], and is turned on in other cases. When the sixth transistor T6 is turned off, the connection between the first transistor T1 and the first light source unit LSU1 (e.g., the first separation electrode ELT11 of the first light source unit LSU1) is interrupted. When the sixth transistor T6 is turned on, the first light source unit LSU1 is connected to the first transistor T1, and the driving current from the first transistor T1 is supplied to the first light source unit LSU1.

[0102] The second switch unit 103 includes at least one switch element (e.g., a seventh transistor T7 (also referred to as a "second switch element")) connected between the drive current generator 101 and the second light source unit LSU2. In addition, the second switch unit 103 may further include a second capacitor C2 and an eighth transistor T8 and a ninth transistor T9 for controlling the operation of the seventh transistor T7. In an embodiment, the second switch unit 103 is connected to the second data line D2 of the corresponding vertical line (e.g., the j-th second data line D2[j] (hereinafter, "second data line")). Such a second switch unit 103 controls the connection between the drive current generator 101 (specifically, the first transistor T1 as the drive transistor of each pixel PXL) and the second light source unit LSU2 in response to the second data signal supplied to the second data line D2[j].

[0103] The seventh transistor T7 is connected between the first transistor T1 and the second separation electrode ELT12, and a gate electrode of the seventh transistor T7 is connected to the second node N2 via the eighth transistor T8. Such a seventh transistor T7 controls the connection between the first transistor T1 and the second light source unit LSU2 in response to the second data signal supplied to the second data line D2[j].

[0104] For example, when the second data signal of the gate-on voltage is transmitted to the gate electrode of the seventh transistor T7 through the second data line D2[j] and the eighth transistor T8, the seventh transistor T7 may be turned on. When the seventh transistor T7 is turned on, the second light source unit LSU2 is connected to the first transistor T1. Therefore, the driving current from the first transistor T1 is supplied to the second light source unit LSU2.

[0105] At the same time, when the second data signal of the gate-off voltage is transmitted to the gate electrode of the seventh transistor T7 through the second data line D2[j] and the eighth transistor T8, the seventh transistor T7 may be turned off. When the seventh transistor T7 is turned off, the connection between the first transistor T1 and the second light source unit LSU2 (e.g., the second separation electrode ELT12 of the second light source unit LSU2) is interrupted, and the inflow of the driving current to the second light source unit LSU2 is interrupted.

[0106] The eighth transistor T8 is connected between the gate electrode of the seventh transistor T7 and the second node N2, and the gate electrode of the eighth transistor T8 is connected to the emission control line E[i]. The eighth transistor T8 is turned off when the emission control signal of the gate-off voltage is supplied to the emission control line E[i], and is turned on in other cases. When the eighth transistor T8 is turned off, the connection between the gate electrode of the seventh transistor T7 and the second node N2 is interrupted. When the eighth transistor T8 is turned on, the gate electrode of the seventh transistor T7 is connected to the second node N2, and the voltage of the second node N2 is transmitted to the gate electrode of the seventh transistor T7.

[0107] The ninth transistor T9 is connected between the second data line D2[j] and the second node N2, and the gate electrode of the ninth transistor T9 is connected to the scan line S[i]. When a scan signal of a gate-on voltage is supplied from the scan line S[i], such a ninth transistor T9 is turned on. When the ninth transistor T9 is turned on, the second data signal supplied to the second data line D2[j] is transmitted to the second node N2.

[0108] The second capacitor C2 is connected between the first power supply VDD and the second node N2. Such a second capacitor C2 is charged with a voltage corresponding to the second data signal transmitted to the second node N2 in each frame period (specifically, the data programming period of each frame) and the threshold voltage of the first transistor T1, and maintains the charged voltage until the second data signal of the next frame is transmitted.

[0109] The pixel PXL according to the above-described embodiment includes a plurality of light source units LSU connected to different separation electrodes. For example, the pixel PXL may include a first light source unit LSU1 and a second light source unit LSU2 connected to a first separation electrode ELT11 and a second separation electrode ELT12, respectively. The first switching unit 102 and the second switching unit 103 may be connected between the first transistor T1 for generating a driving current of the pixel PXL and the first light source unit LSU1 and the second light source unit LSU2.

[0110] According to the above-described embodiment, by supplying a second data signal of a gate-on voltage or a gate-off voltage to each pixel PXL in each frame period via the second data line D2[j], at least some of the first light source unit LSU1 and the second light source unit LSU2 can be selectively driven for each pixel PXL in each frame period. For example, by supplying a second data signal of a gate-off voltage to a pixel PXL that should represent a low grayscale equal to or less than a predetermined grayscale during a corresponding period, control can be performed so that a driving current flows only to the first light source unit LSU1. Therefore, the amount of current flowing through each light emitting element LD (specifically, at least one first light emitting element LD1 connected to the first light source unit LSU1 in the forward direction) can be increased. According to the above-described embodiment, the difficulty of controlling the light emission of each light emitting element LD with a tiny current can be overcome, and the desired grayscale can be represented more accurately. In other words, according to an embodiment of the present disclosure, even in a low grayscale area, the grayscale can be represented more accurately.

[0111] Figure 6a and Figure 6b Both show Figure 5 Detailedly, Figure 6a and Figure 6b 1 and 2 are plan views showing different embodiments related to the structure and arrangement of the first light source unit LSU1 and the second light source unit LSU2. Figure 6a and Figure 6b Only the display element layer in which the first light source unit LSU1 and the second light source unit LSU2 are arranged is shown. Each pixel PXL may further include a circuit element (eg, Figure 5 The circuit elements may be disposed in a pixel circuit layer or the like disposed below the display element layer, but the positions of the circuit elements are not limited thereto.

[0112] Reference Figure 6a and Figure 6b as well as Figures 1a to 5 , each pixel PXL may include a plurality of light source units LSU (eg, at least a first light source unit LSU1 and a second light source unit LSU2 ).

[0113] In an embodiment, the first light source unit LSU1 may include a first separation electrode ELT11, a second pixel electrode ELT2, and at least one first light emitting element LD1 connected between the first separation electrode ELT11 and the second pixel electrode ELT2. For example, the first light source unit LSU1 may include a first separation electrode ELT11 and a second pixel electrode ELT2 disposed in an emission region of a corresponding pixel PXL to be spaced apart from each other, and a plurality of first light emitting elements LD1 connected in parallel between the first separation electrode ELT11 and the second pixel electrode ELT2.

[0114] In an embodiment, the first separation electrode ELT11 may be connected to one end (hereinafter, referred to as "first end EP1") of each of the first light emitting elements LD1. For example, the first separation electrode ELT11 may be in direct contact with and / or directly connected to the first end EP1 of each of the first light emitting elements LD1, or may be connected to the first end EP1 of each of the first light emitting elements LD1 through at least one first contact electrode CNE1.

[0115] In addition, the first separation electrode ELT11 may be connected to at least one circuit element forming a pixel circuit of the corresponding pixel PXL. For example, the first separation electrode ELT11 may be connected to the Figure 5 The sixth transistor T6.

[0116] However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first separation electrode ELT11 may be connected to the second power source VSS through the first contact hole CH1, and the second pixel electrode ELT2 may be connected to the second power source VSS through the second contact hole CH2. Figure 5 Alternatively, in another embodiment of the present disclosure, any one of the first separation electrode ELT11 and the second pixel electrode ELT2 may be directly connected to the first power line PL1 or the second power line PL2 without passing through a contact hole or a circuit element.

[0117] At least one region of the first separation electrode ELT11 may be disposed opposite to at least one region of the second pixel electrode ELT2, and a plurality of first light emitting elements LD1 may be connected between the first separation electrode ELT11 and the second pixel electrode ELT2. In the present disclosure, there is no particular limitation on the direction in which the first light emitting elements LD1 are arranged. In addition, the first light emitting elements LD1 may be connected in series and / or in parallel between the first separation electrode ELT11 and the second pixel electrode ELT2.

[0118] In an embodiment, the second pixel electrode ELT2 may be connected to the other end (hereinafter, referred to as "second end EP2") of each of the first light emitting elements LD1. For example, the second pixel electrode ELT2 may be in direct contact with and / or directly connected to the second end EP2 of each of the first light emitting elements LD1, or may be connected to the second end EP2 of each of the first light emitting elements LD1 through at least one second contact electrode CNE2.

[0119] In addition, the second pixel electrode ELT2 may be connected to the second power source VSS. For example, the second pixel electrode ELT2 may be connected to the second power source VSS through the second contact hole CH2 and the second power line PL2.

[0120] In an embodiment, the second pixel electrode ELT2 may be commonly formed on the first and second light source units LSU1 and LSU2. For example, the second pixel electrode ELT2 may be commonly connected between the second end EP2 of each of the first and second light emitting elements LD1 and LD2 and the second power source VSS.

[0121] Each of the first light emitting elements LD1 may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size (eg, ranging from a nanometer scale to a micrometer scale). Figures 1a to 3b An ultra-small rod-shaped light emitting diode according to any one of the embodiments.

[0122] In an embodiment, at least one pair of contact electrodes may be connected to both ends of the first light emitting element LD1. For example, at least one first contact electrode CNE1 may be connected to the first end EP1 of each of the first light emitting elements LD1, and at least one second contact electrode CNE2 may be connected to the second end EP2 of each of the first light emitting elements LD1.

[0123] In an embodiment, the second light source unit LSU2 may include a second separation electrode ELT12, a second pixel electrode ELT2, and at least one second light emitting element LD2 connected between the second separation electrode ELT12 and the second pixel electrode ELT2. For example, the second light source unit LSU2 may include a second separation electrode ELT12 and a second pixel electrode ELT2 that are disposed in an emission region of a corresponding pixel PXL to be spaced apart from each other, and a plurality of second light emitting elements LD2 that are connected in parallel between the second separation electrode ELT12 and the second pixel electrode ELT2.

[0124] In an embodiment, the second separation electrode ELT12 may be connected to one end (hereinafter, referred to as "first end EP1") of each of the second light emitting elements LD2. For example, the second separation electrode ELT12 may be in direct contact with and / or directly connected to the first end EP1 of each of the second light emitting elements LD2, or may be connected to the first end EP1 of each of the second light emitting elements LD2 through at least one first contact electrode CNE1.

[0125] In addition, the second separation electrode ELT12 may be connected to at least one circuit element forming a pixel circuit of the corresponding pixel PXL. For example, the second separation electrode ELT12 may be connected to the Figure 5 The seventh transistor T7.

[0126] However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the second separation electrode ELT12 may be connected to the second power source VSS through the third contact hole CH3, and the second pixel electrode ELT2 may be connected to the second power source VSS through the second contact hole CH2. Figure 5 Alternatively, in another embodiment of the present disclosure, any one of the second separation electrode ELT12 and the second pixel electrode ELT2 may be directly connected to the first power line PL1 or the second power line PL2 without passing through a contact hole or a circuit element.

[0127] At least one region of the second separation electrode ELT12 may be arranged to be opposite to at least one region of the second pixel electrode ELT2, and a plurality of second light emitting elements LD2 may be connected between the second separation electrode ELT12 and the second pixel electrode ELT2. In the present disclosure, the direction along which the second light emitting elements LD2 are arranged is not particularly limited. In addition, the second light emitting elements LD2 may be connected in series and / or in parallel between the second separation electrode ELT12 and the second pixel electrode ELT2.

[0128] In an embodiment, the second pixel electrode ELT2 may be connected to the other end (hereinafter, referred to as "second end EP2") of each of the second light emitting elements LD2. For example, the second pixel electrode ELT2 may be in direct contact with and / or directly connected to the second end EP2 of each of the second light emitting elements LD2, or may be connected to the second end EP2 of each of the second light emitting elements LD2 through at least one second contact electrode CNE2. Such a second pixel electrode ELT2 may be connected to a second power supply VSS.

[0129] Each of the second light emitting elements LD2 may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size (eg, ranging from a nanometer scale to a micrometer scale). Figures 1a to 3b An ultra-small rod-shaped light emitting diode according to any one of the embodiments.

[0130] In an embodiment, at least one pair of contact electrodes may be connected to both ends of the second light emitting element LD2, respectively. For example, at least one first contact electrode CNE1 may be connected to the first end EP1 of each of the second light emitting elements LD2, and at least one second contact electrode CNE2 may be connected to the second end EP2 of each of the second light emitting elements LD2.

[0131] In an embodiment, the first light emitting element LD1 and the second light emitting element LD2 (hereinafter, collectively referred to as "light emitting element LD") may be prepared in the form that they are dispersed in a predetermined solution (hereinafter, referred to as "LED solution"), and then may be supplied to each pixel area using an inkjet method. For example, the light emitting element LD may be mixed with a volatile solvent and supplied to the emission area of ​​each pixel PXL. If a predetermined voltage (also referred to as an "alignment voltage") is applied to the first pixel electrode ELT1 (or the first pixel electrode ELT1 integrally connected before the first separation electrode ELT11 and the second separation electrode ELT12 are separated) and the second pixel electrode ELT2, an electric field is generated between the first pixel electrode ELT1 and the second pixel electrode ELT2, so that the light emitting element LD is self-aligned between the first pixel electrode ELT1 and the second pixel electrode ELT2. After aligning the light emitting element LD, the solvent may be removed by a volatilization method or other methods. In this way, the light emitting element LD may be stably arranged between the first pixel electrode ELT1 and the second pixel electrode ELT2.

[0132] Each of the first contact electrode CNE1 and the second contact electrode CNE2 may contact and / or be electrically connected to any one of the first pixel electrode ELT1 and the second pixel electrode ELT2 and at least one end of at least one of the light emitting elements LD. For example, each first contact electrode CNE1 may cover the first end EP1 of at least one first light emitting element LD1 (or at least one second light emitting element LD2), and at least one region of the first separation electrode ELT11 or the second separation electrode ELT12 corresponding to the first end EP1. Through the first contact electrode CNE1, the first end EP1 of at least one first light emitting element LD1 (or at least one second light emitting element LD2) may be connected to the first separation electrode ELT11 or the second separation electrode ELT12. Similarly, each second contact electrode CNE2 may cover the second end EP2 of at least one first light emitting element LD1 (or at least one second light emitting element LD2), and at least one region of the second pixel electrode ELT2 corresponding to the second end EP2. Through the second contact electrode CNE2, the second end EP2 of at least one first light emitting element LD1 (or at least one second light emitting element LD2) may be connected to the second pixel electrode ELT2.

[0133] The light emitting elements LD connected between the first separation electrode ELT11 or the second separation electrode ELT12 and the second pixel electrode ELT2 may be aggregated to form a light source unit LSU of the corresponding pixel PXL. For example, at least one first light emitting element LD1 connected between the first separation electrode ELT11 and the second pixel electrode ELT2 in the forward direction may form a first light source unit LSU1, and at least one second light emitting element LD2 connected between the second separation electrode ELT12 and the second pixel electrode ELT2 in the forward direction may form a second light source unit LSU2. When a driving current is supplied from the driving current generator 101, each of the first light emitting element LD1 and the second light emitting element LD2 may emit light having a brightness corresponding to the driving current.

[0134] In an embodiment, the first light source unit LSU1 and the second light source unit LSU2 may be formed in regions having the same or different areas. Figure 6a, as shown in the figure, is formed in regions having different areas. In this case, the first separate electrode ELT11 and the second separate electrode ELT12 or the second pixel electrode ELT2 provided in the first light source unit LSU1 and the second light source unit LSU2 may have different shapes, quantities and / or areas. However, the present disclosure is not limited thereto. For example, even if the first light source unit LSU1 and the second light source unit LSU2 are provided in regions having different areas, the first separate electrode ELT11 and the second separate electrode ELT12 or the second pixel electrode ELT2 provided in the first light source unit LSU1 and the second light source unit LSU2 may have the same shape, quantity and / or area.

[0135] In another embodiment, the first light source unit LSU1 and the second light source unit LSU2 may be as follows: Figure 6b In this case, the first separate electrode ELT11 and the second separate electrode ELT12 or the second pixel electrode ELT2 provided in the first light source unit LSU1 and the second light source unit LSU2 may have the same shape, number and / or area. However, the present disclosure is not limited thereto. For example, even if the first light source unit LSU1 and the second light source unit LSU2 are provided in an area having the same area, the first separate electrode ELT11 and the second separate electrode ELT12 or the second pixel electrode ELT2 provided in the first light source unit LSU1 and the second light source unit LSU2 may have different shapes, numbers and / or areas.

[0136] In an embodiment, the first light source unit LSU1 and the second light source unit LSU2 may include the same number or different numbers of first light emitting elements LD1 and second light emitting elements LD2. Figure 6a As shown in FIG. 1 , the number of first light emitting elements LD1 provided in the first light source unit LSU1 may be different from the number of second light emitting elements LD2 provided in the second light source unit LSU2 .

[0137] In another embodiment, if Figure 6b As shown in , the number of first light emitting elements LD1 provided in the first light source unit LSU1 may be equal to the number of second light emitting elements LD2 provided in the second light source unit LSU2.

[0138] Furthermore, in an embodiment, the first light source unit LSU1 may include a plurality of first light emitting elements LD1 connected between the first separation electrode ELT11 and the second pixel electrode ELT2 in different directions. For example, some of the first light emitting elements LD1 may be connected between the first separation electrode ELT11 and the second pixel electrode ELT2 in the forward direction for light emission of the pixel PXL, and some of the first light emitting elements LD1 may be connected between the first separation electrode ELT11 and the second pixel electrode ELT2 in the reverse direction. Similarly, some of the second light emitting elements LD2 may be connected between the second separation electrode ELT12 and the second pixel electrode ELT2 in the forward direction for light emission of the pixel PXL, and some of the second light emitting elements LD2 may be connected between the second separation electrode ELT12 and the second pixel electrode ELT2 in the reverse direction.

[0139] However, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the first light source unit LSU1 and / or the second light source unit LSU2 may include only a single light emitting element LD connected between the first pixel electrode ELT1 and the second pixel electrode ELT2, or may include a plurality of light emitting elements LD connected between the first pixel electrode ELT1 and the second pixel electrode ELT2 in any direction (e.g., the forward direction).

[0140] Figure 7 Shows the drive Figure 5 In the following, reference will be made to the method for displaying a pixel PXL. Figure 7 and Figure 5 Further description of the driver Figure 5 The method of the pixel PXL is shown in FIG.

[0141] Reference Figure 5 and Figure 7 During one frame period 1F, the emission control signal EMIi of the gate-off voltage is first supplied to the emission control line E[i]. During the period of supplying the emission control signal EMIi, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 maintain a turned-off state.

[0142] During the period of supplying the emission control signal EMIi of the gate-off voltage, the previous scan signal SSi-1 and the current scan signal SSi are sequentially supplied to the initialization control line CL[i] (for example, the previous scan line S[i-1] of the initialization control line CL[i]) and the current scan line S[i], respectively. The previous scan signal SSi-1 and the current scan signal SSi may both have the gate-on voltage.

[0143] During the first period PI1 of the previous scanning signal SSi-1 supplying the gate-on voltage, the pixel PXL is initialized. For example, if the previous scanning signal SSi-1 is supplied, the fourth transistor T4 is turned on, and the voltage of the initialization power supply VINT is transmitted to the first node N1. Therefore, the voltage stored in the first capacitor C1 and the gate voltage of the first transistor T1 in the previous frame period are initialized by the voltage of the initialization power supply VINIT. When the voltage of the initialization power supply VINIT is set to be less than or equal to the lowest voltage of the first data signal, and therefore the voltage of the initialization power supply VINIT is sent to the first node N1, the first transistor T1 is turned on.

[0144] During the second period PI2 when the current scan signal SSi of the gate-on voltage is supplied, the first data signal DS1 and the second data signal DS2 are transmitted to the pixel PXL. For example, if the current scan signal SSi is supplied, the second transistor T2, the third transistor T3 and the ninth transistor T9 are turned on.

[0145] If the second transistor T2 and the third transistor T3 are turned on, the first data signal DS1 supplied to the first data line D1[j] is sequentially transmitted to the first node N1 through the second transistor T2, the first transistor T1, and the third transistor T3. Since the first transistor T1 is connected in a diode form through the third transistor T3, a voltage corresponding to the first data signal DS1 and the threshold voltage of the first transistor T1 (for example, a voltage corresponding to the voltage difference between the first data signal DS1 and the threshold voltage of the first transistor T1) is transmitted to the first node N1. The voltage transmitted to the first node N1 is charged in the first capacitor C1. For example, a voltage corresponding to the voltage difference between the first power supply VDD and the first node N1 may be charged in the first capacitor C1.

[0146] When the ninth transistor T9 is turned on, the second data signal DS2 supplied to the second data line D2[j] is transmitted to the second node N2 through the ninth transistor T9. The voltage transmitted to the second node N2 is charged in the second capacitor C2.

[0147] After the initialization step and the charging of the first data signal DS1 and the second data signal DS2 are completed, the supply of the emission control signal EMIi of the gate cut-off voltage is stopped. During the third period PI3, the voltage of the emission control signal EMIi maintains the gate on voltage. Therefore, when the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, the pixel PXL emits light with a brightness corresponding to the first data signal DS1 (when the first data signal DS1 corresponding to the black grayscale is supplied, the pixel PXL does not emit light).

[0148] More specifically, if the fifth transistor T5 and the sixth transistor T6 are turned on, a current path is formed from the first power supply VDD via the fifth transistor T5, the first transistor T1 and the sixth transistor T6 and the first light source unit LSU1 toward the second power supply VSS. During the third period PI3, the first transistor T1 generates a driving current corresponding to the voltage of the first node N1. Since the threshold voltage of the first transistor T1 is stored together with the voltage of the first data signal DS1 during the second period PI2, the threshold voltage of the first transistor T1 is offset during the third period PI3, so that the driving current corresponding to the voltage of the first data signal DS1 flows through the pixel PXL regardless of the threshold voltage of the first transistor T1. Therefore, it is possible to Figure 4 ) shows an image of uniform quality.

[0149] At the same time, if the eighth transistor T8 is turned on, the second node N2 is connected to the gate electrode of the seventh transistor T7, so that the voltage of the second data signal DS2 supplied to the second node N2 is transmitted to the gate electrode of the seventh transistor T7. Therefore, the on-off of the seventh transistor T7 can be determined according to the voltage level of the second data signal DS2.

[0150] In an embodiment, the second data signal DS2 may have a predetermined gate-on voltage (hereinafter referred to as "first voltage") (e.g., a low voltage capable of stably turning on the seventh transistor T7), or may have a predetermined gate-off voltage (hereinafter referred to as "second voltage") (e.g., a high voltage capable of stably turning off the seventh transistor T7). When the gate-on voltage is transmitted to the second node N2 during the second period PI2, the seventh transistor T7 is turned on. At the same time, when the gate-off voltage is transmitted to the second node N2 during the second period PI2, the seventh transistor T7 is turned off.

[0151] If the seventh transistor T7 is turned on by the second data signal DS2 of the first voltage, the first light source unit LSU1 and the second light source unit LSU2 are connected in parallel between the first transistor T1 and the second power source VSS during the third period PI3. Therefore, the driving current from the first transistor T1 is distributed and flows in the first light source unit LSU1 and the second light source unit LSU2.

[0152] If the seventh transistor T7 is turned off by the second data signal DS2 of the second voltage, during the third period PI3, the connection between the first transistor T1 and the second light source unit LSU2 is interrupted, and only the connection between the first transistor T1 and the first light source unit LSU1 is maintained through the sixth transistor T6. Therefore, the driving current from the first transistor T1 is supplied only to the first light source unit LSU1.

[0153] Assuming that the pixel PXL expresses the same grayscale, when comparing a case where only the first light source unit LSU1 is selectively driven with a case where both the first light source unit LSU1 and the second light source unit LSU2 are driven, in the former case, the amount of current flowing in each first light emitting element LD1 (specifically, the first light emitting element LD1 connected in the forward direction) increases. Therefore, the low grayscale expression of the pixel PXL can be improved.

[0154] According to the above-described embodiment, by supplying the second data signal DS2 of the first voltage (gate-on voltage) or the second voltage (gate-off voltage) to each pixel PXL in each frame period 1F via the second data line D2[j], at least some of the first light source unit LSU1 and the second light source unit LSU2 can be selectively driven for each pixel PXL in each frame period 1F. For example, by supplying the second data signal DS2 of the second voltage to the pixel PXL during a period in which each pixel PXL exhibits a low grayscale equal to or less than a predetermined grayscale, the seventh transistor T7 can be controlled to be in a cut-off state during an emission period of the corresponding frame period 1F. In this case, the driving current generated from the driving current generator 101 is supplied only to the first light source unit LSU1. Therefore, when comparing a case in which both the first light source unit LSU1 and the second light source unit LSU2 exhibit grayscales with a case in which only the first light source unit LSU1 exhibits the same grayscale, the amount of current flowing in the first light source unit LSU1 increases in the latter case. Therefore, when the amount of current flowing in each first light emitting element LD1 provided in the first light source unit LSU1 (specifically, the first light emitting element LD1 to be activated connected between the first power source VDD and the second power source VSS in the forward direction) increases, the first light emitting element LD1 can emit light with desired brightness. According to an embodiment of the present disclosure, grayscale can be more accurately represented even in a low grayscale area.

[0155] Meanwhile, during each frame period 1F in which each pixel PXL exhibits a high grayscale higher than a predetermined grayscale, a second data signal DS2 of a first voltage (gate-on voltage) may be supplied to the pixel PXL through the second data line D2[j], thereby driving both the first light source unit LSU1 and the second light source unit LSU2. Therefore, by effectively utilizing the light emitting element LD provided in each pixel PXL, the pixel PXL may emit light having a desired brightness.

[0156] Figure 8 1 shows a timing controller 140 according to an embodiment of the present disclosure. For example, Figure 8 It shows that it can be Figure 4 1 is a block diagram of an embodiment of a timing controller 140 provided in a display device.

[0157] refer to Figures 4 to 8 The timing controller 140 according to an embodiment of the present disclosure may output first data DATA1 corresponding to image data RGB and second data DATA2 corresponding to the grayscale of the image data RGB. To achieve the above purpose, the timing controller 140 may include a data processor 141 and a grayscale determiner 142.

[0158] The data processor 141 may process the image data RGB to generate the first data DATA1. For example, the data processor 141 may generate the first data DATA1 by rearranging the image data RGB according to the specification of each display panel.

[0159] The grayscale determiner 142 may compare the grayscale value of each pixel PXL included in the image data RGB with a predetermined reference grayscale value, and then generate the second data DATA2 corresponding to the comparison result. For example, when the grayscale value of each pixel PXL is greater than the reference grayscale value (or, when the grayscale value of each pixel PXL is equal to or greater than the reference grayscale value), the grayscale determiner 142 may output the second data DATA2 having a predetermined first grayscale value (e.g., a white grayscale value) corresponding to the first voltage (gate-on voltage). At the same time, when the grayscale value of each pixel PXL is equal to or less than the reference grayscale value (or, when the grayscale value of each pixel PXL is smaller than the reference grayscale value), the grayscale determiner 142 may output the second data DATA2 having a predetermined second grayscale value (e.g., a black grayscale value) corresponding to the second voltage (gate-off voltage).

[0160] In an embodiment, the reference gray value may be set differently according to the characteristics of the display panel. For example, when the gray value represented by the display device is in the range from 0 gray (e.g., black gray) to 255 gray (e.g., white gray), the reference gray value may be 32 gray falling within the low gray range. However, the present disclosure is not limited thereto, and the reference gray value may be changed differently.

[0161] In an embodiment, the timing controller 140 may alternately output the first data DATA1 and the second data DATA2. For example, in the case of outputting the first data DATA1 and the second data DATA2 corresponding to each frame, the timing controller 140 may sequentially output the first data DATA1 and the second data DATA2 to the second pixel after sequentially outputting the first data DATA1 and the second data DATA2 to the first pixel. In this way, the timing controller 140 may output the first data DATA1 and the second data DATA2 of the pixel PXL corresponding to each frame.

[0162] In another embodiment, the timing controller 140 may output the first data DATA1 and the second data DATA2 simultaneously. For example, in the case of outputting the first data DATA1 and the second data DATA2 corresponding to each frame, the timing controller 140 may output the first data DATA1 and the second data DATA2 simultaneously to the first pixel and then output the first data DATA1 and the second data DATA2 simultaneously to the second pixel. In this way, the timing controller 140 may output the first data DATA1 and the second data DATA2 of the pixel PXL corresponding to each frame.

[0163] The first data DATA1 and the second data DATA2 output from the timing controller 140 are supplied to the data driver 130. Then, the data driver 130 generates a first data signal DS1 and a second data signal DS2 using the first data DATA1 and the second data DATA2, respectively.

[0164] Fig. 9 1 shows a data driver 130 according to an embodiment of the present disclosure. For example, Fig. 9 It shows that it can be Figure 4 1 is a block diagram of an embodiment of a data driver 130 provided in a display device of FIG.

[0165] Reference Figures 4 to 9 The data driver 130 according to an embodiment of the present disclosure may alternately receive first data DATA1 and second data DATA2 of each pixel PXL from the timing controller 140. The data driver 130 may generate first data signals DS1 and second data signals DS2 corresponding to the first data DATA1 and the second data DATA2, respectively.

[0166] In an embodiment, the data driver 130 may include a shift register unit 131, a sampling latch unit 132, a holding latch unit 133, a data signal generator 134, and a buffer unit 135. Here, the shift register unit 131, the sampling latch unit 132, and the holding latch unit 133 may constitute an input circuit of the data driver 130, and the buffer unit 135 may constitute an output circuit of the data driver 130.

[0167] The shift register unit 131 may receive a source start pulse SSP and a source sampling clock SSC from the timing controller 140. The shift register unit 131 may sequentially generate sampling pulses while shifting the source start pulse SSP in each cycle of the source sampling clock SSC. To this end, the shift register unit 131 may be provided with a plurality of shift registers. For example, the shift register unit 131 may be provided with shift registers corresponding to the number of the first data lines D1 and the second data lines D2 (e.g., 2m shift registers).

[0168] The sampling latch unit 132 may sequentially store the first data DATA1 and the second data DATA2 supplied from the timing controller 140 to correspond to the sampling pulses sequentially supplied from the shift register unit 131. To this end, the sampling latch unit 132 may be provided with a plurality of sampling latches. For example, the sampling latch unit 132 may be provided with sampling latches corresponding to the number of the first data line D1 and the second data line D2 (for example, 2m sampling latches). In an embodiment, the first data DATA1 corresponding to the first pixel may be stored in the sampling latch of the first channel, and the second data DATA2 corresponding to the first pixel may be stored in the sampling latch of the second channel. In addition, the first data DATA1 corresponding to the second pixel may be stored in the sampling latch of the third channel, and the second data DATA2 corresponding to the second pixel may be stored in the sampling latch of the fourth channel. In this way, the first data DATA1 or the second data DATA2 corresponding to any one pixel PXL may be stored in each sampling latch.

[0169] The holding latch unit 133 may receive a source output enable signal SOE from the timing controller 140. When the source output enable signal SOE is input, such a holding latch unit 133 may receive the first data DATA1 and the second data DATA2 from the sampling latch unit 132 to store the first data DATA1 and the second data DATA2. For example, the holding latch unit 133 may simultaneously receive the first data DATA1 and the second data DATA2 from the sampling latch unit 132 in response to the source output enable signal SOE. In addition, when the source output enable signal SOE is input, the holding latch unit 133 may supply the first data DATA1 and the second data DATA2 stored therein to the data signal generator 134. To this end, the holding latch unit 133 may be provided with a plurality of holding latches. For example, the holding latch unit 133 may be provided with holding latches corresponding to the number of the first data line D1 and the second data line D2 (for example, 2m holding latches).

[0170] Despite Fig. 9 1 shows that the input circuit of the data driver 130 is composed of a shift register unit 131, a sampling latch unit 132, and a holding latch unit 133, but the present disclosure is not limited thereto. For example, the input circuit may also include various known components.

[0171] The data signal generator 134 may generate a first data signal DS1 and a second data signal DS2 using the first data DATA1 and the second data DATA2 supplied from the input circuit, respectively. To this end, the data signal generator 134 may include a plurality of digital-to-analog converters arranged in each channel. Each digital-to-analog converter (hereinafter, referred to as a "DAC") may select any one of the gamma voltages Gamma in response to the first data DATA1 or the second data DATA2 supplied to the converter, and may supply the selected gamma voltage Gamma as the first data signal DS1 or the second data signal DS2 to each channel of the buffer unit 135. For example, a first DAC located in a first channel of the data signal generator 134 may generate a first data signal DS1 corresponding to the first data DATA1 of the first pixel, and may supply the first data signal DS1 to a first buffer provided in the first channel of the buffer unit 135. In addition, a second DAC located in a second channel of the data signal generator 134 may generate a second data signal DS2 corresponding to the second data DATA2 of the first pixel, and may supply the second data signal DS2 to a second buffer provided in a second channel of the buffer unit 135. Similarly, the third DAC located in the third channel of the data signal generator 134 may generate a first data signal DS1 corresponding to the first data DATA1 of the second pixel, and may supply the first data signal DS1 to a third buffer provided in the third channel of the buffer unit 135. In addition, the fourth DAC located in the fourth channel of the data signal generator 134 may generate a second data signal DS2 corresponding to the second data DATA2 of the second pixel, and may supply the second data signal DS2 to a fourth buffer provided in the fourth channel of the buffer unit 135. In this manner, the data signal generator 134 may generate the first data signal DS1 and the second data signal DS2 corresponding to the first data DATA1 and the second data DATA2 of each pixel PXL, respectively, and may output the first data signal DS1 and the second data signal DS2 to each channel of the buffer unit 135.

[0172] The buffer unit 135 includes a plurality of buffers provided in each channel of the data driver 130. Such a buffer unit 135 supplies the first data signal DS1 and the second data signal DS2 supplied from the data signal generator 134 to the first data line D1 and the second data line D2, respectively. For example, the buffer unit 135 may supply the first data signal DS1 of the first pixel supplied from the first channel of the data signal generator 134 to the 1st first data line D1[1], and may supply the second data signal DS2 of the first pixel supplied from the second channel of the data signal generator 134 to the 1st second data line D2[1]. In this manner, the buffer unit 135 may supply the first data signal DS1 and the second data signal DS2 supplied from the data signal generator 134 to the first data line D1 and the second data line D2, respectively. For example, the buffer unit 135 may supply the first data signal DS1 and the second data signal DS2 supplied from the data signal generator 134 to the 1st first data line D1[1] to the mth first data line D1[m] and the 1st second data line D2[1] to the mth second data line D2[m], respectively.

[0173] The data driver 130 according to the above-described embodiment may be provided with data channels having a number corresponding to the number of the first data lines D1 and the second data lines D2. For example, the data driver 130 may include odd data channels corresponding to each first data line D1 (hereinafter, referred to as "first data channels") and even data channels corresponding to each second data line D2 (hereinafter, referred to as "second data channels"). For example, the data driver 130 may include m j-th data channel pairs CH[j], the j-th data channel pair CH[j] including the j-th first data channel CH1[j] and the j-th second data channel CH2[j], which are connected to the pixels PXL arranged on the j-th (j is a natural number greater than or equal to 1 and less than or equal to m) vertical line.

[0174] The data driver 130 may generate first and second data signals DS1 and DS2 corresponding to first and second data DATA1 and DATA2 of each pixel PXL. The first and second data signals DS1 and DS2 generated from the data driver 130 are supplied to corresponding pixels PXL through corresponding first and second data lines D1 and D2.

[0175] Fig.10 1 shows a data driver 130 according to an embodiment of the present disclosure. For example, Fig.10 It shows that according to Fig. 9 A modified block diagram of the data driver 130 of the embodiment of FIG. Fig.10 In the drawings, the same reference numerals are used to indicate Fig. 9The components of the embodiments are similar or identical components, and further description thereof will be omitted.

[0176] refer to Fig.10 According to an embodiment of the present disclosure, the data driver 130 may simultaneously receive the first data DATA1 and the second data DATA2 from the timing controller 140, and may generate the first data signal DS1 and the second data signal DS2 corresponding to the first data DATA1 and the second data DATA2. To this end, the shift register unit 131 may include a first shift register part 1311 and a second shift register part 1312 that are simultaneously driven by the source start pulse SSP and the source sampling clock SSC.

[0177] The first shift register part 1311 may sequentially generate sampling pulses in response to the source start pulse SSP and the source sampling clock SSC, and may supply the sampling pulses to some channels of the sampling latch unit 132. For example, the first shift register part 1311 may sequentially supply the sampling pulses from the timing controller 140 to the shift registers of the odd channels into which the first data DATA1 is input.

[0178] The second shift register part 1312 may sequentially generate sampling pulses in response to the source start pulse SSP and the source sampling clock SSC, and may supply the sampling pulses to other channels of the sampling latch unit 132. For example, the second shift register part 1312 may sequentially supply the sampling pulses from the timing controller 140 to the shift registers of the even channels into which the second data DATA2 is input.

[0179] Therefore, first data DATA1 of the corresponding pixel PXL may be sequentially input into the sampling latches disposed in odd channels of the sampling latch unit 132 , and second data DATA2 of the corresponding pixel PXL may be sequentially input into the sampling latches disposed in even channels of the sampling latch unit 132 .

[0180] The remaining operations of the data driver 130 may be substantially equal to or similar to those of the above-described embodiment. Therefore, detailed descriptions thereof will be omitted.

[0181] The pixel PXL and the display device having the same according to the above-described embodiment selectively drives at least some of the light emitting elements LD, and in response to the grayscale to be represented in the pixel PXL, the light emitting element LD drives each pixel PXL to emit light having a brightness corresponding to the image data RGB, and constitutes the light source unit LSU of the pixel PXL. To this end, the first pixel electrode ELT1 of each pixel PXL is divided into a first separation electrode ELT11 and a second separation electrode ELT12 to be connected to different switching elements (e.g., the sixth transistor T6 and the seventh transistor T7).

[0182] In an embodiment, when the grayscale value of the image data RGB corresponding to each pixel PXL falls within a low grayscale range (or low grayscale area) equal to or less than a predetermined reference grayscale value, during the emission period (e.g., Figure 7 During the third period PI3 of the embodiment, the seventh transistor T7 is controlled to be in the off state, thereby supplying the driving current only to the first light source unit LSU1 and preventing the driving current from being supplied to the second light source unit LSU2. According to the embodiment of the present disclosure, even in a low grayscale area, grayscale can be more accurately represented.

[0183] More specifically, if both the first light source unit LSU1 and the second light source unit LSU2 are driven to express corresponding grayscales, the driving current is distributed to the first light source unit LSU1 and the second light source unit LSU2, so that the intensity of the current flowing in each light emitting element LD is reduced. It is difficult to control the brightness of each light emitting element LD with a low current compared to controlling the brightness of each light emitting element LD with a higher current. Therefore, when grayscales are expressed by driving both the first light source unit LSU1 and the second light source unit LSU2 in a low grayscale range where the grayscale is equal to or less than a predetermined reference grayscale value, it may be difficult to accurately express the grayscale.

[0184] On the contrary, if only some light emitting elements LD (for example, the first light emitting element LD1 provided in the first light source unit LSU1) are selectively driven in a low grayscale range in which the grayscale is equal to or less than a predetermined reference grayscale value as in the embodiment of the present disclosure, the driving current is not supplied to the second light source unit LSU2 but only to the first light source unit LSU1, so that the current flowing in each first light emitting element LD1 increases. Therefore, the low grayscale expression of each pixel PXL and the display device including the pixel PX can be improved.

[0185] A method of driving a display device according to an embodiment of the present disclosure will be briefly described. The method of driving a display device may include: a step of generating first data DATA1 and second data DATA2 in response to image data RGB, a step of generating first data signals DS1 and second data signals DS2 in response to the first data DATA1 and second data DATA2 and supplying the first data signals DS1 and second data signals DS2 to each pixel PXL, and a step of generating a driving current in each pixel PXL in response to the first data signal DS1 and driving the light source unit LSU of the corresponding pixel PXL by the driving current. In addition, in an embodiment of the present disclosure, at least some of the light emitting elements LD (e.g., the first light emitting element LD1 or the first light emitting element LD1 and the second light emitting element LD2) among the plurality of light emitting elements LD (e.g., the first light emitting element LD1 and the second light emitting element LD2) constituting the light source unit LSU of each pixel PXL are selectively driven in response to the second data signal DS2.

[0186] In an embodiment, the step of generating the second data DATA2 may be a step of comparing the grayscale value of each pixel PXL included in the image data RGB with a predetermined reference grayscale value and generating the second data DATA2 corresponding to the comparison result. For example, the step of generating the second data DATA2 may include the step of outputting the second data DATA2 having a predetermined first grayscale value corresponding to the first voltage (gate-on voltage) when the grayscale value of the image data RGB corresponding to each pixel PXL is greater than the reference grayscale value, and outputting the second data DATA2 having a predetermined second grayscale value corresponding to the second voltage (gate-off voltage) when the grayscale value of the image data RGB corresponding to the pixel PXL is equal to or less than the reference grayscale value. In this case, when the grayscale value of the image data RGB corresponding to the pixel PXL is equal to or less than the reference grayscale value, the connection between some of the effective light-emitting elements LD (for example, the second light-emitting element LD2 among the effective light-emitting elements LD) set in the pixel PXL (for example, the first light-emitting element LD1 and the second light-emitting element LD2 connected in the forward direction) and the first transistor T1 (driving transistor) of the pixel PXL is interrupted, so that only other light-emitting elements LD among the effective light-emitting elements LD (for example, the first light-emitting element LD1 among the effective light-emitting elements LD) can be selectively driven. Therefore, the low grayscale expression of the pixel PXL and the display device including the pixel PXL can be improved. According to an embodiment of the present disclosure, the image quality of the display device can be improved.

[0187] Although the scope of the present disclosure is described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and modifications may be made here without departing from the scope of the disclosure as defined by the claims.

[0188] The scope of the present disclosure is not limited by the detailed description of this specification, but should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A pixel, comprising: A first light source unit including at least one first light emitting element connected between the first separation electrode and the second power source; A second light source unit including at least one second light emitting element connected between a second separation electrode and the second power source; a driving current generator including a first transistor connected between a first power source and the first and second light source units and generating a driving current corresponding to a first data signal supplied to a first data line; A first switching unit, comprising a first switching element connected between the driving current generator and the first light source unit; as well as a second switching unit including a second switching element connected between the driving current generator and the second light source unit and controlling a connection between the first transistor and the second light source unit in response to a second data signal supplied to a second data line, Among them, the second switching unit includes: a seventh transistor, which is connected between the first transistor and the second separation electrode as the second switching element; an eighth transistor, which is connected between the gate electrode of the seventh transistor and the second node and includes a gate electrode connected to the emission control line; a ninth transistor, which is connected between the second data line and the second node and includes a gate electrode connected to the scan line; and a second capacitor, which is connected between the first power supply and the second node.

2. The pixel according to claim 1, wherein: The first transistor includes a first electrode connected to the first power source, a second electrode commonly connected to the first switching element and the second switching element, and a gate electrode connected to a first node.

3. The pixel according to claim 2, wherein: The drive current generator further includes at least one of the following: a second transistor connected between the first data line and the first electrode of the first transistor and including a gate electrode connected to a scan line; a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected to the scan line; a fourth transistor connected between the first node and an initialization power source and including a gate electrode connected to an initialization control line; a fifth transistor connected between the first power source and the first electrode of the first transistor and including a gate electrode connected to an emission control line; as well as The first capacitor is connected between the first power source and the first node.

4. The pixel according to claim 1, in, The first switching unit includes a sixth transistor as the first switching element, and The sixth transistor is connected between the first transistor and the first separation electrode, and includes a gate electrode connected to an emission control line.

5. The pixel according to claim 1, wherein: The first light source unit comprises: the first separation electrode; a second pixel electrode spaced apart from the first separation electrode; and A plurality of first light emitting elements, including the at least one first light emitting element, are connected in parallel between the first separation electrode and the second pixel electrode.

6. The pixel according to claim 1, wherein: The second light source unit comprises: the second separation electrode; a second pixel electrode spaced apart from the second separation electrode; and A plurality of second light emitting elements, including the at least one second light emitting element, are connected in parallel between the second separation electrode and the second pixel electrode.

7. The pixel according to claim 1, in, The first split electrode and the second split electrode are disposed in a predetermined emission region to be spaced apart from each other, and The first light source unit and the second light source unit further include a second pixel electrode commonly connected between a first end of each of the at least one first light emitting element and the at least one second light emitting element and the second power source.

8. A display device, comprising: a timing controller configured to output first data corresponding to the image data and second data corresponding to the grayscale level of the image data; a data driver configured to generate a first data signal and a second data signal corresponding to the first data and the second data, respectively, and output the first data signal and the second data signal to a first data line and a second data line, respectively; as well as pixels, connected to the first data line and the second data line, Wherein, the pixels include: A first light source unit including at least one first light emitting element connected between the first separation electrode and the second power source; A second light source unit including at least one second light emitting element connected between a second separation electrode and the second power source; a driving current generator including a first transistor connected between a first power source and the first light source unit and the second light source unit, and generating a driving current corresponding to the first data signal; A first switching unit including a first switching element connected between the driving current generator and the first light source unit; and a second switching unit including a second switching element connected between the driving current generator and the second light source unit and controlling a connection between the first transistor and the second light source unit in response to the second data signal, Among them, the second switching unit includes: a seventh transistor, which is connected between the first transistor and the second separation electrode as the second switching element; an eighth transistor, which is connected between the gate electrode of the seventh transistor and the second node, and includes a gate electrode connected to the emission control line of the corresponding horizontal line; a ninth transistor, which is connected between the second data line and the second node, and includes a gate electrode connected to the scanning line of the corresponding horizontal line; and a second capacitor, which is connected between the first power supply and the second node.

9. The display device according to claim 8, wherein: The timing controller includes: a data processor configured to process the image data to generate the first data; and a grayscale determiner configured to compare the grayscale value of each pixel included in the image data with a predetermined reference grayscale value and generate the second data corresponding to the comparison result.

10. The display device according to claim 9, wherein: When the grayscale value of each pixel is greater than the reference grayscale value, the grayscale determiner outputs the second data having a predetermined first grayscale value corresponding to the gate-on voltage, and when the grayscale value of each pixel is equal to or less than the reference grayscale value, the grayscale determiner outputs the second data having a predetermined second grayscale value corresponding to the gate-off voltage.

11. The display device according to claim 8, comprising a pixel unit, wherein the pixel unit comprises: A plurality of pixels are arranged on n horizontal lines and m vertical lines, where n is a natural number of 2 or more, and m is a natural number of 2 or more; at least n scan lines connected to pixels of each horizontal line; and m first data lines and m second data lines connected to pixels of each vertical line, and The data driver includes 2m data channels connected to different data lines among the first data line and the second data line.

12. The display device according to claim 8, wherein: The first transistor includes a first electrode connected to the first power source, a second electrode commonly connected to the first switching element and the second switching element, and a gate electrode connected to a first node.

13. The display device according to claim 12, wherein: The drive current generator further includes at least one of the following: a second transistor connected between the first data line and the first electrode of the first transistor and including a gate electrode connected to a scan line of a corresponding horizontal line; a third transistor connected between the second electrode of the first transistor and the first node and including a gate electrode connected to the scan line; a fourth transistor connected between the first node and an initialization power source and including a gate electrode connected to an initialization control line of the corresponding horizontal line; a fifth transistor connected between the first power source and the first electrode of the first transistor and including a gate electrode connected to the emission control line of the corresponding horizontal line; as well as The first capacitor is connected between the first power source and the first node.

14. The display device according to claim 8, in, The first switching unit includes a sixth transistor as the first switching element, and The sixth transistor is connected between the first transistor and the first separation electrode, and includes a gate electrode connected to an emission control line of a corresponding horizontal line.

15. The display device according to claim 8, in, The first separation electrode and the second separation electrode are disposed in an emission region of the pixel to be spaced apart from each other, and The first light source unit and the second light source unit further include a second pixel electrode commonly connected between a first end of each of the at least one first light emitting element and the at least one second light emitting element and the second power source.

16. A method for driving the display device according to claim 8, the method comprising: generating first data corresponding to the image data; comparing the image data with a predetermined reference grayscale value, and generating second data corresponding to the comparison result; generating a first data signal and a second data signal corresponding to the first data and the second data, respectively, and supplying the first data signal and the second data signal to a pixel; as well as generating a driving current corresponding to the first data signal, and driving a light source unit of the pixel by the driving current, Wherein, in response to the second data signal, at least some of the plurality of light emitting elements of the light source unit forming the pixel are selectively driven.

17. The method according to claim 16, wherein: Generating the second data includes: When the grayscale value of the image data corresponding to the pixel is greater than the reference grayscale value, outputting the second data having a predetermined first grayscale value corresponding to the gate-on voltage, and When the grayscale value of the image data corresponding to the pixel is equal to or less than the reference grayscale value, the second data having a predetermined second grayscale value corresponding to a gate-off voltage is output.

18. The method according to claim 16, wherein: When the grayscale value of the image data corresponding to the pixel is equal to or less than the reference grayscale value, the connection between some of the plurality of light emitting elements and the driving transistor of the pixel is interrupted.

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