Low parasitic capacitance radio frequency transistor

Abstract

Structures and methods of manufacture for transistors with low parasitic capacitance, including an insulating low dielectric constant first handle wafer or second handle wafer. In one embodiment, an insulating LDC handle wafer is positioned proximate to a metal interconnect / metal layer stack of an SOI transistor using a single layer transfer technique in place of a conventional design silicon substrate. In another embodiment, a double layer transfer technique is used to replace a silicon substrate of a prior art structure with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity that reduces the effective dielectric constant of the material surrounding the RF FET. The insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides a more desirable division voltage for stacked transistors, enables a higher Q factor due to lower coupling loss, and additionally mitigates various parasitic effects.

Description

[0001] Cross-referencing of related applications – priority requirements

[0002] This application claims priority to U.S. Patent Application No. 16 / 243,947, filed January 9, 2019, entitled “Low Parasitic Capacitance RF Transistors,” which claims priority to U.S. Provisional Patent Application No. 62 / 712,845, filed July 31, 2018, also entitled “Low Parasitic Capacitance RF Transistors,” the entire contents of which are incorporated herein by reference.

[0003] This invention may relate to the following patent applications, which are assigned in their entirety to the assignee of this invention, the entire contents of which are incorporated herein by reference:

[0004] • U.S. Patent Application Serial No. 15 / 920,321, filed on March 13, 2018, entitled “Semiconductor-on-Insulator Transistor with Improved Breakdown Characteristics”;

[0005] • U.S. Patent Application Serial No. 16 / 040,295, entitled “Thermal Extraction of Single Layer Transfer Integrated Circuits”, filed on July 19, 2018;

[0006] • U.S. Patent Application Serial No. 16 / 040,390, entitled “SLT Integrated Circuit Capacitor Structure and Methods”, filed on July 19, 2018. Background Technology (1) Technical Field

[0008] This invention relates to electronic integrated circuits, and more specifically, to electronic integrated circuits having transistors manufactured using semiconductor-on-insulator technology. (2) Background Technology

[0010] Almost all modern electronic products, including laptop computers, mobile phones, and electric cars, use Complementary Metal Oxide Semiconductor (CMOS) Field Effect Transistors (FETs) integrated circuits (ICs) as switching devices, particularly for switching of radio frequency (RF) signals. In many cases, the CMOS ICs are fabricated using a semiconductor-on-insulator process such as Silicon-on-Insulator (SOI) or Germanium-on-Insulator. SOI transistors in which the electrical insulator is aluminum oxide (i.e., sapphire) are also known as Silicon-on-Sapphire or "SOS" devices. CMOS SOI FET circuits typically include n-type SOI FETs and p-type SOI FETs.

[0011] Figure 1 is a cross-sectional view of a prior art n-type SOI FET 100 fabricated on a buried oxide (BOX) layer 102, typically silicon dioxide SiO2, formed on a silicon substrate 104. The FET structure includes a doped source S spaced apart from a doped drain D by a body of opposite doping (for a so-called enhancement mode FET) in and / or on a silicon active layer 106 on the BOX layer 102. An electrically conductive gate (typically metal or polysilicon) is defined by an insulator 108 (e.g., oxide) that is spaced apart from the body. As is known in the art, a silicide layer (not shown) is typically formed over the source region, the drain region, and the gate region, and one or more metal interconnect layers (not shown) and one or more layers of insulating dielectric material (ILD) 110 (e.g., oxide or nitride) and a passivation layer (not shown) are typically formed over the FET structure to provide circuit connections, insulation, and environmental protection. The various layers of the FET structure can be formed by implantation, diffusion, and / or deposition in known ways. As is known in the art, a p-type SOI FET has a similar structure but with different dopants. Figure 1 is not shown in Figure 4 but see

[0012] Fabrication of the SOI FET 100 structure avoids certain parasitic effects typical of bulk silicon (Si) CMOS ICs. However, the BOX layer 102 itself causes some problems, such as parasitic capacitive coupling to the substrate, creation of so-called "back channel" transistors 112, thermal resistance to heat flow, and voltage breakdown paths to the substrate. The capacitive coupling to / from the substrate can cause many side effects for both analog and digital transistors, such as increased leakage current, lower breakdown voltage, cross-talk, increased junction temperature, and reduced linearity, all of which are compared to bulk silicon transistors or to SOI transistors with a truly insulating substrate such as SOS. For RF transistors, and especially for RF switches, additional side effects are insertion loss, isolation, non-ideal division voltage of stacked transistors, and distortion (also called non-linearity).

[0013] As described in the above-referenced U.S. Patent Application Serial No. 15 / 920,321, some parasitic side effects can be mitigated using a manufacturing technique known as single layer transfer or SLT. The SLT process utilizes mechanical support provided by a so-called handle wafer, typically fabricated from silicon, to invert the entire SOI transistor structure upside down. Figure 2 is a cross-sectional view of a prior art SLT transistor. Essentially, Figure 1 The “top” of the FET structure of is bonded to a handle wafer 202, and the original substrate 104 is removed (silicide and metal interconnect layers are not shown for clarity). A second ILD layer 204 can be formed on the newly exposed BOX layer for insulation and environmental protection.

[0014] Figure 3 is a more detailed cross-sectional view of an SLT transistor 300 with internal metal interconnect layers 304 plus a redistribution layer (RDL) 306 with source, drain, and gate (all within the dashed oval 302). More specifically, referring to Figure 3 The RDL 306 includes a conductive (e.g., metal) layer configured to control capacitive back channel parasitic effects using a conductive alignment supplement (“CAS”) gate 306a formed above the added ILD layer 204, as further described in U.S. Patent Application Serial No. 15 / 920,321. In the example shown, the internal metal interconnect layers 304 (example layers M1 through M5 are shown interspersed with layers of insulating dielectric material) are typically formed within the ILD layer 110 that insulates most of the active layer 106 from the first (M1) metal interconnect layer, except where holes or vias (omitted for clarity) are formed for electrical contact with the gate, source, and drain. Note that while the ILD layer 110 is shown as a unitary element in Figure 3 (and other figures), the ILD layer 110 is typically built in multiple layers during formation of the metal interconnect layers 304. Thus, the metal interconnect layers 304 are effectively embedded in the ILD layer 110, and are electrically connected between one another by conductive vias formed, for example, by etching and filling holes in the ILD layer 110.

[0015] The basic transistor structure including the internal metal interconnect layers 304 is typically formed within a CMOS manufacturing device, while the RDL 306 is typically formed after the SLT “flip” process step. Thus, the RDL 306 is added after the wafer has completed most or all of the CMOS manufacturing process.

[0016] Although Figure 3The RDL 306 and CAS gate 306a shown can control parasitic back-channel effects, but in the region near the transistor active region (which is within the dashed ellipse 302), the RDL 306 is spaced from the transistor active region by a relatively thick insulating layer 204 (typically an insulating dielectric material such as SiO2), and in some cases, the RDL 306 is spaced from the transistor active region by a passivation layer 206. Both the relatively thick insulating layer 204 and the passivation layer 206 are poor thermal conductors. Because the transistor generates heat that must be removed, it is difficult to remove heat from SLT transistors, leading to many performance degradations, such as decreased transistor performance and reliability. Some structures and methods for mitigating this heat flow problem are taught in U.S. Patent Application Serial No. 16 / 040,295 cited above.

[0017] Figure 3 Another problem with the structure shown is that the metal interconnect layers 304 (especially the thicker M5 and M4 layers) are very close to the silicon processing wafer 202, which can cause issues related to the target Figure 1 The structure discussed in the text represents similar or larger parasitic effects.

[0018] Figure 4 This is an inverted cross-sectional view of a field-effect transistor structure 400 (within the dashed ellipse 302) attached to a printed circuit board (PCB) 402, where an internal metal interconnect layer 304 is shown. The field-effect transistor structure 400 shown includes a passivation layer 408 covering the exposed surface of the ILD layer 110. Figure 4 The diagram depicts a FET structure 400 after the flip-chip solder bumps and die are attached to a PCB 402 via terminals including solder bumps 404, which contact conductive vias 406 to at least one metal interconnect layer 304. It can be seen that the silicon substrate 104 remains adjacent to the back channel 112 of the SOI transistor, resulting in the RF parasitic effects discussed above.

[0019] Therefore, in conventional CMOS SOI ICs, the active region of the transistor is adjacent to the silicon substrate (e.g., Figure 1 and Figure 4 (as in the example), or connected to a metal interconnect layer (such as) adjacent to the silicon processing wafer. Figure 3 (as in the case of the silicon substrate / processing wafer). In either case, the silicon substrate / processing wafer is coupled to the signals carried by the transistors and their interconnecting metal layers, resulting in insertion loss, nonlinearity, reduced isolation, non-ideal voltage division of stacked transistors, and other parasitic effects discussed above.

[0020] about Figures 1 to 4The described prior art structures all include a silicon substrate / handling wafer on either the top or bottom surface. In either case, the various types of coupling to the silicon substrate / handling wafer as described above degrade performance. The primary objective of the present invention is to retain Figures 1 to 4 the various benefits of the transistor structures shown in the middle while eliminating the silicon substrate / handling wafer and its deleterious side effects. SUMMARY

[0021] The present invention includes transistor structures with low parasitic capacitance and methods for manufacturing such transistor structures, particularly RF MOSFET signal switches. The transistor structures include an insulating low dielectric constant first or second handling wafer.

[0022] In one embodiment, a single layer transfer or SLT manufacturing technique is utilized. For example, an SOI transistor is manufactured in the conventional manner on a silicon substrate (up to a point), then flipped over to a handling wafer that includes an insulating low dielectric constant (LDC) substrate, at which point the original silicon substrate is removed. The entire structure is then flipped back to its original manufacturing orientation, meaning that the BOX layer and active layer are now at the "bottom" of the stacked structure. The insulating LDC handling wafer is thus now positioned "above" the metal interconnect / metal layer stack of the original SOI transistor, in place of the silicon substrate of a conventional SLT design.

[0023] In another embodiment, a double layer transfer or DLT manufacturing technique is utilized. For example, an SOI transistor is manufactured in the conventional manner on a silicon substrate (up to a point), then flipped over to a first handling wafer, at which point the original silicon substrate is removed. The exposed top of the transistor structure is then bonded to a second handling wafer that includes an insulating LDC handling wafer, and the first handling wafer is removed. The insulating LDC substrate has thus replaced the silicon substrate of a prior art structure.

[0024] In some embodiments, the insulating LDC handling wafer is selectively etched or ground to create at least one air cavity prior to bonding to the transistor structure, further reducing the effective dielectric constant of the material surrounding the RF FET.

[0025] The use of the insulating LDC handling wafer reduces insertion loss and non-linearity, increases isolation, provides a more ideal division voltage for the stacked transistor, enables a higher Q factor due to lower coupling loss, and additionally mitigates the parasitic effects discussed above.

[0026] Variant embodiments can include additional structures for mitigating or eliminating thermal conductivity issues.

[0027] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a cross-sectional view of a prior art n-type SOI FET fabricated on a buried oxide (BOX) layer of typically silicon dioxide, Si02, formed on a silicon substrate.

[0029] Figure 2 is a cross-sectional view of a prior art SLT transistor without metal interconnect layers for clarity.

[0030] Figure 3 is a more detailed cross-sectional view of an SLT transistor with internal metal interconnect layers plus a redistribution layer (RDL) with source, drain and gate (all within the dashed oval).

[0031] Figure 4 is a cross-sectional view of a "flipped" image of one field effect transistor structure (within the dashed oval) of a prior art SOI FET IC (with internal metal interconnect layers) attached to a printed circuit board (PCB).

[0032] Figure 5 is a cross-sectional view of a first embodiment of an RF SLT SOI transistor according to the present application with source, drain and gate (all within the dashed oval) after attachment to a printed circuit board (PCB).

[0033] Figure 6A is a cross-sectional view of a second embodiment of an RF SLT SOI transistor according to the present application after attachment to a PCB.

[0034] Figure 6B is a cross-sectional view of a third embodiment of an RF SLT SOI transistor according to the present application showing two air cavities.

[0035] Figure 6C is a plan view of a rectangular cross-section of an insulating LDC handling wafer with a plurality of perforations.

[0036] Figure 6D is a cross-sectional view of a rectangular cross-section taken along line A-A of Figure 6C

[0037] Figure 7 is a cross-sectional view of a first embodiment of an RF DLT SOI transistor according to the present application after attachment to a PCB.

[0038] Figure 8A ​is a top view of an SOI IC FET structure with thermal extraction structure at an intermediate stage of fabrication.

[0039] Figure 8B is a cross-sectional view of the SOI IC FET structure of Figure 8A along line A-B of Figure 8A at a later stage of fabrication.

[0040] Figure 9 is a cross-sectional view of one embodiment of an SOI IC structure for a single FET that has been configured to conduct heat away from the FET to the "bottom" of the IC structure, as depicted by the heat flow arrows.

[0041] Figure 10A is a top view of a conventional SOI IC FET structure at an intermediate stage of fabrication.

[0042] Figure 10B is a cross-sectional view of the SOI IC FET structure of Figure 10A along line A-B of Figure 10A at a later stage of fabrication.

[0043] Figure 11A is a top view of an SOI IC FET structure with a thermally coupled dummy gate at an intermediate stage of fabrication.

[0044] Figure 11B is a cross-sectional view of the SOI IC FET structure of Figure 11A after application of a backside access process such as SLT.

[0045] Figure 12 is a process flow diagram of a first method of fabricating a low parasitic capacitance transistor.

[0046] Figure 13 is a process flow diagram of a second method of fabricating a low parasitic capacitance transistor.

[0047] The same reference numbers and designations in the various drawings refer to the same elements. DETAILED DESCRIPTION

[0048] The present invention includes transistor structures with low parasitic capacitance, particularly RF MOSFET signal switches, and methods for fabricating such transistor structures. The transistor structures include an insulating low dielectric constant first handle wafer or second handle wafer.

[0049] Relative sizes and orientations in the drawings

[0050] With respect to the drawings cited in this disclosure, note that the dimensions of the various elements are not drawn to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for the sake of clarity or emphasis. Also, references to orientation and direction (e.g., "top," "bottom," "above," "below," "lateral," "orthogonal," etc.) are with respect to the example drawings and are not necessarily absolute orientations or directions.

[0051] Single layer transfer implementation

[0052] Figure 5 is a cross-sectional view of a first implementation 500 of an RF SLT SOI transistor according to the present invention having a source, a drain, and a gate (all within the dashed oval 302) after attachment to a printed circuit board (PCB). As can be seen, the structure has eliminated the silicon substrate 104 (see Figure 4 ) of the prior art. More specifically, the SOI transistor is fabricated in the conventional manner on a silicon substrate (up to a point), then flipped over to a handle wafer 502 including an insulating low dielectric constant (LDC) substrate, at which point the original silicon substrate is removed. The entire structure is then flipped back to its original fabrication orientation, meaning that the BOX layer 102 and active layer 106 are now at the "bottom" of the stacked structure relative to Figure 5 the depiction of Figure 5 depicts the FET implementation 500 after flip chip solder bumping and die attachment to a PCB 402 through terminals including solder bumps 404 in contact with conductive vias 406. Figure 5 It is also shown that the SLT process enables formation of a CAS gate 504 proximate to the active transistor region (within the dashed oval 302) to control capacitive back channel parasitic effects, as further described in U.S. Patent Application Serial No. 15 / 920,321 (electrical connections to the CAS gate 504 are omitted for clarity).

[0053] The insulating LDC handle wafer 502 provides the mechanical support needed for the transistor structure, which is necessary because the transistor structure stack 506 is very thin (e.g., about 10 microns in a typical FET manufacturing process). The thin transistor structure stack 506 is extremely fragile and needs a support structure that is rigid and strong enough to enable subsequent process steps (e.g., die singulation, die pick and place, etc.) to be performed with acceptable yield. In this example, the thickness 508 of the insulating LDC handle wafer 502 can be about 500-700 microns. However, thicknesses 508 less than 500 microns (e.g., 100-200 microns) can be used for many mobile applications (e.g., cellular smart phones) where thinness is very important.

[0054] The insulating LDC handle wafer 502 should be chosen to exhibit both of the following independent characteristics: to be a good electrical insulator and to have a low dielectric constant. The advantage of being a good electrical insulator is higher Q-factor and linearity. For this aspect, the insulating LDC handle wafer 502 can be, for example, glass (e.g., low alkali glass or soda-lime glass), quartz or fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

[0055] The advantage of having a low dielectric constant is low insertion loss, better isolation, and better voltage division. Importantly, the insulating LDC handle wafer 502 should have a dielectric constant that is less than that of a silicon substrate. As one example, in one implementation, the chosen glass LDC handle wafer 502 has a dielectric constant ε of about 5.8, while a typical silicon substrate has a dielectric constant of about 11.7 (and can be as high as 12.9 for some types). Typical dielectric constants for the example insulating LDC handle wafer 502 materials listed above at 18 GHz are: glass (~5.8 to ~6.72, although some types of glass can be higher), quartz or fused silica (~3.8 to ~4.2), sapphire (~9.4 for perpendicular to the C-axis), aluminum nitride (~8.8 to ~10.8), silicon carbide (~9.66 to ~10.03 for static, ~6.52 to ~6.6.7 for high frequency), high-temperature co-fired ceramic (HTCC) (~10), or low-temperature co-fired ceramic (LTCC) (~5 to ~9).

[0056] A third characteristic is high thermal conductivity, which would be advantageous, but few materials that have high resistivity, low dielectric constant, and high thermal conductivity characteristics, such as aluminum nitride or silicon carbide, often have other issues such as cost, manufacturability, or relatively high dielectric constant that can limit their use in some applications.

[0057] The use of an insulating LDC handle wafer 502 with good electrical isolation and a dielectric constant less than that of silicon replaces the conventional silicon substrate, reducing or eliminating nonlinear effects that can be caused by voltages on the transistor structure stack 506 and coupled back into the silicon of the active transistor region, distorting the signals applied to the transistor. Thus, the use of an insulating LDC handle wafer 502 reduces insertion loss and nonlinearity, increases isolation, provides a more ideal division of voltage for stacked transistors, enables a higher Q factor due to lower coupling loss, and additionally mitigates the parasitic effects discussed above.

[0058] Figure 5 The transistor structure shown in FIG. 6 can also include: a thermal extraction structure as taught in U.S. Patent Application Serial No. 16 / 040,295 (see more detailed discussion below regarding FIGS. 8-11); and / or an RDL back gate structure on the (now) bottom surface of the IC as taught in U.S. Patent Application Serial No. 15 / 920,321 (one example is shown as CAS gate 504); and those structures typically formed prior to the addition of solder bumps to attach to a PCB.

[0059] Figure 6A is a cross-sectional view of a second embodiment 600 of an RF SLT SOI transistor according to the present application after attachment to a PCB. In this embodiment, the insulating LDC handle wafer 502 (e.g., glass) has been selectively etched or ground to create at least one air cavity 602 prior to bonding to the transistor structure. As one example, a glass insulating LDC handle wafer would be etched in the region proximate to the metal interconnect layers of the FET to create at least one air cavity. Since the dielectric constant of air is approximately 1.0, the one or more air cavities further reduce parasitic capacitive coupling. Thus, the use of an insulating LDC handle wafer 502 etched to create at least one air cavity proximate to the metal interconnect layers of the RF FET further reduces the effective dielectric constant of the material surrounding the RF FET. Such an embodiment can be highly advantageous when using a material such as aluminum nitride or silicon carbide for the LDC handle wafer 502 to obtain high thermal conductivity while mitigating the relatively high dielectric constant of such materials. Thus, capacitive coupling between nearby transistors will be reduced, increasing isolation between them. Capacitive coupling between the source side and the drain side of each transistor will also be reduced, decreasing the off-capacitance (C OFF ) of the transistor, improving the switching quality factor (equal to the on-resistance R ON times C OFF ) of the transistor. In one embodiment of the air cavity configuration shown in FIG. 6, C Figure 6A is less than that of a similar embodiment with the non-cavity configuration shown in FIG. 5. Figure 5 ​OFF about 30%.

[0060] Figure 6A An insulating LDC handle wafer 502 is shown with a single air cavity 602 proximate a single transistor structure. In alternative embodiments, the single air cavity 602 can span multiple transistor structures, including up to all transistor structures on a single integrated circuit die. More than one air cavity 602 can also be used. For example, Figure 6B is a cross-sectional view showing a third embodiment 650 of an RF SLT SOI transistor according to the present invention with two air cavities 602. Each of the air cavities 602 is located above a corresponding portion of the metal interconnect layer 304 underneath. The average dielectric constant of the insulating LDC handle wafer 502 with dual air cavities will still be lower than a solid insulating LDC handle wafer 502, but will be structurally stronger and more resistant to flexing than a single air cavity.

[0061] It should be noted that in Figure 6A and Figure 6B , the metal interconnect layer 304 will typically extend laterally (all across the page and in and out of the page), and the one or more air cavities 602 will typically extend above these laterally extending metal interconnect layers 304 to provide the benefit of reduced capacitive coupling. It should also be noted that the one or more air cavities 602 are not drawn to scale relative to the vertical dimension of the overall insulating LDC handle wafer 502. The one or more air cavities 602 should typically be reasonably deep to reduce the dielectric constant of the insulating LDC handle wafer 502, as seen by the nearby transistor structure. For example, if the thickness 508 of the insulating LDC handle wafer 502 is about 500 to 700 microns, the thickness 604 (see Figure 6A ) of the one or more air cavities 602 can be about 100 to 200 microns.

[0062] Figure 6C is a plan view of a rectangular cross-section of an insulating LDC handle wafer 502 with multiple perforations 610. Figure 6D is a cross-sectional view of a rectangular cross-section taken along line A-A of Figure 6C . In both views, the illustrated portion of the insulating LDC handle wafer 502 includes multiple air cavities in the form of perforations 610 that are preferably spaced apart so as to be proximate each underlying transistor structure, for example Figure 6BThe example transistor structure provides at least one air cavity / via. The via 610 can be formed, for example, by masking and etching the solid-state insulating LDC processing wafer 502. The average dielectric constant of the via-insulated LDC processing wafer 502 will be lower than that of the solid-state insulating LDC processing wafer 502, but it will be structurally more robust and more flexurally resistant than a single air cavity. In some embodiments, the via 610 can be replaced by forming a “dead-angle” air cavity (i.e., an opening only adjacent to one side of the transistor structure stack 506), which is formed, for example, by etching one side of the insulating LDC processing wafer 502 to the desired depth.

[0063] and Figure 5 The transistor structure shown is the same. Figure 6A and Figure 6B The transistor structure shown may also include: an additional heat extraction structure as taught in U.S. Patent Application Serial No. 16 / 040,295. Figures 6A to 6B (not shown in Figures 8 through 11); and / or an RDL back gate structure on the (now) bottom surface of the IC as taught in U.S. Patent Application Serial No. 15 / 920,321 (an example is shown as CAS gate 504).

[0064] In summary, in one aspect, embodiments of the present invention include a semiconductor structure comprising a stack of formed layers, the stack of formed layers comprising, in a relative order (meaning it may include other unlisted layers): an insulating low-dielectric-constant substrate; at least one metal interconnect layer embedded in an insulating dielectric material; a silicon active layer including at least one field-effect transistor; a buried oxide layer; and an insulating dielectric material layer. In a preferred embodiment, the insulating low-dielectric-constant substrate includes at least one air cavity formed adjacent to the at least one metal interconnect layer.

[0065] Two-layer transfer implementation method

[0066] Figure 5 , Figure 6A and Figure 6B All implementations utilize single-layer transfer or SLT manufacturing techniques. Alternative implementations utilize double-layer transfer or DLT manufacturing techniques. For example, Figure 7is a cross-sectional view of a first embodiment of an RF DLT SOI transistor 700 according to the present invention after attachment to a PCB. In one process, the SOI transistor is fabricated in a conventional manner on a silicon substrate (up to a point), then flipped over to a first handle wafer (e.g., silicon not shown), at which point the original silicon substrate is removed in a known manner, and a protective layer of ILD 702 is deposited on the BOX layer 102. The exposed top of the transistor structure (in this example, the protective layer of ILD 702) is then bonded to a second handle wafer comprising the insulating LDC handle wafer 502, and the first handle wafer is removed. Thereafter, additional steps can be performed, such as flip chip solder bumps (to the metal interconnect layer 304 of the transistor structure) and die attachment to a PCB 402.

[0067] Thus, the insulating LDC substrate has replaced the silicon substrate of prior art structures using a dual layer transfer process. As with the previous embodiments, the silicon substrate has been completely removed from the structure and the only semiconductor material is the silicon active layer 106, and the FET gate and / or non-metallic connection structures (typically polysilicon). While the resulting structure has similarities to a conventional SOI transistor structure of Figure 4 Figure 4 the SOI transistor structure of Figure 7 the embodiments eliminates the parasitic effects caused by traditional SOI transistors that always require a silicon substrate.

[0068] As with the embodiments of Figure 5 , Figure 6A and Figure 6B the embodiments of Figure 7 the embodiments can utilize an insulating LDC handle wafer 502 with a single air cavity or multiple air cavities, and one or more air cavities can be formed as perforations through the insulating LDC handle wafer 502. Figure 7 An advantage of is that, while involving a dual layer transfer process in order to provide an insulating LDC handle wafer 502 to replace a high dielectric constant silicon substrate 104, the process is compatible with conventional SOI fabrication steps such as die singulation, die pick and place, and solder bumping and die attachment to a PCB 402.

[0069] It should be noted that the illustrated Figure 7 is a result of the dual layer transfer process. In some embodiments, it can be desirable to include a CAS gate for the field effect transistor structure (within the dashed oval 302), as in the embodiments of Figure 6B For example, this can be accomplished by forming a redistribution layer 306 after the first SLT transfer and then forming the CAS gate (not shown) on the redistribution layer 306. Figure 7 ​Not shown in the image, but see [link / reference]. Figure 6B This is accomplished using the CAS gate 504. An ILD layer can then be formed over the CAS gate 504 and RDL 306, followed by planarization and polishing if necessary. Afterward, a second wafer transfer is performed, leaving the CAS gate 504 and RDL 306 between the active layer 106 and the insulating LDC processing wafer 502.

[0070] In summary, in one aspect, embodiments of the present invention include a semiconductor structure comprising a stack of formed layers, the stack of formed layers comprising, in a relative order (meaning it may include other unlisted layers): an insulating low-dielectric-constant substrate; an insulating dielectric material layer; a buried oxide layer; a silicon active layer including at least one field-effect transistor; at least one metal interconnect layer embedded in the insulating dielectric material; and a passivation layer.

[0071] Thermal Extraction Structure

[0072] Compared to the original silicon substrate, the insulating LDC processing wafer 502 (with or without an air cavity) located near the active region of the transistor structure increases thermal resistance; therefore, the addition of a heat extraction structure can provide the highest overall performance for such RF. For example, Figure 5 , Figure 6A , Figure 6B and Figure 7 One or more of the transistor structures shown may include heat extraction structures as taught in U.S. Patent Application Serial No. 16 / 040,295. More specifically, during the fabrication of the FET, one or more electrically isolated laterally extending thermal paths may be formed adjacent to the FET, and said one or more electrically isolated laterally extending thermal paths are configured to conduct heat laterally (e.g., "horizontally") away from the FET to generally orthogonal (e.g., "vertical") thermal paths (e.g., vias or heat pipes), and thus to corresponding thermal pads that are externally accessible at the "top" or "bottom" of the complete integrated circuit (IC). Such heat extraction configurations are particularly useful for ICs mounted in "flip-chip" packages.

[0073] As an example, Figure 8A This is a top view of the SOI IC FET structure 820 with a thermal extraction structure during the intermediate stage of manufacturing. Figure 8B yes Figure 8A along Figure 8AA cross-sectional view of the SOI IC FET structure 820 at a later stage of fabrication, taken along the dashed line A-B. In this example, a silicon island 822 has been formed within the field oxide region 824. A silicide layer can be formed on the exposed surface of the silicon island 822 in a conventional manner. Within the silicon island 822, the FET device 802 has been formed. In addition, the silicon island 822 is patterned to create an electrically isolated structure 828 to electrically isolate the portion of the silicon island 822 containing the FET device 802 from the edge portions 822a, 822b of the silicon island 822. Such an electrically isolated structure 828 can be fabricated. Such an electrically isolated structure 828 can be fabricated, for example, using shallow trench isolation (STI), a known technique commonly used to prevent current leakage between nearby semiconductor device components. An STI process includes etching a pattern of trenches in the silicon island 822, depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches, and removing excess dielectric using a technique such as chemical mechanical planarization. However, other techniques such as local oxidation of silicon regions between transistors (also known as LOCOS isolation) can be used to form the electrically isolated structure 828.

[0074] During formation of a first metallization layer (commonly referred to as "metal 1" or "Ml") for the IC FET structure 820, various terminals of the FET device 802 (e.g., source, drain, gate) are electrically connected 826. In addition, in the illustrated example, the Ml layer, which is also thermally conductive and is patterned over a first interlayer dielectric layer (ILD), is patterned to form one or more electrically isolated laterally-extending thermal paths 804, each thermal path including: (1) a near portion 804a that is in thermal contact with the edge portions 822a, 822b of the FET device 802 through the ILD; and (2) a far portion 804b that is spaced apart from the edge portions 822a, 822b of the FET device 802 along a lateral direction (e.g., "horizontally") adjacent to the FET device 802. Figure 8B Figure 8B

[0075] In the illustrated example, the generally orthogonal thermal via 840 is thermally coupled to an externally-accessible thermal pad 806 that can be coupled to a conventional heat sink. While the thermal pad 806 is shown as being formed on the same layer as the FET device 802, it is contemplated that the thermal pad 806 can be formed on a different layer than the FET device 802.​​Figure 8B The SLT-type SOIFET and the generally orthogonal thermal via 840 projecting upwardly relative to the FET device 802 is shown, but in other embodiments the generally orthogonal thermal via 840 can project downwardly to a different externally accessible thermal pad (see Figure 9 and accompanying description).

[0076] It should be clear that the heat generated by the FET device 802 (especially at its drain D) will flow laterally through the active area of the FET device 802, thus through the electrical isolation structure 828, and finally through the edge portions 822a, 822b. After this lateral heat diffusion, the heat generated by the transistor will diffuse vertically through the ILD layer located between the edge regions 822a, 822b and the Ml layer, and thus into the near and far portions 804a, 804b, respectively, of the electrically isolated laterally extending thermal path 804 that is patterned from the Ml layer. Since the Ml layer is an excellent thermal conductor, the near portion 804a will conduct heat to the far portion 804b of the electrically isolated laterally extending thermal path 804, and ultimately onto an external heat sink (e.g. the thermal pad 806 in Figure 8B ). The properly configured near and far portions 804a, 804b of the electrically isolated laterally extending thermal path 804 will enable a much lower thermal resistance from the FET device 802 through the generally orthogonal thermal via 840 to the externally accessible thermal pad 806.

[0077] Thus, the purpose of the electrically isolated laterally extending thermal path 804 is to conduct heat away from the FET device 802 in a lateral direction when the fabrication of the IC FET structure 820 is completed. Note that while Figure 8A The electrically isolated laterally extending thermal path 804 is shown disposed on both sides of the FET device 802, but in some embodiments one electrically isolated laterally extending thermal path 804 can be sufficient (especially on the drain D side of the FET device 802); such a configuration can also require less area on the IC. It should also be noted that the material on which the Ml metallization layer is formed (e.g. silicide) can be etched and backfilled with a conductive material to form a via, such that the Ml layer is in more direct thermal contact with the edge portions 822a, 822b of the silicon island 822.

[0078] In Figure 8B , additional steps of fabrication using the SLT process are shown. In particular, as described above, Figure 8AIC FET structure 820 has been "flipped" over the top of the handle wafer. Thus, FET devices 802 now face "downward," away from the "new top" of the overall structure. Near portions 804a of electrically isolated laterally extending thermal paths 804 are positioned adjacent to respective edge regions 822a, 822b and access FET devices 802 (ideally, as much as possible under a set of applicable IC design rules). Far portions 804b of electrically isolated laterally extending thermal paths 804 laterally extend from FET devices 802 far enough that generally orthogonal (e.g., "vertical") thermal vias (e.g., vias or heat pipes) 840 (e.g., copper or aluminum) can be fabricated through the passivation and BOX layers to make intimate thermal contact with far portions 804b of electrically isolated laterally extending thermal paths 804. In the illustrated example, generally orthogonal thermal vias 840 can be formed, for example, by etching holes through the passivation and BOX layers using known techniques and filling these holes with thermally conductive material. Note that some manufacturing design rules for a particular IC foundry can not allow the use of a single large diameter orthogonal thermal via 840, and thus, a plurality of smaller diameter thermal vias 840 (e.g., a plurality of vias) can be substituted Figure 8B for the illustrated single thermal via 840.

[0079] Each generally orthogonal thermal via 840 can be covered by a thermal pad 806 fabricated from thermally conductive material. If thermal via 840 is fabricated from copper, the material used for thermal pad 806 will typically be aluminum to avoid oxidation of the copper. Thermal pad 806 can be shaped as part of an RDL process for forming a CAS gate for FET devices 802 as in Figure 5 , Figure 6A and Figure 6B . Of course, other thermally conductive materials compatible with IC fabrication processes can be used for both generally orthogonal thermal via 840 and thermal pad 806.

[0080] It is worth noting that the use of STI trenches for electrically isolated structure 828 is particularly beneficial because STI trenches can be made very narrow (e.g., about 200 nm or 2000 Angstroms) and they extend along the entire width of the active transistor region (i.e., silicon island 822). Thus, the thermal resistance from FET devices 802 to electrically isolated laterally extending thermal paths 804 through the STI trenches is much less than the thermal resistance through the top or bottom of a complete SOI IC structure 800.

[0081] While it is very convenient from a manufacturing perspective to use the Ml metallization layer to form the electrically isolated laterally extending thermal path 804, other metallization layers (including custom layers) or combinations of metallization layers can also be used. For example, one or more generally orthogonal thermal vias can be formed in thermal contact with the electrically isolated edge portions 822a, 822b of the silicon island 822 to thermally couple to the edge portions 822a, 822b. Such orthogonal thermal vias can then be thermally coupled to a lateral thermal path formed from one or more metallization layers other than Ml. Other generally orthogonal thermal vias 840 and corresponding thermal pads 806 can then be thermally coupled to the lateral thermal path, similar to Figure 8B the configuration of

[0082] It will be appreciated that in the context of the present disclosure, "electrically isolated" means substantially isolated from direct current. As will be appreciated by those skilled in the art, AC coupling through a capacitor-like structure is inherent in the conductor / insulator / conductor structure as described above. Such AC coupling can be managed and mitigated through known design techniques.

[0083] Figure 9 is a cross-sectional view of one embodiment of an SOI IC structure 900 for a single FET structure (within the dashed oval 302) that has been configured to conduct heat away from the FET device 302 to the "bottom" of the IC structure 900, as depicted by the thermal flow arrows 902. The IC structure 900 is formed in substantially the same manner as the IC structures of Figure 7 and Figure 8A Thus, as in Figure 8A the thermally conductive Ml layer is patterned to form one or more electrically isolated laterally extending thermal paths having a near portion 804a in thermal contact with the FET device 302 and a far portion 804b spaced apart from the FET device 302 in a lateral direction in the manner described above. As with the embodiment of Figure 7 as described above, the CAS gate 504 can be formed relative to the FET device 302 prior to adding the insulating LDC handle wafer 502.

[0084] The metal interconnect layers 304 can be patterned and interconnected in known manners to provide lateral thermal vias and vertical thermal vias (e.g., "vertical" relative to the plane of the FET device 302 in Figure 9 In particular, vertical structures in the metal interconnect layers (e.g., vias) can be formed to provide thermal paths from the metal interconnect layer (i.e., Ml in this example, and thus including Figure 8A and Figure 8BThe electrically isolated, laterally extending thermal path 804 leads to the final metal interconnect layer (M5 in this example), forming an overall orthogonal electrically isolated thermal path, known as a "thermal via". Patterning and interconnecting the metal interconnect layers to create such thermal vias is part of the standard manufacturing process; that is, no additional manufacturing steps are required, only reconfiguration of the existing mask. In the example shown, the M5 metal interconnect layer is thermally coupled to the PCB 402 via conductive vias 406 and solder bumps 404.

[0085] Figure 9 The advantage of the configuration shown is that since the metal interconnect layer 304 for the thermal vias (i.e., generally orthogonal electrically isolated thermal paths) is formed as part of the normal manufacturing process for the IC structure, virtually no additional manufacturing steps are required.

[0086] Figures 8A to 8B as well as Figure 9 The illustrated embodiment utilizes an electrically isolated structure 828 (e.g., an STI trench) to electrically isolate the portion of the silicon island 822 containing the FET device 802 from the edge portions 822a, 822b of the silicon island 822, and then uses a metallization layer (typically an M1 layer) for a laterally extending thermal path 804 from the edge portions 822a, 822b of the FET devices 802, 302. However, these STI-like structures are very large when compared to the thickness of a typical MOS gate oxide (GOX), which may be less than 30 angstroms thick. Therefore, in some embodiments, the electrically isolated laterally extending thermal path 804 may alternatively utilize and include one or more dummy gates, each dummy gate comprising a polysilicon gate-like structure formed on a GOX above the extending active region (typically in the direction of gate length L), and each dummy gate is specifically configured to conduct heat in the following order: laterally away from the FET along the extending active region; vertically through the thin (i.e., low thermal resistance) GOX; laterally along the dummy gate; perpendicular to the region of the M1 layer in contact with the dummy gate; and finally to an generally orthogonal thermal path (e.g., a vertical heat pipe and / or interconnect metallization structure) to an external heat sink (e.g., Figure 8B The externally accessible thermal pad 806 avoids the need to utilize a higher thermal resistance STI-shaped structure.

[0087] Figure 10A This is a top view of a conventional SOI IC FET structure 1000 during an intermediate stage of manufacturing. Figure 10B yes Figure 10A along Figure 10AThe image shows a cross-sectional view of the SOI IC FET structure 1000 taken at a later stage of manufacturing, using line AB. In the example shown, the silicon island 1002 includes a FET comprising: a source region with associated contacts 1004a located beneath a metallization layer 1004; and a drain region with associated contacts 1006a located beneath a metallization layer 1006. The source and drain regions are separated by a body B located beneath and defined by a gate 1008. The gate 1008 is typically fabricated from polysilicon overlying a gate oxide layer 1012 grown on the silicon island 1002. In some processes, a dummy gate 1010 ( Figure 10B The X element (in the diagram) can be formed when forming the gate 1008 and can be used for various purposes (e.g., electrical isolation, to meet specific design rule density constraints, etc.). Like the gate 1008, the dummy gates 1010 are typically made of polysilicon overlaid with gate oxide 1012 on the silicon island 1002, typically have an upper silicide layer, and extend beyond the edge of the silicon island 1002. However, unlike the gate 1008, the dummy gates 1010 have no electrical connections, and they do not always have doped (e.g., N+) regions or silicide regions implanted into the active region to space adjacent dummy gates 1010. Figure 10B (N+ regions and silicide regions are not shown in the image).

[0088] As mentioned above, the main obstacle to heat flow within an IC FET is the numerous layers of ILD (e.g., SiO2) or other insulating layers. As already noted, the STI separation region described above can be very narrow, typically around 2000 angstroms, according to lateral dimension standards. However, one of the thinnest insulators in the FET, and therefore the lowest thermally resistive path (of the insulating layers in an IC FET), passes through the gate oxide 1012, which is typically tens of angstroms thick. Furthermore, the gate material, typically polysilicon, is a relatively good thermal conductor. These properties can be adapted to provide lateral thermal paths to conduct heat away from the FET.

[0089] As an example, Figure 11A This is a top view of an SOI IC FET structure 1100 in the intermediate stage of manufacturing, including a thermally coupled dummy gate 1010. Figure 11B After the application of back-side access technologies such as SLT Figure 11A A cross-sectional view of the SOI IC FET structure 1100. More specifically, Figure 11B It is along Figure 11A A cross-sectional view taken from both line CD (used for foreground features) and line AB (used for background features). Figure 11A The transistor structure (i.e., from through) Figure 11A The section cut by line AB is shown in dashed outline.Figure 11B The ellipse 1101 is provided for reference. Figure 11B Other components come from passing through Figure 11A The cross-section of line CD (line CD does not cut through the transistor). Additionally, although the gate oxide 1012 layer appears to cover the source (S) and drain (D) of the transistor, it does not actually cover the source (S) and drain (D). Instead, it is replaced by... Figure 10B The transistors are connected in a configuration similar to that in the example.

[0090] exist Figure 11A and Figure 11B In the example shown, one or more dummy gates 1010 are formed to extend beyond the edge of the silicon island 1002. One or more dummy gates 1010 are connected via one or more thermally conductive structures 1102 that can extend to a thermal pad 1104. The thermally conductive structure 1102 may be, for example, part of the M1 layer connected to the dummy gates 1010 via a thermal via 1106, such as... Figure 11B As shown. The heat generated by the FET is conducted from the "near" (relative to the FET) dummy gate 1010 through the via 1106 to the thermally conductive structure 1102 of the M1 layer, and thus laterally to the "far" thermal pad 1104. Figure 11A ).

[0091] like Figure 8B In the configuration, each thermal pad 1104 can be thermally coupled to an generally orthogonal thermal path, and thus thermally coupled to a thermal pad 806 on the BOX side of the structure. Each thermal pad 1104 can also be thermally coupled to a patterned metal interconnect layer 1108 (e.g., M1 to M5) of the upper structure of the device and thermally coupled to a thermal via 1112.

[0092] Therefore, heat flows from the FET to the thermal pad 1104 across the entire region of the silicon island 1002 covered by the dummy gate 1010, thus penetrating the extremely thin gate oxide material beneath the dummy gate 1010. Compared to embodiments utilizing electrically isolated STI trenches, the illustrated "trenchless" configuration significantly reduces thermal resistance (reducing the ratio of the STI trench's planar width to the gate oxide's thickness) due to the elimination of the STI trench's series thermal resistance. Another advantage of this embodiment is that the thermally conductive polysilicon dummy gate 1010 is typically thicker than the underlying silicon island 1002, further reducing lateral thermal resistance.

[0093] Although Figure 11ATwo heat-conducting structures 1102 and associated heat-spreading pads 1104 are shown coupled to a pair of dummy gates 1010 on the left side of the illustrated silicon island 1002, but in some implementations, one heat-conducting structure 1102 and associated heat-spreading pad 1104 can be sufficient (especially on the drain D side of the FET); such a configuration can also require less area on the IC. Since the dummy gates 1010 extend beyond both the left and right sides of the illustrated silicon island 1002, the heat-conducting structures 1102 and associated heat-spreading pads 1104 can be formed on both the left (as illustrated) and right (not shown) sides of the silicon island 1002. Moreover, while the illustrated heat-conducting structures 1102 and associated heat-spreading pads 1104 are shown coupled to a pair of dummy gates 1010, in general, the heat-conducting structures 1102 and associated heat-spreading pads 1104 can be coupled to one or more dummy gates 1010. In some implementations, the illustrated set of dummy gates (i.e., two or more dummy gates per drain and / or source side of the FET) can be replaced with a single wide dummy gate (in effect, the dummy gate will thermally short the active area).

[0094] In some implementations, the connection of the heat-conducting structures 1102 to the dummy gates 1010 can be made at locations other than the ends (i.e., through the thermal via to the electrically isolated heat-conducting structure 1102 along the dashed line AB), and more than one heat-conducting structure 1102 on each "side" of the gate 1008 can be used. One or more dummy gates 1010 can be interconnected with one or more other dummy gates 1010 by, for example, using a polysilicon "band" (e.g., band 1010a in Figure 11A ) spanning two or more dummy gates 1010, and thus increasing the number of thermal pathways. One or more bands 1010a can be formed at the ends of the dummy gates 1010 or across intermediate portions of the dummy gates 1010. Such a configuration can better collect heat for conduction through the heat-conducting structures 1102.

[0095] In a variation of the implementation of Figure 11A , an extension of the Ml layer of the heat-conducting structure 1102 can be deposited over substantially the entire length of one or more dummy gates 1010, and the extension of the Ml layer of the heat-conducting structure 1102 is thermally coupled to these dummy gates 1010 by a thermal via similar to the via 11010 shown in Figure 11B . For example, in Figure 11A , one such extension 1110 of the Ml layer is shown over the uppermost dummy gate 1010; such a structure is commonly referred to as a "band gate," meaning a metal contact over polysilicon on the active area. The Ml layer provides better thermal conductivity than the polysilicon of the dummy gate 1010, and thus, such a configuration enables better control of heat.

[0096] Additional details of the structure for mitigating heat flow and methods of manufacturing the same can be found in the above-referenced U.S. Patent Application Serial No. 16 / 040,295.

[0097] Method

[0098] Another aspect of the present disclosure includes a method for manufacturing a transistor structure having low parasitic capacitance, particularly an RF MOSFET signal switch. For example, Figure 12 is a process flow diagram 1200 of a first method of manufacturing a low parasitic capacitance transistor. The method includes: fabricating at least one electronic circuit element (e.g., a field effect transistor) in a silicon active layer on a buried oxide layer on a silicon substrate and / or on a silicon active layer on a buried oxide layer on a silicon substrate (block 1202); fabricating a connection layer including one or more metal interconnect layers embedded in an insulating dielectric material on the silicon active layer (block 1204); attaching the connection layer to a handle wafer including an insulating low dielectric constant substrate (block 1206); removing the silicon substrate from the buried oxide layer (block 1208); and fabricating a layer of insulating dielectric material on the buried oxide layer (block 1210).

[0099] As another example, Figure 13 is a process flow diagram 1300 of a second method of manufacturing a low parasitic capacitance transistor. The method includes: fabricating at least one electronic circuit element (e.g., a field effect transistor) in a silicon active layer on a buried oxide layer on a silicon substrate and / or on a silicon active layer on a buried oxide layer on a silicon substrate (block 1302); fabricating a connection layer including one or more metal interconnect layers embedded in an insulating dielectric material on the silicon active layer (block 1304); fabricating a passivation layer on the connection layer (block 1306); attaching the passivation layer to a first handle wafer (block 1308); removing the silicon substrate from the buried oxide layer (block 1310); fabricating a layer of insulating dielectric material on the buried oxide layer (block 1312); attaching the layer of insulating dielectric material to a second handle wafer including an insulating low dielectric constant substrate (block 1314); and removing the first handle wafer (block 1316).

[0100] Optionally, the above method can include one or more of: fabricating at least one air cavity in the insulating low dielectric constant substrate proximate the one or more metal interconnect layers; wherein the insulating low dielectric constant substrate is one of: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high temperature co-fired ceramic (HTCC), or low temperature co-fired ceramic (LTCC); wherein the dielectric constant of the insulating low dielectric constant substrate is less than the dielectric constant of silicon; wherein the dielectric constant of the insulating low dielectric constant substrate is no greater than about 10.8; wherein the dielectric constant of the insulating low dielectric constant substrate is less than about 7.

[0101] For example methods of any of Figure 12 and Figure 13 Any of the example methods shown can include other process steps (many of which are known in the art), such as the fabrication of passivation layers and / or regions, isolation structures, external connections, special doping and structural configurations for FETs, etc. Optionally, the insulating low-k substrate can include one or more air cavities proximate to one or more metal interconnect layers or active transistor regions. The thermal extraction structures and configurations of the present disclosure can be included, as well as those taught in U.S. Patent Application Serial No. 16 / 040,295. Additionally, the CAS gate structures and configurations of the present disclosure can be included, as well as those taught in U.S. Patent Application Serial No. 15 / 920,321.

[0102] Manufacturing techniques and choices

[0103] As will be appreciated by one of ordinary skill in the art, other and / or different materials and process steps (e.g., adding layers and / or structures) can be included or substituted for those described above.

[0104] As used in this specification, the term “proximate” means “accessed” or “very near”; thus, “proximate” includes “abutting” and “adjacent,” but does not exclude intermediate structures or layers that can space a first structure or element from a second structure or element to some extent.

[0105] As used in this disclosure, the term “MOSFET” means any field effect transistor (FET) having an insulating gate and including a metal or metal-like, an insulator, and a semiconductor structure. The term “metal” or “metal-like” includes at least one electrically conductive material (e.g., aluminum, copper, or other metal, or heavily doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (e.g., silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductive material.

[0106] As used in this specification, the term “radio frequency” (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be frequencies of electromagnetic waves or alternating current in a circuit.

[0107] It should be apparent to those of ordinary skill in the art that various implementations of the present application can be realized to satisfy various specifications. Unless otherwise specified above, selection of appropriate component values is a design choice and various implementations of the present application can be realized in any appropriate integrated circuit (IC) technology, including but not limited to MOSFET structures, or in hybrid or discrete circuit form. Integrated circuit implementations can be fabricated using any appropriate substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise specified above, the present application can be implemented in other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful for SOI-based fabrication processes, including SOS, as well as fabrication processes with similar characteristics. CMOS fabrication based on SOI or SOS processes makes possible circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and beyond 50 GHz). Monolithic IC implementations are particularly useful because, with careful design, parasitic capacitances can generally be kept low (or kept minimal, uniform across all cells so that they can be compensated for).

[0108] Voltage levels can be adjusted, and / or voltage and / or logic signal polarities can be inverted, depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage handling capability, current handling capability, and power handling capability can be adjusted as needed, for example, by adjusting device sizes, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or by using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality, without significantly altering the functionality of the disclosed circuits.

[0109] CONCLUSION

[0110] A number of implementations of the application have been described. It is to be understood that various modifications can be made without departing from the spirit and scope of the application. For example, some of the steps described above can be order-independent, and thus can be performed in an order different from that described. Also, some of the steps described above can be optional. Various actions described with respect to the methods described above can be performed in a repetitive, serial, or parallel manner.

[0111] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the application, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the use of parentheses in the claims is used only to ease reading and is not intended to limit the specific order or enumeration of elements; moreover, such notations can be reused in dependent claims as references to additional elements without necessarily being construed as beginning a conflicting series of markers).

Claims

1. A semiconductor structure, comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer adjacent to at least one patterned metal interconnect layer in the set; as well as (7) An insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate being adjacent to the third insulating layer and spaced apart from the silicon active layer by the second insulating layer and the set of at least one patterned metal interconnect layers, the insulating low-dielectric-constant substrate including at least one air cavity positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure comprising: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

2. The semiconductor structure according to claim 1 further includes a redistribution layer adjacent to the first insulating layer.

3. The semiconductor structure of claim 1 further includes a conductive alignment supplementary CAS gate, the CAS gate being close to the first insulating layer, such that at least a portion of the CAS gate and the first insulating layer located between the CAS gate and the MOSFET is positioned relative to the source, drain, and body of the MOSFET to control capacitive back channel parasitic effects in the region close to the MOSFET.

4. The semiconductor structure according to claim 1, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

5. The semiconductor structure according to claim 1, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

6. The semiconductor structure according to claim 1, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

7. The semiconductor structure according to claim 1, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

8. The semiconductor structure according to claim 1, wherein, The at least one air cavity is formed close to the at least one set of patterned metal interconnect layers.

9. A semiconductor structure, comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer adjacent to at least one patterned metal interconnect layer in the set; as well as (7) An insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate being adjacent to the third insulating layer and spaced apart from the silicon active layer by the second insulating layer and the set of at least one patterned metal interconnect layers, the insulating low-dielectric-constant substrate including at least one air cavity positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

10. The semiconductor structure of claim 9, further comprising a redistribution layer adjacent to the first insulating layer.

11. The semiconductor structure according to claim 9, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

12. The semiconductor structure according to claim 9, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

13. The semiconductor structure according to claim 9, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

14. The semiconductor structure according to claim 9, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

15. The semiconductor structure according to claim 9, wherein, The at least one air cavity is formed close to the at least one set of patterned metal interconnect layers.

16. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer near the first insulating layer; as well as (7) An insulating low-dielectric-constant substrate adjacent to the third insulating layer, the insulating low-dielectric-constant substrate including at least one air cavity extending laterally above the source and drain of the transistor device, the at least one air cavity being positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure comprising: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the MOSFET along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

17. The semiconductor structure of claim 16, further comprising a redistribution layer adjacent to the first insulating layer.

18. The semiconductor structure of claim 16, further comprising a conductive alignment supplementary CAS gate, the CAS gate being close to the first insulating layer such that at least a portion of the CAS gate and the first insulating layer between the CAS gate and the MOSFET is positioned relative to the source, drain, and body of the MOSFET to control capacitive back channel parasitic effects in the region close to the MOSFET.

19. The semiconductor structure according to claim 16, wherein, The at least one air cavity is formed in the insulating low-dielectric-constant substrate near the transistor device.

20. The semiconductor structure according to claim 16, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

21. The semiconductor structure according to claim 16, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

22. The semiconductor structure according to claim 16, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

23. The semiconductor structure according to claim 16, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

24. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer near the first insulating layer; as well as (7) An insulating low-dielectric-constant substrate adjacent to the third insulating layer, the insulating low-dielectric-constant substrate including at least one air cavity extending laterally above the source and drain of the transistor device, the at least one air cavity being positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

25. The semiconductor structure of claim 24, further comprising a redistribution layer adjacent to the first insulating layer.

26. The semiconductor structure according to claim 24, wherein, The at least one air cavity is formed in the insulating low-dielectric-constant substrate near the transistor device.

27. The semiconductor structure according to claim 24, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

28. The semiconductor structure according to claim 24, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

29. The semiconductor structure according to claim 24, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

30. The semiconductor structure according to claim 24, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

31. A semiconductor structure comprising a stack of formed layers, the stack of formed layers comprising, in a relative order, the following: (1) An insulating low-dielectric-constant substrate including at least one air cavity; (2) At least one metal interconnect layer embedded in an insulating dielectric material; (3) A silicon active layer comprising at least one field-effect transistor, each field-effect transistor comprising a source and a drain; (4) Embed the oxide layer; as well as (5) Insulating dielectric material layer, in, The at least one air cavity is spaced apart from the silicon active layer by the at least one metal interconnect layer and is positioned relative to at least one of the at least one field-effect transistors to reduce capacitive coupling between the source and drain of the at least one of the at least one field-effect transistors. Wherein, the at least one field-effect transistor includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure including: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

32. A semiconductor structure comprising a stack of formed layers, the stack of formed layers comprising, in a relative order, the following: (1) An insulating low-dielectric-constant substrate including at least one air cavity; (2) At least one metal interconnect layer embedded in an insulating dielectric material; (3) A silicon active layer comprising at least one field-effect transistor, each field-effect transistor comprising a source and a drain; (4) Embed the oxide layer; as well as (5) Insulating dielectric material layer, in, The at least one air cavity is spaced apart from the silicon active layer by the at least one metal interconnect layer and is positioned relative to at least one of the at least one field-effect transistors to reduce capacitive coupling between the source and drain of the at least one of the at least one field-effect transistors. Wherein, the at least one field-effect transistor includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

33. A semiconductor structure comprising a stack of formed layers, the stack of formed layers comprising, in a relative order: (1) An insulating low-dielectric-constant substrate including at least one air cavity; (2) Insulating dielectric material layer; (3) Embedding an oxide layer; (4) A silicon active layer comprising at least one field-effect transistor, each field-effect transistor comprising a source and a drain; (5) At least one metal interconnect layer embedded in an insulating dielectric material; as well as (6) Passivation layer, The at least one air cavity extends laterally over the source and drain of at least one of the at least one field-effect transistors, and the at least one air cavity is positioned relative to the at least one of the at least one field-effect transistors to reduce capacitive coupling between the source and drain of the at least one of the at least one field-effect transistors. Wherein, the at least one field-effect transistor includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure including: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

34. A semiconductor structure comprising a stack of formed layers, the stack of formed layers comprising, in a relative order: (1) An insulating low-dielectric-constant substrate including at least one air cavity; (2) Insulating dielectric material layer; (3) Embedding an oxide layer; (4) A silicon active layer comprising at least one field-effect transistor, each field-effect transistor comprising a source and a drain; (5) At least one metal interconnect layer embedded in an insulating dielectric material; as well as (6) Passivation layer, The at least one air cavity extends laterally over the source and drain of at least one of the at least one field-effect transistors, and the at least one air cavity is positioned relative to the at least one of the at least one field-effect transistors to reduce capacitive coupling between the source and drain of the at least one of the at least one field-effect transistors. Wherein, the at least one field-effect transistor includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

35. A method for manufacturing a low parasitic capacitance transistor, comprising: (1) Fabricating at least one electronic circuit element in and / or on the silicon active layer on the buried oxide layer on the silicon substrate; (2) Fabricating a connection layer comprising one or more metal interconnect layers embedded with insulating dielectric material on the silicon active layer; (3) Attach the bonding layer to a processing wafer including an insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate including at least one air cavity; (4) Remove the silicon substrate from the buried oxide layer; as well as (5) An insulating dielectric material layer is fabricated on the embedded oxide layer. Wherein, the at least one electronic circuit element is a transistor device including a source and a drain, and the at least one air cavity is spaced apart from the transistor device by the one or more metal interconnect layers and positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. Wherein, the at least one electronic circuit element includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the method further includes fabricating at least one thermally conductive structure for the MOSFET, the method comprising: (a) At least one electrically isolated structure is fabricated within the silicon island, each electrically isolated structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrically isolated structure; (b) Fabricating an interlayer dielectric layer on top of at least one of the at least one electrically isolated structures; (c) Fabricating at least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can be coupled to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) Create at least one orthogonal thermal path thermally coupled to the second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

36. The method of claim 35, further comprising forming a redistribution layer on the insulating dielectric material layer.

37. The method of claim 35, further comprising fabricating a conductive alignment supplementary CAS gate, the CAS gate being adjacent to the insulating dielectric layer such that at least a portion of the CAS gate and the insulating dielectric layer between the CAS gate and the MOSFET is positioned relative to the source, drain, and body of the MOSFET to control capacitive back channel parasitic effects in the region adjacent to the MOSFET.

38. The method according to claim 35, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

39. The method according to claim 35, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

40. The method of claim 35, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

41. The method according to claim 35, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

42. The method according to claim 35, wherein, The at least one air cavity is formed close to the one or more metal interconnect layers.

43. A method for manufacturing a low parasitic capacitance transistor, comprising: (1) Fabricating at least one electronic circuit element in and / or on the silicon active layer on the buried oxide layer on the silicon substrate; (2) Fabricating a connection layer comprising one or more metal interconnect layers embedded with insulating dielectric material on the silicon active layer; (3) Attach the bonding layer to a processing wafer including an insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate including at least one air cavity; (4) Remove the silicon substrate from the buried oxide layer; as well as (5) An insulating dielectric material layer is fabricated on the embedded oxide layer. Wherein, the at least one electronic circuit element is a transistor device including a source and a drain, and the at least one air cavity is spaced apart from the transistor device by the one or more metal interconnect layers and positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. Wherein, the at least one electronic circuit element includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within the field oxide region of the silicon active layer, and the method further includes: (a) Fabricating an insulating gate oxide above the silicon island; (b) One or more dummy gates are formed on the insulating gate oxide above the silicon island, and the one or more dummy gates include portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) Fabricating at least one thermally conductive structure, the at least one thermally conductive structure being in thermal contact with a portion of at least one of the one or more dummy gates extending beyond at least one edge of the silicon island, and the at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of the at least one thermally conductive structure is deposited over the entire length of the one or more dummy gates and thermally coupled to the one or more dummy gates through thermal vias; and (d) Create at least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

44. The method of claim 43, further comprising forming a redistribution layer on the insulating dielectric material layer.

45. The method according to claim 43, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

46. ​​The method according to claim 43, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

47. The method according to claim 43, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

48. The method according to claim 43, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

49. The method according to claim 43, wherein, The at least one air cavity is formed close to the one or more metal interconnect layers.

50. A method for manufacturing a low parasitic capacitance transistor, comprising: (1) Fabricating at least one electronic circuit element in and / or on the silicon active layer on the buried oxide layer on the silicon substrate; (2) Fabricating a connection layer comprising one or more metal interconnect layers embedded with insulating dielectric material on the silicon active layer; (3) A passivation layer is formed on the connecting layer; (4) Attach the passivation layer to the first processing wafer; (5) Remove the silicon substrate from the buried oxide layer; (6) An insulating dielectric material layer is fabricated on the embedded oxide layer; (7) Attaching the insulating dielectric material layer to a second processing wafer including an insulating low dielectric constant substrate, the insulating low dielectric constant substrate including at least one air cavity; as well as (8) Remove the first processed chip. Wherein, the at least one electronic circuit element is a transistor device including a source and a drain, and the at least one air cavity extends laterally above the source and drain of the transistor device and is positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. Wherein, the at least one electronic circuit element includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the method further includes fabricating at least one thermally conductive structure for the MOSFET, the method comprising: (a) At least one electrically isolated structure is fabricated within the silicon island, each electrically isolated structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrically isolated structure; (b) Fabricating an interlayer dielectric layer on top of at least one of the at least one electrically isolated structures; (c) Fabricating at least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can be coupled to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) Create at least one orthogonal thermal path thermally coupled to the second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

51. The method of claim 50, further comprising forming a redistribution layer on the insulating dielectric material layer prior to attaching the insulating dielectric material layer.

52. The method of claim 50, further comprising fabricating a conductive alignment supplementary CAS gate, the CAS gate being adjacent to the insulating dielectric layer such that at least a portion of the CAS gate and the insulating dielectric layer between the CAS gate and the MOSFET is positioned relative to the source, drain, and body of the MOSFET to control capacitive back channel parasitic effects in the region adjacent to the MOSFET.

53. The method of claim 50, further comprising forming the at least one air cavity in the insulating low-dielectric-constant substrate near the at least one electronic circuit element.

54. The method according to claim 50, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

55. The method according to claim 50, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

56. The method of claim 50, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

57. The method of claim 50, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

58. A method for manufacturing a low parasitic capacitance transistor, comprising: (1) Fabricating at least one electronic circuit element in and / or on the silicon active layer on the buried oxide layer on the silicon substrate; (2) Fabricating a connection layer comprising one or more metal interconnect layers embedded with insulating dielectric material on the silicon active layer; (3) A passivation layer is formed on the connecting layer; (4) Attach the passivation layer to the first processing wafer; (5) Remove the silicon substrate from the buried oxide layer; (6) An insulating dielectric material layer is fabricated on the embedded oxide layer; (7) Attaching the insulating dielectric material layer to a second processing wafer including an insulating low dielectric constant substrate, the insulating low dielectric constant substrate including at least one air cavity; as well as (8) Remove the first processed chip. Wherein, the at least one electronic circuit element is a transistor device including a source and a drain, and the at least one air cavity extends laterally above the source and drain of the transistor device and is positioned relative to the transistor device to reduce capacitive coupling between the source and drain of the transistor device. Wherein, the at least one electronic circuit element includes a MOSFET, the MOSFET including a source, a body, a gate, and a drain, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within the field oxide region of the silicon active layer, and the method further includes: (a) Fabricating an insulating gate oxide above the silicon island; (b) One or more dummy gates are formed on the insulating gate oxide above the silicon island, and the one or more dummy gates include portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) Fabricating at least one thermally conductive structure, the at least one thermally conductive structure being in thermal contact with a portion of at least one of the one or more dummy gates extending beyond at least one edge of the silicon island, and the at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of the at least one thermally conductive structure is deposited over the entire length of the one or more dummy gates and thermally coupled to the one or more dummy gates through thermal vias; and (d) Create at least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

59. The method of claim 58, further comprising forming a redistribution layer on the insulating dielectric layer prior to attaching the insulating dielectric layer.

60. The method of claim 58, further comprising forming the at least one air cavity in the insulating low-dielectric-constant substrate near the at least one electronic circuit element.

61. The method according to claim 58, wherein, The insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high-temperature co-fired ceramic (HTCC), or low-temperature co-fired ceramic (LTCC).

62. The method according to claim 58, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than that of silicon.

63. The method according to claim 58, wherein, The dielectric constant of the insulating low dielectric constant substrate is no greater than 10.

8.

64. The method according to claim 58, wherein, The dielectric constant of the insulating low-dielectric-constant substrate is less than 7.

65. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer adjacent to at least one patterned metal interconnect layer in the set; as well as (7) An insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate being adjacent to the third insulating layer and spaced apart from the silicon active layer by the second insulating layer and the set of at least one patterned metal interconnect layers, the insulating low-dielectric-constant substrate including at least one air cavity, the at least one air cavity being positioned relative to the source and drain of the transistor device to reduce the cutoff capacitance C of the transistor device. OFF Furthermore, it improves the switching quality factor of the transistor device, which is equal to the on-resistance R of the transistor device. ON Multiplied by the cutoff capacitance C OFF , The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure comprising: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

66. The semiconductor structure according to claim 65, wherein, The at least one air cavity is also positioned relative to the at least one set of patterned metal interconnect layers to reduce capacitive coupling between the source and drain of the transistor device.

67. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer adjacent to at least one patterned metal interconnect layer in the set; as well as (7) An insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate being adjacent to the third insulating layer and spaced apart from the silicon active layer by the second insulating layer and the set of at least one patterned metal interconnect layers, the insulating low-dielectric-constant substrate including at least one air cavity, the at least one air cavity being positioned relative to the source and drain of the transistor device to reduce the cutoff capacitance C of the transistor device. OFF Furthermore, it improves the switching quality factor of the transistor device, which is equal to the on-resistance R of the transistor device. ON Multiplied by the cutoff capacitance C OFF , The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

68. The semiconductor structure according to claim 67, wherein, The at least one air cavity is also positioned relative to the at least one set of patterned metal interconnect layers to reduce capacitive coupling between the source and drain of the transistor device.

69. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer; (6) A third insulating layer close to at least one patterned metal interconnect layer and the transistor device; as well as (7) An insulating low-dielectric-constant substrate adjacent to the third insulating layer, the insulating low-dielectric-constant substrate including at least one air cavity extending laterally above the source and drain of the transistor device, the at least one air cavity being positioned relative to the set of at least one patterned metal interconnect layers to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure comprising: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

70. The semiconductor structure according to claim 69, wherein, The at least one air cavity is also positioned relative to the source and drain of the transistor device to reduce the cutoff capacitance C of the transistor device. OFF Furthermore, it improves the switching quality factor of the transistor device, which is equal to the on-resistance R of the transistor device. ON Multiplied by the cutoff capacitance C OFF .

71. A semiconductor structure, comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer; (6) A third insulating layer close to at least one patterned metal interconnect layer and the transistor device; as well as (7) An insulating low-dielectric-constant substrate adjacent to the third insulating layer, the insulating low-dielectric-constant substrate including at least one air cavity extending laterally above the source and drain of the transistor device, the at least one air cavity being positioned relative to the set of at least one patterned metal interconnect layers to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

72. The semiconductor structure according to claim 71, wherein, The at least one air cavity is also positioned relative to the source and drain of the transistor device to reduce the cutoff capacitance C of the transistor device. OFF Furthermore, it improves the switching quality factor of the transistor device, which is equal to the on-resistance R of the transistor device. ON Multiplied by the cutoff capacitance C OFF .

73. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer adjacent to at least one patterned metal interconnect layer in the set; as well as (7) An insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate being adjacent to the third insulating layer and spaced apart from the silicon active layer by the second insulating layer and the set of at least one patterned metal interconnect layers, the insulating low-dielectric-constant substrate including at least one air cavity positioned relative to the transistor device and relative to the set of at least one patterned metal interconnect layers to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes a thermally conductive structure for the MOSFET, the thermally conductive structure comprising: (a) At least one electrical isolation structure formed within the silicon island, each electrical isolation structure being positioned to electrically isolate a portion of the silicon island containing the MOSFET from an edge portion of the silicon island, each edge portion being located in the lateral direction of the MOSFET, but each edge portion being thermally coupled to the portion of the silicon island containing the MOSFET via a corresponding electrical isolation structure; (b) An interlayer dielectric layer formed over at least one of the at least one electrically isolated structures; (c) At least one thermal path, the at least one thermal path comprising a first portion and a second portion, the first portion being in thermal contact with a corresponding edge portion of the silicon island via the interlayer dielectric layer, and the second portion being spaced apart from the corresponding edge portion of the silicon island along the lateral direction of the MOSFET, such that the second portion can couple to the orthogonal thermal path without being blocked by or interfering with the MOSFET, each thermal path being electrically isolated from the MOSFET; and (d) At least one orthogonal thermal path thermally coupled to a second portion of a corresponding one of the at least one thermal paths, and the at least one orthogonal thermal path is configured to transfer heat from a corresponding one of the at least one thermal path to at least one externally accessible thermal pad.

74. A semiconductor structure comprising: (1) A silicon active layer including a first surface and a second surface; (2) A first insulating layer near a portion of the first surface of the silicon active layer; (3) A transistor device formed in and / or on the active silicon layer, the transistor device comprising a source and a drain; (4) A second insulating layer near a portion of the second surface of the silicon active layer; (5) At least one patterned metal interconnect layer adjacent to the second insulating layer and the transistor device; (6) A third insulating layer adjacent to at least one patterned metal interconnect layer in the set; as well as (7) An insulating low-dielectric-constant substrate, the insulating low-dielectric-constant substrate being adjacent to the third insulating layer and spaced apart from the silicon active layer by the second insulating layer and the set of at least one patterned metal interconnect layers, the insulating low-dielectric-constant substrate including at least one air cavity positioned relative to the transistor device and relative to the set of at least one patterned metal interconnect layers to reduce capacitive coupling between the source and drain of the transistor device. The transistor device includes a MOSFET, the MOSFET comprising a source, a body, a gate, and a drain formed in and / or on the silicon active layer, and wherein the MOSFET is formed within a portion of a silicon island, the silicon island being formed within a field oxide region of the silicon active layer, and the semiconductor structure further includes: (a) An insulating gate oxide, said insulating gate oxide being formed above the silicon island; (b) One or more dummy gates formed on the insulating gate oxide above the silicon island, and the one or more dummy gates including portions extending beyond at least one edge of the silicon island, the one or more dummy gates being electrically isolated from and thermally contacted with the MOSFET through the insulating gate oxide, wherein one or more bands are formed across the middle portion or end of the one or more dummy gates; (c) At least one thermally conductive structure, said at least one thermally conductive structure being formed in thermal contact with a portion of at least one of the one or more dummy gates extending beyond said at least one edge of the silicon island, and said at least one thermally conductive structure being electrically isolated from the MOSFET, wherein the extension of said at least one thermally conductive structure is deposited over the entire length of said one or more dummy gates and thermally coupled to said one or more dummy gates through thermal vias; and (d) At least one orthogonal thermal path thermally coupled to one or more of the at least one thermally conductive structure, and the at least one orthogonal thermal path is configured to transfer heat from the one or more of the at least one thermally conductive structure to at least one externally accessible thermal pad.

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