Pixels, related image sensors and methods

Abstract

A pixel includes a semiconductor substrate, a low-κ dielectric, and a photodiode region in the semiconductor substrate. The semiconductor substrate has a substrate top surface forming a trench. The trench extends into the semiconductor substrate and has a trench depth relative to a planar region surrounding the substrate top surface. The low-κ dielectric is located in the trench between the trench depth and a low-κ depth relative to the planar region. The low-κ depth is less than the trench depth. The photodiode region is in the semiconductor substrate and includes (i) a bottom photodiode portion below the trench and (ii) a top photodiode portion adjacent to the trench. The top photodiode portion begins at a photodiode depth relative to the planar region that is less than the low-κ depth and extends toward and adjacent to the bottom photodiode portion.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and more particularly to a pixel, an associated image sensor, and a method for manufacturing the same. Background Technology

[0002] Camera modules in commercial products such as standalone digital cameras, mobile devices, automotive parts, and medical devices include image sensors and their pixel arrays. A pixel array comprises multiple pixels. The pixel density of a pixel array is the number of pixels per unit area on the image sensor. In operation, a lens of the camera module forms an image of an object in its field of view on the image sensor. The object can be observed as multiple infinitesimally small sources of illumination incident on the camera—“pulses”. The lens images each of these pulses at the plane of the pixel array as a corresponding one of multiple point spread functions—“impulse responses”. The resolution of the image captured by the image sensor depends in part on the pixel size compared to the magnitude of the impulse response. Therefore, one way to increase the maximum achievable resolution of a camera is to increase the pixel density by reducing the pixel size. The motivation to reduce pixel size has led to the development of pixels with vertical transfer grids.

[0003] Each of the multiple pixels includes a photodiode region, a floating diffusion region, and a transfer gate. The transfer gate controls the current flow from the photodiode region to the floating diffusion region and may include a field-effect transistor. The potential of the photodiode region exceeds the potential of the floating diffusion region. Light reaching the photodiode region generates photoelectrons. Turning on the transfer gate forms a conductive channel that allows accumulated photoelectrons to transfer from the photodiode region or flow to the floating diffusion region. When the transfer gate is pulsed to the off state, the potential barrier is higher than that of the photodiode region, thus preventing photoelectrons from flowing to the floating diffusion region.

[0004] In a common pixel architecture, the photodiode and floating diffuser region are laterally shifted within the pixel in a direction parallel to the pixel array, with a transfer gate in between. This plane is horizontally oriented relative to a vertical direction that defines the direction of normal incidence to the pixel array. This horizontal orientation limits how much the pixel density can be reduced. Therefore, one way to increase pixel density is to orient the photodiode, transfer gate, and floating diffuser in a direction with a vertical component. Such a transfer gate is an example of a vertical transfer gate. Summary of the Invention

[0005] While vertical transfer gates enable increased pixel density, pixels with vertical transfer gates are susceptible to electron transport hysteresis and dark current, both of which produce image artifacts. Electron transport hysteresis can create black spots in still images and ghosting in videos. Dark current produces bright artifacts in images. The embodiments disclosed herein improve upon these problems.

[0006] A pixel includes a semiconductor substrate, a low-κ dielectric, and a photodiode region in the semiconductor substrate. The semiconductor substrate has a substrate top surface forming a trench. The trench extends into the semiconductor substrate and has a trench depth relative to a planar region surrounding the substrate top surface. The low-κ dielectric is located in the trench between the trench depth and the low-κ depth. The low-κ depth is less than the trench depth relative to the planar region. The photodiode region is in the semiconductor substrate and includes (i) a bottom photodiode portion below the trench and (ii) a top photodiode portion adjacent to the trench. The top photodiode portion begins at a photodiode depth less than the low-κ depth relative to the planar region and extends toward and adjacent to the bottom photodiode portion.

[0007] A pixel fabrication method includes lining the surface of a trench using an etch-stop layer. The trench extends into a top surface of a semiconductor substrate and has a trench depth relative to a planar region surrounding the top surface of the trench. The semiconductor substrate includes a photodiode region located adjacent to the trench. The photodiode region is formed at the photodiode depth and extends away from the planar region. The photodiode depth is less than the trench depth relative to the planar region. The method further includes (a) partially filling the trench to a low-κ depth relative to the planar region using a low-κ dielectric; (b) removing the etch-stop layer between the low-κ depth and the planar region; and (c) depositing a dielectric layer on the surface of the trench at a depth between the planar region and the low-κ depth. Attached Figure Description

[0008] Figure 1 Describe the camera that images the scene.

[0009] Figure 2A This is a cross-sectional schematic diagram of a semiconductor substrate. The semiconductor substrate is... Figure 1 An example of a semiconductor substrate for a camera.

[0010] Figure 2B This is a circuit diagram for a four-transistor ("4T") pixel. A 4T pixel is... Figure 2A The candidate pixel circuit architecture for the pixel.

[0011] Figure 3 This is a cross-sectional view of a pixel in the embodiment. The pixel is formed on... Figure 2A An example of a pixel in a semiconductor substrate.

[0012] Figure 4 This is a schematic cross-sectional view of the first low-κ dielectric in the embodiment. The first low-κ dielectric is... Figure 3 Examples of low-κ dielectrics for pixels.

[0013] Figure 5 This is a schematic cross-sectional view of the second low-k dielectric in the embodiment. The second low-k dielectric is... Figure 3 Examples of low-κ dielectrics for pixels.

[0014] Figure 6-9 The example shown is used in manufacturing Figure 3 The corresponding intermediate substrate obtained during the example process of the pixel.

[0015] Figure 10 This is an example of manufacturing. Figure 3 The flowchart shows the method for calculating pixels. Detailed Implementation

[0016] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same example. Furthermore, specific features, structures, or characteristics may be combined in one or more examples in any suitable manner.

[0017] For ease of description, spatial relative terms such as “below,” “under,” “bottom,” “below,” “above,” and “top” are used herein to describe the relationship between one element or feature and another element or feature as shown in the accompanying drawings. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation besides those shown in the figures. For example, if the device in the figures is flipped, an element described as “below,” “below,” or “below” other elements or features would be oriented as “above” other elements or features. Thus, the terms “below” and “below” can include orientations above and below. The device may be oriented in other ways (rotated ninety degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. Additionally, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0018] Several technical terms are used throughout this specification. These terms will take their common meaning in the field from which they originate, unless explicitly defined herein or their context of use will otherwise clearly imply otherwise. It should be noted that element names and symbols are used interchangeably in this document (e.g., Si relative to silicon); however, both have the same meaning.

[0019] Figure 1 A camera 190 is depicted for imaging a scene. The camera 190 includes an image sensor 100, which includes a semiconductor substrate 110. The semiconductor substrate 110 may be composed of silicon and germanium. The semiconductor substrate 110 includes a pixel array 112A. The image sensor 100 may be a portion of a chip-scale package or an on-board chip package.

[0020] Figure 2A This is a schematic cross-sectional view of semiconductor substrate 210, which is an example of semiconductor substrate 110 of image sensor 100. Semiconductor substrate 210 includes at least one of silicon and germanium. Figure 2A The cross-section shown is parallel to the plane formed by orthogonal directions 298X and 298Z, hereinafter referred to as the xz plane, each orthogonal to direction 298Y. Here, the xz plane is formed by orthogonal directions 298X and 298Y, and the plane parallel to the xz plane is called the transverse plane. Unless otherwise stated, the height of an object in this document refers to the extent of the object in direction 298Z or in the direction 180° opposite to it. Here, references to axes x, y, or related directions ±x, ±y, or ±z refer to directions 298X, 298Y, and 298Z, respectively. Furthermore, here, the horizontal plane is parallel to the xy plane, the width refers to the object's extension in the y-direction, and the perpendicular refers to the z-direction.

[0021] Semiconductor substrate 210 has a bottom substrate surface 211 and a top substrate surface 219, each of which is perpendicular to direction 298Z. Here, the top substrate surface 219 can be referred to as the front surface of semiconductor substrate 210. The top substrate surface 219 can also be referred to as the non-illuminated surface of semiconductor substrate 210, and the bottom substrate surface 211, opposite to the top substrate surface 219, can be referred to as the illuminated surface of semiconductor substrate 210. Semiconductor substrate 210 includes a plurality of pixels 212 forming a pixel array 212A, which is an example of pixel array 212A. The plurality of pixels 212 are arranged in a plurality of rows and columns in directions 298X and 298Y, respectively. Pixel array 212A has a pixel pitch 213 in direction 298X. In an embodiment, in direction 298Y, pixel array 212A has a pitch P equal to the pixel pitch 213. yIn this embodiment, the pixel pitch 213 is less than 1.1 μm; for example, the pixel pitch 213 can be equal to 0.9 μm.

[0022] Figure 2B This is a circuit diagram of a four-transistor (“4T”) pixel 290, which is a candidate pixel circuit architecture for pixel 212. Pixel 290 includes a photodiode PD, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. Pixel 290 is electrically connected to bit line 202 of image sensor 100. Figure 2A and 2B In the following description, they are best observed together.

[0023] Each pixel 212 includes a corresponding photodiode region 240 of a corresponding photodiode PD, a vertical transfer gate 280 of a corresponding transfer transistor (e.g., transfer transistor TX), and a corresponding floating diffusion region 260. The photodiode region 240 of each pixel 212 is configured to generate and accumulate charge in response to incident light, such as incident light entering from the bottom substrate surface 211 of the semiconductor substrate 210 (e.g., the back surface of the semiconductor substrate 210) during the integration cycle of the image sensor 100. The electrical connection from the photodiode region 240 to the floating diffusion region 260 depends on the voltage applied to the vertical transfer gate 280. For example, during the integration cycle of the image sensor 100, the charge (e.g., photoelectrons) accumulated in the photodiode region 240 (e.g., the source of the transfer transistor TX) may be selectively transferred to the floating diffusion region 260 (e.g., the drain of the transfer transistor TX) depending on the voltage applied to the vertical transfer gate 280 of the transfer transistor (e.g., the transfer transistor TX) associated with the pixel 212. The photodiode region 240 can be configured in various ways, including pinned photodiode configurations and partially pinned photodiode configurations.

[0024] Each vertical transfer gate 280 of the transfer transistor (e.g., the vertical gate portion of the transfer transistor TX) is formed in a corresponding trench 220 formed by the top substrate surface 219. The trench 220 includes a side surface 219S and a bottom surface 219B. Some photoelectrons flow through the side surface 219S to the floating diffusion region 260. However, other photoelectrons are trapped at the bottom surface 219B, making them unlikely to reach the floating diffusion region 260 within their lifetime. These trapped electrons cause the aforementioned image artifacts.

[0025] In this embodiment, each pixel 212 is a four-transistor pixel or a 4T pixel, and also includes a reset transistor RST, a source follower transistor SF, and a row select transistor RS. The reset transistor RST is coupled between the power supply line and the floating diffuser 260 to reset under the control of a reset signal during a reset cycle (e.g., discharging or charging the floating diffuser region 260 to a preset voltage, such as the power supply voltage V). DD The reset transistor RST is also coupled to the photodiode region 240 of the photodiode PD via the transfer transistor TX to selectively reset the photodiode region 240 to a preset voltage during the reset cycle. The floating diffusion region 260 is coupled to the gate of the source follower transistor SF. The source follower transistor is coupled between the power supply line and the row select transistor RS. The source follower transistor SF operates to modulate the output image signal based on the received voltage of the floating diffusion region 260, where the image signal corresponds to the amount of photoelectrons accumulated in the photodiode region 240 at its gate during the integration cycle. The row select transistor RS selectively couples the output of the source follower transistor RS (e.g., the image signal) to the readout column line under the control of the row select signal.

[0026] During operation, during the integration period (also known as the exposure or accumulation period) of the image sensor 100, the photodiode region 240 of the photodiode PD detects or absorbs light incident on the pixel 212. The photogenerated charge accumulated in the photodiode region 240 represents the amount of light incident on the photodiode region 240 of the photodiode PD. After the integration period, once a transfer signal (e.g., a positive bias voltage) is received at the vertical transfer gate 280, the transfer transistor TX transfers the photogenerated charge to the floating diffusion region 260. The source follower transistor SF generates the image signal. The row selection transistor RS, coupled to the source follower transistor, then selectively reads the signal onto the column bit lines for subsequent image processing.

[0027] The disclosed vertical transfer gate structure can be applied to any of a variety of additional or alternative types of pixel units, such as five-transistor pixel units or six-transistor pixel units and / or the like.

[0028] Figure 3 This is a cross-sectional view of pixel 300, which is an example of pixel 212. Pixel 300 is formed in a semiconductor substrate 310, which is... Figure 2AAn example of a semiconductor substrate 210. Pixel 300 includes a trench 320, a low-k dielectric 330, and a photodiode region 340. In an embodiment, pixel 300 includes at least one of a floating diffusion region 360, a gate electrode material 325, and a dielectric layer 350. Each of the low-k dielectric 330 and the dielectric layer 350 may include at least one of a nitride material and an oxide material. The gate electrode material 325 may include at least one of polysilicon and a metal. In one embodiment, the low-k dielectric 330 and the dielectric layer 350 are formed of the same material but have different thicknesses to modulate the capacitance associated with different portions or segments of the vertical transfer gate 280.

[0029] In this embodiment, the semiconductor substrate 310 is p-doped, the photodiode region 340 is n-doped, and the floating diffusion region 360 is n-doped. + Doped. In an embodiment, the floating diffusion region 360 has a density of 10 per cubic centimeter. 19 One charge carrier and 5 × 10⁵ per cubic centimeter 20 The doping concentration between individual charge carriers.

[0030] Semiconductor substrate 310 has a surface 319 forming a trench 320. Surface 319 includes a planar region 318 surrounding the trench 320. The trench 320 extends into the semiconductor substrate 310 to a trench depth 323 relative to the planar region 318. Surface 319 is an example of top substrate surface 219. The bottom region of trench 320 (e.g., the region between planes 305 and 306) has a low-κ dielectric 330 disposed therein, which acts as a capacitor with low capacitance relative to the region of trench 320 above the low-κ dielectric 330, thereby suppressing the vertical flow of photoelectrons between the photodiode region 340 and the gate electrode material 325 near the bottom of trench 320, and thus preventing the aforementioned image artifacts. In this document and by convention, a low-κ dielectric is a dielectric material with a dielectric constant κ < 3.9, where 3.9 is the dielectric constant of silicon dioxide. High-κ dielectrics are dielectric materials with a dielectric constant κ > 7, where 7 is the dielectric constant of silicon nitride. Examples of high-κ dielectrics include (but are not limited to) alumina (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂), and combinations thereof.

[0031] In an embodiment, the trench depth 323 is between 0.1 and 0.9 micrometers. In at least one of the 298X and 298Y directions, the trench 320 has a width 321 that may be between 50 nanometers and 0.3 micrometers. In an embodiment, the trench 320 has a non-uniform width between the planar region 318 and its bottom at the trench depth 323. Therefore, the width 321 may be the width of the trench 320 at a depth equal to half the trench depth 323. The semiconductor substrate 310 has a bottom substrate surface 311, which is... Figure 2A Example of the bottom substrate surface 211.

[0032] Photodiode region 340 is Figure 2A An example of a photodiode region 240 is provided, including a bottom photodiode portion 341 below a trench 320 and a top photodiode portion 345 adjacent to the trench 320. The top photodiode portion 345 is formed at a photodiode depth 343 relative to the planar region 318, which is less than the trench depth 323, and extends toward a horizontal plane 307 toward the bottom substrate surface 311. The bottom photodiode portion 341 is adjacent to the top photodiode portion 345 at the horizontal plane 307 and extends toward the bottom substrate surface 311 away from the planar region 318. The horizontal plane 307 is perpendicular to direction 298Z.

[0033] In addition to level 307 Figure 3 Six other horizontal planes 301-306 are represented, each of which is perpendicular to direction 298Z. Plane 301 corresponds to the top surface 359 of the dielectric layer 350 above planar region 318. Plane 302 includes planar region 318. Planes 302 and 303 are perpendicularly separated by junction depth 363. Planes 302 and 304 are perpendicularly separated by photodiode depth 343. Planes 302 and 306 are perpendicularly separated by trench depth 323. Horizontal planes 306 and 307 are separated by a distance 342.

[0034] The bottom photodiode portion 341 has a width 344 exceeding the width 349 of the top photodiode portion 345. In an embodiment, the top photodiode portion 345 has a non-uniform width that varies with direction 298Z. For example, Figure 3 A region 347 is depicted within the photodiode portion 345 and spans between plane 307 and horizontal plane 309. Horizontal plane 309 may be between planes 304 and 305, or between planes 305 and 306. In an embodiment, the top photodiode portion 345 does not include region 347, such that the top photodiode portion 345 has a width 349 between planes 304 and 309, and a narrower width 348 between planes 309 and 307, wherein width 349 exceeds width 348.

[0035] However, by suppressing current flow between the photodiode region 340 and the gate electrode material 325 near the bottom of the trench 320, the low-k dielectric 330 allows the top photodiode portion 345 to be positioned closer to the trench 320 in the horizontal direction than could otherwise be achieved. Therefore, the top photodiode portion 345 can have a uniform width 349, and forming this photodiode region requires fewer process steps than forming a top photodiode portion 345 with two widths 349 and 348. The top photodiode portion 345 is separated from the surface 319 by a minimum distance 346 in the horizontal direction. In an embodiment, the minimum distance 346 is between 1 nanometer and 20 nanometers to allow charge to transfer from the top photodiode portion 345 to the gate electrode material 325.

[0036] The trench depth 323 exceeds the photodiode depth 343, such that a portion of the trench 320 is coplanar with the top photodiode portion 345, for example, at a horizontal plane between planes 304 and 306. The bottom photodiode portion 341 is separated from the surface 319 by a distance 342 in the xy plane. The top photodiode portion 345 is separated from the surface 319 by a photodiode depth 343 in the vertical direction (e.g., along direction 298Z).

[0037] In this embodiment, each of distances 342 and 346 is between 30 nanometers and 300 nanometers. A floating diffusion region 360 is formed in the semiconductor substrate 310, adjacent to the trench 320, and extends away from the planar region 318 to a junction depth 363 less than the trench depth 323. In this embodiment, the junction depth 363 is also less than the low-k depth 333 relative to the planar region 318.

[0038] The dielectric layer 350 serves as a liner for the trench 320 between the low-κ depth 333 and the planar region 318. The gate electrode material 325 fills the trench 320 between the low-κ depth 333 and the planar region 318. The trench 320, dielectric layer 350, low-κ dielectric 330, and gate electrode material 325 together form the vertical transfer gate 380 of the transfer transistor of the vertical gate pixel 300. The vertical transfer gate 380 is electrically connected to the photodiode region 340. The vertical transfer gate 380 is... Figure 2A An example of a vertical transfer gate 280. Because the low-κ dielectric 330 in the bottom region of trench 320 disables the capacitor (e.g., a second capacitor) formed at the bottom of vertical transfer gate 380, when vertical transfer gate 380 is biased (e.g., by a positive voltage) to turn on the transfer transistor, the photocurrent only crosses the conductive channel formed near the vertical (or near-vertical) sidewalls of trench 320 (e.g., between planes 303 and 305).

[0039] A low-κ dielectric 330 is located in a trench 320 between a trench depth 323 and an additional low-κ depth 333 above it. In orientation 298Z, the low-κ dielectric 330 has a thickness 334 less than the trench depth 323. In this embodiment, the thickness 334 is between 10 nanometers and 200 nanometers. This thickness range results in the low-κ dielectric 330, the semiconductor substrate 310, and the gate electrode material 325 functioning as a capacitor with sufficiently low capacitance to prevent photoelectrons from being trapped at the bottom of the trench 320.

[0040] To reiterate, trench 320, dielectric layer 350, gate electrode material 325, and semiconductor substrate 310 can collectively form a first capacitor with a first capacitance. Trench 320, low-k dielectric 330, gate electrode material 325, and semiconductor substrate 310 can collectively form a second capacitor with a second capacitance, which is sufficiently lower than the first capacitance, such that when the vertical transfer gate 380 is biased to turn on, photoelectrons are attracted to travel through the conductive channel path formed around the sidewalls of the vertical transfer gate 380 to reach the floating diffusion region 360, and no photoelectrons travel through the bottom of trench 320.

[0041] The low-κ dielectric 330 has a top surface 339. In an embodiment, the low-κ depth 333 between the planar region 318 and the top surface 339 exceeds the photodiode depth 343 relative to the planar region 318, such that the low-κ dielectric 330 does not impede current flow between the top photodiode portion 345 and the gate electrode material 325. For example, the difference between the photodiode depth 343 and the low-κ depth 333 can be between 10 nanometers and 200 nanometers. In an embodiment, the thickness 334 is less than half the trench depth 323, which can cause the low-κ depth 333 to exceed the photodiode depth 343 relative to the planar region 318. In this embodiment, photoelectrons accumulated in the bottom photodiode portion 341 can travel from the top photodiode portion 345 through the conductive channel region formed on the sidewall of the vertical transfer gate 380 to the floating diffusion region 360 during charge transfer operation.

[0042] In this embodiment, the top surface 339 of the low-k dielectric 330 is planar, such as... Figure 3 As shown. In an embodiment, the low-κ dielectric 330 is concave or conformal to surface 319, while also exceeding a minimum thickness (to meet manufacturing limitations), so that its capacitance is low enough to prevent photoelectrons from being trapped at the bottom of trench 320.

[0043] In one embodiment, pixel 300 includes an etch stop layer 370. The etch stop layer 370 serves as a liner for trench 320 between the low-k dielectric 330 and the surface 319 of the semiconductor substrate 310, for example, between horizontal planes 305 and 306. In one embodiment, the etch stop layer 370 has a higher etch selectivity than the low-k dielectric 330, where etch selectivity is relative to the semiconductor substrate 310. That is, for a given etchant, the etch stop layer 370 has an etch rate exceeding that of the low-k dielectric 330, such that, in one embodiment, the semiconductor substrate 310 is not damaged during the formation of the trench for the low-k dielectric 330. The process may include reactive ion etching. The etch stop layer 370 has a thickness 374 that may be between 1 nanometer and 21 nanometers.

[0044] In this embodiment, the etch stop layer 370 is formed of a high-κ dielectric, which has the benefit of reduced dark current. The high-κ material has a negative fixed charge (depending on thickness) and can form a hole accumulation layer to passivate the sidewalls of the trench 320 near the bottom of the photodiode region 340. The hole accumulation layer reduces dark current by preventing charges generated, for example, from traps / defects formed at the interface between the trench 320 and the semiconductor substrate 310 during the trench etching process from being detected as dark current.

[0045] The dielectric layer 350 has a thickness 354 that can be between 2 nanometers and 10 nanometers. In an embodiment, the thickness 354 is 7.5 nanometers. In an embodiment, the dielectric layer 350 includes a portion 352 that covers the top surface 339 of the low-k dielectric 330.

[0046] A low-k dielectric 330 is used as the capacitor dielectric between the gate electrode material 325 and the semiconductor substrate 310, wherein the portions of the gate electrode material 325 and the semiconductor substrate 310 adjacent to the low-k dielectric 330 serve as capacitor electrodes. The resulting capacitor has a capacitance C. 330 =∈0κ 330 / t 330 , where ∈0 is the permittivity of free space, κ 330 It is the dielectric constant of low-κ dielectric 330, and t 330 Equal to thickness 334. When the low-κ dielectric 330 includes air gaps or pores, the dielectric constant κ... 330 It is the effective dielectric constant of the material that forms the low-κ dielectric 330 and the voids therein.

[0047] The etch stop layer 370 serves as the capacitor dielectric between the gate electrode material 325 and the semiconductor substrate 310, with both the gate electrode material 325 and the semiconductor substrate 310 serving as capacitor electrodes. The resulting capacitor has a capacitance C. 370 =∈0κ 370 / t 370, where κ 370 The dielectric constant of the etch stop layer 370 and t 370 The thickness is equal to 374. The dielectric layer 350 serves as the capacitor dielectric between the gate electrode material 325 and the semiconductor substrate 310, wherein the portions of the gate electrode material 325 and the semiconductor substrate 310 adjacent to the dielectric layer 350 serve as capacitor electrodes. The resulting capacitor has a capacitance C. 350 =∈0κ 350 / t 350 , where κ 350 The dielectric constant of dielectric layer 350 and t 350 Equal to a thickness of 354. In the embodiment, the quotient κ... 330 / t 330 Less than the quotient κ 370 / t 370 He Shang 350 / t 350 At least one of them. In an embodiment, capacitor C 330 and capacitor C 370 The equivalent series capacitance is less than the capacitance C. 350 :(1 / C 330 +1 / C 370 ) -1 <C 350 In this embodiment, the low-k dielectric 330 and the etch-stop layer 370 are configured in terms of thickness and material properties to effectively disable the bottom capacitor of the vertical transfer gate 380 between planes 305 and 306. As a result, photogenerated electrons are not attracted during the charge transfer cycle and travel through the bottom portion of the vertical transfer gate, during which the vertical transfer gate 380 is biased to turn on the corresponding transfer transistor, thereby forming a conductive channel for the photogenerated electrons to travel through.

[0048] Figure 4 This is a schematic cross-sectional view of a low-κ dielectric 400, which is an example of a low-κ dielectric 330. The low-κ dielectric 400 has a thickness 434, which is an example of a thickness 334. The low-κ dielectric 400 includes a plurality of pores 410, making it a porous dielectric. Since the dielectric constant of air is practically equal to 1, the pores 410 help define the low-κ dielectric 400 as a low-κ dielectric. The pores 410 may have an average diameter of less than 2 nanometers. In embodiments, the low-κ dielectric 400 includes at least one of micropores (pore width less than 2 nanometers) and macropores (pore width greater than 100 nanometers). In embodiments, the low-κ dielectric 400 is a porous material comprising a solid network and a gaseous filler. The solid network may be formed of at least one of silica, alumina, and titanium dioxide.

[0049] Figure 5This is a schematic cross-sectional view of a low-k dielectric 500, which is an example of a low-k dielectric 330. The low-k dielectric 500 has a thickness 534, which is an example of a thickness 334. The low-k dielectric 500 includes at least one air gap 520. Since the dielectric constant of air is practically equal to 1, the air gap 520 helps to define the low-k dielectric 500 as a low-k dielectric. The air gap 520 may have a diameter greater than half the thickness 534. In an embodiment, the low-k dielectric 500 includes at least one aperture 410. In an embodiment, the low-k dielectric 400 includes at least one air gap 520.

[0050] Figure 6-9 The various intermediate substrates obtained during an exemplary process of manufacturing pixel 300 are shown. Figure 6 This is a schematic cross-sectional view of the coated substrate 610, which is a semiconductor substrate 310 having an etch stop layer 670 deposited on surface 319 to line trench 320. In this embodiment, the etch stop layer 370 of pixel 300 is formed by the etch stop layer 670.

[0051] Figure 7 This is a cross-sectional schematic diagram of the coated substrate 710, which is a coated substrate 610 with a low-k dielectric 330 added to the trench 320, such that a portion of the etch stop layer 670, referred to as layer portion 672, is located between the surface 319 and the low-k dielectric 330. Figure 7 The layer portion 671 supplements the layer portion 672 by indicating the remaining portion of the etch stop layer 670 that is not covered by the low-κ dielectric 330.

[0052] Figure 8 This is a schematic cross-sectional view of the etched substrate 810, which is the coated substrate 710 after the removal of layer portion 671. The etched substrate 810 includes layer portion 672 between the low-k layer 330 and the surface 319.

[0053] Figure 9 This is a schematic cross-sectional view of the coated substrate 910, which is the etched substrate 810 after the deposition of the dielectric layer 950 on the etched substrate 810. The dielectric layer 950 is... Figure 3 Example of dielectric layer 350.

[0054] Figure 10 This is a flowchart illustrating a method 1000 for manufacturing pixels, such as pixel 300. Method 1000 includes steps 1010, 1020, and 1040. In an embodiment, method 1000 further includes at least one of steps 1030, 1050, and 1060.

[0055] Step 1010 includes lining the surface of the trench with an etch stop layer. The trench extends into the top surface of the semiconductor substrate and has a trench depth relative to a planar region surrounding the top surface of the trench. The semiconductor substrate includes a photodiode region located near the trench. The photodiode region is formed at the photodiode depth and extends away from the planar region. The photodiode depth is less than the trench depth relative to the planar region. In the example of step 1010, the trench 320 of the semiconductor substrate 310 is lined with an etch stop layer 670, which produces Figure 6 The coated substrate 610.

[0056] The etch stop layer 670 can be conformally deposited onto the trench structure of trench 320 using appropriate deposition processes, such as atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD). The etch stop layer 670 prevents damage to the semiconductor substrate 610 during the etching process. In one example, the etch stop layer 670 is formed of a high-k dielectric, which benefits by reducing dark current.

[0057] Step 1020 includes partially filling the trench to a low-κ depth using a low-κ dielectric, the low-κ depth being smaller than the trench depth relative to the planar region. In an example of step 1020, the trench 320 is partially filled to a low-κ depth 333 with a low-κ dielectric layer 330, producing a result such as Figure 7 The coated substrate 710 is shown. In this example, a plasma chemical vapor deposition (CVD) process can be used to form a low-k dielectric, such that the low-k dielectric may include at least an air gap, as... Figure 4 and / or Figure 5 As shown.

[0058] Step 1030 includes dry etching of the low-κ dielectric using an etchant until the thickness of the low-κ dielectric is equal to the difference between the trench depth and the low-κ depth. In step 1030, the etch rate of the low-κ dielectric exceeds the etch rate of the etch stop layer, such that the surrounding semiconductor substrate 310 is protected by the etch stop layer. Step 1030 may be part of step 1020. In an embodiment, step 1030 includes dry etching via a reactive ion etching process, which may be fluorine-based or chlorine-based. In an example of step 1030, the low-κ dielectric material partially filling the trench 320 is dry etched until its thickness is reduced to a thickness 334. The dry etching produces a low-κ dielectric 330. The thickness 334 is equal to the difference between the trench depth 323 and the low-κ depth 333.

[0059] Step 1040 includes removing the etch stop layer between the low κ depth and the planar region. In an embodiment, step 1040 includes removing the etch stop layer via a wet etching process. In an example of step 1040, layer portion 671 of the etch stop layer 670 is removed from surface 319, which produces Figure 8 The etched substrate 810.

[0060] Step 1050 includes depositing a dielectric layer on the surface of the trench at a depth between the planar region and the low κ depth. In an example of step 1050, the dielectric layer 950 is deposited on surface 319, which produces... Figure 9 The coated substrate 910. In one example, the dielectric layer is conformally formed to the sidewalls of the trench 320 and the top surface with a low κ depth.

[0061] Step 1060 includes filling a trench between the low κ depth and the planar region using a gate electrode material. Step 1060 occurs after step 1020. In an example of step 1060, the trench 320 of the coated substrate 910 is filled with a gate electrode material 325, which forms a vertical transfer gate 380 for transferring transistor TX. In an embodiment, method 1000 includes forming a floating diffusion region 360 in a semiconductor substrate 310 adjacent to the trench 320 by ion implantation. The floating diffusion region 360 extends away from the planar region to a junction depth less than the trench depth, such that method 1000 produces Figure 3 In pixel 300, a photodiode region 340 serves as the source of a transfer transistor TX, and a floating diffusion region serves as the drain of the transfer transistor TX.

[0062] Combination of features

[0063] The features described above, as well as the features claimed below, can be combined in various ways without departing from the scope of the invention. The following examples illustrate some possible non-limiting combinations:

[0064] (A1) A pixel comprising a semiconductor substrate, a low-κ dielectric, and a photodiode region in the semiconductor substrate. The semiconductor substrate has a substrate top surface forming a trench. The trench extends into the semiconductor substrate and has a trench depth relative to a planar region surrounding the substrate top surface. The low-κ dielectric is located in the trench between the trench depth and the low-κ depth. The low-κ depth is less than the trench depth relative to the planar region. The photodiode region is in the semiconductor substrate and includes (i) a bottom photodiode portion below the trench and (ii) a top photodiode portion adjacent to the trench. The top photodiode portion begins at a photodiode depth less than the low-κ depth relative to the planar region and extends toward and adjacent to the bottom photodiode portion.

[0065] (A2) Pixel (A1) may also include (i) a gate electrode material that fills the trench between the low-κ depth and the planar region, and (ii) an oxide layer that lines the trench between the low-κ depth and the planar region. The trench, oxide layer, low-κ dielectric, and gate electrode material together form a vertical transfer gate electrically connected to the top photodiode portion.

[0066] (A3) In any pixel (A2), the gate electrode material may include at least one of polysilicon and metal.

[0067] (A4) In either pixel (A2) or (A3), the oxide layer has a dielectric constant κ. o Thickness t o and κ o / t o Proportional oxide layer capacitance, low κ dielectric with dielectric constant k L Thickness t L and with κ L / t L Proportional low-κ capacitance. Low-κ capacitance can be smaller than the oxide layer capacitance.

[0068] (A5) In any of the pixels (A1)-(A4), the thickness of the low-κ dielectric in the direction perpendicular to the planar region can be between 10 nanometers and 200 nanometers.

[0069] (A6) In any of the pixels (A1)-(A5), the thickness of the low-κ dielectric in a first direction perpendicular to the planar region may be less than half the trench depth.

[0070] (A7) In any of the pixels (A1)-(A6), the difference between the photodiode depth and the low κ depth can be between 10 nanometers and 200 nanometers.

[0071] (A8) In any of the pixels (A1)-(A7), in a cross-sectional plane perpendicular to the top surface of the substrate, the photodiode region may be L-shaped, and the bottom photodiode portion may have a first width that exceeds the second width of the top photodiode portion in a direction parallel to the top surface of the substrate.

[0072] Any of the (A9) pixels (A1)-A8) may further include a floating diffusion region in the semiconductor substrate that is adjacent to the trench and extends away from the planar region to a junction depth less than the trench depth.

[0073] (A10) In any of the pixels (A1)-(A9), the low-κ dielectric may include at least one air gap having a diameter that is more than half the thickness of the low-κ dielectric.

[0074] (A11) In any of the pixels (A1)-(A10), the low-κ dielectric can be formed of a porous material.

[0075] Any of pixels (A1)-(A11) in (A12) may further include an etch-stop layer lining a trench between the low-k dielectric and the semiconductor substrate. The etch-stop layer has an etch selectivity exceeding that of the low-k dielectric. Each etch selectivity is relative to the semiconductor substrate.

[0076] (A13) In any of the pixels (A12), the thickness of the etch stop layer can be between 1 nanometer and 21 nanometers.

[0077] (A14) In either of pixels (A12) and (A13), the etch stop layer can be a high-k dielectric.

[0078] (A15) In any of pixels (A12)-(A14), the etch stop layer has a dielectric constant κ. s Thickness t s and with κ s / t s Proportional etch stop capacitor C s Low-κ dielectrics have a dielectric constant κ. L Thickness t L and κ L / t L Proportional low κ capacitance C L The low-k capacitance can be smaller than the etching-stop capacitance.

[0079] (A16) pixel (A15) may also include an oxide layer lining the trench between the low κ depth and the planar region, and having a dielectric constant κ o Thickness t o and with κ o / t o Proportional and exceeding (1 / C) L +1 / C s ) -1 oxide layer capacitance C o .

[0080] (B1) An image sensor comprising any one of a plurality of (A1)-(A15) pixels, wherein for each pixel of the plurality of pixels, its semiconductor substrate is a portion of the same semiconductor substrate of the image sensor.

[0081] (C1) A pixel manufacturing method includes lining the surface of a trench using an etch-stop layer. The trench extends into a top surface of a semiconductor substrate and has a trench depth relative to a planar region surrounding the top surface of the trench. The semiconductor substrate includes a photodiode region located near the trench. The photodiode region is formed at the photodiode depth and extends away from the planar region. The photodiode depth is less than the trench depth relative to the planar region. The method further includes (a) partially filling the trench to a low-κ depth less than the trench depth relative to the planar region using a low-κ dielectric; (b) removing the etch-stop layer between the low-κ depth and the planar region; and (c) depositing a dielectric layer on the surface of the trench at a depth between the planar region and the low-κ depth.

[0082] (C2) Method (C1) may further include dry etching of the low-κ dielectric using an etchant until the thickness of the low-κ dielectric is equal to the difference between the trench depth and the low-κ depth. For the etchant, the etching rate of the low-κ dielectric exceeds the etching rate of the etch termination layer.

[0083] (C3) In either of methods (C1) and (C2), the removal may include a wet etching termination layer.

[0084] (C4) Any of (C1) to (C3) may further include filling the trench between the low κ depth and the planar region with the gate electrode material after partial filling.

[0085] Modifications to the methods and systems described above may be made without departing from the scope of the invention. Therefore, it should be noted that content included in the above description or shown in the accompanying drawings should be interpreted as illustrative rather than restrictive. In this document, unless otherwise stated, the phrase "in an embodiment" is equivalent to the phrase "in a particular embodiment" and does not refer to all embodiments. The appended claims are intended to cover all general and specific features described herein, as well as all statements within the scope of the methods and systems, and linguistically, these statements may be said to fall within the scope of the claims.

Claims

1. A pixel, comprising: A semiconductor substrate having a substrate top surface forming a trench that extends into the semiconductor substrate and has a trench depth relative to a planar region surrounding the substrate top surface; A low-κ dielectric, wherein the low-κ dielectric is in the trench between the trench depth and a low-κ depth above the trench depth, the low-κ depth being smaller than the trench depth relative to the planar region; An oxide layer that serves as a liner for the trench between the low κ depth and the planar region; A photodiode region, the photodiode region being in the semiconductor substrate and comprising (i) a bottom photodiode portion below the trench and (ii) a top photodiode portion adjacent to the trench, the top photodiode portion extending toward and adjacent to the bottom photodiode portion from a photodiode depth less than the low κ depth relative to the planar region; as well as A gate electrode material that fills the trench between the low κ depth and the planar region; The trench, the oxide layer, the low-k dielectric, and the gate electrode material together form a vertical transfer gate electrically connected to the photodiode region; The trench, the oxide layer, the gate electrode material, and the semiconductor substrate together form a first capacitor with a first capacitance, and the trench, the low-k dielectric, the gate electrode material, and the semiconductor substrate together form a second capacitor with a second capacitance. The second capacitance is lower than the first capacitance, such that when the vertical transfer gate is biased to turn on, photoelectrons are attracted to travel through the conductive channel path formed around the sidewall of the vertical transfer gate to reach the floating diffusion region.

2. The pixel as described in claim 1, In the direction perpendicular to the planar region, the thickness of the oxide layer differs from the thickness of the low-κ dielectric, and the thickness of the oxide layer is equal to the difference between the trench depth and the low-κ depth.

3. The pixel as claimed in claim 2, wherein the gate electrode material comprises at least one of polycrystalline silicon and a metal.

4. The pixel of claim 2, wherein the oxide layer has a dielectric constant. ,thickness and with Proportional oxide layer capacitance, wherein the low-κ dielectric has a dielectric constant k. L ,thickness and with A low κ capacitance that is proportional to and smaller than the capacitance of the oxide layer.

5. The pixel of claim 1, wherein the thickness of the low-k dielectric in the direction perpendicular to the planar region is between 10 nanometers and 200 nanometers.

6. The pixel of claim 1, wherein the thickness of the low-k dielectric in a first direction perpendicular to the planar region is less than half the depth of the trench.

7. The pixel of claim 1, wherein the difference between the photodiode depth and the low-k depth is between 10 nanometers and 200 nanometers.

8. The pixel of claim 1, wherein in a cross-sectional plane perpendicular to the top surface of the substrate, the photodiode region is L-shaped, the bottom photodiode portion has a first width, the first width exceeding the second width of the top photodiode portion in a direction parallel to the top surface of the substrate.

9. The pixel as claimed in claim 1, further comprising: A floating diffusion region in the semiconductor substrate, adjacent to the trench and extending away from the planar region to a junction depth less than the trench depth.

10. The pixel of claim 1, wherein the low-k dielectric includes at least one air gap having a diameter exceeding half the thickness of the low-k dielectric.

11. The pixel of claim 1, wherein the low-k dielectric is formed of a porous material.

12. The pixel of claim 1, further comprising: An etch stop layer, which lines the trench between the low-k dielectric and the semiconductor substrate and has an etch selectivity exceeding that of the low-k dielectric, each etch selectivity being relative to the semiconductor substrate.

13. The pixel of claim 12, wherein the thickness of the etch stop layer is between 1 nanometer and 21 nanometers.

14. The pixel of claim 12, wherein the etch stop layer is a high-k dielectric.

15. The pixel of claim 12, wherein the etch stop layer has a dielectric constant. ,thickness and with Proportional etch stop capacitor The low-k dielectric has a dielectric constant. ,thickness and with Proportional to and smaller than the etch-stop capacitor Low κ capacitance .

16. The pixel of claim 15, wherein the oxide layer has a dielectric constant. ,thickness and with Proportionate and exceeding oxide layer capacitor .

17. An image sensor comprising a plurality of pixels as claimed in claim 1, wherein for each of the plurality of pixels, its semiconductor substrate is a portion of the same semiconductor substrate of the image sensor.

18. A pixel manufacturing method, comprising: An etch-stop layer is used to line the surface of a trench that extends into the top surface of a semiconductor substrate and has a trench depth relative to a planar region surrounding the top surface of the trench. The semiconductor substrate includes a photodiode region adjacent to the trench and formed at the photodiode depth and extending away from the planar region, wherein the photodiode depth is less than the trench depth relative to the planar region. The trench is partially filled to a low-κ depth relative to the planar region, which is smaller than the trench depth, using a low-κ dielectric. Remove the etch stop layer between the low κ depth and the planar region; as well as An oxide layer is deposited on the surface of the trench at a depth between the planar region and the low κ depth; It also includes filling the trench between the low κ depth and the planar region with a gate electrode material after partial filling; The trench, the oxide layer, the low-k dielectric, and the gate electrode material together form a vertical transfer gate electrically connected to the photodiode region; The trench, the oxide layer, the gate electrode material, and the semiconductor substrate together form a first capacitor with a first capacitance, and the trench, the low-k dielectric, the gate electrode material, and the semiconductor substrate together form a second capacitor with a second capacitance. The second capacitance is lower than the first capacitance, such that when the vertical transfer gate is biased to turn on, photoelectrons are attracted to travel through the conductive channel path formed around the sidewall of the vertical transfer gate to reach the floating diffusion region.

19. The method of claim 18, further comprising dry etching the low-κ dielectric with an etchant until the thickness of the low-κ dielectric is equal to the difference between the trench depth and the low-κ depth, wherein the etch rate of the low-κ dielectric exceeds the etch rate of the etch termination layer with respect to the etchant.

Images