Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and a method for operating the semiconductor memory device. The semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, and a control logic circuit. The memory cell array includes memory cell rows. The refresh control circuit performs a refresh operation on the memory cell rows. The control logic circuit controls the ECC engine so that the ECC engine generates an error generation signal by performing ECC decoding on a subpage in at least one first memory cell row during a read operation. The control logic circuit compares an error occurrence count of the first memory cell row with a threshold value, and provides a first address of the first memory cell row as an error address to the refresh control circuit based on the comparison. The refresh control circuit increases the number of refresh operations performed in the first memory cell row during a refresh period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0151829 filed in the Korean Intellectual Property Office on November 25, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to memory devices, and more particularly, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Art

[0004] Random Access Memory (RAM) is an example of a computer memory device used to store working (temporary) information. RAM devices are commonly found in devices such as laptops, mobile phones, etc. Dynamic RAM (DRAM) is a subset of RAM in which information can be stored and read regardless of its physical location on the chip.

[0005] A bit error is a bit of information that is altered during programming, storage, or reading due to external factors. Bit errors can be corrected using error correction codes (ECC). For example, ECC can be used to correct bit errors by performing calculations to detect errors in bits and, if an error is detected, attempting to correct the error.

[0006] As DRAM devices get smaller in size (ie, as electronic devices get smaller), the bit error rate increases. Therefore, there is a need in the art for more robust ECC operation to compensate for smaller DRAM devices. Summary of the invention

[0007] Some example embodiments provide a semiconductor memory device capable of adjusting refresh using error information.

[0008] Some example embodiments provide a method of operating a semiconductor memory device capable of adjusting refresh using error information.

[0009] According to example embodiments, a semiconductor memory device includes: a memory cell array; an error correction code (ECC) engine; a refresh control circuit configured to perform a refresh operation on the plurality of memory cell rows; and a control logic circuit configured to control the ECC engine based on a command and an address from an external memory controller, wherein the control logic circuit is further configured to control the ECC engine so that the ECC engine generates an error generation signal by performing an ECC decoding operation on a subpage in at least one first memory cell row among the memory cell rows during a read operation, wherein the control logic circuit is further configured to compare an error occurrence count of the first memory cell row with a threshold value and provide a first address of the first memory cell row as an error address to the refresh control circuit based on the comparison, wherein the error occurrence count is generated based on the error generation signal, and wherein the refresh control circuit is configured to increase the number of refresh operations performed in the first memory cell row during a refresh period based on the error occurrence count.

[0010] According to example embodiments, a semiconductor memory device includes: a memory cell array including a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of volatile memory cells; an error correction code (ECC) engine; a refresh control circuit configured to perform a refresh operation on the plurality of memory cell rows; an error information register; and a control logic circuit configured to control the ECC engine based on a command and an address from an external memory controller, wherein the control logic circuit is further configured to control the ECC engine so that the ECC engine generates an error generation signal by performing an ECC decoding operation on a subpage in at least one first memory cell row in the memory cell rows during a read operation. , wherein the control logic circuit is further configured to: compare an error occurrence count of the first storage cell row with a threshold value, and based on the comparison, provide a first address of the first storage cell row as an error address to the refresh control circuit, wherein the error occurrence count is generated based on the error generation signal; or record error information in the error information register during the read operation, and provide the error address to the refresh control circuit by referring to the error information register, wherein the error information includes at least the number of error occurrences in the first storage cell row and the second storage cell row, and wherein the refresh control circuit is further configured to increase the number of refresh operations performed in the first storage cell row during the refresh period.

[0011] According to an example embodiment, a method for operating a semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, the memory cell array includes a plurality of memory cell rows, and the plurality of memory cell rows each include a plurality of volatile memory cells. According to the method, an error correction code (ECC) engine performs ECC decoding on a subpage in at least one first memory cell row in the memory cell rows during a read operation. A control logic circuit counts the occurrence of errors in the at least one first memory cell row based on the result of the ECC decoding. The control logic circuit compares the error occurrence count of the first memory cell row with a threshold value, and provides a first address of the first memory cell row as an error address to a refresh control circuit in response to the error occurrence count being equal to or greater than the threshold value. The refresh control circuit increases the number of refresh operations performed on the first memory cell row during a refresh period.

[0012] According to example embodiments, a method of operating a memory device includes: performing an error correction code (ECC) operation on a portion of memory cells in the memory device; modifying a mode of refresh operation of the portion of memory cells based on the ECC operation; and performing a refresh operation on the portion of memory cells based on the modified mode of the refresh operation. In some cases, the method includes identifying an error count based on the ECC operation; determining that the error count is equal to or greater than a threshold; and increasing the number of refresh operations on the portion of memory cells, wherein modifying the mode of refresh operation of the portion of memory cells is based on the increased number of refresh operations.

[0013] Therefore, the semiconductor memory device can improve reliability by increasing the number of refresh operations performed on some memory cell rows designated by error addresses during a refresh period using error information obtained as a result of ECC decoding the memory cell rows during a read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0015] Figure 1 is a block diagram illustrating a storage system according to example embodiments.

[0016] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 Block diagram of a semiconductor memory device in FIG.

[0017] Figure 3 According to an example embodiment, Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0018] Figure 4According to an example embodiment, Figure 2 A memory bank array and an ECC engine are shown in a semiconductor memory device.

[0019] Figure 5 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of a refresh control circuit in a semiconductor memory device.

[0020] Figure 6 is a diagram showing a method according to an example embodiment Figure 5 A circuit diagram of an example of a refresh clock generator in a refresh control circuit.

[0021] Figure 7 is a diagram showing a method according to an example embodiment Figure 5 A circuit diagram of another example of a refresh clock generator in a refresh control circuit of FIG.

[0022] Figure 8 According to an example embodiment, Figure 5 A weak address generator in the refresh control circuit of .

[0023] Fig. 9 According to an example embodiment, Figure 5 The address comparison circuit is shown in the refresh control circuit.

[0024] Fig.10 Shows Fig. 9 One of the unit comparison circuits shown in .

[0025] Fig.11 According to an example embodiment, Figure 5 The address converter in the refresh control circuit.

[0026] Fig.12 Shown in Figure 2 A normal refresh operation and a weak refresh operation are performed in parallel in a semiconductor memory device.

[0027] Fig.13 Shown in Fig.12 A normal refresh operation and a weak refresh operation are sequentially performed in a semiconductor memory device.

[0028] Fig.14 shows the write operation Figure 2 A portion of a semiconductor memory device.

[0029] Fig.15 shows the read operation Figure 2 semiconductor memory devices.

[0030] Fig.16 According to an example embodiment, Fig.15An error information register in a semiconductor memory device.

[0031] Fig.17 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of an ECC engine in a semiconductor memory device.

[0032] Fig.18 According to an example embodiment, Fig.17 Example of an ECC decoder in an ECC engine.

[0033] Fig.19 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0034] Fig. 20 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0035] Fig.21 According to the exemplary embodiment, Fig. 20 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0036] Fig. 22 is a diagram illustrating a semiconductor package including a stacked memory device according to example embodiments. DETAILED DESCRIPTION

[0037] The present disclosure relates to a semiconductor memory device. More specifically, some embodiments relate to a semiconductor memory device having an error correction code.

[0038] In some cases, semiconductor memory devices can refresh certain portions of memory to preserve the stored information and increase the reliability of the memory. Memory refresh refers to the process of periodically reading information from an area of ​​memory and rewriting the information to the same area without modification. Memory refresh can be a background maintenance process performed during the operation of a dynamic random access memory (DRAM).

[0039] In DRAM memory, each bit of data can be stored as the presence or absence of a charge on a small capacitor. Over time, the charge leaks away. Therefore, if there is no memory refresh, the stored data is lost. To prevent this data loss, the memory device can periodically read each cell and rewrite the stored data. The rewrite can restore the charge on the capacitor.

[0040] Each memory refresh cycle may be performed on memory cells in a specific area. According to embodiments of the present disclosure, different cells in the memory may be refreshed according to different periodicities. The refresh process may be performed automatically in the background by the memory circuit. In some cases, a memory cell may not be available for rewriting while a refresh cycle is occurring. Therefore, it may be desirable to limit the refresh cycle so that the overhead time associated with the memory refresh process is not large enough to significantly slow down memory operations.

[0041] According to at least one embodiment, a semiconductor memory device may include a memory cell array, an error correction code (ECC) engine, a refresh control circuit, and a control logic circuit. The memory cell array includes memory cell rows, and the refresh control circuit performs a refresh operation on the memory cell rows. The ECC engine generates an error generation signal by performing an ECC decoding operation on a subpage in at least one first memory cell row during a read operation. The control logic circuit controls the ECC engine based on a command and an address from an external memory controller. The control logic circuit controls the ECC engine so that the ECC engine generates an error generation signal by performing an ECC decoding on a subpage in at least one first memory cell row in the memory cell rows during a read operation.

[0042] The control logic circuit compares the error occurrence count of the first memory cell row with a threshold value and provides a first address of the first memory cell row as an error address to the refresh control circuit based on the comparison. The error occurrence count is generated based on the error generation signal. The refresh control circuit increases the amount of refresh operations performed in the first memory cell row during the refresh period.

[0043] Therefore, the semiconductor memory device may increase the number of refresh operations performed on certain memory cell rows based on the result of the ECC decoding operation.

[0044] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

[0045] Figure 1 is a block diagram illustrating a storage system according to example embodiments.

[0046] Reference Figure 1 , the memory system 20 may include a memory controller 100 and a semiconductor memory device 200 .

[0047] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 may write data to or read data from the semiconductor memory device 200 in response to a request from the host.

[0048] Additionally or alternatively, the memory controller 100 may issue an operation command to the semiconductor memory device 200 to control the semiconductor memory device 200 .

[0049] In some example embodiments, the semiconductor memory device 200 is a memory device including a dynamic memory cell, for example, a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or a LPDDR5 SDRAM.

[0050] The memory controller 100 transmits a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device 200 , and exchanges main data MD with the semiconductor memory device 200 .

[0051] The semiconductor memory device 200 includes a memory cell array (MCA) 300 storing main data MD and parity bits, an error correction code (ECC) engine 400 , a control logic circuit 210 , and a refresh control circuit 500 .

[0052] The memory cell array 300 includes a plurality of memory cell rows, each of which includes a plurality of volatile memory cells.

[0053] The ECC engine 400 may perform ECC encoding on write data to be stored in a target memory cell row (target page) of the memory cell array 300, and may perform ECC decoding on data read from the target page under the control of the control logic circuit 210. The ECC engine 400 may provide information of the error bit to the control logic circuit 210 in response to detecting the error bit. The detection of the error bit may be based on the result of the ECC decoding.

[0054] The control logic circuit 210 may control the ECC engine 400 so that the ECC engine 400 generates an error generation signal by performing ECC decoding on a subpage in at least one first memory cell row in the memory cell rows during a read operation. The control logic circuit 210 may compare an error occurrence count of the first memory cell row with a threshold value, and may provide a first address of the first memory cell row as an error address to the refresh control circuit 500 based on the comparison. The error occurrence count may be generated based on the error generation signal.

[0055] The refresh control circuit 500 may perform a refresh operation on a plurality of memory cell rows, may include a first memory cell row in one or more weak pages of the memory cell array 300, and may increase the number of refresh operations performed in the one or more weak pages including the first memory cell row during a refresh period. A weak page may refer to a page in which errors are expected to occur at a frequency greater than a threshold.

[0056] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 Block diagram of a semiconductor memory device in FIG.

[0057] Reference Figure 2 , the semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a bank control logic 230, a refresh control circuit 500, a row address multiplexer (RAMUX) 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an I / O gating circuit 290, an ECC engine 400, and a data I / O buffer 295. The semiconductor memory device 200 may further include an error information register (EIR) 594.

[0058] The memory cell array 300 includes first to eighth memory bank arrays 310-380. The row decoder 260 includes first to eighth memory bank row decoders 260a-260h respectively coupled to the first to eighth memory bank arrays 310-380. The column decoder 270 includes first to eighth memory bank column decoders 270a-270h respectively coupled to the first to eighth memory bank arrays 310-380. The sense amplifier unit 285 includes first to eighth memory bank sense amplifiers 285a-285h respectively coupled to the first to eighth memory bank arrays 310-380.

[0059] The first to eighth memory bank arrays 310-380, the first to eighth memory bank row decoders 260a-260h, the first to eighth memory bank column decoders 270a-270h, and the first to eighth memory bank sense amplifiers 285a-285h may form the first to eighth memory banks. The first to eighth memory bank arrays 310-380 each include a plurality of volatile memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0060] The address register 220 receives an address ADDR, wherein the address ADDR includes a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230. Additionally or alternatively, the address register 220 provides the received row address ROW_ADDR to the row address multiplexer 240. The address register 220 also provides the received column address COL_ADDR to the column address latch 250.

[0061] The bank control logic 230 generates a bank control signal in response to the bank address BANK_ADDR. The bank row decoders corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 260a-260h are activated in response to the bank control signal, and the bank column decoders corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders 270a-270h are activated in response to the bank control signal.

[0062] The row address multiplexer 240 receives the row address ROW_ADDR from the address register 220 and receives the refresh row address REF_ADDR from the refresh control circuit 500. The row address multiplexer 240 selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 is applied to the first to eighth bank row decoders 260a-260h.

[0063] The refresh control circuit 500 may output a refresh row address REF_ADDR that sequentially changes in response to the first refresh control signal IREF1 or the second refresh control signal IREF2 from the control logic circuit 210. The refresh control circuit 500 may store an error address EADDR from the control logic circuit 210 in a lookup table therein.

[0064] When the command CMD from the memory controller 100 corresponds to an auto refresh command, the control logic circuit 210 may apply the first refresh control signal IREF1 to the refresh control circuit 500 whenever the control logic circuit 210 receives the auto refresh command.

[0065] When the command CMD from the memory controller 100 corresponds to a self-refresh entry (SRE) command, the control logic circuit 210 may apply the second refresh control signal IREF2 to the refresh control circuit 500. Therefore, the second refresh control signal IREF2 is activated from the time point when the control logic circuit 210 receives the self-refresh entry command to the time point when the control logic circuit 210 receives the self-refresh exit (SRX) command. The refresh control circuit 500 may sequentially increase or decrease the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2. The control logic circuit 210 may provide the refresh control circuit 500 with a mode signal MS indicating a refresh mode based on the command CMD.

[0066] The bank row decoder activated by the bank control logic 230 among the first to eighth bank row decoders 260a-260h decodes the row address RA output from the row address multiplexer 240 and activates a word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line driving voltage to the word line corresponding to the row address RA.

[0067] The column address latch 250 receives the column address COL_ADDR from the address register 220 and temporarily stores the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 250 generates a column address COL_ADDR' based on the received column address COL_ADDR. The column address latch 250 applies the temporarily stored or generated column address COL_ADDR' to the first to eighth bank column decoders 270a-270h.

[0068] The activated bank column decoder among the first to eighth bank column decoders 270 a - 270 h activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR′ through the I / O gating circuit 290 .

[0069] The I / O gating circuit 290 includes a circuit for gating input / output data. The I / O gating circuit 290 also includes input data masking logic, a read data latch for storing data output from the first to eighth memory bank arrays 310-380, and a write driver for writing data into the first to eighth memory bank arrays 310-380.

[0070] The codeword CW read from one of the first to eighth memory bank arrays 310-380 may be sensed by a sense amplifier, wherein the sense amplifier may be coupled to the memory bank array from which data will be read. The codeword CW is then stored in a read data latch. After the ECC engine 400 performs ECC decoding on the codeword CW, the codeword CW stored in the read data latch may be provided to the memory controller 100 via the data I / O buffer 295.

[0071] The main data MD to be written into one of the first to eighth memory bank arrays 310-380 may be provided from the memory controller 100 to the data I / O buffer 295. The main data MD may also be provided from the data I / O buffer 295 to the ECC engine 400. The ECC engine 400 may perform ECC encoding on the main data MD to generate parity bits. The ECC engine 400 may also provide the main data MD and the parity bits to the I / O gating circuit 290. The I / O gating circuit 290 may write the main data MD and the parity bits into a sub-page of a target page of one memory bank array through a write driver.

[0072] The data I / O buffer 295 may provide the main data MD from the memory controller 100 to the ECC engine 400 in a write operation of the semiconductor memory device 200 based on the clock signal CLK. The data I / O buffer 295 may also provide the main data MD from the ECC engine 400 to the memory controller 100 in a read operation of the semiconductor memory device 200.

[0073] The ECC engine 400 performs ECC decoding on the codeword read from the sub-page of the target page. The ECC engine 400 can also provide an error generation signal EGS to the control logic circuit 210 so that when at least one error bit is detected in the main data MD of the codeword in the read operation of the semiconductor memory device 200, the at least one error bit is corrected.

[0074] The control logic circuit 210 may count the error generation signal EGS in units of memory cell rows (pages). Then, the control logic circuit 210 may compare the error occurrence count of each memory cell row with a threshold value, and in response to the error occurrence count of the first memory cell row being equal to or greater than the threshold value, provide the first address of at least one first memory cell row as the error address EADDR to the refresh control circuit 500.

[0075] In an example embodiment, the control logic circuit 210 may store a row address and a column address associated with a codeword in which at least one error bit is detected in the error information register 594 as error information EINF.

[0076] The control logic circuit 210 may control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 includes a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the semiconductor memory device 200.

[0077] For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, and the like.

[0078] The control logic circuit 210 may generate a first control signal CTL1 for controlling the I / O strobe circuit 290 , a second control signal CTL2 for controlling the ECC engine 400 , and a third control signal CTL3 for controlling the error information register 594 .

[0079] The error information register 594 may provide (send) information associated with some error information EINF stored therein as an error information signal EIS to the memory controller 100. The error information register 594 may send the error information signal EIS to the memory controller 100 via one of the dedicated pins or the data I / O pins in response to the third control signal CTL3.

[0080] Figure 3 According to an example embodiment, Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0081] Reference Figure 3 , the first memory bank array 310 includes: a plurality of word lines WL1-WLm (m is a natural number equal to or greater than 2), a plurality of bit lines BTL1-BTLn (n is a natural number equal to or greater than 2), and a plurality of memory cells MC arranged at intersections between the word lines WL1-WLm and the bit lines BTL1-BTLn. Each memory cell MC may include a cell capacitor and a cell transistor coupled to each word line WL1-WLm and each bit line BTL1-BTLn. The cell capacitor is coupled to the cell transistor.

[0082] Figure 4 Shows Figure 2 A memory bank array and an ECC engine are shown in a semiconductor memory device.

[0083] Reference Figure 4 , the size of each page of the first memory bank array 310 is 8Kb, and the size of each subpage of the page is 128 bits. Each subpage stores an 8-bit parity bit. The 128-bit data and the corresponding 8-bit parity bit from each subpage are sequentially read and provided to the ECC engine 400.

[0084] Figure 5 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of a refresh control circuit in a semiconductor memory device.

[0085] Reference Figure 5The refresh control circuit 500 may include a refresh clock generator 510 , a refresh address counter 530 , a weak page address generator 540 , an address comparison circuit 550 , a control signal generator 570 , an address converter 580 , and a refresh address output circuit 590 .

[0086] The refresh clock generator 510 may generate a refresh clock signal RCK based on a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS. Additionally or alternatively, the first refresh control signal IREF1 may be associated with an automatic refresh mode based on a command from the memory controller 100. The second refresh control signal IREF2 may be associated with a self-refresh mode. In the automatic refresh mode, the refresh control circuit 500 may perform a normal refresh operation on a memory cell row in the memory cell array 300 in response to a refresh command from the memory controller 100. In the self-refresh mode, the refresh control circuit 500 may perform a normal refresh operation on a memory cell row in the memory cell array 300.

[0087] Additionally or alternatively, the mode signal MS may indicate whether the weak refresh operation of one or more weak pages is performed in parallel with the normal refresh operation or sequentially after the normal refresh operation. For example, when the mode signal MS has a first logic level (logic high level), the refresh control circuit 500 may perform a weak refresh operation in parallel with the normal refresh operation (parallel refresh mode). When the mode signal MS has a second logic level (logic low level), the refresh control circuit 500 may perform a weak refresh operation after completing the normal refresh operation (sequential refresh mode). The mode register 212 may provide the first refresh control signal IREF1 and the second refresh control signal IREF2 and the mode signal MS to the refresh control circuit 500.

[0088] The one or more weak pages include at least one weak cell, and a data retention time of the weak cell is shorter than a data retention time of a normal cell.

[0089] The refresh clock generator 510 may change the period of the refresh clock signal RCK in response to the first refresh control signal IREF1 and the second refresh control signal IREF2 and the mode signal MS. For example, when the first refresh control signal IREF1 specifies the auto refresh mode or the self refresh mode and the mode signal MS indicates the sequential refresh mode, the refresh clock generator 510 may reduce the period of the refresh clock signal RCK.

[0090] When the cycle of the refresh clock signal RCK decreases, the refresh interval also decreases. Therefore, the refresh control circuit 500 can sequentially perform a normal refresh operation and a weak refresh operation within a refresh period defined in the specification of the semiconductor memory device 200. For example, a weak page is refreshed at least twice during the refresh period.

[0091] The refresh address counter 530 may generate a counting address CNT_ADDR designating a corresponding memory cell row by performing a counting operation in a cycle of the refresh clock signal RCK. When the refresh address counter 530 outputs a maximum value of the counting address CNT_ADDR, the refresh address counter 530 may output a completion signal DS.

[0092] The control logic circuit 210 may provide a reset signal RST to the refresh address counter 530 during a power-up sequence. The refresh address counter 530 may be reset in response to the reset signal RST to initialize the value of the count address CNT_ADDR. The weak page address generator 540 may store a weak page address of a weak page and may output a weak page address WEAK_ADDR. The weak page address generator 540 may store an error address EADDR as a weak page address WEAK_ADDR.

[0093] When the mode signal MS has a first logic level, for example, when the mode signal MS indicates a parallel refresh mode, the address comparison circuit 550 is enabled. The address comparison circuit 550 may also compare each weak page address WEAK_ADDR1-WEAK_ADDRK (where K is a natural number greater than 1) with the counting address CNT_ADDR to provide a first match signal MATCH1 and a second match signal MATCH2. When each bit of the counting address CNT_ADDR matches each bit of one of the weak page addresses WEAK_ADDR1-WEAK_ADDRK, the first match signal MATCH1 and the second match signal MATCH2 both have a first logic level. When each bit of the counting address CNT_ADDR except at least one bit (e.g., the most significant bit (MSB)) matches each bit of one of the weak page addresses WEAK_ADDR1-WEAK_ADDRK, the first match signal MATCH1 has a second logic level, and the second match signal MATCH2 has a first logic level.

[0094] The control signal generator 570 may generate a plurality of control signals CTRL1, CTRL2, and CTRL3 based on the first match signal MATCH1, the second match signal MATCH2, the first refresh control signal IREF1, the second refresh control signal IREF2, the mode signal MS, and the completion signal DS. The control signal generator 570 may output the first control signal CTRL1 and the second control signal CTRL2 to the refresh address output circuit 590, and may output the third control signal CTRL3 to the address converter 580.

[0095] When the first refresh control signal IREF1 indicates the auto-refresh mode or the self-refresh mode and the mode signal MS indicates the parallel refresh mode of the weak refresh operation, the control signal generator 570 may output the second control signal CTRL2 and the third control signal CTRL3 having the second logic level. When the first refresh control signal IREF indicates the auto-refresh mode or the self-refresh mode and the mode signal MS indicates the sequential refresh mode of the weak refresh operation, the control signal generator 570 may output the second control signal CTRL2 having the first logic level and may output the first control signal CTRL1 having the second logic level. Then, the control signal generator 570 may output the first control signal CTRL1 transitioned to the first logic level in response to the completion signal DS transitioning to the first logic level.

[0096] When the mode signal MS indicates the parallel refresh mode, the address converter 580 is activated and can perform a do-not-care process on at least one bit of the counting address CNT_ADDR (e.g., the MSB of the counting address CNT_ADDR) in response to the third control signal CTRL3 to output the changed refresh row address CREF_ADDR. When the changed refresh row address CREF_ADDR is output as the refresh row address REF_ADDR, two memory cell rows corresponding to two page addresses with different MSBs are enabled at the same time. The two memory cell rows corresponding to the two page addresses with different MSBs belong to different memory blocks in the memory cell array 300, and they do not share a sense amplifier.

[0097] The refresh address output circuit 590 may include a first multiplexer 591 and a second multiplexer 593. The first multiplexer 591 may select one of the count address CNT_ADDR and the weak page address WEAK_ADDR (WEAK_ADDR1-WEAK_ADDRK) in response to the first control signal CTRL1. The second multiplexer 593 may select one of the changed refresh row address CREF_ADDR and the output of the first multiplexer 591 in response to the second control signal CTRL2 to output the refresh row address REF_ADDR.

[0098] Figure 6 is a diagram showing a method according to an example embodiment Figure 5 A circuit diagram of an example of a refresh clock generator in a refresh control circuit.

[0099] Reference Figure 6 , the refresh clock generator 510a may include a plurality of oscillators 521, 522, and 523, a multiplexer 524, and a decoder 525. The decoder 525 may decode the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS1. The oscillators 521, 522, and 523 generate refresh clock signals RCK1, RCK2, and RCK3 having different periods. The multiplexer 524 selects one of the refresh clock signals RCK1, RCK2, and RCK3 in response to the clock control signal RCS1 to provide the refresh clock signal RCK.

[0100] Figure 7 is a diagram showing a method according to an example embodiment Figure 5 A circuit diagram of another example of a refresh clock generator in a refresh control circuit of FIG.

[0101] Reference Figure 7 , the refresh clock generator 510b may include a decoder 526, a bias unit 527, and an oscillator 528. The decoder 526 may decode the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS2. The bias unit 527 generates a control voltage VCON in response to the clock control signal RCS2. The oscillator 528 generates a refresh clock signal RCK having a variable period according to the control voltage VCON.

[0102] Figure 8 According to an example embodiment, Figure 5 A weak address generator in the refresh control circuit of .

[0103] Reference Figure 8 , the weak address generator 540 may include a lookup table (LUT) pointer 541 and a LUT 543 .

[0104] The LUT pointer 541 generates a list pointing signal TPS indicating to increment the list address of the LUT 543 based on the first refresh control signal IREF1, the second refresh control signal IREF2 and the mode signal MS, and delays the list pointing signal TPS provided to the LUT 543 by the wait clock indicated by the wait clock information WCKI. The LUT pointer 541 provides the list pointing signal TPS to the LUT 543.

[0105] As the address increases, the LUT 543 may store the weak addresses WEAK_ADDR1-WEAK_ADDRK of the memory cell array 300 in order. Additionally or alternatively, the LUT 543 may store the error address EADDR as a part of the weak addresses WEAK_ADDR1-WEAK_ADDRK. The LUT 543 may store the wait clock information WCKI for specifying the output timing of the weak address WEAK_ADDR.

[0106] The LUT pointer 541 can delay the list pointing signal TPS provided to the LUT 543 by the wait clock indicated by the wait clock information WCKI based on the first refresh control signal IREF1, the second refresh control signal IREF2 and the mode signal MS, or output the list pointing signal TPS to the LUT 543 synchronously with the refresh clock signal RCK.

[0107] For example, when the mode signal MS indicates the parallel refresh mode, the LUT pointer 541 may delay the provision of the list pointing signal TPS to the LUT 543 by the wait clock indicated by the wait clock information WCKI. For example, when the mode signal MS indicates the sequential refresh mode, the LUT pointer 541 may provide the list pointing signal TPS to the LUT 543 in synchronization with the refresh clock signal RCK regardless of the wait clock information WCKI.

[0108] Fig. 9 According to an example embodiment, Figure 5 The address comparison circuit is shown in the refresh control circuit.

[0109] Reference Fig. 9 , the address comparison circuit 550 may include a plurality of unit comparison circuits 551 - 55K and an operation unit 560 .

[0110] Each of the unit comparison circuits 551-55K may compare each of the weak page addresses WEAK_ADDR1-WEAK_ADDRK with the counting address CNT_ADDR to provide a plurality of first match signals MATCH11-MATCH1K, and compare each reduced weak page address with the reduced counting address to provide a plurality of second match signals MATCH21-MATCH2K. Each reduced weak page address may be obtained by omitting at least one bit (e.g., MSB) of each of the weak page addresses WEAK_ADDR1-WEAK_ADDRK, and the reduced counting address may be obtained by omitting the MSB of the counting address CNT_ADDR.

[0111] The operation unit 560 provides a first match signal MATCH1 and a second match signal MATCH2 based on the first match signals MATCH11-MATCH1K and the second match signals MATCH21-MATCH2K, respectively. The operation unit 560 may include OR gates 561 and 563. The OR gate 561 performs a logic OR operation on the first match signals MATCH11-MATCH1K to provide the first match signal MATCH1, and the OR gate 563 performs a logic OR operation on the second match signals MATCH21-MATCH2K to provide the second match signal MATCH2.

[0112] Therefore, when at least one of the weak page addresses WEAK_ADDR1-WEAK_ADDRK matches the counting address CNT_ADDR, the first match signal MATCH1 is a first logic level. Additionally or optionally, when at least one of the reduced weak page addresses matches the reduced counting address, the second match signal MATCH2 is a first logic level. For example, when each bit of at least one of the weak page addresses WEAK_ADDR1-WEAK_ADDRK matches each bit of the counting address CNT_ADDR, the first match signal MATCH1 and the second match signal MATCH2 are a first logic level. When each address bit of at least one of the weak page addresses WEAK_ADDR1-WEAK_ADDRK except at least one bit (e.g., the most significant bit MSB) matches each address bit of the counting address CNT_ADDR, the first match signal MATCH1 is a second logic level and the second match signal MATCH2 is a first logic level.

[0113] Fig.10 Shows Fig. 9 One of the single-bit comparator circuits shown.

[0114] exist Fig.10 In the Fig. 9 Configuration of the first unit comparison circuit 551 among the unit comparison circuits 551-55K.

[0115] Reference Fig.10, the first unit comparison circuit 551 may include a plurality of comparators C1-CN and AND gates 5511 and 5513. The comparator C1-CN compares the bits WA11-WA1N of the first weak page address WEAK_ADDR1 with the bits CTA1-CTAN of the counting address CNT_ADDR, respectively. The AND gate 5511 performs a logic AND operation on the outputs of the comparators C1-CN-1 except the output of the comparator CN to provide a second match signal MATCH21, and the comparator CN is used to compare the MSB of the weak page address WEAK_ADDR1 with the MSB of the counting address CNT_ADDR. The AND gate 5513 performs a logic AND operation on the output of the AND gate 5511 and the output of the comparator CN to provide a first match signal MATCH11.

[0116] Therefore, when each bit WA11-WA1N of the first weak page address WEAK_ADDR1 matches the corresponding bit CTA1-CTAN of the counting address CNT_ADDR, the first match signal MATCH11 is a first logic high level. Additionally or alternatively, when each bit WA11-WA1N-1 of the first weak page address WEAK_ADDR1 except the MSB matches the corresponding bit CTA1-CTAN-1 of the counting address CNT_ADDR except the MSB, the second match signal MATCH21 is a first level. For example, when the first match signal MATCH11 is a second logic level and the second match signal MATCH21 is a first logic level, the MSB of the counting address CNT_ADDR is different from the MSB of the first weak page address WEAK_ADDR1.

[0117] Fig.11 According to an example embodiment, Figure 5 The address converter in the refresh control circuit.

[0118] Reference Fig.11 , the address converter 580 may include NAND gates 581 and 582, an inverter 583, inverters 584 and 585, and inverters 586 and 587. The NAND gate 581 performs a logic NAND operation on the MSB CTAN of the counting address CNT_ADDR and the third control signal CTRL3 to output the MSB CAN of the changed refresh row address CREF_ADDR.

[0119] Inverter 583 inverts the MSB CTAN of the counting address CNT_ADDR. NAND gate 582 performs a logic NAND operation on the output of inverter 583 and the third control signal CTRL3 to output an inverted version CANB of the MSBCAN of the changed refresh row address CREF_ADDR. Inverters 584 and 585 buffer bit CTAN-1 of the counting address CNT_ADDR to output bit CAN-1 of the changed refresh row address CREF_ADDR. Inverters 586 and 587 buffer the first bit CTA1 of the counting address CNT_ADDR to output the first bit CA1 of the changed refresh row address CREF_ADDR.

[0120] When the third control signal CTRL3 has a second logic level, the NAND gates 581 and 582 can provide complementary outputs CAN and CANB having the same logic level, regardless of the logic level of the MSB CTAN of the counting address CNT_ADDR. For example, when the MSB of the counting address CNT_ADDRCTAN is not treated as being concerned, two memory cell rows can be selected according to the bits of the changed refresh row address CREF_ADDR except the MSB of the changed refresh row address CREF_ADDR. Therefore, when the third control signal CTRL3 has a second logic level, two memory cell rows can be refreshed by one refresh row address REF_ADDR at the same time.

[0121] Fig.12 Shown in Figure 2 A normal refresh operation and a weak refresh operation are performed in parallel in a semiconductor memory device.

[0122] Reference Fig.12 , when the semiconductor memory device 200 receives the command CMD from the memory controller 100, during the refresh period tREF, a weak refresh operation for a weak page is performed in parallel with a normal refresh operation. The memory cell rows corresponding to the row addresses R1-RN are sequentially refreshed. When one or more memory cell rows corresponding to the row address R3 are refreshed, the weak page corresponding to the weak page address WP1 whose MSB is different from the row address R3 is refreshed at the same time.

[0123] Additionally or optionally, when refreshing one or more memory cell rows corresponding to a row address RQ (Q is a natural number greater than 3 and less than N), a weak page corresponding to a weak page address WPK whose MSB is different from the row address RQ is refreshed at the same time. Fig.12 In the refresh period tREF, memory cell rows corresponding to the row addresses R1-RN may be sequentially refreshed according to the first refresh interval tREFI1.

[0124] Fig.13 Shown in Figure 2A normal refresh operation and a weak refresh operation are sequentially performed in a semiconductor memory device.

[0125] Reference Fig.13 , in response to the command CMD from the memory controller 100, a weak refresh operation for a weak page is performed after a normal refresh operation. During the first sub-interval SINT1 within the refresh period tREF, the memory cell rows corresponding to the row addresses R1-RN are sequentially refreshed according to the second refresh interval tREFI2. During the second sub-interval SINT2 within the refresh period tREF, the weak pages WP1-WPK are sequentially refreshed according to the second refresh interval tREFI2. Fig.12 Compared with the situation in Fig.13 In this case, the refresh clock generator 510 may reduce the period of the refresh clock signal RCK by, for example, half.

[0126] Fig.14 shows the write operation Figure 2 A portion of a semiconductor memory device.

[0127] exist Fig.14 , a control logic circuit 210, a first memory bank array 310, an I / O gating circuit 290, and an ECC engine 400 are shown.

[0128] Reference Fig.14 , the first memory bank array 310 includes a normal cell array NCA and a redundant cell array RCA.

[0129] The normal cell array NCA includes a plurality of first storage blocks MB0-MB15 (i.e., 311-313), and the redundant cell array RCA includes at least a second storage block 314. The first storage blocks 311-313 are storage blocks that determine the storage capacity of the semiconductor memory device 200. The second storage block 314 is used for ECC and / or redundancy repair. Since the second storage block 314 used for ECC and / or redundancy repair is used for ECC, data line repair and block repair to repair the "fault" cell generated in the first storage block 311-313, the second storage block 314 is also referred to as an EDB block. In each of the first storage blocks 311-313, a plurality of first storage cells are arranged in rows and columns. In the second storage block 314, a plurality of second storage cells are arranged in rows and columns. The first storage cell connected to the intersection of the word line WL and the bit line BTL can be a dynamic storage cell. The second storage cell connected to the intersection of the word line WL and the bit line RBTL can be a dynamic storage cell.

[0130] The I / O gating circuit 290 includes a plurality of switch circuits (MUX) 291a-291d connected to the first storage block 311-313 and the second storage block 314, respectively. In the semiconductor memory device 200, bit lines corresponding to data of a burst length (BL) can be accessed simultaneously to support the BL indicating the maximum number of column positions that can be accessed. For example, the BL can be set to 8.

[0131] The ECC engine 400 may be connected to the switch circuits 291a-291d through the first data line GIO[0:127] and the second data line EDBIO[0:7]. The control logic circuit 210 may receive a command CMD and an address ADDR, and may decode the command CMD to generate a first control signal CTL1 for controlling the switch circuits 291a-291d and a second control signal CTL2 for controlling the ECC engine 400.

[0132] When the command CMD is a write command, the control logic circuit 210 provides the second control signal CTL2 to the ECC engine 400, and the ECC engine 400 performs ECC encoding on the main data MD to generate parity bits associated with the main data MD, and provides the codeword CW including the main data MD and the parity bits to the I / O strobe circuit 290. The control logic circuit 210 provides the first control signal CTL1 to the I / O strobe circuit 290 so that the codeword CW will be stored in a subpage of the target page in the first memory bank array 310.

[0133] Fig.15 shows the read operation Figure 2 semiconductor memory devices.

[0134] exist Fig.15 , the control logic circuit 210, the first memory bank array 310, the I / O gating circuit 290, the ECC engine 400, the refresh control circuit 500 and the error information register 594 are shown.

[0135] Reference Fig.15 When the command CMD is a read command for designating a read operation, the control logic circuit 210 provides the first control signal CTL1 to the I / O gating circuit 290, so that the read codeword RCW in the subpage of the target page stored in the first memory bank array 310 is provided to the ECC engine 400. Fig.15 An example of a sense amplifier is shown that is not disclosed, but the first bank sense amplifier 285 a may be coupled between the first bank array 310 and the I / O gating circuit 290 .

[0136] In a read operation, the ECC engine 400 performs ECC decoding on a read codeword RCW read from each sub-page, and the ECC engine 400 provides an error generation signal EGS to the control logic circuit 210 in response to detecting an error bit in the read codeword RCW. The control logic circuit 210 may include an error counter 214 and a register 216. The error counter 214 in the control logic circuit 210 counts the error generation signal EGS in units of pages, and compares the counted error generation signal (error occurrence count) with a threshold value stored in the register 216. If the error occurrence count of the first page is equal to or greater than the threshold value, the control logic circuit 210 may store the address of the first page in the LUT 543 in the refresh control circuit 500 as the error address EADDR.

[0137] In some example embodiments, the ECC engine 400 may correct the correctable error bits in the read codeword RCW to output the corrected main data C_MD. In some example embodiments, the ECC engine 400 may correct the correctable error bits in the read codeword RCW to write the corrected main data C_MD back to the storage location of the storage subpage.

[0138] In some example embodiments, the control logic circuit 210 may record the error information EINF in the error information register 594 based on the error generation signal EGS.

[0139] The error information EINF may include address information ADDINF, an error occurrence number ECNT, a sub-page number FCWCNT including an error bit, and flag information FG indicating whether the error information EINF is initially written in the error information register 594. The control logic circuit 210 controls the error information register 594 through the third control signal CTL3 to transmit the error information EINF of some memory cell rows or sub-pages as the error information signal EIS to the memory controller 100. The control logic circuit 210 may store the error address EADDR in the LUT 543 in the refresh control circuit 500 by referring to the error information register 594.

[0140] Fig.16 According to an example embodiment, Fig.15 An error information register in a semiconductor memory device.

[0141] Reference Fig.16 , indexes (e.g., entries) Idx1, Indx2, ..., Idxu (u is a natural number greater than 2) may each include page error information about each of some pages of the memory cell array 300. Each entry may correspond to one of the pages. The error information register 594 includes a plurality of columns 595, 596, 597, 598, and 599.

[0142] The first column 595 stores sorting information RNK that sorts the number of error occurrences based on the number of error occurrences of each of some pages. The entry of sorting information RNK with the lowest value (e.g., 1) can be considered as the highest level, and the entry of sorting information RNK with the highest value can be considered as the lowest level. For example, if the first page associated with Idx1 has 2 errors in a given period, its RNK can be filled with 2. When the second page associated with Idx2 has 4 errors in a given period, the higher RNK of the second page can be filled with 1.

[0143] The second column 596 stores address information ADDINF of each of some pages. In example embodiments, the address information ADDINF includes at least one of a bank group address ("BGA"), a bank address ("BA"), and a row address ("RA"). Figure 2 A group of memory bank arrays (e.g., 310-380) is shown, but there may be other groups of memory bank arrays. The memory bank group address may identify one of these groups. For example, if there is a first group of memory bank arrays including memory bank arrays 310-380 and a second group of memory bank arrays, and an error occurs in the first group, the BGA will identify the first group. The memory bank address may identify one of the memory banks in the identified group. The row address may identify a page of the memory bank.

[0144] The third column 597 stores the number of errors ECNT for each of the pages. Fig.16 The error information register 594 shows that the error occurrence number ECNT of the page having address A is 2, and the error occurrence number ECNT of the page having address B is 4.

[0145] The fourth column 598 stores the number of subpages FCWCNT including bit errors for each of some pages. For example, if the second page has 4 bit errors (ECNT=4), the second page has 64 subpages, but 3 of the 64 subpages have bit errors (e.g., subpages 1 and 12 each have 1 bit error, and subpage 43 has 2 bit errors), then the FCWCNT of the entry for the second page is 3.

[0146] The fifth column 599 stores flag information FG of each of some pages. The flag information FG indicates whether the error information of the corresponding page is initially written into the error information register 594. When the error information of the corresponding page is initially written into the error information register 594, the flag information FG has a first logic level (e.g., 0). In an embodiment, if the flag information FG of a page has a second logic level (e.g., 1), the page previously had error information.

[0147] The memory controller 100 may determine an error handling strategy for a memory cell row or sub-page having an uncorrectable error based on the error information EINF in the error information register 594 .

[0148] Fig.17 is a diagram showing a method according to an example embodiment Figure 2 A block diagram of an example of an ECC engine in a semiconductor memory device.

[0149] Reference Fig.17 , the ECC engine 400 includes an ECC encoder 410 and an ECC decoder 430 .

[0150] The ECC encoder 410 may generate a parity bit PRT associated with write data WMD to be stored in a normal cell array NCA of the first memory bank array 310. The parity bit PRT may be stored in a redundant cell array RCA of the first memory bank array 310.

[0151] The ECC decoder 430 may perform ECC decoding on the read data RMD based on the read data RMD and the parity bits PRT read from the first memory bank array 310. When the read data RMD includes at least one error bit based on the result of the ECC decoding, the ECC decoder 430 provides an error generation signal EGS to the control logic circuit 210, and corrects the error bit in the read data RMD to output corrected main data C_MD.

[0152] Fig.18 According to an example embodiment, Fig.17 Example of an ECC decoder in an ECC engine.

[0153] Reference Fig.18 , the ECC decoder 430 may include a syndrome generation circuit 440 , an error locator 460 , and a data corrector 470 . The syndrome generation circuit 440 may include a check bit generator 441 and a syndrome generator 443 .

[0154] The parity bit generator 441 generates a parity bit CHB by performing an XOR array operation based on the read data RMD, and the syndrome generator 443 generates a syndrome SDR by comparing the parity bit PRT with corresponding bits of the parity bit CHB.

[0155] When the bit of the syndrome SDR is not "0", the error locator 460 generates an error position signal EPS indicating the position of the error bit in the read data RMD by decoding the syndrome SDR to provide the error position signal EPS to the data corrector 470. Additionally or alternatively, when the read data RMD includes an error bit, the error locator 460 provides an error generation signal EGS to the control logic circuit 210.

[0156] The data corrector 470 receives the read data RMD, corrects the error bits in the read data RMD based on the error position signal EPS when the read data RMD includes error bits, and outputs corrected main data C_MD.

[0157] Fig.19 is a flowchart illustrating a method of operating a semiconductor memory device according to example embodiments.

[0158] Reference Figures 2 to 19 , a method of operating a semiconductor memory device 200 is provided, the semiconductor memory device 200 including a memory cell array 300 having a plurality of memory cell rows, and each memory cell row including a plurality of volatile memory cells.

[0159] In the method, the ECC engine 400 performs ECC decoding on a subpage in at least one first memory cell row in the memory cell rows during a read operation (S110). When an error bit is detected due to the ECC decoding, the ECC engine 400 provides an error generation signal EGS to the control logic circuit 210, and the control logic circuit 210 counts the error occurrence of the at least one first memory cell row (S120).

[0160] The control logic circuit 210 compares the error occurrence count of the first memory cell row with a threshold value to provide the first address of the first memory cell row as an error address to the refresh control circuit 500 in response to the error occurrence count being equal to or greater than the threshold value (S130). The refresh control circuit 500 increases the number of refresh operations performed on the first memory cell row during the refresh period (S140).

[0161] According to example embodiments, a method of operating a memory device includes: performing an error correction code (ECC) operation on a portion of memory cells in the memory device; based on the ECC operation, modifying a mode of a refresh operation of the portion of memory cells; based on the modified mode of the refresh operation, performing a refresh operation on the portion of memory cells. In some cases, the method includes: identifying an error count based on the ECC operation; determining that the error count is equal to or greater than a threshold; and increasing the number of refresh operations on the portion of memory cells, wherein modifying the mode of the refresh operation is based on the increased number of refresh operations.

[0162] Fig. 20 is a block diagram illustrating a semiconductor memory device according to example embodiments.

[0163] Reference Fig. 20 , a semiconductor memory device 600 may include a first group of buffer dies 610 and a second group of memory dies 620 that provide soft error analysis and correction functions in a stacked chip structure.

[0164] The first group of dies 610 may include at least one buffer or logic die 611. The second group of dies 620 may include a plurality of memory dies 620-1 to 620-p stacked on the buffer die 611 and transmitting data through a plurality of through-substrate via lines (e.g., through-silicon via (TSV) lines). The memory dies 620-1 to 620-p may each include a cell core 622, which includes a memory cell array having a plurality of memory cell rows. Each memory cell row includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines. Additionally or alternatively, each memory die 620-1 to 620-p may include a refresh control circuit (RCC) 624 that performs refresh operations on the plurality of memory cell rows. Additionally or alternatively, the memory dies 620-1 to 620-p may each include an ECC engine, such as Fig.17 ECC engine 400.

[0165] The buffer die 611 may include an ECC engine 612 that corrects a transmission error using a transmission parity bit and generates error-corrected data when a transmission error is detected from transmission data received through the TSV line, and an error counter 614 that counts the number of error occurrences.

[0166] The refresh control circuit 624 can be used Figure 5 Therefore, the semiconductor memory device 600 can increase the number of refresh operations performed on at least one memory cell row where an error occurs.

[0167] The semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines. The TSV lines may also be referred to as “through electrodes”.

[0168] A transmission error occurring at the transmission data may be caused by noise occurring at the TSV line. Because a data failure due to noise occurring at the TSV line can be distinguished from a data failure due to an erroneous operation of the memory die, the data failure may be considered a soft data failure (or soft error). A soft data failure may be caused by a transmission failure on the transmission path, and the soft data failure may be detected and corrected by an ECC operation.

[0169] For example, when the transmission data is 128-bit data, the transmission parity bit can be set to 8 bits. However, the scope and spirit of the inventive concept are not limited thereto. The number of transmission parity bits increases or decreases.

[0170] Through the above description, the data TSV line group 632 formed at one memory die 620-p may include 128 TSV lines L1 to Lp, and the parity bit TSV line group 634 may include 8 TSV lines L10 to Lq. The TSV lines L1 to Lp in the data TSV line group 632 and the parity bit TSV lines L10 to Lq in the parity bit TSV line group 634 may be connected to the micro bumps MCB formed correspondingly between the memory dies 620-1 to 620-p.

[0171] At least one of the memory dies 620 - 1 to 620 - p may include a DRAM cell, each DRAM cell including at least one access transistor and one storage capacitor.

[0172] The semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with an external device through a data bus B10. The buffer die 610 may be connected to the memory controller 100 through the data bus B10.

[0173] Fig.21 According to an exemplary embodiment, Fig. 20 A cross-sectional view of a 3D chip structure of a semiconductor memory device.

[0174] Fig.21 A 3D chip structure 700 is shown in which the host and HBM are directly connected without an intervening layer.

[0175] Reference Fig.21 , a host die 710 such as a system on chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU) may be disposed on a printed circuit board (PCB) 720 using flip chip bumps FB. The memory dies D11 to D14 may be stacked on the host die 710 to implement the HBM 620 as Fig. 20 The memory die in the .

[0176] exist Fig.21 In, omitted Fig. 20 The buffer die 610 or logic die in the host die 710. However, the buffer die 610 or logic chip can be set between the memory chip D11 and the host die 710. In order to realize the HBM (620) structure, TSV lines can be formed at the memory chips D11 and D14. The TSV lines can be electrically connected to the micro bumps MCB placed between the memory dies.

[0177] Fig. 22 is a diagram illustrating a semiconductor package including a stacked memory device according to example embodiments.

[0178] Reference Fig. 22 , the semiconductor package 900 may include one or more stacked memory devices 910 and a memory controller (CONT) 920 .

[0179] The stacked memory device 910 and the memory controller 920 may be mounted on the interposer 930, and the interposer on which the stacked memory device 910 and the memory controller 920 are mounted may be mounted on the package substrate 940. The memory controller 920 may be mounted on the interposer 930. Figure 1 The storage controller 100 in FIG.

[0180] Each stacked memory device 910 can be implemented in various forms, and can be a memory device in the form of a high bandwidth memory (HBM) in which multiple layers are stacked. Therefore, each stacked memory device 910 may include a buffer die and multiple memory dies. The buffer die may include an ECC engine and an error information register, and each memory die may include a memory cell array and a refresh control circuit. Therefore, each stacked memory device 910 can increase the number of refresh operations performed on some memory cell rows whose error occurrence count is equal to or greater than a threshold value during the refresh period.

[0181] A plurality of stacked memory devices 910 may be mounted on the interposer 930 , and the memory controller 920 may communicate with the plurality of stacked memory devices 910 .

[0182] For example, each of the stacked memory device 910 and the memory controller 920 may include a physical region, and communication may be performed between the stacked memory device 910 and the memory controller 920 through the physical region. Meanwhile, when each stacked memory device 910 includes a direct access region, a test signal may be provided to each stacked memory device 910 through a conductive device (e.g., solder ball 950) mounted under the package substrate 940 and the direct access region.

[0183] Aspects of the inventive concept may be applied to a system using a semiconductor memory device employing a volatile memory cell, an ECC engine, and a refresh control circuit.

[0184] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept as defined in the appended claims.

Claims

1. A semiconductor memory device, comprising: A memory cell array, the memory cell array comprising a plurality of memory cell rows, each of the plurality of memory cell rows comprising a plurality of volatile memory cells; Error correction code engine; a refresh control circuit configured to perform a refresh operation on the plurality of memory cell rows; as well as a control logic circuit configured to control the ECC engine based on commands and addresses from an external memory controller, wherein the control logic circuit is further configured to control the error correction code engine so that the error correction code engine generates an error generation signal by performing an error correction code decoding operation on a subpage in at least one first memory cell row in the memory cell rows during a read operation, wherein the control logic circuit is further configured to compare an error occurrence count of the first memory cell row with a threshold value, and provide a first address of the first memory cell row as an error address to the refresh control circuit based on the comparison, wherein the error occurrence count is generated based on the error generation signal, and The refresh control circuit is further configured to increase the number of refresh operations performed in the first memory cell row during a refresh period based on the error occurrence count.

2. The semiconductor memory device according to claim 1, in, The control logic circuit is also configured to control the error correction code engine so that the error correction code engine performs the error correction code decoding by: reading data corresponding to a codeword from each of the sub-pages, detecting and correcting at least one error bit in the codeword, and outputting the corrected codeword.

3. The semiconductor memory device according to claim 1, wherein: The control logic circuit is further configured to provide the first address as the error address to the refresh control circuit in response to the error occurrence count associated with the subpage of the first memory cell row being equal to or greater than the threshold.

4. The semiconductor memory device according to claim 1, wherein: The refresh control circuit is also configured to: when a normal refresh operation is performed on the memory cell row in response to the command during the refresh period, perform a weak refresh operation on one or more weak pages in parallel with the normal refresh operation on the memory cell row during the refresh period, and the one or more weak pages include the first memory cell row.

5. The semiconductor memory device according to claim 4, wherein: The refresh control circuit is also configured to perform the normal refresh operation on the memory cell row during the refresh period, and when the refresh control circuit refreshes a second memory cell row among the memory cell rows, the corresponding weak page is refreshed at the same time, and the second memory cell row has a first page address, and the first page address is equal to a weak page address in a weak page address set of the one or more weak pages, except that the first page address has at least one bit different from the weak page address.

6. The semiconductor memory device according to claim 1, wherein The refresh control circuit is further configured to perform a normal refresh operation on the memory cell row during the refresh period, and after completing the normal refresh operation on the memory cell row, perform a weak refresh operation on one or more weak pages including the first memory cell row.

7. The semiconductor memory device according to claim 6, wherein: The refresh control circuit is also configured to: reduce a refresh interval of the semiconductor memory device; perform the normal refresh operation during a first sub-interval of the refresh period; and perform the weak refresh operation during a second sub-interval of the refresh period, the second sub-interval being after the first sub-interval.

8. The semiconductor memory device according to claim 1, wherein: The refresh control circuit comprises: a refresh clock generator configured to generate a refresh clock signal based on the first refresh control signal, the second refresh control signal, and the mode signal; a refresh counter configured to generate a count address for sequentially refreshing the memory cell row in response to the refresh clock signal and output a completion signal when a maximum count address is generated; a weak page address generator, the weak page address generator being configured to store weak page addresses of one or more weak pages in the plurality of memory cell rows and to store the error address as one of the weak page addresses, the weak page address generator being further configured to output the weak page address in response to the refresh clock signal, the one or more weak pages each including at least one weak cell, the data retention time of the weak cell being shorter than the data retention time of a normal cell; an address comparison circuit configured to compare the count address with each of the weak page addresses to output a first match signal and a second match signal; a control signal generator configured to generate a plurality of control signals based on the first refresh control signal, the second refresh control signal, the mode signal, the completion signal, the first match signal, and the second match signal; an address converter configured to generate a changed refresh row address by performing a don't care process on at least one bit of the count address in response to a third control signal among the plurality of control signals; and A refresh address output circuit is configured to output one of the count address, the weak page address and the changed refresh row address as a refresh row address according to a refresh mode based on a first control signal and a second control signal among the plurality of control signals.

9. The semiconductor memory device according to claim 8, wherein: The refresh address output circuit comprises: a first multiplexer configured to select one of the counting address and the weak page address in response to the first control signal; and A second multiplexer configured to select one of the changed refresh row address and the output of the first multiplexer in response to the second control signal to output the refresh row address.

10. The semiconductor memory device according to claim 8, wherein: The control signal generator is further configured to: outputting the second control signal and the third control signal having a second logic level when the first refresh control signal indicates one of an auto refresh operation and a self refresh operation on the memory cell row and the mode signal indicates a parallel mode of a weak refresh operation on the one or more weak pages; or When the first refresh control signal indicates one of the automatic refresh operation and the self-refresh operation on the memory cell row, and the mode signal indicates a sequential mode of weak refresh operations on the one or more weak pages, the second control signal and the first control signal having a first logic level and a second logic level, respectively, are output, and the first control signal is changed to the first logic level in response to the completion signal being changed to the first logic level.

11. The semiconductor memory device according to claim 8, wherein: The control signal generator is configured to output the first control signal and the second control signal having a first logic level when the second refresh control signal indicates a weak refresh operation on the one or more weak pages.

12. The semiconductor memory device according to claim 1, wherein: The error correction code engine comprises: an error correction code encoder configured to perform error correction code encoding on data to be stored in the memory cell array to generate parity bits; and An error correction code decoder is configured to read data corresponding to a code word and the parity bit from each of the sub-pages and perform the error correction code decoding operation on the data based on the parity bit.

13. The semiconductor memory device according to claim 12, wherein: The error correction code decoder comprises: a syndrome generation circuit configured to generate a syndrome based on the data and the parity bit; an error locator configured to generate the error generation signal and an error location signal indicating a location of at least one erroneous bit in the data based on the syndrome; and A data corrector is configured to receive the data, correct the at least one error bit based on the error location signal, and output corrected data.

14. The semiconductor memory device according to claim 1, further comprising: Error message register, wherein the control logic circuit is further configured to record error information in the error information register during the read operation, and provide the error information to the refresh control circuit by referring to the error information register, and The error information at least includes the number of errors occurring in the plurality of storage unit rows.

15. The semiconductor memory device according to claim 14, wherein: The control logic circuit is further configured to transmit the error information of the memory cell row recorded in the error information register to the memory controller as an error information signal.

16. The semiconductor memory device according to claim 1, further comprising: at least one buffer die; as well as a plurality of memory dies stacked on the at least one buffer die and configured to transmit data through a plurality of through-silicon via routes, wherein the plurality of memory dies each include the refresh control circuit and a memory core including the memory cell array, and Wherein, the at least one buffer die comprises the error correction code engine.

17. The semiconductor memory device according to claim 16, wherein: The at least one buffer die is configured to communicate with the memory controller.

18. A semiconductor memory device, comprising: A memory cell array, the memory cell array comprising a plurality of memory cell rows, each of the plurality of memory cell rows comprising a plurality of volatile memory cells; Error correction code engine; a refresh control circuit configured to perform a refresh operation on the plurality of memory cell rows; Error message register; as well as a control logic circuit configured to control the ECC engine based on commands and addresses from an external memory controller, wherein the control logic circuit is further configured to control the error correction code engine so that the error correction code engine generates an error generation signal by performing an error correction code decoding operation on a subpage in at least one first memory cell row in the memory cell rows during a read operation, The control logic circuit is further configured to: compare an error occurrence count of the first memory cell row with a threshold value, and based on the comparison, provide a first address of the first memory cell row as an error address to the refresh control circuit, wherein the error occurrence count is generated based on the error generation signal; or, during the read operation, record error information in the error information register, and provide the error address to the refresh control circuit by referring to the error information register, The error information at least includes the number of errors occurring in the first storage unit row and the second storage unit row, and The refresh control circuit is further configured to increase the number of refresh operations performed in the first memory cell row during a refresh period.

19. The semiconductor memory device according to claim 18, wherein: The refresh control circuit is further configured to perform a normal refresh operation on the memory cell row during the refresh period, and after completing the normal refresh operation on the memory cell row, perform a weak refresh operation on one or more weak pages including the first memory cell row, and In which, the refresh control circuit is also configured to reduce the refresh interval of the semiconductor memory device, and perform the normal refresh operation during the first sub-interval of the refresh period, and is configured to perform the weak refresh operation during the second sub-interval of the refresh period, and the second sub-interval is after the first sub-interval.

20. A method of operating a semiconductor memory device comprising a memory cell array, wherein: The memory cell array includes a plurality of memory cell rows, and each of the plurality of memory cell rows includes a plurality of volatile memory cells. The method includes: performing, by an error correction code engine during a read operation, an error correction code decoding operation on a subpage in at least one first memory cell row in the memory cell rows; counting, by the control logic circuit, the occurrence of errors of the at least one first memory cell row based on the result of the error correction code decoding operation; comparing, by the control logic circuit, an error occurrence count of the first memory cell row with a threshold value, and providing a first address of the first memory cell row as an error address to a refresh control circuit in response to the error occurrence count being equal to or greater than the threshold value; and The refresh control circuit increases the number of refresh operations performed on the first memory cell row during a refresh period.

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