Storage device and method of manufacturing the same

Abstract

The present invention discloses a storage device and a manufacturing method thereof. The storage device comprises a drain columnar structure, a source columnar structure, a charge capture structure, a vertical channel structure and a gate structure. The drain columnar structure is formed in a first opening. The source columnar structure is formed in a second opening. The vertical channel structure and the charge capture structure are formed in a hole, and the hole partially overlaps the first opening and the second opening. The vertical channel structure is divided into two arc-shaped channel parts by the drain columnar structure and the source columnar structure. The gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

Description

Technical Field

[0001] The present invention relates to a storage device and a manufacturing method thereof, and more particularly to a storage device with a vertical channel and a manufacturing method thereof. Background Art

[0002] In modern computer systems, dynamic random access memory (DRAM) type storage devices and NAND flash type storage devices have been widely used to store data. Generally speaking, the advantages of DRAM type storage devices are low latency and high access speed, but the memory capacity of DRAM type storage devices is limited, and the cost per bit is high. In contrast, the advantages of NAND flash type storage devices are high storage density and low cost per bit, but NAND flash type storage devices have high latency and low access speed. Due to the huge gap in access speed between DRAM type storage devices and NAND flash type storage devices, a bottleneck occurs in the data transmission process, which in turn causes a decrease in the data processing speed of the computer system. Although NOR flash type storage devices have long appeared on the market, compared with NAND flash type storage devices, NOR flash type storage devices have higher access speed and lower latency, but the storage density of existing NOR flash type storage devices is limited and cannot meet the storage needs of large capacity.

[0003] In recent years, a new memory technology, storage-class memory (SCM), has been proposed. In the storage architecture of computer systems, storage-class memory is considered to be between DRAM-type storage devices and NAND flash-type storage devices, and can fill the access speed gap between DRAM-type storage devices and NAND flash-type storage devices. Storage-class memory has developed into many types, such as 3D XPoint memory, magnetoresistive random access memory (MRAM) and phase change memory (PCM). However, these types of storage-class memory still cannot meet all the market demands for storage-class memory.

[0004] Therefore, there is a need to provide a three-dimensional memory technology with high storage density, high access speed and low latency. Summary of the invention

[0005] The present invention relates to a memory device and a method for manufacturing the same. According to an embodiment, the manufacturing method can provide a memory device, the memory device comprising a drain columnar structure, a source columnar structure and two arc-shaped channel components, thereby improving the storage density and operation speed of the memory device.

[0006] According to one embodiment of the present invention, a method for manufacturing a storage device is provided. The method for manufacturing a storage device comprises the following steps. A hole is formed in an oxide-nitride stack. A vertical channel structure and a charge capture structure are formed on the inner wall of the hole. A first opening and a second opening are formed, the first opening and the second opening partially overlap the hole, and the first opening and the second opening pass through the vertical channel structure. The vertical channel structure is separated into two arc-shaped channel parts by the first opening and the second opening. A drain columnar structure and a source columnar structure are formed in the first opening and the second opening, respectively. A gate structure is formed, and the gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

[0007] According to one embodiment of the present invention, a storage device is provided. The storage device includes a drain columnar structure, a source columnar structure, a charge capture structure, a vertical channel structure and a gate structure. The drain columnar structure is formed in a first opening. The source columnar structure is formed in a second opening. The vertical channel structure and the charge capture structure are formed in a hole, and the hole partially overlaps the first opening and the second opening. The vertical channel structure is divided into two arc-shaped channel parts by the drain columnar structure and the source columnar structure. The gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

[0008] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A-Figure 14B FIG. 2 illustrates a method for manufacturing a memory device according to an embodiment of the present invention.

[0010]

Explanation of symbols

[0011] 101: Substrate

[0012] 102: Bottom oxide layer

[0013] 103: Nitride layer

[0014] 103g: Gate material

[0015] 103x: Hollow

[0016] 104: Oxide layer

[0017] 105: Charge trapping structure

[0018] 106: Vertical channel structure

[0019] 107: Dielectric Materials

[0020] 108: High dielectric constant material layer

[0021] 109: Low temperature oxide layer

[0022] 110: Holes

[0023] 115: Channel

[0024] 116: Conductive film

[0025] 120: External circuit

[0026] 510, 512, 514, 516: First opening

[0027] 511, 513, 515, 517: Second opening

[0028] 601: Drain columnar structure

[0029] 601s: Dielectric Department

[0030] 602: Source columnar structure

[0031] 710, 712: Slit

[0032] 710r, 712r: Alcove

[0033] C1: Center point

[0034] D1: First direction

[0035] D2: Second direction

[0036] D3: Third direction

[0037] P5-P14: Line

[0038] R1, R2, R3: Distance DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040] In an embodiment of the present invention, a storage device and a method for manufacturing the storage device are provided. According to the embodiment of the manufacturing method, a storage device can be obtained, for example, a storage device including a drain columnar structure, a source columnar structure and two arc-shaped channel components, the two arc-shaped channel components are separated by the drain columnar structure and the source columnar structure, thereby filling the access speed gap between a DRAM type storage device and a NAND flash type storage device, and optimizing the storage density and operation speed of the storage device at the same time.

[0041] In practical applications, the embodiments of the present invention can be implemented as a variety of different storage devices. For example, the embodiments can be applied to three-dimensional vertical channel type storage devices, but the present invention is not limited to this application. The following is a related embodiment, with accompanying drawings to describe in detail the storage device and its manufacturing method proposed by the present invention. However, the present invention is not limited to this. The description in the embodiments, such as the local structure, the steps of the manufacturing method and the application of materials, etc., is only for illustrative purposes, and the scope of protection of the present invention is not limited to the embodiments.

[0042] At the same time, it should be noted that the present invention does not show all possible embodiments. Those skilled in the art may change and modify the structure and manufacturing method of the embodiment to meet the needs of practical applications without departing from the spirit and scope of the present invention. Therefore, other embodiments not proposed in the present invention may also be applicable. Furthermore, the drawings are simplified to facilitate the clear description of the contents of the embodiments, and the dimensional ratios on the drawings are not drawn in proportion to the actual products. Therefore, the description and drawings are only used to describe the embodiments, and are not used to limit the scope of protection of the present invention.

[0043] Furthermore, the ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", "third", etc., are used to modify the elements of the claims. They themselves do not mean or represent any previous ordinal numbers of the claimed elements, nor do they represent the order of one claimed element and another claimed element, or the order of manufacturing methods. The use of these ordinal numbers is only used to clearly distinguish a claimed element with a certain name from another claimed element with the same name.

[0044] Figure 1A-Figure 14B A method for manufacturing a memory device according to an embodiment of the present invention is illustrated. Figure 1A is a top view of an exemplary structure at this stage of processing, and Figure 1B Figure 1 is a cross-sectional view of an exemplary structure at this processing stage. Figure 1A-1BAs shown, a bottom oxide layer 102 is formed on a substrate 101, and an oxide-nitride stack is formed on the bottom oxide layer 102. The oxide-nitride stack includes a plurality of nitride layers 103 and a plurality of oxide layers 104, and the plurality of nitride layers 103 and the plurality of oxide layers 104 are alternately stacked along a third direction D3 (e.g., Z direction) perpendicular to the substrate 101. In one example, the plurality of nitride layers 103 may include silicon nitride (SiN). In one example, the oxide-nitride stack may include only a nitride layer 103 and an oxide layer 104 formed on the nitride layer 103.

[0045] Then, as Figure 2A-2B As shown, Figure 2A is a top view of an exemplary structure at this stage of processing, and Figure 2B 1 is a cross-sectional view of an exemplary structure at this processing stage. In this processing stage, the oxide-nitride stack is patterned to form a plurality of holes 110, for example, by patterning the oxide-nitride stack through a photolithography process. The hole 110 may have a cylindrical or conical shape, but the present invention is not limited thereto. The hole 110 exposes the sidewall of the oxide-nitride stack. In one example, the etching process of the hole 110 may stop at the bottom oxide layer 102, that is, the hole 110 extends downward in the third direction D3 to penetrate the oxide-nitride stack and the bottom oxide layer 102 to expose the bottom oxide layer 102. Next, the charge trapping structure 105 is formed on the oxide-nitride stack and lined in the hole 110. In the hole 110, the charge trapping structure 105 is formed on the inner wall and the bottom of the hole 110. The charge trapping structure 105 may be formed by a deposition process, such as a chemical vapor deposition (CVD) process. In one example, the charge trapping structure 105 is formed in a furnace. Next, the vertical channel structure 106 is formed on the charge trapping structure 105 and exposes the charge trapping structure 105 at the bottom of the hole 110.

[0046] The charge trapping structure 105 described above may include a multilayer structure, such as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap engineered silicon-oxide-nitride-oxide-silicon), TANOS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon) known in memory technology, or other types of charge trapping layers, or combinations of these layers. In one example, the vertical channel structure 106 may include polysilicon.

[0047] Then, as Figure 3A-3B As shown, Figure 3A is a top view of an exemplary structure at this stage of processing, and Figure 3B An exemplary cross-sectional view of the structure at this stage of processing is shown. A dielectric material 107 is formed on the vertical channel structure 106 and fills the hole 110. The dielectric material 107 may include an oxide.

[0048] Figure 4A is a top view of an exemplary structure at this stage of processing, and Figure 4B An exemplary structural cross-sectional view of this processing stage is depicted. In this processing stage, the charge trapping structure 105, the vertical channel structure 106, and the dielectric material 107 above the oxide-nitride stack are removed to expose the top of the oxide-nitride stack and form a flat top surface of the structure in a first direction D1 (e.g., X direction). In one example, a planarization process may be applied to the structure, and the planarization process stops at the vertical channel structure 106 on the oxide-nitride stack. The planarization process may be a chemical-mechanical planarization (CMP) process. Next, an etching process is applied to the structure, and the etching process stops at the top of the oxide-nitride stack. In one example, as Figure 4B As shown, the charge trapping structure 105 has a hollow columnar shape with one end closed, while the vertical channel structure 106 has a hollow columnar shape with both ends open.

[0049] Figure 5A Department for Figure 4A-4B An exemplary top view of the structure after the processing stage is shown, and Figure 5B Along the Figure 5A 10 is an exemplary structural cross-sectional view shown along line P5 of FIG. The first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 are formed to partially overlap with the hole 110. The first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 may be formed by a dry etching process, but the present invention is not limited thereto. The first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 extend downward in the third direction D3 to penetrate the oxide-nitride stack, the charge trapping structure 105, the vertical channel structure 106 and the dielectric material 107. In an example, in the third direction D3, the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 stop at the bottom oxide layer 102. In one example, in the third direction D3, the depths of the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 are greater than the depth of the hole 110 in the third direction D3. In one example, the first openings 510, 512, 514, and 516 and the second openings 511, 513, 515, and 517 may have a cylindrical or conical shape, but the present invention is not limited thereto.

[0050] The first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 are formed on both sides of the hole 110. In one example, the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 are formed on opposite sides of the hole 110.

[0051] After the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 are formed, the vertical channel structure 106 in the hole 110 is divided into two arc-shaped channel components by the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517. In one example, the arc-shaped channel components are respectively disposed on the inner walls of the opposite sides of the hole 110. In addition, the charge capture structure 105 is divided into two arc-shaped charge capture components by the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517.

[0052] Fig. 6A Department for Figure 5A-Figure 5B An exemplary top view of the structure after the processing stage is shown, and Figure 6B Along the Fig. 6A 6. The exemplary structure cross-section diagram is shown along line P6 of FIG. 6. In this processing stage, the drain columnar structure 601 and the source columnar structure 602 are formed in the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517, respectively. Specifically, the conductive material is deposited in the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517, and then a planarization process is applied to the top surface of the structure to form the drain columnar structure 601 and the source columnar structure 602. The drain columnar structure 601 and the source columnar structure 602 directly contact the charge trapping structure 105 and the vertical channel structure 106. The charge trapping structure 105 in the hole 110 is separated into two arc-shaped charge trapping components by the drain columnar structure 601 and the source columnar structure 602. The vertical channel structure 106 in the hole 110 is divided into two arc-shaped channel components by the drain columnar structure 601 and the source columnar structure 602. Two ends of the arc-shaped channel component are connected to the drain columnar structure 601 and the source columnar structure 602 respectively.

[0053] In one example, the conductive material may include N+ polysilicon. In one example, the planarization process may be a chemical mechanical planarization process. In one example, when the first openings 510, 512, 514 and 516 and the second openings 511, 513, 515 and 517 partially overlap the hole 110, the drain columnar structure 601 and the source columnar structure 602 are partially located in the hole 110 and partially located outside the hole 110. In one example, the drain columnar structure 601 and the source columnar structure 602 are both partially located in the hole 110 and partially located outside the hole 110. In one example, one of the drain columnar structure 601 and the source columnar structure 602 is partially located in the hole 110 and partially located outside the hole 110, and the other of the drain columnar structure 601 and the source columnar structure 602 is completely disposed in the hole 110. On a plane including the first direction D1 and the second direction D2 (ie, on the D1 - D2 plane), the cross-sectional area of ​​the drain columnar structure 601 and the source columnar structure 602 may be smaller than the cross-sectional area of ​​the hole 110 on the D1 - D2 plane, but the invention is not limited thereto.

[0054] as Fig. 6AAs shown, on the D1-D2 plane, the hole 110 has a center point C1, and the distance between the edge of the hole 110 and the center point C1 is defined as the distance R1 (i.e., the radius of the hole 110). The maximum distance between the edge of the drain columnar structure 601 and the center point C1 is defined as the distance R2. The maximum distance between the edge of the source columnar structure 602 and the center point C1 is defined as the distance R3. The distance R2 and the distance R3 are greater than the distance R1. In one example, the distance R2 and the distance R3 are both greater than the distance R1.

[0055] In one example, on the D1-D2 plane, at least one of the drain columnar structure 601 and the source columnar structure 602 may intersect with the edge of the hole 110 to generate more than two different intersections. For example, on the D1-D2 plane, the edge of the drain columnar structure 601 intersects with the edge of the hole 110 to generate two different intersections. For example, on the D1-D2 plane, the edge of the source columnar structure 602 intersects with the edge of the hole 110 to generate two different intersections. For example, on the D1-D2 plane, the edge of the drain columnar structure 601 and the edge of the source columnar structure 602 intersect with the edge of the hole 110 at two different intersections, respectively, to generate four different intersections.

[0056] Fig. 7A Department for Figure 6A-6B An exemplary top view of the structure after the processing stage is shown, and Figure 7B Along the Fig. 7A 7 is an exemplary structural cross-sectional view of line P7 of FIG. In this processing stage, the oxide-nitride stack is patterned to form slits 710 and 712 and stop at the bottom oxide layer 102, for example, by patterning the oxide-nitride stack through a photolithography process. The slits 710 and 712 extend downward in a third direction D3 to penetrate the oxide-nitride stack and the bottom oxide layer 102 to expose the bottom oxide layer 102.

[0057] Fig. 8A Department for Figure 7A-7B An exemplary top view of the structure after the processing stage is shown, and Figure 8B Along the Fig. 8A The exemplary structural cross-sectional view shown by line P8 is shown in FIG. Figure 8A-8B As shown, the plurality of nitride layers 103 in the oxide-nitride stack are removed through the slits 710 and 712 to form a cavity 103x, which is where the plurality of nitride layers 103 were originally formed. The plurality of nitride layers 103 can be removed by etching. The cavity 103x exposes part of the sidewalls of the drain columnar structure 601, the source columnar structure 602, and the charge trapping layer 105, which are the places that originally contacted the plurality of nitride layers 103.

[0058] Fig.9A Department for Figure 8A-8B An exemplary top view of the structure after the processing stage is shown, and Fig. 9B Along the Fig.9A The exemplary structural cross-sectional view shown by line P9 is shown in FIG. Figure 9A-9B As shown, a plurality of dielectric portions 601s are disposed on the sidewalls of the drain columnar structure 601 and the source columnar structure 602 exposed by the cavity 103x. In one example, the dielectric portion 601s may be formed by applying an oxidation treatment to the sidewalls of the drain columnar structure 601 and the source columnar structure 602 exposed by the cavity 103x. In one example, the dielectric portion 601s may include polysilicon oxide. The width of the dielectric portion 601s in the second direction D2 is approximately 200 angstroms; ), preferably greater than 200 angstroms, but the present invention is not limited to this value. The dielectric portion 601s can avoid or improve the short-circuit problem caused by the contact between the word line and the drain columnar structure 601 or the contact between the word line and the source columnar structure 602.

[0059] Fig. 10A Department for Figure 9A-9B An exemplary top view of the structure after the processing stage is shown, and Fig. 10B Along the Fig. 10A 1 is an exemplary structural cross-sectional view shown along line P10 of . In this processing stage, a high dielectric constant (high-k) material layer 108 is formed on the sidewalls and bottom of the slits 710 and 712, on the walls of the plurality of oxide layers 104 exposed by the voids 103x, on the sidewalls of the charge trapping structure 105 exposed by the voids 103x, and on the sidewalls of the dielectric portion 601s exposed. In other words, the high dielectric constant material layer 108 is formed in a lined manner in the slits 710 and 712 and the voids 103x. The high dielectric constant material layer 108 may include a high dielectric constant material, such as aluminum oxide (Al2O3), hafnium dioxide (HfO2), silicon nitride (Si3N4), zirconium dioxide (ZrO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5), lanthanum oxide (La2O) or other suitable materials. The high dielectric constant material layer 108 may be formed by a deposition process or a wet etching process using a phosphoric acid (H 3 PO 4 ) solution.

[0060] Fig.11A Department for Figure 10A-10B An exemplary top view of the structure after the processing stage is shown, and Fig. 11B Along the Fig.11A1 and 10. In this process stage, the gate material 103g is formed in the remaining space between the void 103x and the slits 710 and 712. In one example, the gate material 103g is deposited in the remaining space between the void 103x and the slits 710 and 712. The gate material 103g may include a metal, such as titanium nitride (TiN), tantalum nitride (TaN), etc.

[0061] Fig. 12A Department for Figure 11A-11B An exemplary top view of the structure after the processing stage is shown, and Fig. 12B Along the Fig. 12A Next, an etching back process is applied to the structure to remove a portion of the gate material 103g through the slits 710 and 712, thereby forming a plurality of recesses 710r and 712r, as shown in FIG. Fig. 12B As shown. In one example, each of the plurality of recesses 710r and 712r is a lateral recess extending from the slits 710 and 712 (along the second direction D2) into the gate material 103g. Therefore, each of the recesses 710r is connected to the slit 710, and each of the recesses 712r is connected to the slit 712. Each of the recesses 710r can be defined as a space formed by two adjacent oxide layers 104, the gate material 103g between the two adjacent oxide layers 104, and the slit 710. Each of the recesses 712r can be defined as a space formed by two adjacent oxide layers 104, the gate material 103g between the two adjacent oxide layers 104, and the slit 712. After the etch-back process, the remaining gate material 103g can be regarded as a gate structure, and the gate structure surrounds the drain columnar structure 601, the source columnar structure 602, and the vertical channel structure 106. The dielectric portion 601s is formed between the drain columnar structure 601 and the gate structure, or between the source columnar structure 602 and the gate structure.

[0062] Thus, a plurality of memory cells are formed in the structure. Each memory cell includes a drain columnar structure 601, a source columnar structure 602, two arc-shaped channel components and a gate material 103g (i.e., a gate structure), wherein the two arc-shaped channel components are formed in a hole 110 and between the drain columnar structure 601 and the source columnar structure 602. Each memory cell is a dual-channel type.

[0063] In one embodiment of the present invention, Figure 12A-12B After the processing stages shown, the exemplary structure can also be subjected to Figure 13A-Figure 14B Processing stages are depicted.

[0064] Fig.13A Department for Figure 12A-12BAn exemplary top view of the structure after the processing stage is shown, and Fig. 13B Along the Fig.13A 1 is an exemplary structural cross-sectional view shown along line P13 of FIG. In this process stage, a low temperature oxide (LTO) layer 109 is formed in the slits 710 and 712, and then a channel 115 is formed, and the channel 115 extends downward in the third direction D3 to penetrate the low temperature oxide layer 109. The channel 115 exposes the low temperature oxide layer 109, but the gate material 103g (i.e., the gate structure) and the high dielectric constant material layer 108 are not exposed by the channel 115. In one example, the low temperature oxide layer 109 is formed in the slits 710 and 712 by a deposition process, and then the low temperature oxide layer 109 is etched to form the channel 115.

[0065] Then, as Figure 14A-14B As shown, a conductive film 116 is formed in the channel 115 . Fig.14A Department for Figure 13A-13B An exemplary top view of the structure after the processing stage is shown, and Fig. 14B Along the Fig.14A 14 is a cross-sectional view of an exemplary structure shown by line P14. In one example, a conductive film 116 is deposited in and fills the trench 115, and then a chemical mechanical planarization process is applied to the structure. In one example, the conductive film 116 may include the same material as the gate material 103g. In the slits 710 and 712, the low temperature oxide layer 109 separates the conductive film 116 and the gate material 103g.

[0066] Next, an external circuit 120 is connected to the conductive film 116 to apply a current to the conductive film 116. The current passing through the conductive film 116 can generate heat, also known as Joule heating. The heat generated by this process helps repair the memory cell.

[0067] According to the present invention, the drain columnar structure and the source columnar structure of the storage device overlap with the hole portion in which the vertical channel structure is formed, so that the size of the hole is reduced. Therefore, the benefits of the present invention are that the size of each storage unit in the storage device is reduced, the storage density and storage capacity of the storage device are improved, and the size of the storage device is reduced. In addition, the architecture of the storage device proposed by the present invention can perform random access, that is, no matter what the memory address to be read or written is, it can be completed in the same time. Therefore, compared with NAND flash type storage devices that can only perform sequential access (block access), the storage device proposed by the present invention has a higher access speed. Furthermore, compared with traditional planar (2D) architecture storage devices, the storage device proposed by the present invention has a three-dimensional stacked architecture, so it can significantly improve the storage density and storage capacity of the storage device.

[0068] It should be noted that the drawings, structures and steps described above are used to describe some embodiments or application examples of the present invention, and the present invention is not limited to the scope and application embodiments of the above structures and steps. Embodiments of other different structural embodiments, such as known components of different internal elements, can be applied, and the exemplified structures and steps can be adjusted according to the needs of actual applications. Therefore, the structure of the drawings is only used for illustration, not for limiting the present invention. Those skilled in the art should know that the relevant structures and step processes of the present invention, such as the arrangement or configuration of the relevant elements and layers in the storage device, or the details of the manufacturing steps, may be adjusted and changed accordingly according to the actual application requirements.

[0069] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a storage device, comprising: forming a hole in the oxide-nitride stack; forming a vertical channel structure and a charge trapping structure on an inner wall of the hole; forming a first opening and a second opening, wherein the first opening and the second opening partially overlap the hole, and the first opening and the second opening penetrate the vertical channel structure, wherein the vertical channel structure is divided into two arc-shaped channel components by the first opening and the second opening; forming a drain columnar structure and a source columnar structure in the first opening and the second opening respectively; as well as A gate structure is formed, and the gate structure surrounds the drain columnar structure, the source columnar structure and the vertical channel structure.

2. The manufacturing method according to claim 1, wherein in the step of forming the drain columnar structure and the source columnar structure in the first opening and the second opening respectively, the drain columnar structure or the source columnar structure is partially located inside the hole and partially located outside the hole.

3. The manufacturing method according to claim 1, wherein in the step of forming the drain columnar structure and the source columnar structure in the first opening and the second opening respectively, two end points in each of the arc-shaped channel components are respectively connected to the drain columnar structure and the source columnar structure. 4 . The manufacturing method according to claim 1 , wherein in the step of forming the first opening and the second opening, the charge trapping structure is divided into two arc-shaped charge trapping components by the first opening and the second opening.

5. A storage device, comprising: A drain columnar structure is formed in a first opening; A source columnar structure formed in a second opening; a charge trapping structure; a vertical channel structure, the vertical channel structure and the charge trapping structure are formed in a hole, the hole partially overlaps the first opening and the second opening, wherein the vertical channel structure is divided into two arc-shaped channel components by the drain columnar structure and the source columnar structure; as well as A gate structure surrounds the drain column structure, the source column structure and the vertical channel structure. 6 . The storage device according to claim 5 , wherein the drain columnar structure or the source columnar structure is partially located in the hole, and the drain columnar structure or the source columnar structure is partially located outside the hole. 7 . The storage device according to claim 5 , wherein on a plane, a maximum distance between an edge of the drain pillar structure and a center point of the hole is greater than a radius of the hole. 8 . The storage device according to claim 5 , wherein two end points of each of the arc-shaped channel components are respectively connected to the drain columnar structure and the source columnar structure. 9 . The memory device according to claim 5 , further comprising a dielectric portion formed between the drain pillar structure and the gate structure. 10 . The memory device according to claim 5 , wherein the charge trapping structure is divided into two arc-shaped charge trapping components by the drain pillar structure and the source pillar structure.

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